drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  82                                       struct rte_mbuf **tx_pkts,
  83                                       uint16_t nb_pkts);
  84
  85 static inline void
  86 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  87 {
  88         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  89                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_VLAN_PKT;
  91                 mb->vlan_tci =
  92                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  93                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  94                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  95         } else {
  96                 mb->vlan_tci = 0;
  97         }
  98 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  99         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 100                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 101                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 102                 mb->vlan_tci_outer = mb->vlan_tci;
 103                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 104                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 105                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 107         } else {
 108                 mb->vlan_tci_outer = 0;
 109         }
 110 #endif
 111         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 112                    mb->vlan_tci, mb->vlan_tci_outer);
 113 }
 114
 115 /* Translate the rx descriptor status to pkt flags */
 116 static inline uint64_t
 117 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 118 {
 119         uint64_t flags;
 120
 121         /* Check if RSS_HASH */
 122         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 123                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 124                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 125
 126         /* Check if FDIR Match */
 127         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 128                                                         PKT_RX_FDIR : 0);
 129
 130         return flags;
 131 }
 132
 133 static inline uint64_t
 134 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 135 {
 136         uint64_t flags = 0;
 137         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 138
 139 #define I40E_RX_ERR_BITS 0x3f
 140         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 141                 return flags;
 142         /* If RXE bit set, all other status bits are meaningless */
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 144                 flags |= PKT_RX_MAC_ERR;
 145                 return flags;
 146         }
 147
 148         /* If RECIPE bit set, all other status indications should be ignored */
 149         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 150                 flags |= PKT_RX_RECIP_ERR;
 151                 return flags;
 152         }
 153         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 154                 flags |= PKT_RX_HBUF_OVERFLOW;
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 156                 flags |= PKT_RX_IP_CKSUM_BAD;
 157         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 158                 flags |= PKT_RX_L4_CKSUM_BAD;
 159         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 160                 flags |= PKT_RX_EIP_CKSUM_BAD;
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 162                 flags |= PKT_RX_OVERSIZE;
 163
 164         return flags;
 165 }
 166
 167 /* Function to check and set the ieee1588 timesync index and get the
 168  * appropriate flags.
 169  */
 170 #ifdef RTE_LIBRTE_IEEE1588
 171 static inline uint64_t
 172 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 173 {
 174         uint64_t pkt_flags = 0;
 175         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 176                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 177                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 178
 179         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 180                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 181                 pkt_flags = PKT_RX_IEEE1588_PTP;
 182         if (tsyn & 0x04) {
 183                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 184                 mb->timesync = tsyn & 0x03;
 185         }
 186
 187         return pkt_flags;
 188 }
 189 #endif
 190
 191 /* For each value it means, datasheet of hardware can tell more details
 192  *
 193  * @note: fix i40e_dev_supported_ptypes_get() if any change here.
 194  */
 195 static inline uint32_t
 196 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 197 {
 198         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 199                 /* L2 types */
 200                 /* [0] reserved */
 201                 [1] = RTE_PTYPE_L2_ETHER,
 202                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 203                 /* [3] - [5] reserved */
 204                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 205                 /* [7] - [10] reserved */
 206                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 207                 /* [12] - [21] reserved */
 208
 209                 /* Non tunneled IPv4 */
 210                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                         RTE_PTYPE_L4_FRAG,
 212                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 213                         RTE_PTYPE_L4_NONFRAG,
 214                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 215                         RTE_PTYPE_L4_UDP,
 216                 /* [25] reserved */
 217                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 218                         RTE_PTYPE_L4_TCP,
 219                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 220                         RTE_PTYPE_L4_SCTP,
 221                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 222                         RTE_PTYPE_L4_ICMP,
 223
 224                 /* IPv4 --> IPv4 */
 225                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 226                         RTE_PTYPE_TUNNEL_IP |
 227                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 228                         RTE_PTYPE_INNER_L4_FRAG,
 229                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 230                         RTE_PTYPE_TUNNEL_IP |
 231                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 232                         RTE_PTYPE_INNER_L4_NONFRAG,
 233                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 234                         RTE_PTYPE_TUNNEL_IP |
 235                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 236                         RTE_PTYPE_INNER_L4_UDP,
 237                 /* [32] reserved */
 238                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 239                         RTE_PTYPE_TUNNEL_IP |
 240                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 241                         RTE_PTYPE_INNER_L4_TCP,
 242                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 243                         RTE_PTYPE_TUNNEL_IP |
 244                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 245                         RTE_PTYPE_INNER_L4_SCTP,
 246                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 247                         RTE_PTYPE_TUNNEL_IP |
 248                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 249                         RTE_PTYPE_INNER_L4_ICMP,
 250
 251                 /* IPv4 --> IPv6 */
 252                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 253                         RTE_PTYPE_TUNNEL_IP |
 254                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 255                         RTE_PTYPE_INNER_L4_FRAG,
 256                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 257                         RTE_PTYPE_TUNNEL_IP |
 258                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 259                         RTE_PTYPE_INNER_L4_NONFRAG,
 260                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 261                         RTE_PTYPE_TUNNEL_IP |
 262                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 263                         RTE_PTYPE_INNER_L4_UDP,
 264                 /* [39] reserved */
 265                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 266                         RTE_PTYPE_TUNNEL_IP |
 267                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 268                         RTE_PTYPE_INNER_L4_TCP,
 269                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 270                         RTE_PTYPE_TUNNEL_IP |
 271                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 272                         RTE_PTYPE_INNER_L4_SCTP,
 273                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 274                         RTE_PTYPE_TUNNEL_IP |
 275                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 276                         RTE_PTYPE_INNER_L4_ICMP,
 277
 278                 /* IPv4 --> GRE/Teredo/VXLAN */
 279                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 280                         RTE_PTYPE_TUNNEL_GRENAT,
 281
 282                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 283                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 284                         RTE_PTYPE_TUNNEL_GRENAT |
 285                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 286                         RTE_PTYPE_INNER_L4_FRAG,
 287                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 288                         RTE_PTYPE_TUNNEL_GRENAT |
 289                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 290                         RTE_PTYPE_INNER_L4_NONFRAG,
 291                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 292                         RTE_PTYPE_TUNNEL_GRENAT |
 293                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 294                         RTE_PTYPE_INNER_L4_UDP,
 295                 /* [47] reserved */
 296                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 297                         RTE_PTYPE_TUNNEL_GRENAT |
 298                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 299                         RTE_PTYPE_INNER_L4_TCP,
 300                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 301                         RTE_PTYPE_TUNNEL_GRENAT |
 302                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 303                         RTE_PTYPE_INNER_L4_SCTP,
 304                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 305                         RTE_PTYPE_TUNNEL_GRENAT |
 306                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 307                         RTE_PTYPE_INNER_L4_ICMP,
 308
 309                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 310                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 311                         RTE_PTYPE_TUNNEL_GRENAT |
 312                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 313                         RTE_PTYPE_INNER_L4_FRAG,
 314                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 315                         RTE_PTYPE_TUNNEL_GRENAT |
 316                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 317                         RTE_PTYPE_INNER_L4_NONFRAG,
 318                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 319                         RTE_PTYPE_TUNNEL_GRENAT |
 320                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 321                         RTE_PTYPE_INNER_L4_UDP,
 322                 /* [54] reserved */
 323                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 324                         RTE_PTYPE_TUNNEL_GRENAT |
 325                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 326                         RTE_PTYPE_INNER_L4_TCP,
 327                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 328                         RTE_PTYPE_TUNNEL_GRENAT |
 329                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 330                         RTE_PTYPE_INNER_L4_SCTP,
 331                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 332                         RTE_PTYPE_TUNNEL_GRENAT |
 333                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 334                         RTE_PTYPE_INNER_L4_ICMP,
 335
 336                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 337                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 338                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 339
 340                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 341                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 342                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 343                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 344                         RTE_PTYPE_INNER_L4_FRAG,
 345                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 346                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 347                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 348                         RTE_PTYPE_INNER_L4_NONFRAG,
 349                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 350                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 351                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 352                         RTE_PTYPE_INNER_L4_UDP,
 353                 /* [62] reserved */
 354                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 355                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 356                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 357                         RTE_PTYPE_INNER_L4_TCP,
 358                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 359                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 360                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 361                         RTE_PTYPE_INNER_L4_SCTP,
 362                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 363                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 364                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 365                         RTE_PTYPE_INNER_L4_ICMP,
 366
 367                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 368                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 369                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 370                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 371                         RTE_PTYPE_INNER_L4_FRAG,
 372                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 373                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 374                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 375                         RTE_PTYPE_INNER_L4_NONFRAG,
 376                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 377                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 378                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 379                         RTE_PTYPE_INNER_L4_UDP,
 380                 /* [69] reserved */
 381                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 382                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 383                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 384                         RTE_PTYPE_INNER_L4_TCP,
 385                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 386                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 387                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 388                         RTE_PTYPE_INNER_L4_SCTP,
 389                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 390                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 391                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 392                         RTE_PTYPE_INNER_L4_ICMP,
 393
 394                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 395                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 396                         RTE_PTYPE_TUNNEL_GRENAT |
 397                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 398
 399                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 400                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 401                         RTE_PTYPE_TUNNEL_GRENAT |
 402                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 403                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 404                         RTE_PTYPE_INNER_L4_FRAG,
 405                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 406                         RTE_PTYPE_TUNNEL_GRENAT |
 407                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 408                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 409                         RTE_PTYPE_INNER_L4_NONFRAG,
 410                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 411                         RTE_PTYPE_TUNNEL_GRENAT |
 412                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 413                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 414                         RTE_PTYPE_INNER_L4_UDP,
 415                 /* [77] reserved */
 416                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 417                         RTE_PTYPE_TUNNEL_GRENAT |
 418                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 419                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 420                         RTE_PTYPE_INNER_L4_TCP,
 421                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 422                         RTE_PTYPE_TUNNEL_GRENAT |
 423                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 424                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 425                         RTE_PTYPE_INNER_L4_SCTP,
 426                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 427                         RTE_PTYPE_TUNNEL_GRENAT |
 428                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 429                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 430                         RTE_PTYPE_INNER_L4_ICMP,
 431
 432                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 433                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 434                         RTE_PTYPE_TUNNEL_GRENAT |
 435                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 436                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 437                         RTE_PTYPE_INNER_L4_FRAG,
 438                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 439                         RTE_PTYPE_TUNNEL_GRENAT |
 440                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 441                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 442                         RTE_PTYPE_INNER_L4_NONFRAG,
 443                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 444                         RTE_PTYPE_TUNNEL_GRENAT |
 445                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 446                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 447                         RTE_PTYPE_INNER_L4_UDP,
 448                 /* [84] reserved */
 449                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 450                         RTE_PTYPE_TUNNEL_GRENAT |
 451                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 452                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 453                         RTE_PTYPE_INNER_L4_TCP,
 454                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 455                         RTE_PTYPE_TUNNEL_GRENAT |
 456                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 457                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 458                         RTE_PTYPE_INNER_L4_SCTP,
 459                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 460                         RTE_PTYPE_TUNNEL_GRENAT |
 461                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 462                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 463                         RTE_PTYPE_INNER_L4_ICMP,
 464
 465                 /* Non tunneled IPv6 */
 466                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 467                         RTE_PTYPE_L4_FRAG,
 468                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 469                         RTE_PTYPE_L4_NONFRAG,
 470                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 471                         RTE_PTYPE_L4_UDP,
 472                 /* [91] reserved */
 473                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 474                         RTE_PTYPE_L4_TCP,
 475                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 476                         RTE_PTYPE_L4_SCTP,
 477                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 478                         RTE_PTYPE_L4_ICMP,
 479
 480                 /* IPv6 --> IPv4 */
 481                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 482                         RTE_PTYPE_TUNNEL_IP |
 483                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 484                         RTE_PTYPE_INNER_L4_FRAG,
 485                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 486                         RTE_PTYPE_TUNNEL_IP |
 487                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 488                         RTE_PTYPE_INNER_L4_NONFRAG,
 489                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 490                         RTE_PTYPE_TUNNEL_IP |
 491                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 492                         RTE_PTYPE_INNER_L4_UDP,
 493                 /* [98] reserved */
 494                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 495                         RTE_PTYPE_TUNNEL_IP |
 496                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 497                         RTE_PTYPE_INNER_L4_TCP,
 498                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 499                         RTE_PTYPE_TUNNEL_IP |
 500                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 501                         RTE_PTYPE_INNER_L4_SCTP,
 502                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 503                         RTE_PTYPE_TUNNEL_IP |
 504                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 505                         RTE_PTYPE_INNER_L4_ICMP,
 506
 507                 /* IPv6 --> IPv6 */
 508                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 509                         RTE_PTYPE_TUNNEL_IP |
 510                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 511                         RTE_PTYPE_INNER_L4_FRAG,
 512                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 513                         RTE_PTYPE_TUNNEL_IP |
 514                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 515                         RTE_PTYPE_INNER_L4_NONFRAG,
 516                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 517                         RTE_PTYPE_TUNNEL_IP |
 518                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 519                         RTE_PTYPE_INNER_L4_UDP,
 520                 /* [105] reserved */
 521                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 522                         RTE_PTYPE_TUNNEL_IP |
 523                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 524                         RTE_PTYPE_INNER_L4_TCP,
 525                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 526                         RTE_PTYPE_TUNNEL_IP |
 527                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 528                         RTE_PTYPE_INNER_L4_SCTP,
 529                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 530                         RTE_PTYPE_TUNNEL_IP |
 531                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 532                         RTE_PTYPE_INNER_L4_ICMP,
 533
 534                 /* IPv6 --> GRE/Teredo/VXLAN */
 535                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 536                         RTE_PTYPE_TUNNEL_GRENAT,
 537
 538                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 539                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 540                         RTE_PTYPE_TUNNEL_GRENAT |
 541                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 542                         RTE_PTYPE_INNER_L4_FRAG,
 543                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 544                         RTE_PTYPE_TUNNEL_GRENAT |
 545                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 546                         RTE_PTYPE_INNER_L4_NONFRAG,
 547                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 548                         RTE_PTYPE_TUNNEL_GRENAT |
 549                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 550                         RTE_PTYPE_INNER_L4_UDP,
 551                 /* [113] reserved */
 552                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 553                         RTE_PTYPE_TUNNEL_GRENAT |
 554                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 555                         RTE_PTYPE_INNER_L4_TCP,
 556                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 557                         RTE_PTYPE_TUNNEL_GRENAT |
 558                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 559                         RTE_PTYPE_INNER_L4_SCTP,
 560                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 561                         RTE_PTYPE_TUNNEL_GRENAT |
 562                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 563                         RTE_PTYPE_INNER_L4_ICMP,
 564
 565                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 566                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 567                         RTE_PTYPE_TUNNEL_GRENAT |
 568                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 569                         RTE_PTYPE_INNER_L4_FRAG,
 570                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 571                         RTE_PTYPE_TUNNEL_GRENAT |
 572                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 573                         RTE_PTYPE_INNER_L4_NONFRAG,
 574                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 575                         RTE_PTYPE_TUNNEL_GRENAT |
 576                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 577                         RTE_PTYPE_INNER_L4_UDP,
 578                 /* [120] reserved */
 579                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 580                         RTE_PTYPE_TUNNEL_GRENAT |
 581                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 582                         RTE_PTYPE_INNER_L4_TCP,
 583                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 584                         RTE_PTYPE_TUNNEL_GRENAT |
 585                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 586                         RTE_PTYPE_INNER_L4_SCTP,
 587                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 588                         RTE_PTYPE_TUNNEL_GRENAT |
 589                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 590                         RTE_PTYPE_INNER_L4_ICMP,
 591
 592                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 593                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 594                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 595
 596                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 597                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 598                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 599                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 600                         RTE_PTYPE_INNER_L4_FRAG,
 601                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 602                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 603                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 604                         RTE_PTYPE_INNER_L4_NONFRAG,
 605                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 606                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 607                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 608                         RTE_PTYPE_INNER_L4_UDP,
 609                 /* [128] reserved */
 610                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 611                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 612                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 613                         RTE_PTYPE_INNER_L4_TCP,
 614                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 615                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 616                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 617                         RTE_PTYPE_INNER_L4_SCTP,
 618                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 619                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 620                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 621                         RTE_PTYPE_INNER_L4_ICMP,
 622
 623                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 624                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 625                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 626                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 627                         RTE_PTYPE_INNER_L4_FRAG,
 628                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 629                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 630                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 631                         RTE_PTYPE_INNER_L4_NONFRAG,
 632                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 633                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 634                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 635                         RTE_PTYPE_INNER_L4_UDP,
 636                 /* [135] reserved */
 637                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 638                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 639                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 640                         RTE_PTYPE_INNER_L4_TCP,
 641                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 642                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 643                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 644                         RTE_PTYPE_INNER_L4_SCTP,
 645                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 646                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 647                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 648                         RTE_PTYPE_INNER_L4_ICMP,
 649
 650                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 651                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 652                         RTE_PTYPE_TUNNEL_GRENAT |
 653                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 654
 655                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 656                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 657                         RTE_PTYPE_TUNNEL_GRENAT |
 658                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 659                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 660                         RTE_PTYPE_INNER_L4_FRAG,
 661                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 662                         RTE_PTYPE_TUNNEL_GRENAT |
 663                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 664                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 665                         RTE_PTYPE_INNER_L4_NONFRAG,
 666                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 667                         RTE_PTYPE_TUNNEL_GRENAT |
 668                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 669                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 670                         RTE_PTYPE_INNER_L4_UDP,
 671                 /* [143] reserved */
 672                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 673                         RTE_PTYPE_TUNNEL_GRENAT |
 674                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 675                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 676                         RTE_PTYPE_INNER_L4_TCP,
 677                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 678                         RTE_PTYPE_TUNNEL_GRENAT |
 679                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 680                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 681                         RTE_PTYPE_INNER_L4_SCTP,
 682                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 683                         RTE_PTYPE_TUNNEL_GRENAT |
 684                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 685                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 686                         RTE_PTYPE_INNER_L4_ICMP,
 687
 688                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 689                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 690                         RTE_PTYPE_TUNNEL_GRENAT |
 691                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 692                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 693                         RTE_PTYPE_INNER_L4_FRAG,
 694                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 695                         RTE_PTYPE_TUNNEL_GRENAT |
 696                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 697                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 698                         RTE_PTYPE_INNER_L4_NONFRAG,
 699                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 700                         RTE_PTYPE_TUNNEL_GRENAT |
 701                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 702                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 703                         RTE_PTYPE_INNER_L4_UDP,
 704                 /* [150] reserved */
 705                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 706                         RTE_PTYPE_TUNNEL_GRENAT |
 707                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 708                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 709                         RTE_PTYPE_INNER_L4_TCP,
 710                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 711                         RTE_PTYPE_TUNNEL_GRENAT |
 712                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 713                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 714                         RTE_PTYPE_INNER_L4_SCTP,
 715                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 716                         RTE_PTYPE_TUNNEL_GRENAT |
 717                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 718                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 719                         RTE_PTYPE_INNER_L4_ICMP,
 720
 721                 /* All others reserved */
 722         };
 723
 724         return type_table[ptype];
 725 }
 726
 727 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 728 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 729 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 730 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 731 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 732
 733 static inline uint64_t
 734 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 735 {
 736         uint64_t flags = 0;
 737 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 738         uint16_t flexbh, flexbl;
 739
 740         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 741                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 742                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 743         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 744                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 745                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 746
 747
 748         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 749                 mb->hash.fdir.hi =
 750                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 751                 flags |= PKT_RX_FDIR_ID;
 752         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 753                 mb->hash.fdir.hi =
 754                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 755                 flags |= PKT_RX_FDIR_FLX;
 756         }
 757         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 758                 mb->hash.fdir.lo =
 759                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 760                 flags |= PKT_RX_FDIR_FLX;
 761         }
 762 #else
 763         mb->hash.fdir.hi =
 764                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 765         flags |= PKT_RX_FDIR_ID;
 766 #endif
 767         return flags;
 768 }
 769 static inline void
 770 i40e_txd_enable_checksum(uint64_t ol_flags,
 771                         uint32_t *td_cmd,
 772                         uint32_t *td_offset,
 773                         union i40e_tx_offload tx_offload,
 774                         uint32_t *cd_tunneling)
 775 {
 776         /* UDP tunneling packet TX checksum offload */
 777         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 778
 779                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 780                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 781
 782                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 783                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 784                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 785                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 786                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 787                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 788
 789                 /* Now set the ctx descriptor fields */
 790                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 791                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 792                                 (tx_offload.l2_len >> 1) <<
 793                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 794
 795         } else
 796                 *td_offset |= (tx_offload.l2_len >> 1)
 797                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 798
 799         /* Enable L3 checksum offloads */
 800         if (ol_flags & PKT_TX_IP_CKSUM) {
 801                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 802                 *td_offset |= (tx_offload.l3_len >> 2)
 803                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 804         } else if (ol_flags & PKT_TX_IPV4) {
 805                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 806                 *td_offset |= (tx_offload.l3_len >> 2)
 807                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 808         } else if (ol_flags & PKT_TX_IPV6) {
 809                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 810                 *td_offset |= (tx_offload.l3_len >> 2)
 811                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 812         }
 813
 814         if (ol_flags & PKT_TX_TCP_SEG) {
 815                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 816                 *td_offset |= (tx_offload.l4_len >> 2)
 817                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 818                 return;
 819         }
 820
 821         /* Enable L4 checksum offloads */
 822         switch (ol_flags & PKT_TX_L4_MASK) {
 823         case PKT_TX_TCP_CKSUM:
 824                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 825                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 826                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 827                 break;
 828         case PKT_TX_SCTP_CKSUM:
 829                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 830                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 831                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 832                 break;
 833         case PKT_TX_UDP_CKSUM:
 834                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 835                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 836                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 837                 break;
 838         default:
 839                 break;
 840         }
 841 }
 842
 843 static inline struct rte_mbuf *
 844 rte_rxmbuf_alloc(struct rte_mempool *mp)
 845 {
 846         struct rte_mbuf *m;
 847
 848         m = __rte_mbuf_raw_alloc(mp);
 849         __rte_mbuf_sanity_check_raw(m, 0);
 850
 851         return m;
 852 }
 853
 854 /* Construct the tx flags */
 855 static inline uint64_t
 856 i40e_build_ctob(uint32_t td_cmd,
 857                 uint32_t td_offset,
 858                 unsigned int size,
 859                 uint32_t td_tag)
 860 {
 861         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 862                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 863                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 864                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 865                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 866 }
 867
 868 static inline int
 869 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 870 {
 871         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 872         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 873         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 874         uint16_t nb_tx_desc = txq->nb_tx_desc;
 875         uint16_t desc_to_clean_to;
 876         uint16_t nb_tx_to_clean;
 877
 878         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 879         if (desc_to_clean_to >= nb_tx_desc)
 880                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 881
 882         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 883         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 884                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 885                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 886                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 887                         "(port=%d queue=%d)", desc_to_clean_to,
 888                                 txq->port_id, txq->queue_id);
 889                 return -1;
 890         }
 891
 892         if (last_desc_cleaned > desc_to_clean_to)
 893                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 894                                                         desc_to_clean_to);
 895         else
 896                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 897                                         last_desc_cleaned);
 898
 899         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 900
 901         txq->last_desc_cleaned = desc_to_clean_to;
 902         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 903
 904         return 0;
 905 }
 906
 907 static inline int
 908 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 909 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 910 #else
 911 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 912 #endif
 913 {
 914         int ret = 0;
 915
 916 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 917         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 918                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 919                              "rxq->rx_free_thresh=%d, "
 920                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 921                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 922                 ret = -EINVAL;
 923         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 924                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 925                              "rxq->rx_free_thresh=%d, "
 926                              "rxq->nb_rx_desc=%d",
 927                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 928                 ret = -EINVAL;
 929         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 930                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 931                              "rxq->nb_rx_desc=%d, "
 932                              "rxq->rx_free_thresh=%d",
 933                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 934                 ret = -EINVAL;
 935         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 936                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 937                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 938                              "rxq->nb_rx_desc=%d, "
 939                              "I40E_MAX_RING_DESC=%d, "
 940                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 941                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 942                              RTE_PMD_I40E_RX_MAX_BURST);
 943                 ret = -EINVAL;
 944         }
 945 #else
 946         ret = -EINVAL;
 947 #endif
 948
 949         return ret;
 950 }
 951
 952 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 953 #define I40E_LOOK_AHEAD 8
 954 #if (I40E_LOOK_AHEAD != 8)
 955 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 956 #endif
 957 static inline int
 958 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 959 {
 960         volatile union i40e_rx_desc *rxdp;
 961         struct i40e_rx_entry *rxep;
 962         struct rte_mbuf *mb;
 963         uint16_t pkt_len;
 964         uint64_t qword1;
 965         uint32_t rx_status;
 966         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 967         int32_t i, j, nb_rx = 0;
 968         uint64_t pkt_flags;
 969
 970         rxdp = &rxq->rx_ring[rxq->rx_tail];
 971         rxep = &rxq->sw_ring[rxq->rx_tail];
 972
 973         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 974         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 975                                 I40E_RXD_QW1_STATUS_SHIFT;
 976
 977         /* Make sure there is at least 1 packet to receive */
 978         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 979                 return 0;
 980
 981         /**
 982          * Scan LOOK_AHEAD descriptors at a time to determine which
 983          * descriptors reference packets that are ready to be received.
 984          */
 985         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 986                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 987                 /* Read desc statuses backwards to avoid race condition */
 988                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 989                         qword1 = rte_le_to_cpu_64(\
 990                                 rxdp[j].wb.qword1.status_error_len);
 991                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 992                                         I40E_RXD_QW1_STATUS_SHIFT;
 993                 }
 994
 995                 /* Compute how many status bits were set */
 996                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 997                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 998
 999                 nb_rx += nb_dd;
1000
1001                 /* Translate descriptor info to mbuf parameters */
1002                 for (j = 0; j < nb_dd; j++) {
1003                         mb = rxep[j].mbuf;
1004                         qword1 = rte_le_to_cpu_64(\
1005                                 rxdp[j].wb.qword1.status_error_len);
1006                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1007                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1008                         mb->data_len = pkt_len;
1009                         mb->pkt_len = pkt_len;
1010                         mb->ol_flags = 0;
1011                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1012                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1013                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1014                         mb->packet_type =
1015                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1016                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1017                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1018                         if (pkt_flags & PKT_RX_RSS_HASH)
1019                                 mb->hash.rss = rte_le_to_cpu_32(\
1020                                         rxdp[j].wb.qword0.hi_dword.rss);
1021                         if (pkt_flags & PKT_RX_FDIR)
1022                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1023
1024 #ifdef RTE_LIBRTE_IEEE1588
1025                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1026 #endif
1027                         mb->ol_flags |= pkt_flags;
1028
1029                 }
1030
1031                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1032                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1033
1034                 if (nb_dd != I40E_LOOK_AHEAD)
1035                         break;
1036         }
1037
1038         /* Clear software ring entries */
1039         for (i = 0; i < nb_rx; i++)
1040                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1041
1042         return nb_rx;
1043 }
1044
1045 static inline uint16_t
1046 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1047                         struct rte_mbuf **rx_pkts,
1048                         uint16_t nb_pkts)
1049 {
1050         uint16_t i;
1051         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1052
1053         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1054
1055         for (i = 0; i < nb_pkts; i++)
1056                 rx_pkts[i] = stage[i];
1057
1058         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1059         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1060
1061         return nb_pkts;
1062 }
1063
1064 static inline int
1065 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1066 {
1067         volatile union i40e_rx_desc *rxdp;
1068         struct i40e_rx_entry *rxep;
1069         struct rte_mbuf *mb;
1070         uint16_t alloc_idx, i;
1071         uint64_t dma_addr;
1072         int diag;
1073
1074         /* Allocate buffers in bulk */
1075         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1076                                 (rxq->rx_free_thresh - 1));
1077         rxep = &(rxq->sw_ring[alloc_idx]);
1078         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1079                                         rxq->rx_free_thresh);
1080         if (unlikely(diag != 0)) {
1081                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1082                 return -ENOMEM;
1083         }
1084
1085         rxdp = &rxq->rx_ring[alloc_idx];
1086         for (i = 0; i < rxq->rx_free_thresh; i++) {
1087                 if (likely(i < (rxq->rx_free_thresh - 1)))
1088                         /* Prefetch next mbuf */
1089                         rte_prefetch0(rxep[i + 1].mbuf);
1090
1091                 mb = rxep[i].mbuf;
1092                 rte_mbuf_refcnt_set(mb, 1);
1093                 mb->next = NULL;
1094                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1095                 mb->nb_segs = 1;
1096                 mb->port = rxq->port_id;
1097                 dma_addr = rte_cpu_to_le_64(\
1098                         rte_mbuf_data_dma_addr_default(mb));
1099                 rxdp[i].read.hdr_addr = 0;
1100                 rxdp[i].read.pkt_addr = dma_addr;
1101         }
1102
1103         /* Update rx tail regsiter */
1104         rte_wmb();
1105         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1106
1107         rxq->rx_free_trigger =
1108                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1109         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1110                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1111
1112         return 0;
1113 }
1114
1115 static inline uint16_t
1116 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1117 {
1118         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1119         uint16_t nb_rx = 0;
1120
1121         if (!nb_pkts)
1122                 return 0;
1123
1124         if (rxq->rx_nb_avail)
1125                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1126
1127         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1128         rxq->rx_next_avail = 0;
1129         rxq->rx_nb_avail = nb_rx;
1130         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1131
1132         if (rxq->rx_tail > rxq->rx_free_trigger) {
1133                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1134                         uint16_t i, j;
1135
1136                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1137                                    "port_id=%u, queue_id=%u",
1138                                    rxq->port_id, rxq->queue_id);
1139                         rxq->rx_nb_avail = 0;
1140                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1141                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1142                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1143
1144                         return 0;
1145                 }
1146         }
1147
1148         if (rxq->rx_tail >= rxq->nb_rx_desc)
1149                 rxq->rx_tail = 0;
1150
1151         if (rxq->rx_nb_avail)
1152                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1153
1154         return 0;
1155 }
1156
1157 static uint16_t
1158 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1159                           struct rte_mbuf **rx_pkts,
1160                           uint16_t nb_pkts)
1161 {
1162         uint16_t nb_rx = 0, n, count;
1163
1164         if (unlikely(nb_pkts == 0))
1165                 return 0;
1166
1167         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1168                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1169
1170         while (nb_pkts) {
1171                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1172                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1173                 nb_rx = (uint16_t)(nb_rx + count);
1174                 nb_pkts = (uint16_t)(nb_pkts - count);
1175                 if (count < n)
1176                         break;
1177         }
1178
1179         return nb_rx;
1180 }
1181 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1182
1183 uint16_t
1184 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1185 {
1186         struct i40e_rx_queue *rxq;
1187         volatile union i40e_rx_desc *rx_ring;
1188         volatile union i40e_rx_desc *rxdp;
1189         union i40e_rx_desc rxd;
1190         struct i40e_rx_entry *sw_ring;
1191         struct i40e_rx_entry *rxe;
1192         struct rte_mbuf *rxm;
1193         struct rte_mbuf *nmb;
1194         uint16_t nb_rx;
1195         uint32_t rx_status;
1196         uint64_t qword1;
1197         uint16_t rx_packet_len;
1198         uint16_t rx_id, nb_hold;
1199         uint64_t dma_addr;
1200         uint64_t pkt_flags;
1201
1202         nb_rx = 0;
1203         nb_hold = 0;
1204         rxq = rx_queue;
1205         rx_id = rxq->rx_tail;
1206         rx_ring = rxq->rx_ring;
1207         sw_ring = rxq->sw_ring;
1208
1209         while (nb_rx < nb_pkts) {
1210                 rxdp = &rx_ring[rx_id];
1211                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1212                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1213                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1214
1215                 /* Check the DD bit first */
1216                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1217                         break;
1218
1219                 nmb = rte_rxmbuf_alloc(rxq->mp);
1220                 if (unlikely(!nmb))
1221                         break;
1222                 rxd = *rxdp;
1223
1224                 nb_hold++;
1225                 rxe = &sw_ring[rx_id];
1226                 rx_id++;
1227                 if (unlikely(rx_id == rxq->nb_rx_desc))
1228                         rx_id = 0;
1229
1230                 /* Prefetch next mbuf */
1231                 rte_prefetch0(sw_ring[rx_id].mbuf);
1232
1233                 /**
1234                  * When next RX descriptor is on a cache line boundary,
1235                  * prefetch the next 4 RX descriptors and next 8 pointers
1236                  * to mbufs.
1237                  */
1238                 if ((rx_id & 0x3) == 0) {
1239                         rte_prefetch0(&rx_ring[rx_id]);
1240                         rte_prefetch0(&sw_ring[rx_id]);
1241                 }
1242                 rxm = rxe->mbuf;
1243                 rxe->mbuf = nmb;
1244                 dma_addr =
1245                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1246                 rxdp->read.hdr_addr = 0;
1247                 rxdp->read.pkt_addr = dma_addr;
1248
1249                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1250                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1251
1252                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1253                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1254                 rxm->nb_segs = 1;
1255                 rxm->next = NULL;
1256                 rxm->pkt_len = rx_packet_len;
1257                 rxm->data_len = rx_packet_len;
1258                 rxm->port = rxq->port_id;
1259                 rxm->ol_flags = 0;
1260                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1261                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1262                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1263                 rxm->packet_type =
1264                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1265                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1266                 if (pkt_flags & PKT_RX_RSS_HASH)
1267                         rxm->hash.rss =
1268                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1269                 if (pkt_flags & PKT_RX_FDIR)
1270                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1271
1272 #ifdef RTE_LIBRTE_IEEE1588
1273                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1274 #endif
1275                 rxm->ol_flags |= pkt_flags;
1276
1277                 rx_pkts[nb_rx++] = rxm;
1278         }
1279         rxq->rx_tail = rx_id;
1280
1281         /**
1282          * If the number of free RX descriptors is greater than the RX free
1283          * threshold of the queue, advance the receive tail register of queue.
1284          * Update that register with the value of the last processed RX
1285          * descriptor minus 1.
1286          */
1287         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1288         if (nb_hold > rxq->rx_free_thresh) {
1289                 rx_id = (uint16_t) ((rx_id == 0) ?
1290                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1291                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1292                 nb_hold = 0;
1293         }
1294         rxq->nb_rx_hold = nb_hold;
1295
1296         return nb_rx;
1297 }
1298
1299 uint16_t
1300 i40e_recv_scattered_pkts(void *rx_queue,
1301                          struct rte_mbuf **rx_pkts,
1302                          uint16_t nb_pkts)
1303 {
1304         struct i40e_rx_queue *rxq = rx_queue;
1305         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1306         volatile union i40e_rx_desc *rxdp;
1307         union i40e_rx_desc rxd;
1308         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1309         struct i40e_rx_entry *rxe;
1310         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1311         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1312         struct rte_mbuf *nmb, *rxm;
1313         uint16_t rx_id = rxq->rx_tail;
1314         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1315         uint32_t rx_status;
1316         uint64_t qword1;
1317         uint64_t dma_addr;
1318         uint64_t pkt_flags;
1319
1320         while (nb_rx < nb_pkts) {
1321                 rxdp = &rx_ring[rx_id];
1322                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1323                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1324                                         I40E_RXD_QW1_STATUS_SHIFT;
1325
1326                 /* Check the DD bit */
1327                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1328                         break;
1329
1330                 nmb = rte_rxmbuf_alloc(rxq->mp);
1331                 if (unlikely(!nmb))
1332                         break;
1333                 rxd = *rxdp;
1334                 nb_hold++;
1335                 rxe = &sw_ring[rx_id];
1336                 rx_id++;
1337                 if (rx_id == rxq->nb_rx_desc)
1338                         rx_id = 0;
1339
1340                 /* Prefetch next mbuf */
1341                 rte_prefetch0(sw_ring[rx_id].mbuf);
1342
1343                 /**
1344                  * When next RX descriptor is on a cache line boundary,
1345                  * prefetch the next 4 RX descriptors and next 8 pointers
1346                  * to mbufs.
1347                  */
1348                 if ((rx_id & 0x3) == 0) {
1349                         rte_prefetch0(&rx_ring[rx_id]);
1350                         rte_prefetch0(&sw_ring[rx_id]);
1351                 }
1352
1353                 rxm = rxe->mbuf;
1354                 rxe->mbuf = nmb;
1355                 dma_addr =
1356                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1357
1358                 /* Set data buffer address and data length of the mbuf */
1359                 rxdp->read.hdr_addr = 0;
1360                 rxdp->read.pkt_addr = dma_addr;
1361                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1362                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1363                 rxm->data_len = rx_packet_len;
1364                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1365
1366                 /**
1367                  * If this is the first buffer of the received packet, set the
1368                  * pointer to the first mbuf of the packet and initialize its
1369                  * context. Otherwise, update the total length and the number
1370                  * of segments of the current scattered packet, and update the
1371                  * pointer to the last mbuf of the current packet.
1372                  */
1373                 if (!first_seg) {
1374                         first_seg = rxm;
1375                         first_seg->nb_segs = 1;
1376                         first_seg->pkt_len = rx_packet_len;
1377                 } else {
1378                         first_seg->pkt_len =
1379                                 (uint16_t)(first_seg->pkt_len +
1380                                                 rx_packet_len);
1381                         first_seg->nb_segs++;
1382                         last_seg->next = rxm;
1383                 }
1384
1385                 /**
1386                  * If this is not the last buffer of the received packet,
1387                  * update the pointer to the last mbuf of the current scattered
1388                  * packet and continue to parse the RX ring.
1389                  */
1390                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1391                         last_seg = rxm;
1392                         continue;
1393                 }
1394
1395                 /**
1396                  * This is the last buffer of the received packet. If the CRC
1397                  * is not stripped by the hardware:
1398                  *  - Subtract the CRC length from the total packet length.
1399                  *  - If the last buffer only contains the whole CRC or a part
1400                  *  of it, free the mbuf associated to the last buffer. If part
1401                  *  of the CRC is also contained in the previous mbuf, subtract
1402                  *  the length of that CRC part from the data length of the
1403                  *  previous mbuf.
1404                  */
1405                 rxm->next = NULL;
1406                 if (unlikely(rxq->crc_len > 0)) {
1407                         first_seg->pkt_len -= ETHER_CRC_LEN;
1408                         if (rx_packet_len <= ETHER_CRC_LEN) {
1409                                 rte_pktmbuf_free_seg(rxm);
1410                                 first_seg->nb_segs--;
1411                                 last_seg->data_len =
1412                                         (uint16_t)(last_seg->data_len -
1413                                         (ETHER_CRC_LEN - rx_packet_len));
1414                                 last_seg->next = NULL;
1415                         } else
1416                                 rxm->data_len = (uint16_t)(rx_packet_len -
1417                                                                 ETHER_CRC_LEN);
1418                 }
1419
1420                 first_seg->port = rxq->port_id;
1421                 first_seg->ol_flags = 0;
1422                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1423                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1424                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1425                 first_seg->packet_type =
1426                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1427                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1428                 if (pkt_flags & PKT_RX_RSS_HASH)
1429                         rxm->hash.rss =
1430                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1431                 if (pkt_flags & PKT_RX_FDIR)
1432                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1433
1434 #ifdef RTE_LIBRTE_IEEE1588
1435                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1436 #endif
1437                 first_seg->ol_flags |= pkt_flags;
1438
1439                 /* Prefetch data of first segment, if configured to do so. */
1440                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1441                         first_seg->data_off));
1442                 rx_pkts[nb_rx++] = first_seg;
1443                 first_seg = NULL;
1444         }
1445
1446         /* Record index of the next RX descriptor to probe. */
1447         rxq->rx_tail = rx_id;
1448         rxq->pkt_first_seg = first_seg;
1449         rxq->pkt_last_seg = last_seg;
1450
1451         /**
1452          * If the number of free RX descriptors is greater than the RX free
1453          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1454          * register. Update the RDT with the value of the last processed RX
1455          * descriptor minus 1, to guarantee that the RDT register is never
1456          * equal to the RDH register, which creates a "full" ring situtation
1457          * from the hardware point of view.
1458          */
1459         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1460         if (nb_hold > rxq->rx_free_thresh) {
1461                 rx_id = (uint16_t)(rx_id == 0 ?
1462                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1463                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1464                 nb_hold = 0;
1465         }
1466         rxq->nb_rx_hold = nb_hold;
1467
1468         return nb_rx;
1469 }
1470
1471 /* Check if the context descriptor is needed for TX offloading */
1472 static inline uint16_t
1473 i40e_calc_context_desc(uint64_t flags)
1474 {
1475         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1476                 PKT_TX_TCP_SEG |
1477                 PKT_TX_QINQ_PKT;
1478
1479 #ifdef RTE_LIBRTE_IEEE1588
1480         mask |= PKT_TX_IEEE1588_TMST;
1481 #endif
1482
1483         return (flags & mask) ? 1 : 0;
1484 }
1485
1486 /* set i40e TSO context descriptor */
1487 static inline uint64_t
1488 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1489 {
1490         uint64_t ctx_desc = 0;
1491         uint32_t cd_cmd, hdr_len, cd_tso_len;
1492
1493         if (!tx_offload.l4_len) {
1494                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1495                 return ctx_desc;
1496         }
1497
1498         /**
1499          * in case of tunneling packet, the outer_l2_len and
1500          * outer_l3_len must be 0.
1501          */
1502         hdr_len = tx_offload.outer_l2_len +
1503                 tx_offload.outer_l3_len +
1504                 tx_offload.l2_len +
1505                 tx_offload.l3_len +
1506                 tx_offload.l4_len;
1507
1508         cd_cmd = I40E_TX_CTX_DESC_TSO;
1509         cd_tso_len = mbuf->pkt_len - hdr_len;
1510         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1511                 ((uint64_t)cd_tso_len <<
1512                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1513                 ((uint64_t)mbuf->tso_segsz <<
1514                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1515
1516         return ctx_desc;
1517 }
1518
1519 uint16_t
1520 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1521 {
1522         struct i40e_tx_queue *txq;
1523         struct i40e_tx_entry *sw_ring;
1524         struct i40e_tx_entry *txe, *txn;
1525         volatile struct i40e_tx_desc *txd;
1526         volatile struct i40e_tx_desc *txr;
1527         struct rte_mbuf *tx_pkt;
1528         struct rte_mbuf *m_seg;
1529         uint32_t cd_tunneling_params;
1530         uint16_t tx_id;
1531         uint16_t nb_tx;
1532         uint32_t td_cmd;
1533         uint32_t td_offset;
1534         uint32_t tx_flags;
1535         uint32_t td_tag;
1536         uint64_t ol_flags;
1537         uint16_t nb_used;
1538         uint16_t nb_ctx;
1539         uint16_t tx_last;
1540         uint16_t slen;
1541         uint64_t buf_dma_addr;
1542         union i40e_tx_offload tx_offload = {0};
1543
1544         txq = tx_queue;
1545         sw_ring = txq->sw_ring;
1546         txr = txq->tx_ring;
1547         tx_id = txq->tx_tail;
1548         txe = &sw_ring[tx_id];
1549
1550         /* Check if the descriptor ring needs to be cleaned. */
1551         if (txq->nb_tx_free < txq->tx_free_thresh)
1552                 i40e_xmit_cleanup(txq);
1553
1554         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1555                 td_cmd = 0;
1556                 td_tag = 0;
1557                 td_offset = 0;
1558                 tx_flags = 0;
1559
1560                 tx_pkt = *tx_pkts++;
1561                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1562
1563                 ol_flags = tx_pkt->ol_flags;
1564                 tx_offload.l2_len = tx_pkt->l2_len;
1565                 tx_offload.l3_len = tx_pkt->l3_len;
1566                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1567                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1568                 tx_offload.l4_len = tx_pkt->l4_len;
1569                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1570
1571                 /* Calculate the number of context descriptors needed. */
1572                 nb_ctx = i40e_calc_context_desc(ol_flags);
1573
1574                 /**
1575                  * The number of descriptors that must be allocated for
1576                  * a packet equals to the number of the segments of that
1577                  * packet plus 1 context descriptor if needed.
1578                  */
1579                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1580                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1581
1582                 /* Circular ring */
1583                 if (tx_last >= txq->nb_tx_desc)
1584                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1585
1586                 if (nb_used > txq->nb_tx_free) {
1587                         if (i40e_xmit_cleanup(txq) != 0) {
1588                                 if (nb_tx == 0)
1589                                         return 0;
1590                                 goto end_of_tx;
1591                         }
1592                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1593                                 while (nb_used > txq->nb_tx_free) {
1594                                         if (i40e_xmit_cleanup(txq) != 0) {
1595                                                 if (nb_tx == 0)
1596                                                         return 0;
1597                                                 goto end_of_tx;
1598                                         }
1599                                 }
1600                         }
1601                 }
1602
1603                 /* Descriptor based VLAN insertion */
1604                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1605                         tx_flags |= tx_pkt->vlan_tci <<
1606                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1607                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1608                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1609                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1610                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1611                 }
1612
1613                 /* Always enable CRC offload insertion */
1614                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1615
1616                 /* Enable checksum offloading */
1617                 cd_tunneling_params = 0;
1618                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1619                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1620                                 tx_offload, &cd_tunneling_params);
1621                 }
1622
1623                 if (nb_ctx) {
1624                         /* Setup TX context descriptor if required */
1625                         volatile struct i40e_tx_context_desc *ctx_txd =
1626                                 (volatile struct i40e_tx_context_desc *)\
1627                                                         &txr[tx_id];
1628                         uint16_t cd_l2tag2 = 0;
1629                         uint64_t cd_type_cmd_tso_mss =
1630                                 I40E_TX_DESC_DTYPE_CONTEXT;
1631
1632                         txn = &sw_ring[txe->next_id];
1633                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1634                         if (txe->mbuf != NULL) {
1635                                 rte_pktmbuf_free_seg(txe->mbuf);
1636                                 txe->mbuf = NULL;
1637                         }
1638
1639                         /* TSO enabled means no timestamp */
1640                         if (ol_flags & PKT_TX_TCP_SEG)
1641                                 cd_type_cmd_tso_mss |=
1642                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1643                         else {
1644 #ifdef RTE_LIBRTE_IEEE1588
1645                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1646                                         cd_type_cmd_tso_mss |=
1647                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1648                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1649 #endif
1650                         }
1651
1652                         ctx_txd->tunneling_params =
1653                                 rte_cpu_to_le_32(cd_tunneling_params);
1654                         if (ol_flags & PKT_TX_QINQ_PKT) {
1655                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1656                                 cd_type_cmd_tso_mss |=
1657                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1658                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1659                         }
1660                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1661                         ctx_txd->type_cmd_tso_mss =
1662                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1663
1664                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1665                                 "tunneling_params: %#x;\n"
1666                                 "l2tag2: %#hx;\n"
1667                                 "rsvd: %#hx;\n"
1668                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1669                                 tx_pkt, tx_id,
1670                                 ctx_txd->tunneling_params,
1671                                 ctx_txd->l2tag2,
1672                                 ctx_txd->rsvd,
1673                                 ctx_txd->type_cmd_tso_mss);
1674
1675                         txe->last_id = tx_last;
1676                         tx_id = txe->next_id;
1677                         txe = txn;
1678                 }
1679
1680                 m_seg = tx_pkt;
1681                 do {
1682                         txd = &txr[tx_id];
1683                         txn = &sw_ring[txe->next_id];
1684
1685                         if (txe->mbuf)
1686                                 rte_pktmbuf_free_seg(txe->mbuf);
1687                         txe->mbuf = m_seg;
1688
1689                         /* Setup TX Descriptor */
1690                         slen = m_seg->data_len;
1691                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1692
1693                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1694                                 "buf_dma_addr: %#"PRIx64";\n"
1695                                 "td_cmd: %#x;\n"
1696                                 "td_offset: %#x;\n"
1697                                 "td_len: %u;\n"
1698                                 "td_tag: %#x;\n",
1699                                 tx_pkt, tx_id, buf_dma_addr,
1700                                 td_cmd, td_offset, slen, td_tag);
1701
1702                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1703                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1704                                                 td_offset, slen, td_tag);
1705                         txe->last_id = tx_last;
1706                         tx_id = txe->next_id;
1707                         txe = txn;
1708                         m_seg = m_seg->next;
1709                 } while (m_seg != NULL);
1710
1711                 /* The last packet data descriptor needs End Of Packet (EOP) */
1712                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1713                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1714                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1715
1716                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1717                         PMD_TX_FREE_LOG(DEBUG,
1718                                         "Setting RS bit on TXD id="
1719                                         "%4u (port=%d queue=%d)",
1720                                         tx_last, txq->port_id, txq->queue_id);
1721
1722                         td_cmd |= I40E_TX_DESC_CMD_RS;
1723
1724                         /* Update txq RS bit counters */
1725                         txq->nb_tx_used = 0;
1726                 }
1727
1728                 txd->cmd_type_offset_bsz |=
1729                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1730                                         I40E_TXD_QW1_CMD_SHIFT);
1731         }
1732
1733 end_of_tx:
1734         rte_wmb();
1735
1736         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1737                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1738                    (unsigned) tx_id, (unsigned) nb_tx);
1739
1740         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1741         txq->tx_tail = tx_id;
1742
1743         return nb_tx;
1744 }
1745
1746 static inline int __attribute__((always_inline))
1747 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1748 {
1749         struct i40e_tx_entry *txep;
1750         uint16_t i;
1751
1752         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1753                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1754                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1755                 return 0;
1756
1757         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1758
1759         for (i = 0; i < txq->tx_rs_thresh; i++)
1760                 rte_prefetch0((txep + i)->mbuf);
1761
1762         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1763                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1764                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1765                         txep->mbuf = NULL;
1766                 }
1767         } else {
1768                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1769                         rte_pktmbuf_free_seg(txep->mbuf);
1770                         txep->mbuf = NULL;
1771                 }
1772         }
1773
1774         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1775         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1776         if (txq->tx_next_dd >= txq->nb_tx_desc)
1777                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1778
1779         return txq->tx_rs_thresh;
1780 }
1781
1782 /* Populate 4 descriptors with data from 4 mbufs */
1783 static inline void
1784 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1785 {
1786         uint64_t dma_addr;
1787         uint32_t i;
1788
1789         for (i = 0; i < 4; i++, txdp++, pkts++) {
1790                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1791                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1792                 txdp->cmd_type_offset_bsz =
1793                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1794                                         (*pkts)->data_len, 0);
1795         }
1796 }
1797
1798 /* Populate 1 descriptor with data from 1 mbuf */
1799 static inline void
1800 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1801 {
1802         uint64_t dma_addr;
1803
1804         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1805         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1806         txdp->cmd_type_offset_bsz =
1807                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1808                                 (*pkts)->data_len, 0);
1809 }
1810
1811 /* Fill hardware descriptor ring with mbuf data */
1812 static inline void
1813 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1814                      struct rte_mbuf **pkts,
1815                      uint16_t nb_pkts)
1816 {
1817         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1818         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1819         const int N_PER_LOOP = 4;
1820         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1821         int mainpart, leftover;
1822         int i, j;
1823
1824         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1825         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1826         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1827                 for (j = 0; j < N_PER_LOOP; ++j) {
1828                         (txep + i + j)->mbuf = *(pkts + i + j);
1829                 }
1830                 tx4(txdp + i, pkts + i);
1831         }
1832         if (unlikely(leftover > 0)) {
1833                 for (i = 0; i < leftover; ++i) {
1834                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1835                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1836                 }
1837         }
1838 }
1839
1840 static inline uint16_t
1841 tx_xmit_pkts(struct i40e_tx_queue *txq,
1842              struct rte_mbuf **tx_pkts,
1843              uint16_t nb_pkts)
1844 {
1845         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1846         uint16_t n = 0;
1847
1848         /**
1849          * Begin scanning the H/W ring for done descriptors when the number
1850          * of available descriptors drops below tx_free_thresh. For each done
1851          * descriptor, free the associated buffer.
1852          */
1853         if (txq->nb_tx_free < txq->tx_free_thresh)
1854                 i40e_tx_free_bufs(txq);
1855
1856         /* Use available descriptor only */
1857         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1858         if (unlikely(!nb_pkts))
1859                 return 0;
1860
1861         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1862         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1863                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1864                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1865                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1866                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1867                                                 I40E_TXD_QW1_CMD_SHIFT);
1868                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1869                 txq->tx_tail = 0;
1870         }
1871
1872         /* Fill hardware descriptor ring with mbuf data */
1873         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1874         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1875
1876         /* Determin if RS bit needs to be set */
1877         if (txq->tx_tail > txq->tx_next_rs) {
1878                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1879                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1880                                                 I40E_TXD_QW1_CMD_SHIFT);
1881                 txq->tx_next_rs =
1882                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1883                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1884                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1885         }
1886
1887         if (txq->tx_tail >= txq->nb_tx_desc)
1888                 txq->tx_tail = 0;
1889
1890         /* Update the tx tail register */
1891         rte_wmb();
1892         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1893
1894         return nb_pkts;
1895 }
1896
1897 static uint16_t
1898 i40e_xmit_pkts_simple(void *tx_queue,
1899                       struct rte_mbuf **tx_pkts,
1900                       uint16_t nb_pkts)
1901 {
1902         uint16_t nb_tx = 0;
1903
1904         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1905                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1906                                                 tx_pkts, nb_pkts);
1907
1908         while (nb_pkts) {
1909                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1910                                                 I40E_TX_MAX_BURST);
1911
1912                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1913                                                 &tx_pkts[nb_tx], num);
1914                 nb_tx = (uint16_t)(nb_tx + ret);
1915                 nb_pkts = (uint16_t)(nb_pkts - ret);
1916                 if (ret < num)
1917                         break;
1918         }
1919
1920         return nb_tx;
1921 }
1922
1923 /*
1924  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1925  * application used, which assume having sequential ones. But from driver's
1926  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1927  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1928  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1929  * use queue_idx from 0 to 95 to access queues, while real queue would be
1930  * different. This function will do a queue mapping to find VSI the queue
1931  * belongs to.
1932  */
1933 static struct i40e_vsi*
1934 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1935 {
1936         /* the queue in MAIN VSI range */
1937         if (queue_idx < pf->main_vsi->nb_qps)
1938                 return pf->main_vsi;
1939
1940         queue_idx -= pf->main_vsi->nb_qps;
1941
1942         /* queue_idx is greater than VMDQ VSIs range */
1943         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1944                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1945                 return NULL;
1946         }
1947
1948         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1949 }
1950
1951 static uint16_t
1952 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1953 {
1954         /* the queue in MAIN VSI range */
1955         if (queue_idx < pf->main_vsi->nb_qps)
1956                 return queue_idx;
1957
1958         /* It's VMDQ queues */
1959         queue_idx -= pf->main_vsi->nb_qps;
1960
1961         if (pf->nb_cfg_vmdq_vsi)
1962                 return queue_idx % pf->vmdq_nb_qps;
1963         else {
1964                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1965                 return (uint16_t)(-1);
1966         }
1967 }
1968
1969 int
1970 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1971 {
1972         struct i40e_rx_queue *rxq;
1973         int err = -1;
1974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975
1976         PMD_INIT_FUNC_TRACE();
1977
1978         if (rx_queue_id < dev->data->nb_rx_queues) {
1979                 rxq = dev->data->rx_queues[rx_queue_id];
1980
1981                 err = i40e_alloc_rx_queue_mbufs(rxq);
1982                 if (err) {
1983                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1984                         return err;
1985                 }
1986
1987                 rte_wmb();
1988
1989                 /* Init the RX tail regieter. */
1990                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1991
1992                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1993
1994                 if (err) {
1995                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1996                                     rx_queue_id);
1997
1998                         i40e_rx_queue_release_mbufs(rxq);
1999                         i40e_reset_rx_queue(rxq);
2000                 } else
2001                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2002         }
2003
2004         return err;
2005 }
2006
2007 int
2008 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2009 {
2010         struct i40e_rx_queue *rxq;
2011         int err;
2012         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013
2014         if (rx_queue_id < dev->data->nb_rx_queues) {
2015                 rxq = dev->data->rx_queues[rx_queue_id];
2016
2017                 /*
2018                 * rx_queue_id is queue id aplication refers to, while
2019                 * rxq->reg_idx is the real queue index.
2020                 */
2021                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2022
2023                 if (err) {
2024                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2025                                     rx_queue_id);
2026                         return err;
2027                 }
2028                 i40e_rx_queue_release_mbufs(rxq);
2029                 i40e_reset_rx_queue(rxq);
2030                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2031         }
2032
2033         return 0;
2034 }
2035
2036 int
2037 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2038 {
2039         int err = -1;
2040         struct i40e_tx_queue *txq;
2041         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042
2043         PMD_INIT_FUNC_TRACE();
2044
2045         if (tx_queue_id < dev->data->nb_tx_queues) {
2046                 txq = dev->data->tx_queues[tx_queue_id];
2047
2048                 /*
2049                 * tx_queue_id is queue id aplication refers to, while
2050                 * rxq->reg_idx is the real queue index.
2051                 */
2052                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2053                 if (err)
2054                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2055                                     tx_queue_id);
2056                 else
2057                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2058         }
2059
2060         return err;
2061 }
2062
2063 int
2064 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2065 {
2066         struct i40e_tx_queue *txq;
2067         int err;
2068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069
2070         if (tx_queue_id < dev->data->nb_tx_queues) {
2071                 txq = dev->data->tx_queues[tx_queue_id];
2072
2073                 /*
2074                 * tx_queue_id is queue id aplication refers to, while
2075                 * txq->reg_idx is the real queue index.
2076                 */
2077                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2078
2079                 if (err) {
2080                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2081                                     tx_queue_id);
2082                         return err;
2083                 }
2084
2085                 i40e_tx_queue_release_mbufs(txq);
2086                 i40e_reset_tx_queue(txq);
2087                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2088         }
2089
2090         return 0;
2091 }
2092
2093 const uint32_t *
2094 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2095 {
2096         static const uint32_t ptypes[] = {
2097                 /* refers to i40e_rxd_pkt_type_mapping() */
2098                 RTE_PTYPE_L2_ETHER,
2099                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2100                 RTE_PTYPE_L2_ETHER_LLDP,
2101                 RTE_PTYPE_L2_ETHER_ARP,
2102                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2103                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2104                 RTE_PTYPE_L4_FRAG,
2105                 RTE_PTYPE_L4_ICMP,
2106                 RTE_PTYPE_L4_NONFRAG,
2107                 RTE_PTYPE_L4_SCTP,
2108                 RTE_PTYPE_L4_TCP,
2109                 RTE_PTYPE_L4_UDP,
2110                 RTE_PTYPE_TUNNEL_GRENAT,
2111                 RTE_PTYPE_TUNNEL_IP,
2112                 RTE_PTYPE_INNER_L2_ETHER,
2113                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2114                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2115                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2116                 RTE_PTYPE_INNER_L4_FRAG,
2117                 RTE_PTYPE_INNER_L4_ICMP,
2118                 RTE_PTYPE_INNER_L4_NONFRAG,
2119                 RTE_PTYPE_INNER_L4_SCTP,
2120                 RTE_PTYPE_INNER_L4_TCP,
2121                 RTE_PTYPE_INNER_L4_UDP,
2122                 RTE_PTYPE_UNKNOWN
2123         };
2124
2125         if (dev->rx_pkt_burst == i40e_recv_pkts ||
2126 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2127             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2128 #endif
2129             dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2130                 return ptypes;
2131         return NULL;
2132 }
2133
2134 int
2135 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2136                         uint16_t queue_idx,
2137                         uint16_t nb_desc,
2138                         unsigned int socket_id,
2139                         const struct rte_eth_rxconf *rx_conf,
2140                         struct rte_mempool *mp)
2141 {
2142         struct i40e_vsi *vsi;
2143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2145         struct i40e_adapter *ad =
2146                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2147         struct i40e_rx_queue *rxq;
2148         const struct rte_memzone *rz;
2149         uint32_t ring_size;
2150         uint16_t len, i;
2151         uint16_t base, bsf, tc_mapping;
2152         int use_def_burst_func = 1;
2153
2154         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2155                 struct i40e_vf *vf =
2156                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2157                 vsi = &vf->vsi;
2158         } else
2159                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2160
2161         if (vsi == NULL) {
2162                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2163                             "index exceeds the maximum");
2164                 return I40E_ERR_PARAM;
2165         }
2166         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2167                         (nb_desc > I40E_MAX_RING_DESC) ||
2168                         (nb_desc < I40E_MIN_RING_DESC)) {
2169                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2170                             "invalid", nb_desc);
2171                 return I40E_ERR_PARAM;
2172         }
2173
2174         /* Free memory if needed */
2175         if (dev->data->rx_queues[queue_idx]) {
2176                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2177                 dev->data->rx_queues[queue_idx] = NULL;
2178         }
2179
2180         /* Allocate the rx queue data structure */
2181         rxq = rte_zmalloc_socket("i40e rx queue",
2182                                  sizeof(struct i40e_rx_queue),
2183                                  RTE_CACHE_LINE_SIZE,
2184                                  socket_id);
2185         if (!rxq) {
2186                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2187                             "rx queue data structure");
2188                 return -ENOMEM;
2189         }
2190         rxq->mp = mp;
2191         rxq->nb_rx_desc = nb_desc;
2192         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2193         rxq->queue_id = queue_idx;
2194         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2195                 rxq->reg_idx = queue_idx;
2196         else /* PF device */
2197                 rxq->reg_idx = vsi->base_queue +
2198                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2199
2200         rxq->port_id = dev->data->port_id;
2201         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2202                                                         0 : ETHER_CRC_LEN);
2203         rxq->drop_en = rx_conf->rx_drop_en;
2204         rxq->vsi = vsi;
2205         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2206
2207         /* Allocate the maximun number of RX ring hardware descriptor. */
2208         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2209         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2210         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2211                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2212         if (!rz) {
2213                 i40e_dev_rx_queue_release(rxq);
2214                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2215                 return -ENOMEM;
2216         }
2217
2218         /* Zero all the descriptors in the ring. */
2219         memset(rz->addr, 0, ring_size);
2220
2221         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2222         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2223
2224 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2225         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2226 #else
2227         len = nb_desc;
2228 #endif
2229
2230         /* Allocate the software ring. */
2231         rxq->sw_ring =
2232                 rte_zmalloc_socket("i40e rx sw ring",
2233                                    sizeof(struct i40e_rx_entry) * len,
2234                                    RTE_CACHE_LINE_SIZE,
2235                                    socket_id);
2236         if (!rxq->sw_ring) {
2237                 i40e_dev_rx_queue_release(rxq);
2238                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2239                 return -ENOMEM;
2240         }
2241
2242         i40e_reset_rx_queue(rxq);
2243         rxq->q_set = TRUE;
2244         dev->data->rx_queues[queue_idx] = rxq;
2245
2246         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2247
2248         if (!use_def_burst_func) {
2249 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2250                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2251                              "satisfied. Rx Burst Bulk Alloc function will be "
2252                              "used on port=%d, queue=%d.",
2253                              rxq->port_id, rxq->queue_id);
2254 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2255         } else {
2256                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2257                              "not satisfied, Scattered Rx is requested, "
2258                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2259                              "not enabled on port=%d, queue=%d.",
2260                              rxq->port_id, rxq->queue_id);
2261                 ad->rx_bulk_alloc_allowed = false;
2262         }
2263
2264         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2265                 if (!(vsi->enabled_tc & (1 << i)))
2266                         continue;
2267                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2268                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2269                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2270                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2271                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2272
2273                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2274                         rxq->dcb_tc = i;
2275         }
2276
2277         return 0;
2278 }
2279
2280 void
2281 i40e_dev_rx_queue_release(void *rxq)
2282 {
2283         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2284
2285         if (!q) {
2286                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2287                 return;
2288         }
2289
2290         i40e_rx_queue_release_mbufs(q);
2291         rte_free(q->sw_ring);
2292         rte_free(q);
2293 }
2294
2295 uint32_t
2296 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2297 {
2298 #define I40E_RXQ_SCAN_INTERVAL 4
2299         volatile union i40e_rx_desc *rxdp;
2300         struct i40e_rx_queue *rxq;
2301         uint16_t desc = 0;
2302
2303         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2304                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2305                 return 0;
2306         }
2307
2308         rxq = dev->data->rx_queues[rx_queue_id];
2309         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2310         while ((desc < rxq->nb_rx_desc) &&
2311                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2312                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2313                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2314                 /**
2315                  * Check the DD bit of a rx descriptor of each 4 in a group,
2316                  * to avoid checking too frequently and downgrading performance
2317                  * too much.
2318                  */
2319                 desc += I40E_RXQ_SCAN_INTERVAL;
2320                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2321                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2322                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2323                                         desc - rxq->nb_rx_desc]);
2324         }
2325
2326         return desc;
2327 }
2328
2329 int
2330 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2331 {
2332         volatile union i40e_rx_desc *rxdp;
2333         struct i40e_rx_queue *rxq = rx_queue;
2334         uint16_t desc;
2335         int ret;
2336
2337         if (unlikely(offset >= rxq->nb_rx_desc)) {
2338                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2339                 return 0;
2340         }
2341
2342         desc = rxq->rx_tail + offset;
2343         if (desc >= rxq->nb_rx_desc)
2344                 desc -= rxq->nb_rx_desc;
2345
2346         rxdp = &(rxq->rx_ring[desc]);
2347
2348         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2349                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2350                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2351
2352         return ret;
2353 }
2354
2355 int
2356 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2357                         uint16_t queue_idx,
2358                         uint16_t nb_desc,
2359                         unsigned int socket_id,
2360                         const struct rte_eth_txconf *tx_conf)
2361 {
2362         struct i40e_vsi *vsi;
2363         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2365         struct i40e_tx_queue *txq;
2366         const struct rte_memzone *tz;
2367         uint32_t ring_size;
2368         uint16_t tx_rs_thresh, tx_free_thresh;
2369         uint16_t i, base, bsf, tc_mapping;
2370
2371         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2372                 struct i40e_vf *vf =
2373                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2374                 vsi = &vf->vsi;
2375         } else
2376                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2377
2378         if (vsi == NULL) {
2379                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2380                             "exceeds the maximum", queue_idx);
2381                 return I40E_ERR_PARAM;
2382         }
2383
2384         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2385                         (nb_desc > I40E_MAX_RING_DESC) ||
2386                         (nb_desc < I40E_MIN_RING_DESC)) {
2387                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2388                             "invalid", nb_desc);
2389                 return I40E_ERR_PARAM;
2390         }
2391
2392         /**
2393          * The following two parameters control the setting of the RS bit on
2394          * transmit descriptors. TX descriptors will have their RS bit set
2395          * after txq->tx_rs_thresh descriptors have been used. The TX
2396          * descriptor ring will be cleaned after txq->tx_free_thresh
2397          * descriptors are used or if the number of descriptors required to
2398          * transmit a packet is greater than the number of free TX descriptors.
2399          *
2400          * The following constraints must be satisfied:
2401          *  - tx_rs_thresh must be greater than 0.
2402          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2403          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2404          *  - tx_rs_thresh must be a divisor of the ring size.
2405          *  - tx_free_thresh must be greater than 0.
2406          *  - tx_free_thresh must be less than the size of the ring minus 3.
2407          *
2408          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2409          * race condition, hence the maximum threshold constraints. When set
2410          * to zero use default values.
2411          */
2412         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2413                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2414         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2415                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2416         if (tx_rs_thresh >= (nb_desc - 2)) {
2417                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2418                              "number of TX descriptors minus 2. "
2419                              "(tx_rs_thresh=%u port=%d queue=%d)",
2420                              (unsigned int)tx_rs_thresh,
2421                              (int)dev->data->port_id,
2422                              (int)queue_idx);
2423                 return I40E_ERR_PARAM;
2424         }
2425         if (tx_free_thresh >= (nb_desc - 3)) {
2426                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2427                              "tx_free_thresh must be less than the "
2428                              "number of TX descriptors minus 3. "
2429                              "(tx_free_thresh=%u port=%d queue=%d)",
2430                              (unsigned int)tx_free_thresh,
2431                              (int)dev->data->port_id,
2432                              (int)queue_idx);
2433                 return I40E_ERR_PARAM;
2434         }
2435         if (tx_rs_thresh > tx_free_thresh) {
2436                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2437                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2438                              " tx_rs_thresh=%u port=%d queue=%d)",
2439                              (unsigned int)tx_free_thresh,
2440                              (unsigned int)tx_rs_thresh,
2441                              (int)dev->data->port_id,
2442                              (int)queue_idx);
2443                 return I40E_ERR_PARAM;
2444         }
2445         if ((nb_desc % tx_rs_thresh) != 0) {
2446                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2447                              "number of TX descriptors. (tx_rs_thresh=%u"
2448                              " port=%d queue=%d)",
2449                              (unsigned int)tx_rs_thresh,
2450                              (int)dev->data->port_id,
2451                              (int)queue_idx);
2452                 return I40E_ERR_PARAM;
2453         }
2454         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2455                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2456                              "tx_rs_thresh is greater than 1. "
2457                              "(tx_rs_thresh=%u port=%d queue=%d)",
2458                              (unsigned int)tx_rs_thresh,
2459                              (int)dev->data->port_id,
2460                              (int)queue_idx);
2461                 return I40E_ERR_PARAM;
2462         }
2463
2464         /* Free memory if needed. */
2465         if (dev->data->tx_queues[queue_idx]) {
2466                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2467                 dev->data->tx_queues[queue_idx] = NULL;
2468         }
2469
2470         /* Allocate the TX queue data structure. */
2471         txq = rte_zmalloc_socket("i40e tx queue",
2472                                   sizeof(struct i40e_tx_queue),
2473                                   RTE_CACHE_LINE_SIZE,
2474                                   socket_id);
2475         if (!txq) {
2476                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2477                             "tx queue structure");
2478                 return -ENOMEM;
2479         }
2480
2481         /* Allocate TX hardware ring descriptors. */
2482         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2483         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2484         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2485                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2486         if (!tz) {
2487                 i40e_dev_tx_queue_release(txq);
2488                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2489                 return -ENOMEM;
2490         }
2491
2492         txq->nb_tx_desc = nb_desc;
2493         txq->tx_rs_thresh = tx_rs_thresh;
2494         txq->tx_free_thresh = tx_free_thresh;
2495         txq->pthresh = tx_conf->tx_thresh.pthresh;
2496         txq->hthresh = tx_conf->tx_thresh.hthresh;
2497         txq->wthresh = tx_conf->tx_thresh.wthresh;
2498         txq->queue_id = queue_idx;
2499         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2500                 txq->reg_idx = queue_idx;
2501         else /* PF device */
2502                 txq->reg_idx = vsi->base_queue +
2503                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2504
2505         txq->port_id = dev->data->port_id;
2506         txq->txq_flags = tx_conf->txq_flags;
2507         txq->vsi = vsi;
2508         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2509
2510         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2511         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2512
2513         /* Allocate software ring */
2514         txq->sw_ring =
2515                 rte_zmalloc_socket("i40e tx sw ring",
2516                                    sizeof(struct i40e_tx_entry) * nb_desc,
2517                                    RTE_CACHE_LINE_SIZE,
2518                                    socket_id);
2519         if (!txq->sw_ring) {
2520                 i40e_dev_tx_queue_release(txq);
2521                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2522                 return -ENOMEM;
2523         }
2524
2525         i40e_reset_tx_queue(txq);
2526         txq->q_set = TRUE;
2527         dev->data->tx_queues[queue_idx] = txq;
2528
2529         /* Use a simple TX queue without offloads or multi segs if possible */
2530         i40e_set_tx_function_flag(dev, txq);
2531
2532         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2533                 if (!(vsi->enabled_tc & (1 << i)))
2534                         continue;
2535                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2536                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2537                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2538                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2539                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2540
2541                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2542                         txq->dcb_tc = i;
2543         }
2544
2545         return 0;
2546 }
2547
2548 void
2549 i40e_dev_tx_queue_release(void *txq)
2550 {
2551         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2552
2553         if (!q) {
2554                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2555                 return;
2556         }
2557
2558         i40e_tx_queue_release_mbufs(q);
2559         rte_free(q->sw_ring);
2560         rte_free(q);
2561 }
2562
2563 const struct rte_memzone *
2564 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2565 {
2566         const struct rte_memzone *mz;
2567
2568         mz = rte_memzone_lookup(name);
2569         if (mz)
2570                 return mz;
2571
2572         if (rte_xen_dom0_supported())
2573                 mz = rte_memzone_reserve_bounded(name, len,
2574                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2575         else
2576                 mz = rte_memzone_reserve_aligned(name, len,
2577                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2578         return mz;
2579 }
2580
2581 void
2582 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2583 {
2584         uint16_t i;
2585
2586         /* SSE Vector driver has a different way of releasing mbufs. */
2587         if (rxq->rx_using_sse) {
2588                 i40e_rx_queue_release_mbufs_vec(rxq);
2589                 return;
2590         }
2591
2592         if (!rxq || !rxq->sw_ring) {
2593                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2594                 return;
2595         }
2596
2597         for (i = 0; i < rxq->nb_rx_desc; i++) {
2598                 if (rxq->sw_ring[i].mbuf) {
2599                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2600                         rxq->sw_ring[i].mbuf = NULL;
2601                 }
2602         }
2603 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2604         if (rxq->rx_nb_avail == 0)
2605                 return;
2606         for (i = 0; i < rxq->rx_nb_avail; i++) {
2607                 struct rte_mbuf *mbuf;
2608
2609                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2610                 rte_pktmbuf_free_seg(mbuf);
2611         }
2612         rxq->rx_nb_avail = 0;
2613 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2614 }
2615
2616 void
2617 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2618 {
2619         unsigned i;
2620         uint16_t len;
2621
2622         if (!rxq) {
2623                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2624                 return;
2625         }
2626
2627 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2628         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2629                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2630         else
2631 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2632                 len = rxq->nb_rx_desc;
2633
2634         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2635                 ((volatile char *)rxq->rx_ring)[i] = 0;
2636
2637 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2638         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2639         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2640                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2641
2642         rxq->rx_nb_avail = 0;
2643         rxq->rx_next_avail = 0;
2644         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2645 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2646         rxq->rx_tail = 0;
2647         rxq->nb_rx_hold = 0;
2648         rxq->pkt_first_seg = NULL;
2649         rxq->pkt_last_seg = NULL;
2650
2651         rxq->rxrearm_start = 0;
2652         rxq->rxrearm_nb = 0;
2653 }
2654
2655 void
2656 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2657 {
2658         uint16_t i;
2659
2660         if (!txq || !txq->sw_ring) {
2661                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2662                 return;
2663         }
2664
2665         for (i = 0; i < txq->nb_tx_desc; i++) {
2666                 if (txq->sw_ring[i].mbuf) {
2667                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2668                         txq->sw_ring[i].mbuf = NULL;
2669                 }
2670         }
2671 }
2672
2673 void
2674 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2675 {
2676         struct i40e_tx_entry *txe;
2677         uint16_t i, prev, size;
2678
2679         if (!txq) {
2680                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2681                 return;
2682         }
2683
2684         txe = txq->sw_ring;
2685         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2686         for (i = 0; i < size; i++)
2687                 ((volatile char *)txq->tx_ring)[i] = 0;
2688
2689         prev = (uint16_t)(txq->nb_tx_desc - 1);
2690         for (i = 0; i < txq->nb_tx_desc; i++) {
2691                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2692
2693                 txd->cmd_type_offset_bsz =
2694                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2695                 txe[i].mbuf =  NULL;
2696                 txe[i].last_id = i;
2697                 txe[prev].next_id = i;
2698                 prev = i;
2699         }
2700
2701         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2702         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2703
2704         txq->tx_tail = 0;
2705         txq->nb_tx_used = 0;
2706
2707         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2708         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2709 }
2710
2711 /* Init the TX queue in hardware */
2712 int
2713 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2714 {
2715         enum i40e_status_code err = I40E_SUCCESS;
2716         struct i40e_vsi *vsi = txq->vsi;
2717         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2718         uint16_t pf_q = txq->reg_idx;
2719         struct i40e_hmc_obj_txq tx_ctx;
2720         uint32_t qtx_ctl;
2721
2722         /* clear the context structure first */
2723         memset(&tx_ctx, 0, sizeof(tx_ctx));
2724         tx_ctx.new_context = 1;
2725         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2726         tx_ctx.qlen = txq->nb_tx_desc;
2727
2728 #ifdef RTE_LIBRTE_IEEE1588
2729         tx_ctx.timesync_ena = 1;
2730 #endif
2731         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2732         if (vsi->type == I40E_VSI_FDIR)
2733                 tx_ctx.fd_ena = TRUE;
2734
2735         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2736         if (err != I40E_SUCCESS) {
2737                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2738                 return err;
2739         }
2740
2741         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2742         if (err != I40E_SUCCESS) {
2743                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2744                 return err;
2745         }
2746
2747         /* Now associate this queue with this PCI function */
2748         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2749         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2750                                         I40E_QTX_CTL_PF_INDX_MASK);
2751         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2752         I40E_WRITE_FLUSH(hw);
2753
2754         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2755
2756         return err;
2757 }
2758
2759 int
2760 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2761 {
2762         struct i40e_rx_entry *rxe = rxq->sw_ring;
2763         uint64_t dma_addr;
2764         uint16_t i;
2765
2766         for (i = 0; i < rxq->nb_rx_desc; i++) {
2767                 volatile union i40e_rx_desc *rxd;
2768                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2769
2770                 if (unlikely(!mbuf)) {
2771                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2772                         return -ENOMEM;
2773                 }
2774
2775                 rte_mbuf_refcnt_set(mbuf, 1);
2776                 mbuf->next = NULL;
2777                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2778                 mbuf->nb_segs = 1;
2779                 mbuf->port = rxq->port_id;
2780
2781                 dma_addr =
2782                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2783
2784                 rxd = &rxq->rx_ring[i];
2785                 rxd->read.pkt_addr = dma_addr;
2786                 rxd->read.hdr_addr = 0;
2787 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2788                 rxd->read.rsvd1 = 0;
2789                 rxd->read.rsvd2 = 0;
2790 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2791
2792                 rxe[i].mbuf = mbuf;
2793         }
2794
2795         return 0;
2796 }
2797
2798 /*
2799  * Calculate the buffer length, and check the jumbo frame
2800  * and maximum packet length.
2801  */
2802 static int
2803 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2804 {
2805         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2806         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2807         struct rte_eth_dev_data *data = pf->dev_data;
2808         uint16_t buf_size, len;
2809
2810         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2811                 RTE_PKTMBUF_HEADROOM);
2812
2813         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2814                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2815         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2816                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2817                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2818                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2819                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2820                 rxq->hs_mode = i40e_header_split_enabled;
2821                 break;
2822         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2823         default:
2824                 rxq->rx_hdr_len = 0;
2825                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2826                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2827                 rxq->hs_mode = i40e_header_split_none;
2828                 break;
2829         }
2830
2831         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2832         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2833         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2834                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2835                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2836                         PMD_DRV_LOG(ERR, "maximum packet length must "
2837                                     "be larger than %u and smaller than %u,"
2838                                     "as jumbo frame is enabled",
2839                                     (uint32_t)ETHER_MAX_LEN,
2840                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2841                         return I40E_ERR_CONFIG;
2842                 }
2843         } else {
2844                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2845                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2846                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2847                                     "larger than %u and smaller than %u, "
2848                                     "as jumbo frame is disabled",
2849                                     (uint32_t)ETHER_MIN_LEN,
2850                                     (uint32_t)ETHER_MAX_LEN);
2851                         return I40E_ERR_CONFIG;
2852                 }
2853         }
2854
2855         return 0;
2856 }
2857
2858 /* Init the RX queue in hardware */
2859 int
2860 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2861 {
2862         int err = I40E_SUCCESS;
2863         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2864         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2865         uint16_t pf_q = rxq->reg_idx;
2866         uint16_t buf_size;
2867         struct i40e_hmc_obj_rxq rx_ctx;
2868
2869         err = i40e_rx_queue_config(rxq);
2870         if (err < 0) {
2871                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2872                 return err;
2873         }
2874
2875         /* Clear the context structure first */
2876         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2877         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2878         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2879
2880         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2881         rx_ctx.qlen = rxq->nb_rx_desc;
2882 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2883         rx_ctx.dsize = 1;
2884 #endif
2885         rx_ctx.dtype = rxq->hs_mode;
2886         if (rxq->hs_mode)
2887                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2888         else
2889                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2890         rx_ctx.rxmax = rxq->max_pkt_len;
2891         rx_ctx.tphrdesc_ena = 1;
2892         rx_ctx.tphwdesc_ena = 1;
2893         rx_ctx.tphdata_ena = 1;
2894         rx_ctx.tphhead_ena = 1;
2895         rx_ctx.lrxqthresh = 2;
2896         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2897         rx_ctx.l2tsel = 1;
2898         rx_ctx.showiv = 1;
2899         rx_ctx.prefena = 1;
2900
2901         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2902         if (err != I40E_SUCCESS) {
2903                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2904                 return err;
2905         }
2906         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2907         if (err != I40E_SUCCESS) {
2908                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2909                 return err;
2910         }
2911
2912         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2913
2914         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2915                 RTE_PKTMBUF_HEADROOM);
2916
2917         /* Check if scattered RX needs to be used. */
2918         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2919                 dev_data->scattered_rx = 1;
2920         }
2921
2922         /* Init the RX tail regieter. */
2923         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2924
2925         return 0;
2926 }
2927
2928 void
2929 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2930 {
2931         uint16_t i;
2932
2933         PMD_INIT_FUNC_TRACE();
2934
2935         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2936                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2937                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2938         }
2939
2940         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2941                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2942                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2943         }
2944 }
2945
2946 void
2947 i40e_dev_free_queues(struct rte_eth_dev *dev)
2948 {
2949         uint16_t i;
2950
2951         PMD_INIT_FUNC_TRACE();
2952
2953         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2954                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2955                 dev->data->rx_queues[i] = NULL;
2956         }
2957         dev->data->nb_rx_queues = 0;
2958
2959         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2960                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2961                 dev->data->tx_queues[i] = NULL;
2962         }
2963         dev->data->nb_tx_queues = 0;
2964 }
2965
2966 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2967 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2968
2969 enum i40e_status_code
2970 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2971 {
2972         struct i40e_tx_queue *txq;
2973         const struct rte_memzone *tz = NULL;
2974         uint32_t ring_size;
2975         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2976
2977         if (!pf) {
2978                 PMD_DRV_LOG(ERR, "PF is not available");
2979                 return I40E_ERR_BAD_PTR;
2980         }
2981
2982         /* Allocate the TX queue data structure. */
2983         txq = rte_zmalloc_socket("i40e fdir tx queue",
2984                                   sizeof(struct i40e_tx_queue),
2985                                   RTE_CACHE_LINE_SIZE,
2986                                   SOCKET_ID_ANY);
2987         if (!txq) {
2988                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2989                                         "tx queue structure.");
2990                 return I40E_ERR_NO_MEMORY;
2991         }
2992
2993         /* Allocate TX hardware ring descriptors. */
2994         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2995         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2996
2997         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2998                                       I40E_FDIR_QUEUE_ID, ring_size,
2999                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3000         if (!tz) {
3001                 i40e_dev_tx_queue_release(txq);
3002                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3003                 return I40E_ERR_NO_MEMORY;
3004         }
3005
3006         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3007         txq->queue_id = I40E_FDIR_QUEUE_ID;
3008         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3009         txq->vsi = pf->fdir.fdir_vsi;
3010
3011         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3012         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3013         /*
3014          * don't need to allocate software ring and reset for the fdir
3015          * program queue just set the queue has been configured.
3016          */
3017         txq->q_set = TRUE;
3018         pf->fdir.txq = txq;
3019
3020         return I40E_SUCCESS;
3021 }
3022
3023 enum i40e_status_code
3024 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3025 {
3026         struct i40e_rx_queue *rxq;
3027         const struct rte_memzone *rz = NULL;
3028         uint32_t ring_size;
3029         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3030
3031         if (!pf) {
3032                 PMD_DRV_LOG(ERR, "PF is not available");
3033                 return I40E_ERR_BAD_PTR;
3034         }
3035
3036         /* Allocate the RX queue data structure. */
3037         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3038                                   sizeof(struct i40e_rx_queue),
3039                                   RTE_CACHE_LINE_SIZE,
3040                                   SOCKET_ID_ANY);
3041         if (!rxq) {
3042                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3043                                         "rx queue structure.");
3044                 return I40E_ERR_NO_MEMORY;
3045         }
3046
3047         /* Allocate RX hardware ring descriptors. */
3048         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3049         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3050
3051         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3052                                       I40E_FDIR_QUEUE_ID, ring_size,
3053                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3054         if (!rz) {
3055                 i40e_dev_rx_queue_release(rxq);
3056                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3057                 return I40E_ERR_NO_MEMORY;
3058         }
3059
3060         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3061         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3062         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3063         rxq->vsi = pf->fdir.fdir_vsi;
3064
3065         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3066         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3067
3068         /*
3069          * Don't need to allocate software ring and reset for the fdir
3070          * rx queue, just set the queue has been configured.
3071          */
3072         rxq->q_set = TRUE;
3073         pf->fdir.rxq = rxq;
3074
3075         return I40E_SUCCESS;
3076 }
3077
3078 void
3079 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3080         struct rte_eth_rxq_info *qinfo)
3081 {
3082         struct i40e_rx_queue *rxq;
3083
3084         rxq = dev->data->rx_queues[queue_id];
3085
3086         qinfo->mp = rxq->mp;
3087         qinfo->scattered_rx = dev->data->scattered_rx;
3088         qinfo->nb_desc = rxq->nb_rx_desc;
3089
3090         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3091         qinfo->conf.rx_drop_en = rxq->drop_en;
3092         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3093 }
3094
3095 void
3096 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3097         struct rte_eth_txq_info *qinfo)
3098 {
3099         struct i40e_tx_queue *txq;
3100
3101         txq = dev->data->tx_queues[queue_id];
3102
3103         qinfo->nb_desc = txq->nb_tx_desc;
3104
3105         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3106         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3107         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3108
3109         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3110         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3111         qinfo->conf.txq_flags = txq->txq_flags;
3112         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3113 }
3114
3115 void __attribute__((cold))
3116 i40e_set_rx_function(struct rte_eth_dev *dev)
3117 {
3118         struct i40e_adapter *ad =
3119                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3120         uint16_t rx_using_sse, i;
3121         /* In order to allow Vector Rx there are a few configuration
3122          * conditions to be met and Rx Bulk Allocation should be allowed.
3123          */
3124         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3125                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3126                     !ad->rx_bulk_alloc_allowed) {
3127                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3128                                      " Vector Rx preconditions",
3129                                      dev->data->port_id);
3130
3131                         ad->rx_vec_allowed = false;
3132                 }
3133                 if (ad->rx_vec_allowed) {
3134                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3135                                 struct i40e_rx_queue *rxq =
3136                                         dev->data->rx_queues[i];
3137
3138                                 if (i40e_rxq_vec_setup(rxq)) {
3139                                         ad->rx_vec_allowed = false;
3140                                         break;
3141                                 }
3142                         }
3143                 }
3144         }
3145
3146         if (dev->data->scattered_rx) {
3147                 /* Set the non-LRO scattered callback: there are Vector and
3148                  * single allocation versions.
3149                  */
3150                 if (ad->rx_vec_allowed) {
3151                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3152                                             "callback (port=%d).",
3153                                      dev->data->port_id);
3154
3155                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3156                 } else {
3157                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3158                                            "allocation callback (port=%d).",
3159                                      dev->data->port_id);
3160                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3161                 }
3162         /* If parameters allow we are going to choose between the following
3163          * callbacks:
3164          *    - Vector
3165          *    - Bulk Allocation
3166          *    - Single buffer allocation (the simplest one)
3167          */
3168         } else if (ad->rx_vec_allowed) {
3169                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3170                                     "burst size no less than %d (port=%d).",
3171                              RTE_I40E_DESCS_PER_LOOP,
3172                              dev->data->port_id);
3173
3174                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3175         } else if (ad->rx_bulk_alloc_allowed) {
3176                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3177                                     "satisfied. Rx Burst Bulk Alloc function "
3178                                     "will be used on port=%d.",
3179                              dev->data->port_id);
3180
3181                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3182         } else {
3183                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3184                                     "satisfied, or Scattered Rx is requested "
3185                                     "(port=%d).",
3186                              dev->data->port_id);
3187
3188                 dev->rx_pkt_burst = i40e_recv_pkts;
3189         }
3190
3191         /* Propagate information about RX function choice through all queues. */
3192         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3193                 rx_using_sse =
3194                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3195                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3196
3197                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3198                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3199
3200                         rxq->rx_using_sse = rx_using_sse;
3201                 }
3202         }
3203 }
3204
3205 void __attribute__((cold))
3206 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3207 {
3208         struct i40e_adapter *ad =
3209                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3210
3211         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3212         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3213                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3214                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3215                         PMD_INIT_LOG(DEBUG, "Vector tx"
3216                                      " can be enabled on this txq.");
3217
3218                 } else {
3219                         ad->tx_vec_allowed = false;
3220                 }
3221         } else {
3222                 ad->tx_simple_allowed = false;
3223         }
3224 }
3225
3226 void __attribute__((cold))
3227 i40e_set_tx_function(struct rte_eth_dev *dev)
3228 {
3229         struct i40e_adapter *ad =
3230                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3231         int i;
3232
3233         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3234                 if (ad->tx_vec_allowed) {
3235                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3236                                 struct i40e_tx_queue *txq =
3237                                         dev->data->tx_queues[i];
3238
3239                                 if (i40e_txq_vec_setup(txq)) {
3240                                         ad->tx_vec_allowed = false;
3241                                         break;
3242                                 }
3243                         }
3244                 }
3245         }
3246
3247         if (ad->tx_simple_allowed) {
3248                 if (ad->tx_vec_allowed) {
3249                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3250                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3251                 } else {
3252                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3253                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3254                 }
3255         } else {
3256                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3257                 dev->tx_pkt_burst = i40e_xmit_pkts;
3258         }
3259 }
3260
3261 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3262 int __attribute__((weak))
3263 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3264 {
3265         return -1;
3266 }
3267
3268 uint16_t __attribute__((weak))
3269 i40e_recv_pkts_vec(
3270         void __rte_unused *rx_queue,
3271         struct rte_mbuf __rte_unused **rx_pkts,
3272         uint16_t __rte_unused nb_pkts)
3273 {
3274         return 0;
3275 }
3276
3277 uint16_t __attribute__((weak))
3278 i40e_recv_scattered_pkts_vec(
3279         void __rte_unused *rx_queue,
3280         struct rte_mbuf __rte_unused **rx_pkts,
3281         uint16_t __rte_unused nb_pkts)
3282 {
3283         return 0;
3284 }
3285
3286 int __attribute__((weak))
3287 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3288 {
3289         return -1;
3290 }
3291
3292 int __attribute__((weak))
3293 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3294 {
3295         return -1;
3296 }
3297
3298 void __attribute__((weak))
3299 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3300 {
3301         return;
3302 }
3303
3304 uint16_t __attribute__((weak))
3305 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3306                    struct rte_mbuf __rte_unused **tx_pkts,
3307                    uint16_t __rte_unused nb_pkts)
3308 {
3309         return 0;
3310 }