drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  82                                       struct rte_mbuf **tx_pkts,
  83                                       uint16_t nb_pkts);
  84
  85 static inline void
  86 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  87 {
  88         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  89                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_VLAN_PKT;
  91                 mb->vlan_tci =
  92                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  93                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  94                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  95         } else {
  96                 mb->vlan_tci = 0;
  97         }
  98 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  99         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 100                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 101                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 102                 mb->vlan_tci_outer = mb->vlan_tci;
 103                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 104                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 105                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 107         } else {
 108                 mb->vlan_tci_outer = 0;
 109         }
 110 #endif
 111         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 112                    mb->vlan_tci, mb->vlan_tci_outer);
 113 }
 114
 115 /* Translate the rx descriptor status to pkt flags */
 116 static inline uint64_t
 117 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 118 {
 119         uint64_t flags;
 120
 121         /* Check if RSS_HASH */
 122         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 123                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 124                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 125
 126         /* Check if FDIR Match */
 127         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 128                                                         PKT_RX_FDIR : 0);
 129
 130         return flags;
 131 }
 132
 133 static inline uint64_t
 134 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 135 {
 136         uint64_t flags = 0;
 137         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 138
 139 #define I40E_RX_ERR_BITS 0x3f
 140         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 141                 return flags;
 142         /* If RXE bit set, all other status bits are meaningless */
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 144                 flags |= PKT_RX_MAC_ERR;
 145                 return flags;
 146         }
 147
 148         /* If RECIPE bit set, all other status indications should be ignored */
 149         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 150                 flags |= PKT_RX_RECIP_ERR;
 151                 return flags;
 152         }
 153         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 154                 flags |= PKT_RX_HBUF_OVERFLOW;
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 156                 flags |= PKT_RX_IP_CKSUM_BAD;
 157         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 158                 flags |= PKT_RX_L4_CKSUM_BAD;
 159         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 160                 flags |= PKT_RX_EIP_CKSUM_BAD;
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 162                 flags |= PKT_RX_OVERSIZE;
 163
 164         return flags;
 165 }
 166
 167 /* Function to check and set the ieee1588 timesync index and get the
 168  * appropriate flags.
 169  */
 170 #ifdef RTE_LIBRTE_IEEE1588
 171 static inline uint64_t
 172 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 173 {
 174         uint64_t pkt_flags = 0;
 175         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 176                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 177                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 178
 179         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 180                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 181                 pkt_flags = PKT_RX_IEEE1588_PTP;
 182         if (tsyn & 0x04) {
 183                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 184                 mb->timesync = tsyn & 0x03;
 185         }
 186
 187         return pkt_flags;
 188 }
 189 #endif
 190
 191 /* For each value it means, datasheet of hardware can tell more details
 192  *
 193  * @note: fix i40e_dev_supported_ptypes_get() if any change here.
 194  */
 195 static inline uint32_t
 196 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 197 {
 198         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 199                 /* L2 types */
 200                 /* [0] reserved */
 201                 [1] = RTE_PTYPE_L2_ETHER,
 202                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 203                 /* [3] - [5] reserved */
 204                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 205                 /* [7] - [10] reserved */
 206                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 207                 /* [12] - [21] reserved */
 208
 209                 /* Non tunneled IPv4 */
 210                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                         RTE_PTYPE_L4_FRAG,
 212                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 213                         RTE_PTYPE_L4_NONFRAG,
 214                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 215                         RTE_PTYPE_L4_UDP,
 216                 /* [25] reserved */
 217                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 218                         RTE_PTYPE_L4_TCP,
 219                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 220                         RTE_PTYPE_L4_SCTP,
 221                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 222                         RTE_PTYPE_L4_ICMP,
 223
 224                 /* IPv4 --> IPv4 */
 225                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 226                         RTE_PTYPE_TUNNEL_IP |
 227                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 228                         RTE_PTYPE_INNER_L4_FRAG,
 229                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 230                         RTE_PTYPE_TUNNEL_IP |
 231                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 232                         RTE_PTYPE_INNER_L4_NONFRAG,
 233                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 234                         RTE_PTYPE_TUNNEL_IP |
 235                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 236                         RTE_PTYPE_INNER_L4_UDP,
 237                 /* [32] reserved */
 238                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 239                         RTE_PTYPE_TUNNEL_IP |
 240                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 241                         RTE_PTYPE_INNER_L4_TCP,
 242                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 243                         RTE_PTYPE_TUNNEL_IP |
 244                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 245                         RTE_PTYPE_INNER_L4_SCTP,
 246                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 247                         RTE_PTYPE_TUNNEL_IP |
 248                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 249                         RTE_PTYPE_INNER_L4_ICMP,
 250
 251                 /* IPv4 --> IPv6 */
 252                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 253                         RTE_PTYPE_TUNNEL_IP |
 254                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 255                         RTE_PTYPE_INNER_L4_FRAG,
 256                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 257                         RTE_PTYPE_TUNNEL_IP |
 258                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 259                         RTE_PTYPE_INNER_L4_NONFRAG,
 260                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 261                         RTE_PTYPE_TUNNEL_IP |
 262                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 263                         RTE_PTYPE_INNER_L4_UDP,
 264                 /* [39] reserved */
 265                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 266                         RTE_PTYPE_TUNNEL_IP |
 267                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 268                         RTE_PTYPE_INNER_L4_TCP,
 269                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 270                         RTE_PTYPE_TUNNEL_IP |
 271                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 272                         RTE_PTYPE_INNER_L4_SCTP,
 273                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 274                         RTE_PTYPE_TUNNEL_IP |
 275                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 276                         RTE_PTYPE_INNER_L4_ICMP,
 277
 278                 /* IPv4 --> GRE/Teredo/VXLAN */
 279                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 280                         RTE_PTYPE_TUNNEL_GRENAT,
 281
 282                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 283                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 284                         RTE_PTYPE_TUNNEL_GRENAT |
 285                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 286                         RTE_PTYPE_INNER_L4_FRAG,
 287                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 288                         RTE_PTYPE_TUNNEL_GRENAT |
 289                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 290                         RTE_PTYPE_INNER_L4_NONFRAG,
 291                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 292                         RTE_PTYPE_TUNNEL_GRENAT |
 293                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 294                         RTE_PTYPE_INNER_L4_UDP,
 295                 /* [47] reserved */
 296                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 297                         RTE_PTYPE_TUNNEL_GRENAT |
 298                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 299                         RTE_PTYPE_INNER_L4_TCP,
 300                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 301                         RTE_PTYPE_TUNNEL_GRENAT |
 302                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 303                         RTE_PTYPE_INNER_L4_SCTP,
 304                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 305                         RTE_PTYPE_TUNNEL_GRENAT |
 306                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 307                         RTE_PTYPE_INNER_L4_ICMP,
 308
 309                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 310                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 311                         RTE_PTYPE_TUNNEL_GRENAT |
 312                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 313                         RTE_PTYPE_INNER_L4_FRAG,
 314                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 315                         RTE_PTYPE_TUNNEL_GRENAT |
 316                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 317                         RTE_PTYPE_INNER_L4_NONFRAG,
 318                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 319                         RTE_PTYPE_TUNNEL_GRENAT |
 320                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 321                         RTE_PTYPE_INNER_L4_UDP,
 322                 /* [54] reserved */
 323                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 324                         RTE_PTYPE_TUNNEL_GRENAT |
 325                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 326                         RTE_PTYPE_INNER_L4_TCP,
 327                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 328                         RTE_PTYPE_TUNNEL_GRENAT |
 329                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 330                         RTE_PTYPE_INNER_L4_SCTP,
 331                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 332                         RTE_PTYPE_TUNNEL_GRENAT |
 333                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 334                         RTE_PTYPE_INNER_L4_ICMP,
 335
 336                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 337                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 338                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 339
 340                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 341                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 342                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 343                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 344                         RTE_PTYPE_INNER_L4_FRAG,
 345                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 346                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 347                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 348                         RTE_PTYPE_INNER_L4_NONFRAG,
 349                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 350                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 351                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 352                         RTE_PTYPE_INNER_L4_UDP,
 353                 /* [62] reserved */
 354                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 355                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 356                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 357                         RTE_PTYPE_INNER_L4_TCP,
 358                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 359                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 360                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 361                         RTE_PTYPE_INNER_L4_SCTP,
 362                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 363                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 364                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 365                         RTE_PTYPE_INNER_L4_ICMP,
 366
 367                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 368                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 369                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 370                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 371                         RTE_PTYPE_INNER_L4_FRAG,
 372                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 373                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 374                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 375                         RTE_PTYPE_INNER_L4_NONFRAG,
 376                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 377                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 378                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 379                         RTE_PTYPE_INNER_L4_UDP,
 380                 /* [69] reserved */
 381                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 382                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 383                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 384                         RTE_PTYPE_INNER_L4_TCP,
 385                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 386                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 387                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 388                         RTE_PTYPE_INNER_L4_SCTP,
 389                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 390                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 391                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 392                         RTE_PTYPE_INNER_L4_ICMP,
 393
 394                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 395                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 396                         RTE_PTYPE_TUNNEL_GRENAT |
 397                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 398
 399                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 400                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 401                         RTE_PTYPE_TUNNEL_GRENAT |
 402                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 403                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 404                         RTE_PTYPE_INNER_L4_FRAG,
 405                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 406                         RTE_PTYPE_TUNNEL_GRENAT |
 407                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 408                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 409                         RTE_PTYPE_INNER_L4_NONFRAG,
 410                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 411                         RTE_PTYPE_TUNNEL_GRENAT |
 412                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 413                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 414                         RTE_PTYPE_INNER_L4_UDP,
 415                 /* [77] reserved */
 416                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 417                         RTE_PTYPE_TUNNEL_GRENAT |
 418                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 419                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 420                         RTE_PTYPE_INNER_L4_TCP,
 421                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 422                         RTE_PTYPE_TUNNEL_GRENAT |
 423                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 424                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 425                         RTE_PTYPE_INNER_L4_SCTP,
 426                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 427                         RTE_PTYPE_TUNNEL_GRENAT |
 428                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 429                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 430                         RTE_PTYPE_INNER_L4_ICMP,
 431
 432                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 433                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 434                         RTE_PTYPE_TUNNEL_GRENAT |
 435                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 436                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 437                         RTE_PTYPE_INNER_L4_FRAG,
 438                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 439                         RTE_PTYPE_TUNNEL_GRENAT |
 440                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 441                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 442                         RTE_PTYPE_INNER_L4_NONFRAG,
 443                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 444                         RTE_PTYPE_TUNNEL_GRENAT |
 445                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 446                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 447                         RTE_PTYPE_INNER_L4_UDP,
 448                 /* [84] reserved */
 449                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 450                         RTE_PTYPE_TUNNEL_GRENAT |
 451                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 452                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 453                         RTE_PTYPE_INNER_L4_TCP,
 454                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 455                         RTE_PTYPE_TUNNEL_GRENAT |
 456                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 457                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 458                         RTE_PTYPE_INNER_L4_SCTP,
 459                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 460                         RTE_PTYPE_TUNNEL_GRENAT |
 461                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 462                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 463                         RTE_PTYPE_INNER_L4_ICMP,
 464
 465                 /* Non tunneled IPv6 */
 466                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 467                         RTE_PTYPE_L4_FRAG,
 468                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 469                         RTE_PTYPE_L4_NONFRAG,
 470                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 471                         RTE_PTYPE_L4_UDP,
 472                 /* [91] reserved */
 473                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 474                         RTE_PTYPE_L4_TCP,
 475                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 476                         RTE_PTYPE_L4_SCTP,
 477                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 478                         RTE_PTYPE_L4_ICMP,
 479
 480                 /* IPv6 --> IPv4 */
 481                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 482                         RTE_PTYPE_TUNNEL_IP |
 483                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 484                         RTE_PTYPE_INNER_L4_FRAG,
 485                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 486                         RTE_PTYPE_TUNNEL_IP |
 487                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 488                         RTE_PTYPE_INNER_L4_NONFRAG,
 489                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 490                         RTE_PTYPE_TUNNEL_IP |
 491                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 492                         RTE_PTYPE_INNER_L4_UDP,
 493                 /* [98] reserved */
 494                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 495                         RTE_PTYPE_TUNNEL_IP |
 496                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 497                         RTE_PTYPE_INNER_L4_TCP,
 498                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 499                         RTE_PTYPE_TUNNEL_IP |
 500                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 501                         RTE_PTYPE_INNER_L4_SCTP,
 502                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 503                         RTE_PTYPE_TUNNEL_IP |
 504                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 505                         RTE_PTYPE_INNER_L4_ICMP,
 506
 507                 /* IPv6 --> IPv6 */
 508                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 509                         RTE_PTYPE_TUNNEL_IP |
 510                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 511                         RTE_PTYPE_INNER_L4_FRAG,
 512                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 513                         RTE_PTYPE_TUNNEL_IP |
 514                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 515                         RTE_PTYPE_INNER_L4_NONFRAG,
 516                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 517                         RTE_PTYPE_TUNNEL_IP |
 518                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 519                         RTE_PTYPE_INNER_L4_UDP,
 520                 /* [105] reserved */
 521                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 522                         RTE_PTYPE_TUNNEL_IP |
 523                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 524                         RTE_PTYPE_INNER_L4_TCP,
 525                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 526                         RTE_PTYPE_TUNNEL_IP |
 527                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 528                         RTE_PTYPE_INNER_L4_SCTP,
 529                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 530                         RTE_PTYPE_TUNNEL_IP |
 531                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 532                         RTE_PTYPE_INNER_L4_ICMP,
 533
 534                 /* IPv6 --> GRE/Teredo/VXLAN */
 535                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 536                         RTE_PTYPE_TUNNEL_GRENAT,
 537
 538                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 539                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 540                         RTE_PTYPE_TUNNEL_GRENAT |
 541                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 542                         RTE_PTYPE_INNER_L4_FRAG,
 543                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 544                         RTE_PTYPE_TUNNEL_GRENAT |
 545                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 546                         RTE_PTYPE_INNER_L4_NONFRAG,
 547                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 548                         RTE_PTYPE_TUNNEL_GRENAT |
 549                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 550                         RTE_PTYPE_INNER_L4_UDP,
 551                 /* [113] reserved */
 552                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 553                         RTE_PTYPE_TUNNEL_GRENAT |
 554                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 555                         RTE_PTYPE_INNER_L4_TCP,
 556                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 557                         RTE_PTYPE_TUNNEL_GRENAT |
 558                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 559                         RTE_PTYPE_INNER_L4_SCTP,
 560                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 561                         RTE_PTYPE_TUNNEL_GRENAT |
 562                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 563                         RTE_PTYPE_INNER_L4_ICMP,
 564
 565                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 566                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 567                         RTE_PTYPE_TUNNEL_GRENAT |
 568                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 569                         RTE_PTYPE_INNER_L4_FRAG,
 570                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 571                         RTE_PTYPE_TUNNEL_GRENAT |
 572                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 573                         RTE_PTYPE_INNER_L4_NONFRAG,
 574                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 575                         RTE_PTYPE_TUNNEL_GRENAT |
 576                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 577                         RTE_PTYPE_INNER_L4_UDP,
 578                 /* [120] reserved */
 579                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 580                         RTE_PTYPE_TUNNEL_GRENAT |
 581                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 582                         RTE_PTYPE_INNER_L4_TCP,
 583                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 584                         RTE_PTYPE_TUNNEL_GRENAT |
 585                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 586                         RTE_PTYPE_INNER_L4_SCTP,
 587                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 588                         RTE_PTYPE_TUNNEL_GRENAT |
 589                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 590                         RTE_PTYPE_INNER_L4_ICMP,
 591
 592                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 593                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 594                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 595
 596                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 597                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 598                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 599                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 600                         RTE_PTYPE_INNER_L4_FRAG,
 601                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 602                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 603                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 604                         RTE_PTYPE_INNER_L4_NONFRAG,
 605                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 606                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 607                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 608                         RTE_PTYPE_INNER_L4_UDP,
 609                 /* [128] reserved */
 610                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 611                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 612                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 613                         RTE_PTYPE_INNER_L4_TCP,
 614                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 615                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 616                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 617                         RTE_PTYPE_INNER_L4_SCTP,
 618                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 619                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 620                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 621                         RTE_PTYPE_INNER_L4_ICMP,
 622
 623                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 624                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 625                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 626                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 627                         RTE_PTYPE_INNER_L4_FRAG,
 628                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 629                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 630                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 631                         RTE_PTYPE_INNER_L4_NONFRAG,
 632                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 633                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 634                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 635                         RTE_PTYPE_INNER_L4_UDP,
 636                 /* [135] reserved */
 637                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 638                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 639                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 640                         RTE_PTYPE_INNER_L4_TCP,
 641                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 642                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 643                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 644                         RTE_PTYPE_INNER_L4_SCTP,
 645                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 646                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 647                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 648                         RTE_PTYPE_INNER_L4_ICMP,
 649
 650                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 651                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 652                         RTE_PTYPE_TUNNEL_GRENAT |
 653                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 654
 655                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 656                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 657                         RTE_PTYPE_TUNNEL_GRENAT |
 658                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 659                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 660                         RTE_PTYPE_INNER_L4_FRAG,
 661                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 662                         RTE_PTYPE_TUNNEL_GRENAT |
 663                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 664                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 665                         RTE_PTYPE_INNER_L4_NONFRAG,
 666                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 667                         RTE_PTYPE_TUNNEL_GRENAT |
 668                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 669                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 670                         RTE_PTYPE_INNER_L4_UDP,
 671                 /* [143] reserved */
 672                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 673                         RTE_PTYPE_TUNNEL_GRENAT |
 674                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 675                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 676                         RTE_PTYPE_INNER_L4_TCP,
 677                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 678                         RTE_PTYPE_TUNNEL_GRENAT |
 679                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 680                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 681                         RTE_PTYPE_INNER_L4_SCTP,
 682                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 683                         RTE_PTYPE_TUNNEL_GRENAT |
 684                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 685                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 686                         RTE_PTYPE_INNER_L4_ICMP,
 687
 688                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 689                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 690                         RTE_PTYPE_TUNNEL_GRENAT |
 691                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 692                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 693                         RTE_PTYPE_INNER_L4_FRAG,
 694                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 695                         RTE_PTYPE_TUNNEL_GRENAT |
 696                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 697                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 698                         RTE_PTYPE_INNER_L4_NONFRAG,
 699                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 700                         RTE_PTYPE_TUNNEL_GRENAT |
 701                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 702                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 703                         RTE_PTYPE_INNER_L4_UDP,
 704                 /* [150] reserved */
 705                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 706                         RTE_PTYPE_TUNNEL_GRENAT |
 707                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 708                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 709                         RTE_PTYPE_INNER_L4_TCP,
 710                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 711                         RTE_PTYPE_TUNNEL_GRENAT |
 712                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 713                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 714                         RTE_PTYPE_INNER_L4_SCTP,
 715                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 716                         RTE_PTYPE_TUNNEL_GRENAT |
 717                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 718                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 719                         RTE_PTYPE_INNER_L4_ICMP,
 720
 721                 /* All others reserved */
 722         };
 723
 724         return type_table[ptype];
 725 }
 726
 727 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 728 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 729 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 730 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 731 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 732
 733 static inline uint64_t
 734 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 735 {
 736         uint64_t flags = 0;
 737 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 738         uint16_t flexbh, flexbl;
 739
 740         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 741                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 742                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 743         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 744                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 745                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 746
 747
 748         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 749                 mb->hash.fdir.hi =
 750                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 751                 flags |= PKT_RX_FDIR_ID;
 752         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 753                 mb->hash.fdir.hi =
 754                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 755                 flags |= PKT_RX_FDIR_FLX;
 756         }
 757         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 758                 mb->hash.fdir.lo =
 759                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 760                 flags |= PKT_RX_FDIR_FLX;
 761         }
 762 #else
 763         mb->hash.fdir.hi =
 764                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 765         flags |= PKT_RX_FDIR_ID;
 766 #endif
 767         return flags;
 768 }
 769 static inline void
 770 i40e_txd_enable_checksum(uint64_t ol_flags,
 771                         uint32_t *td_cmd,
 772                         uint32_t *td_offset,
 773                         union i40e_tx_offload tx_offload,
 774                         uint32_t *cd_tunneling)
 775 {
 776         /* UDP tunneling packet TX checksum offload */
 777         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 778
 779                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 780                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 781
 782                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 783                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 784                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 785                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 786                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 787                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 788
 789                 /* Now set the ctx descriptor fields */
 790                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 791                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 792                                 (tx_offload.l2_len >> 1) <<
 793                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 794
 795         } else
 796                 *td_offset |= (tx_offload.l2_len >> 1)
 797                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 798
 799         /* Enable L3 checksum offloads */
 800         if (ol_flags & PKT_TX_IP_CKSUM) {
 801                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 802                 *td_offset |= (tx_offload.l3_len >> 2)
 803                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 804         } else if (ol_flags & PKT_TX_IPV4) {
 805                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 806                 *td_offset |= (tx_offload.l3_len >> 2)
 807                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 808         } else if (ol_flags & PKT_TX_IPV6) {
 809                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 810                 *td_offset |= (tx_offload.l3_len >> 2)
 811                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 812         }
 813
 814         if (ol_flags & PKT_TX_TCP_SEG) {
 815                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 816                 *td_offset |= (tx_offload.l4_len >> 2)
 817                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 818                 return;
 819         }
 820
 821         /* Enable L4 checksum offloads */
 822         switch (ol_flags & PKT_TX_L4_MASK) {
 823         case PKT_TX_TCP_CKSUM:
 824                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 825                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 826                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 827                 break;
 828         case PKT_TX_SCTP_CKSUM:
 829                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 830                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 831                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 832                 break;
 833         case PKT_TX_UDP_CKSUM:
 834                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 835                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 836                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 837                 break;
 838         default:
 839                 break;
 840         }
 841 }
 842
 843 static inline struct rte_mbuf *
 844 rte_rxmbuf_alloc(struct rte_mempool *mp)
 845 {
 846         struct rte_mbuf *m;
 847
 848         m = __rte_mbuf_raw_alloc(mp);
 849         __rte_mbuf_sanity_check_raw(m, 0);
 850
 851         return m;
 852 }
 853
 854 /* Construct the tx flags */
 855 static inline uint64_t
 856 i40e_build_ctob(uint32_t td_cmd,
 857                 uint32_t td_offset,
 858                 unsigned int size,
 859                 uint32_t td_tag)
 860 {
 861         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 862                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 863                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 864                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 865                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 866 }
 867
 868 static inline int
 869 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 870 {
 871         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 872         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 873         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 874         uint16_t nb_tx_desc = txq->nb_tx_desc;
 875         uint16_t desc_to_clean_to;
 876         uint16_t nb_tx_to_clean;
 877
 878         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 879         if (desc_to_clean_to >= nb_tx_desc)
 880                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 881
 882         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 883         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 884                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 885                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 886                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 887                         "(port=%d queue=%d)", desc_to_clean_to,
 888                                 txq->port_id, txq->queue_id);
 889                 return -1;
 890         }
 891
 892         if (last_desc_cleaned > desc_to_clean_to)
 893                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 894                                                         desc_to_clean_to);
 895         else
 896                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 897                                         last_desc_cleaned);
 898
 899         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 900
 901         txq->last_desc_cleaned = desc_to_clean_to;
 902         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 903
 904         return 0;
 905 }
 906
 907 static inline int
 908 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 909 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 910 #else
 911 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 912 #endif
 913 {
 914         int ret = 0;
 915
 916 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 917         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 918                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 919                              "rxq->rx_free_thresh=%d, "
 920                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 921                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 922                 ret = -EINVAL;
 923         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 924                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 925                              "rxq->rx_free_thresh=%d, "
 926                              "rxq->nb_rx_desc=%d",
 927                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 928                 ret = -EINVAL;
 929         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 930                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 931                              "rxq->nb_rx_desc=%d, "
 932                              "rxq->rx_free_thresh=%d",
 933                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 934                 ret = -EINVAL;
 935         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 936                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 937                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 938                              "rxq->nb_rx_desc=%d, "
 939                              "I40E_MAX_RING_DESC=%d, "
 940                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 941                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 942                              RTE_PMD_I40E_RX_MAX_BURST);
 943                 ret = -EINVAL;
 944         }
 945 #else
 946         ret = -EINVAL;
 947 #endif
 948
 949         return ret;
 950 }
 951
 952 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 953 #define I40E_LOOK_AHEAD 8
 954 #if (I40E_LOOK_AHEAD != 8)
 955 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 956 #endif
 957 static inline int
 958 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 959 {
 960         volatile union i40e_rx_desc *rxdp;
 961         struct i40e_rx_entry *rxep;
 962         struct rte_mbuf *mb;
 963         uint16_t pkt_len;
 964         uint64_t qword1;
 965         uint32_t rx_status;
 966         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 967         int32_t i, j, nb_rx = 0;
 968         uint64_t pkt_flags;
 969
 970         rxdp = &rxq->rx_ring[rxq->rx_tail];
 971         rxep = &rxq->sw_ring[rxq->rx_tail];
 972
 973         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 974         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 975                                 I40E_RXD_QW1_STATUS_SHIFT;
 976
 977         /* Make sure there is at least 1 packet to receive */
 978         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 979                 return 0;
 980
 981         /**
 982          * Scan LOOK_AHEAD descriptors at a time to determine which
 983          * descriptors reference packets that are ready to be received.
 984          */
 985         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 986                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 987                 /* Read desc statuses backwards to avoid race condition */
 988                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 989                         qword1 = rte_le_to_cpu_64(\
 990                                 rxdp[j].wb.qword1.status_error_len);
 991                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 992                                         I40E_RXD_QW1_STATUS_SHIFT;
 993                 }
 994
 995                 /* Compute how many status bits were set */
 996                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 997                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 998
 999                 nb_rx += nb_dd;
1000
1001                 /* Translate descriptor info to mbuf parameters */
1002                 for (j = 0; j < nb_dd; j++) {
1003                         mb = rxep[j].mbuf;
1004                         qword1 = rte_le_to_cpu_64(\
1005                                 rxdp[j].wb.qword1.status_error_len);
1006                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1007                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1008                         mb->data_len = pkt_len;
1009                         mb->pkt_len = pkt_len;
1010                         mb->ol_flags = 0;
1011                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1012                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1013                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1014                         mb->packet_type =
1015                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1016                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1017                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1018                         if (pkt_flags & PKT_RX_RSS_HASH)
1019                                 mb->hash.rss = rte_le_to_cpu_32(\
1020                                         rxdp[j].wb.qword0.hi_dword.rss);
1021                         if (pkt_flags & PKT_RX_FDIR)
1022                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1023
1024 #ifdef RTE_LIBRTE_IEEE1588
1025                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1026 #endif
1027                         mb->ol_flags |= pkt_flags;
1028
1029                 }
1030
1031                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1032                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1033
1034                 if (nb_dd != I40E_LOOK_AHEAD)
1035                         break;
1036         }
1037
1038         /* Clear software ring entries */
1039         for (i = 0; i < nb_rx; i++)
1040                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1041
1042         return nb_rx;
1043 }
1044
1045 static inline uint16_t
1046 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1047                         struct rte_mbuf **rx_pkts,
1048                         uint16_t nb_pkts)
1049 {
1050         uint16_t i;
1051         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1052
1053         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1054
1055         for (i = 0; i < nb_pkts; i++)
1056                 rx_pkts[i] = stage[i];
1057
1058         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1059         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1060
1061         return nb_pkts;
1062 }
1063
1064 static inline int
1065 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1066 {
1067         volatile union i40e_rx_desc *rxdp;
1068         struct i40e_rx_entry *rxep;
1069         struct rte_mbuf *mb;
1070         uint16_t alloc_idx, i;
1071         uint64_t dma_addr;
1072         int diag;
1073
1074         /* Allocate buffers in bulk */
1075         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1076                                 (rxq->rx_free_thresh - 1));
1077         rxep = &(rxq->sw_ring[alloc_idx]);
1078         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1079                                         rxq->rx_free_thresh);
1080         if (unlikely(diag != 0)) {
1081                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1082                 return -ENOMEM;
1083         }
1084
1085         rxdp = &rxq->rx_ring[alloc_idx];
1086         for (i = 0; i < rxq->rx_free_thresh; i++) {
1087                 if (likely(i < (rxq->rx_free_thresh - 1)))
1088                         /* Prefetch next mbuf */
1089                         rte_prefetch0(rxep[i + 1].mbuf);
1090
1091                 mb = rxep[i].mbuf;
1092                 rte_mbuf_refcnt_set(mb, 1);
1093                 mb->next = NULL;
1094                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1095                 mb->nb_segs = 1;
1096                 mb->port = rxq->port_id;
1097                 dma_addr = rte_cpu_to_le_64(\
1098                         rte_mbuf_data_dma_addr_default(mb));
1099                 rxdp[i].read.hdr_addr = 0;
1100                 rxdp[i].read.pkt_addr = dma_addr;
1101         }
1102
1103         /* Update rx tail regsiter */
1104         rte_wmb();
1105         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1106
1107         rxq->rx_free_trigger =
1108                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1109         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1110                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1111
1112         return 0;
1113 }
1114
1115 static inline uint16_t
1116 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1117 {
1118         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1119         uint16_t nb_rx = 0;
1120
1121         if (!nb_pkts)
1122                 return 0;
1123
1124         if (rxq->rx_nb_avail)
1125                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1126
1127         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1128         rxq->rx_next_avail = 0;
1129         rxq->rx_nb_avail = nb_rx;
1130         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1131
1132         if (rxq->rx_tail > rxq->rx_free_trigger) {
1133                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1134                         uint16_t i, j;
1135
1136                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1137                                    "port_id=%u, queue_id=%u",
1138                                    rxq->port_id, rxq->queue_id);
1139                         rxq->rx_nb_avail = 0;
1140                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1141                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1142                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1143
1144                         return 0;
1145                 }
1146         }
1147
1148         if (rxq->rx_tail >= rxq->nb_rx_desc)
1149                 rxq->rx_tail = 0;
1150
1151         if (rxq->rx_nb_avail)
1152                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1153
1154         return 0;
1155 }
1156
1157 static uint16_t
1158 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1159                           struct rte_mbuf **rx_pkts,
1160                           uint16_t nb_pkts)
1161 {
1162         uint16_t nb_rx = 0, n, count;
1163
1164         if (unlikely(nb_pkts == 0))
1165                 return 0;
1166
1167         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1168                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1169
1170         while (nb_pkts) {
1171                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1172                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1173                 nb_rx = (uint16_t)(nb_rx + count);
1174                 nb_pkts = (uint16_t)(nb_pkts - count);
1175                 if (count < n)
1176                         break;
1177         }
1178
1179         return nb_rx;
1180 }
1181 #else
1182 static uint16_t
1183 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1184                           struct rte_mbuf __rte_unused **rx_pkts,
1185                           uint16_t __rte_unused nb_pkts)
1186 {
1187         return 0;
1188 }
1189 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1190
1191 uint16_t
1192 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1193 {
1194         struct i40e_rx_queue *rxq;
1195         volatile union i40e_rx_desc *rx_ring;
1196         volatile union i40e_rx_desc *rxdp;
1197         union i40e_rx_desc rxd;
1198         struct i40e_rx_entry *sw_ring;
1199         struct i40e_rx_entry *rxe;
1200         struct rte_mbuf *rxm;
1201         struct rte_mbuf *nmb;
1202         uint16_t nb_rx;
1203         uint32_t rx_status;
1204         uint64_t qword1;
1205         uint16_t rx_packet_len;
1206         uint16_t rx_id, nb_hold;
1207         uint64_t dma_addr;
1208         uint64_t pkt_flags;
1209
1210         nb_rx = 0;
1211         nb_hold = 0;
1212         rxq = rx_queue;
1213         rx_id = rxq->rx_tail;
1214         rx_ring = rxq->rx_ring;
1215         sw_ring = rxq->sw_ring;
1216
1217         while (nb_rx < nb_pkts) {
1218                 rxdp = &rx_ring[rx_id];
1219                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1220                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1221                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1222
1223                 /* Check the DD bit first */
1224                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1225                         break;
1226
1227                 nmb = rte_rxmbuf_alloc(rxq->mp);
1228                 if (unlikely(!nmb))
1229                         break;
1230                 rxd = *rxdp;
1231
1232                 nb_hold++;
1233                 rxe = &sw_ring[rx_id];
1234                 rx_id++;
1235                 if (unlikely(rx_id == rxq->nb_rx_desc))
1236                         rx_id = 0;
1237
1238                 /* Prefetch next mbuf */
1239                 rte_prefetch0(sw_ring[rx_id].mbuf);
1240
1241                 /**
1242                  * When next RX descriptor is on a cache line boundary,
1243                  * prefetch the next 4 RX descriptors and next 8 pointers
1244                  * to mbufs.
1245                  */
1246                 if ((rx_id & 0x3) == 0) {
1247                         rte_prefetch0(&rx_ring[rx_id]);
1248                         rte_prefetch0(&sw_ring[rx_id]);
1249                 }
1250                 rxm = rxe->mbuf;
1251                 rxe->mbuf = nmb;
1252                 dma_addr =
1253                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1254                 rxdp->read.hdr_addr = 0;
1255                 rxdp->read.pkt_addr = dma_addr;
1256
1257                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1258                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1259
1260                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1261                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1262                 rxm->nb_segs = 1;
1263                 rxm->next = NULL;
1264                 rxm->pkt_len = rx_packet_len;
1265                 rxm->data_len = rx_packet_len;
1266                 rxm->port = rxq->port_id;
1267                 rxm->ol_flags = 0;
1268                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1269                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1270                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1271                 rxm->packet_type =
1272                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1273                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1274                 if (pkt_flags & PKT_RX_RSS_HASH)
1275                         rxm->hash.rss =
1276                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1277                 if (pkt_flags & PKT_RX_FDIR)
1278                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1279
1280 #ifdef RTE_LIBRTE_IEEE1588
1281                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1282 #endif
1283                 rxm->ol_flags |= pkt_flags;
1284
1285                 rx_pkts[nb_rx++] = rxm;
1286         }
1287         rxq->rx_tail = rx_id;
1288
1289         /**
1290          * If the number of free RX descriptors is greater than the RX free
1291          * threshold of the queue, advance the receive tail register of queue.
1292          * Update that register with the value of the last processed RX
1293          * descriptor minus 1.
1294          */
1295         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1296         if (nb_hold > rxq->rx_free_thresh) {
1297                 rx_id = (uint16_t) ((rx_id == 0) ?
1298                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1299                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1300                 nb_hold = 0;
1301         }
1302         rxq->nb_rx_hold = nb_hold;
1303
1304         return nb_rx;
1305 }
1306
1307 uint16_t
1308 i40e_recv_scattered_pkts(void *rx_queue,
1309                          struct rte_mbuf **rx_pkts,
1310                          uint16_t nb_pkts)
1311 {
1312         struct i40e_rx_queue *rxq = rx_queue;
1313         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1314         volatile union i40e_rx_desc *rxdp;
1315         union i40e_rx_desc rxd;
1316         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1317         struct i40e_rx_entry *rxe;
1318         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1319         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1320         struct rte_mbuf *nmb, *rxm;
1321         uint16_t rx_id = rxq->rx_tail;
1322         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1323         uint32_t rx_status;
1324         uint64_t qword1;
1325         uint64_t dma_addr;
1326         uint64_t pkt_flags;
1327
1328         while (nb_rx < nb_pkts) {
1329                 rxdp = &rx_ring[rx_id];
1330                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1331                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1332                                         I40E_RXD_QW1_STATUS_SHIFT;
1333
1334                 /* Check the DD bit */
1335                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1336                         break;
1337
1338                 nmb = rte_rxmbuf_alloc(rxq->mp);
1339                 if (unlikely(!nmb))
1340                         break;
1341                 rxd = *rxdp;
1342                 nb_hold++;
1343                 rxe = &sw_ring[rx_id];
1344                 rx_id++;
1345                 if (rx_id == rxq->nb_rx_desc)
1346                         rx_id = 0;
1347
1348                 /* Prefetch next mbuf */
1349                 rte_prefetch0(sw_ring[rx_id].mbuf);
1350
1351                 /**
1352                  * When next RX descriptor is on a cache line boundary,
1353                  * prefetch the next 4 RX descriptors and next 8 pointers
1354                  * to mbufs.
1355                  */
1356                 if ((rx_id & 0x3) == 0) {
1357                         rte_prefetch0(&rx_ring[rx_id]);
1358                         rte_prefetch0(&sw_ring[rx_id]);
1359                 }
1360
1361                 rxm = rxe->mbuf;
1362                 rxe->mbuf = nmb;
1363                 dma_addr =
1364                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1365
1366                 /* Set data buffer address and data length of the mbuf */
1367                 rxdp->read.hdr_addr = 0;
1368                 rxdp->read.pkt_addr = dma_addr;
1369                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1370                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1371                 rxm->data_len = rx_packet_len;
1372                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1373
1374                 /**
1375                  * If this is the first buffer of the received packet, set the
1376                  * pointer to the first mbuf of the packet and initialize its
1377                  * context. Otherwise, update the total length and the number
1378                  * of segments of the current scattered packet, and update the
1379                  * pointer to the last mbuf of the current packet.
1380                  */
1381                 if (!first_seg) {
1382                         first_seg = rxm;
1383                         first_seg->nb_segs = 1;
1384                         first_seg->pkt_len = rx_packet_len;
1385                 } else {
1386                         first_seg->pkt_len =
1387                                 (uint16_t)(first_seg->pkt_len +
1388                                                 rx_packet_len);
1389                         first_seg->nb_segs++;
1390                         last_seg->next = rxm;
1391                 }
1392
1393                 /**
1394                  * If this is not the last buffer of the received packet,
1395                  * update the pointer to the last mbuf of the current scattered
1396                  * packet and continue to parse the RX ring.
1397                  */
1398                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1399                         last_seg = rxm;
1400                         continue;
1401                 }
1402
1403                 /**
1404                  * This is the last buffer of the received packet. If the CRC
1405                  * is not stripped by the hardware:
1406                  *  - Subtract the CRC length from the total packet length.
1407                  *  - If the last buffer only contains the whole CRC or a part
1408                  *  of it, free the mbuf associated to the last buffer. If part
1409                  *  of the CRC is also contained in the previous mbuf, subtract
1410                  *  the length of that CRC part from the data length of the
1411                  *  previous mbuf.
1412                  */
1413                 rxm->next = NULL;
1414                 if (unlikely(rxq->crc_len > 0)) {
1415                         first_seg->pkt_len -= ETHER_CRC_LEN;
1416                         if (rx_packet_len <= ETHER_CRC_LEN) {
1417                                 rte_pktmbuf_free_seg(rxm);
1418                                 first_seg->nb_segs--;
1419                                 last_seg->data_len =
1420                                         (uint16_t)(last_seg->data_len -
1421                                         (ETHER_CRC_LEN - rx_packet_len));
1422                                 last_seg->next = NULL;
1423                         } else
1424                                 rxm->data_len = (uint16_t)(rx_packet_len -
1425                                                                 ETHER_CRC_LEN);
1426                 }
1427
1428                 first_seg->port = rxq->port_id;
1429                 first_seg->ol_flags = 0;
1430                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1431                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1432                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1433                 first_seg->packet_type =
1434                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1435                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1436                 if (pkt_flags & PKT_RX_RSS_HASH)
1437                         rxm->hash.rss =
1438                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1439                 if (pkt_flags & PKT_RX_FDIR)
1440                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1441
1442 #ifdef RTE_LIBRTE_IEEE1588
1443                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1444 #endif
1445                 first_seg->ol_flags |= pkt_flags;
1446
1447                 /* Prefetch data of first segment, if configured to do so. */
1448                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1449                         first_seg->data_off));
1450                 rx_pkts[nb_rx++] = first_seg;
1451                 first_seg = NULL;
1452         }
1453
1454         /* Record index of the next RX descriptor to probe. */
1455         rxq->rx_tail = rx_id;
1456         rxq->pkt_first_seg = first_seg;
1457         rxq->pkt_last_seg = last_seg;
1458
1459         /**
1460          * If the number of free RX descriptors is greater than the RX free
1461          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1462          * register. Update the RDT with the value of the last processed RX
1463          * descriptor minus 1, to guarantee that the RDT register is never
1464          * equal to the RDH register, which creates a "full" ring situtation
1465          * from the hardware point of view.
1466          */
1467         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1468         if (nb_hold > rxq->rx_free_thresh) {
1469                 rx_id = (uint16_t)(rx_id == 0 ?
1470                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1471                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1472                 nb_hold = 0;
1473         }
1474         rxq->nb_rx_hold = nb_hold;
1475
1476         return nb_rx;
1477 }
1478
1479 /* Check if the context descriptor is needed for TX offloading */
1480 static inline uint16_t
1481 i40e_calc_context_desc(uint64_t flags)
1482 {
1483         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1484                 PKT_TX_TCP_SEG |
1485                 PKT_TX_QINQ_PKT;
1486
1487 #ifdef RTE_LIBRTE_IEEE1588
1488         mask |= PKT_TX_IEEE1588_TMST;
1489 #endif
1490
1491         return (flags & mask) ? 1 : 0;
1492 }
1493
1494 /* set i40e TSO context descriptor */
1495 static inline uint64_t
1496 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1497 {
1498         uint64_t ctx_desc = 0;
1499         uint32_t cd_cmd, hdr_len, cd_tso_len;
1500
1501         if (!tx_offload.l4_len) {
1502                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1503                 return ctx_desc;
1504         }
1505
1506         /**
1507          * in case of tunneling packet, the outer_l2_len and
1508          * outer_l3_len must be 0.
1509          */
1510         hdr_len = tx_offload.outer_l2_len +
1511                 tx_offload.outer_l3_len +
1512                 tx_offload.l2_len +
1513                 tx_offload.l3_len +
1514                 tx_offload.l4_len;
1515
1516         cd_cmd = I40E_TX_CTX_DESC_TSO;
1517         cd_tso_len = mbuf->pkt_len - hdr_len;
1518         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1519                 ((uint64_t)cd_tso_len <<
1520                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1521                 ((uint64_t)mbuf->tso_segsz <<
1522                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1523
1524         return ctx_desc;
1525 }
1526
1527 uint16_t
1528 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1529 {
1530         struct i40e_tx_queue *txq;
1531         struct i40e_tx_entry *sw_ring;
1532         struct i40e_tx_entry *txe, *txn;
1533         volatile struct i40e_tx_desc *txd;
1534         volatile struct i40e_tx_desc *txr;
1535         struct rte_mbuf *tx_pkt;
1536         struct rte_mbuf *m_seg;
1537         uint32_t cd_tunneling_params;
1538         uint16_t tx_id;
1539         uint16_t nb_tx;
1540         uint32_t td_cmd;
1541         uint32_t td_offset;
1542         uint32_t tx_flags;
1543         uint32_t td_tag;
1544         uint64_t ol_flags;
1545         uint16_t nb_used;
1546         uint16_t nb_ctx;
1547         uint16_t tx_last;
1548         uint16_t slen;
1549         uint64_t buf_dma_addr;
1550         union i40e_tx_offload tx_offload = {0};
1551
1552         txq = tx_queue;
1553         sw_ring = txq->sw_ring;
1554         txr = txq->tx_ring;
1555         tx_id = txq->tx_tail;
1556         txe = &sw_ring[tx_id];
1557
1558         /* Check if the descriptor ring needs to be cleaned. */
1559         if (txq->nb_tx_free < txq->tx_free_thresh)
1560                 i40e_xmit_cleanup(txq);
1561
1562         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1563                 td_cmd = 0;
1564                 td_tag = 0;
1565                 td_offset = 0;
1566                 tx_flags = 0;
1567
1568                 tx_pkt = *tx_pkts++;
1569                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1570
1571                 ol_flags = tx_pkt->ol_flags;
1572                 tx_offload.l2_len = tx_pkt->l2_len;
1573                 tx_offload.l3_len = tx_pkt->l3_len;
1574                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1575                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1576                 tx_offload.l4_len = tx_pkt->l4_len;
1577                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1578
1579                 /* Calculate the number of context descriptors needed. */
1580                 nb_ctx = i40e_calc_context_desc(ol_flags);
1581
1582                 /**
1583                  * The number of descriptors that must be allocated for
1584                  * a packet equals to the number of the segments of that
1585                  * packet plus 1 context descriptor if needed.
1586                  */
1587                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1588                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1589
1590                 /* Circular ring */
1591                 if (tx_last >= txq->nb_tx_desc)
1592                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1593
1594                 if (nb_used > txq->nb_tx_free) {
1595                         if (i40e_xmit_cleanup(txq) != 0) {
1596                                 if (nb_tx == 0)
1597                                         return 0;
1598                                 goto end_of_tx;
1599                         }
1600                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1601                                 while (nb_used > txq->nb_tx_free) {
1602                                         if (i40e_xmit_cleanup(txq) != 0) {
1603                                                 if (nb_tx == 0)
1604                                                         return 0;
1605                                                 goto end_of_tx;
1606                                         }
1607                                 }
1608                         }
1609                 }
1610
1611                 /* Descriptor based VLAN insertion */
1612                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1613                         tx_flags |= tx_pkt->vlan_tci <<
1614                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1615                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1616                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1617                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1618                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1619                 }
1620
1621                 /* Always enable CRC offload insertion */
1622                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1623
1624                 /* Enable checksum offloading */
1625                 cd_tunneling_params = 0;
1626                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1627                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1628                                 tx_offload, &cd_tunneling_params);
1629                 }
1630
1631                 if (nb_ctx) {
1632                         /* Setup TX context descriptor if required */
1633                         volatile struct i40e_tx_context_desc *ctx_txd =
1634                                 (volatile struct i40e_tx_context_desc *)\
1635                                                         &txr[tx_id];
1636                         uint16_t cd_l2tag2 = 0;
1637                         uint64_t cd_type_cmd_tso_mss =
1638                                 I40E_TX_DESC_DTYPE_CONTEXT;
1639
1640                         txn = &sw_ring[txe->next_id];
1641                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1642                         if (txe->mbuf != NULL) {
1643                                 rte_pktmbuf_free_seg(txe->mbuf);
1644                                 txe->mbuf = NULL;
1645                         }
1646
1647                         /* TSO enabled means no timestamp */
1648                         if (ol_flags & PKT_TX_TCP_SEG)
1649                                 cd_type_cmd_tso_mss |=
1650                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1651                         else {
1652 #ifdef RTE_LIBRTE_IEEE1588
1653                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1654                                         cd_type_cmd_tso_mss |=
1655                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1656                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1657 #endif
1658                         }
1659
1660                         ctx_txd->tunneling_params =
1661                                 rte_cpu_to_le_32(cd_tunneling_params);
1662                         if (ol_flags & PKT_TX_QINQ_PKT) {
1663                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1664                                 cd_type_cmd_tso_mss |=
1665                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1666                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1667                         }
1668                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1669                         ctx_txd->type_cmd_tso_mss =
1670                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1671
1672                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1673                                 "tunneling_params: %#x;\n"
1674                                 "l2tag2: %#hx;\n"
1675                                 "rsvd: %#hx;\n"
1676                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1677                                 tx_pkt, tx_id,
1678                                 ctx_txd->tunneling_params,
1679                                 ctx_txd->l2tag2,
1680                                 ctx_txd->rsvd,
1681                                 ctx_txd->type_cmd_tso_mss);
1682
1683                         txe->last_id = tx_last;
1684                         tx_id = txe->next_id;
1685                         txe = txn;
1686                 }
1687
1688                 m_seg = tx_pkt;
1689                 do {
1690                         txd = &txr[tx_id];
1691                         txn = &sw_ring[txe->next_id];
1692
1693                         if (txe->mbuf)
1694                                 rte_pktmbuf_free_seg(txe->mbuf);
1695                         txe->mbuf = m_seg;
1696
1697                         /* Setup TX Descriptor */
1698                         slen = m_seg->data_len;
1699                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1700
1701                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1702                                 "buf_dma_addr: %#"PRIx64";\n"
1703                                 "td_cmd: %#x;\n"
1704                                 "td_offset: %#x;\n"
1705                                 "td_len: %u;\n"
1706                                 "td_tag: %#x;\n",
1707                                 tx_pkt, tx_id, buf_dma_addr,
1708                                 td_cmd, td_offset, slen, td_tag);
1709
1710                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1711                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1712                                                 td_offset, slen, td_tag);
1713                         txe->last_id = tx_last;
1714                         tx_id = txe->next_id;
1715                         txe = txn;
1716                         m_seg = m_seg->next;
1717                 } while (m_seg != NULL);
1718
1719                 /* The last packet data descriptor needs End Of Packet (EOP) */
1720                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1721                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1722                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1723
1724                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1725                         PMD_TX_FREE_LOG(DEBUG,
1726                                         "Setting RS bit on TXD id="
1727                                         "%4u (port=%d queue=%d)",
1728                                         tx_last, txq->port_id, txq->queue_id);
1729
1730                         td_cmd |= I40E_TX_DESC_CMD_RS;
1731
1732                         /* Update txq RS bit counters */
1733                         txq->nb_tx_used = 0;
1734                 }
1735
1736                 txd->cmd_type_offset_bsz |=
1737                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1738                                         I40E_TXD_QW1_CMD_SHIFT);
1739         }
1740
1741 end_of_tx:
1742         rte_wmb();
1743
1744         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1745                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1746                    (unsigned) tx_id, (unsigned) nb_tx);
1747
1748         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1749         txq->tx_tail = tx_id;
1750
1751         return nb_tx;
1752 }
1753
1754 static inline int __attribute__((always_inline))
1755 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1756 {
1757         struct i40e_tx_entry *txep;
1758         uint16_t i;
1759
1760         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1761                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1762                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1763                 return 0;
1764
1765         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1766
1767         for (i = 0; i < txq->tx_rs_thresh; i++)
1768                 rte_prefetch0((txep + i)->mbuf);
1769
1770         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1771                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1772                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1773                         txep->mbuf = NULL;
1774                 }
1775         } else {
1776                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1777                         rte_pktmbuf_free_seg(txep->mbuf);
1778                         txep->mbuf = NULL;
1779                 }
1780         }
1781
1782         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1783         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1784         if (txq->tx_next_dd >= txq->nb_tx_desc)
1785                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1786
1787         return txq->tx_rs_thresh;
1788 }
1789
1790 /* Populate 4 descriptors with data from 4 mbufs */
1791 static inline void
1792 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1793 {
1794         uint64_t dma_addr;
1795         uint32_t i;
1796
1797         for (i = 0; i < 4; i++, txdp++, pkts++) {
1798                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1799                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1800                 txdp->cmd_type_offset_bsz =
1801                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1802                                         (*pkts)->data_len, 0);
1803         }
1804 }
1805
1806 /* Populate 1 descriptor with data from 1 mbuf */
1807 static inline void
1808 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1809 {
1810         uint64_t dma_addr;
1811
1812         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1813         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1814         txdp->cmd_type_offset_bsz =
1815                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1816                                 (*pkts)->data_len, 0);
1817 }
1818
1819 /* Fill hardware descriptor ring with mbuf data */
1820 static inline void
1821 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1822                      struct rte_mbuf **pkts,
1823                      uint16_t nb_pkts)
1824 {
1825         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1826         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1827         const int N_PER_LOOP = 4;
1828         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1829         int mainpart, leftover;
1830         int i, j;
1831
1832         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1833         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1834         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1835                 for (j = 0; j < N_PER_LOOP; ++j) {
1836                         (txep + i + j)->mbuf = *(pkts + i + j);
1837                 }
1838                 tx4(txdp + i, pkts + i);
1839         }
1840         if (unlikely(leftover > 0)) {
1841                 for (i = 0; i < leftover; ++i) {
1842                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1843                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1844                 }
1845         }
1846 }
1847
1848 static inline uint16_t
1849 tx_xmit_pkts(struct i40e_tx_queue *txq,
1850              struct rte_mbuf **tx_pkts,
1851              uint16_t nb_pkts)
1852 {
1853         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1854         uint16_t n = 0;
1855
1856         /**
1857          * Begin scanning the H/W ring for done descriptors when the number
1858          * of available descriptors drops below tx_free_thresh. For each done
1859          * descriptor, free the associated buffer.
1860          */
1861         if (txq->nb_tx_free < txq->tx_free_thresh)
1862                 i40e_tx_free_bufs(txq);
1863
1864         /* Use available descriptor only */
1865         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1866         if (unlikely(!nb_pkts))
1867                 return 0;
1868
1869         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1870         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1871                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1872                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1873                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1874                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1875                                                 I40E_TXD_QW1_CMD_SHIFT);
1876                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1877                 txq->tx_tail = 0;
1878         }
1879
1880         /* Fill hardware descriptor ring with mbuf data */
1881         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1882         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1883
1884         /* Determin if RS bit needs to be set */
1885         if (txq->tx_tail > txq->tx_next_rs) {
1886                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1887                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1888                                                 I40E_TXD_QW1_CMD_SHIFT);
1889                 txq->tx_next_rs =
1890                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1891                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1892                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1893         }
1894
1895         if (txq->tx_tail >= txq->nb_tx_desc)
1896                 txq->tx_tail = 0;
1897
1898         /* Update the tx tail register */
1899         rte_wmb();
1900         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1901
1902         return nb_pkts;
1903 }
1904
1905 static uint16_t
1906 i40e_xmit_pkts_simple(void *tx_queue,
1907                       struct rte_mbuf **tx_pkts,
1908                       uint16_t nb_pkts)
1909 {
1910         uint16_t nb_tx = 0;
1911
1912         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1913                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1914                                                 tx_pkts, nb_pkts);
1915
1916         while (nb_pkts) {
1917                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1918                                                 I40E_TX_MAX_BURST);
1919
1920                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1921                                                 &tx_pkts[nb_tx], num);
1922                 nb_tx = (uint16_t)(nb_tx + ret);
1923                 nb_pkts = (uint16_t)(nb_pkts - ret);
1924                 if (ret < num)
1925                         break;
1926         }
1927
1928         return nb_tx;
1929 }
1930
1931 /*
1932  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1933  * application used, which assume having sequential ones. But from driver's
1934  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1935  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1936  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1937  * use queue_idx from 0 to 95 to access queues, while real queue would be
1938  * different. This function will do a queue mapping to find VSI the queue
1939  * belongs to.
1940  */
1941 static struct i40e_vsi*
1942 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1943 {
1944         /* the queue in MAIN VSI range */
1945         if (queue_idx < pf->main_vsi->nb_qps)
1946                 return pf->main_vsi;
1947
1948         queue_idx -= pf->main_vsi->nb_qps;
1949
1950         /* queue_idx is greater than VMDQ VSIs range */
1951         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1952                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1953                 return NULL;
1954         }
1955
1956         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1957 }
1958
1959 static uint16_t
1960 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1961 {
1962         /* the queue in MAIN VSI range */
1963         if (queue_idx < pf->main_vsi->nb_qps)
1964                 return queue_idx;
1965
1966         /* It's VMDQ queues */
1967         queue_idx -= pf->main_vsi->nb_qps;
1968
1969         if (pf->nb_cfg_vmdq_vsi)
1970                 return queue_idx % pf->vmdq_nb_qps;
1971         else {
1972                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1973                 return (uint16_t)(-1);
1974         }
1975 }
1976
1977 int
1978 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1979 {
1980         struct i40e_rx_queue *rxq;
1981         int err = -1;
1982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983
1984         PMD_INIT_FUNC_TRACE();
1985
1986         if (rx_queue_id < dev->data->nb_rx_queues) {
1987                 rxq = dev->data->rx_queues[rx_queue_id];
1988
1989                 err = i40e_alloc_rx_queue_mbufs(rxq);
1990                 if (err) {
1991                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1992                         return err;
1993                 }
1994
1995                 rte_wmb();
1996
1997                 /* Init the RX tail regieter. */
1998                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1999
2000                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2001
2002                 if (err) {
2003                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2004                                     rx_queue_id);
2005
2006                         i40e_rx_queue_release_mbufs(rxq);
2007                         i40e_reset_rx_queue(rxq);
2008                 } else
2009                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2010         }
2011
2012         return err;
2013 }
2014
2015 int
2016 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2017 {
2018         struct i40e_rx_queue *rxq;
2019         int err;
2020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021
2022         if (rx_queue_id < dev->data->nb_rx_queues) {
2023                 rxq = dev->data->rx_queues[rx_queue_id];
2024
2025                 /*
2026                 * rx_queue_id is queue id aplication refers to, while
2027                 * rxq->reg_idx is the real queue index.
2028                 */
2029                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2030
2031                 if (err) {
2032                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2033                                     rx_queue_id);
2034                         return err;
2035                 }
2036                 i40e_rx_queue_release_mbufs(rxq);
2037                 i40e_reset_rx_queue(rxq);
2038                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2039         }
2040
2041         return 0;
2042 }
2043
2044 int
2045 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2046 {
2047         int err = -1;
2048         struct i40e_tx_queue *txq;
2049         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050
2051         PMD_INIT_FUNC_TRACE();
2052
2053         if (tx_queue_id < dev->data->nb_tx_queues) {
2054                 txq = dev->data->tx_queues[tx_queue_id];
2055
2056                 /*
2057                 * tx_queue_id is queue id aplication refers to, while
2058                 * rxq->reg_idx is the real queue index.
2059                 */
2060                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2061                 if (err)
2062                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2063                                     tx_queue_id);
2064                 else
2065                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2066         }
2067
2068         return err;
2069 }
2070
2071 int
2072 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2073 {
2074         struct i40e_tx_queue *txq;
2075         int err;
2076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077
2078         if (tx_queue_id < dev->data->nb_tx_queues) {
2079                 txq = dev->data->tx_queues[tx_queue_id];
2080
2081                 /*
2082                 * tx_queue_id is queue id aplication refers to, while
2083                 * txq->reg_idx is the real queue index.
2084                 */
2085                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2086
2087                 if (err) {
2088                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2089                                     tx_queue_id);
2090                         return err;
2091                 }
2092
2093                 i40e_tx_queue_release_mbufs(txq);
2094                 i40e_reset_tx_queue(txq);
2095                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2096         }
2097
2098         return 0;
2099 }
2100
2101 const uint32_t *
2102 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2103 {
2104         static const uint32_t ptypes[] = {
2105                 /* refers to i40e_rxd_pkt_type_mapping() */
2106                 RTE_PTYPE_L2_ETHER,
2107                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2108                 RTE_PTYPE_L2_ETHER_LLDP,
2109                 RTE_PTYPE_L2_ETHER_ARP,
2110                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2111                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2112                 RTE_PTYPE_L4_FRAG,
2113                 RTE_PTYPE_L4_ICMP,
2114                 RTE_PTYPE_L4_NONFRAG,
2115                 RTE_PTYPE_L4_SCTP,
2116                 RTE_PTYPE_L4_TCP,
2117                 RTE_PTYPE_L4_UDP,
2118                 RTE_PTYPE_TUNNEL_GRENAT,
2119                 RTE_PTYPE_TUNNEL_IP,
2120                 RTE_PTYPE_INNER_L2_ETHER,
2121                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2122                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2123                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2124                 RTE_PTYPE_INNER_L4_FRAG,
2125                 RTE_PTYPE_INNER_L4_ICMP,
2126                 RTE_PTYPE_INNER_L4_NONFRAG,
2127                 RTE_PTYPE_INNER_L4_SCTP,
2128                 RTE_PTYPE_INNER_L4_TCP,
2129                 RTE_PTYPE_INNER_L4_UDP,
2130                 RTE_PTYPE_UNKNOWN
2131         };
2132
2133         if (dev->rx_pkt_burst == i40e_recv_pkts ||
2134 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2135             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2136 #endif
2137             dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2138                 return ptypes;
2139         return NULL;
2140 }
2141
2142 int
2143 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2144                         uint16_t queue_idx,
2145                         uint16_t nb_desc,
2146                         unsigned int socket_id,
2147                         const struct rte_eth_rxconf *rx_conf,
2148                         struct rte_mempool *mp)
2149 {
2150         struct i40e_vsi *vsi;
2151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153         struct i40e_adapter *ad =
2154                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2155         struct i40e_rx_queue *rxq;
2156         const struct rte_memzone *rz;
2157         uint32_t ring_size;
2158         uint16_t len, i;
2159         uint16_t base, bsf, tc_mapping;
2160         int use_def_burst_func = 1;
2161
2162         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2163                 struct i40e_vf *vf =
2164                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2165                 vsi = &vf->vsi;
2166         } else
2167                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2168
2169         if (vsi == NULL) {
2170                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2171                             "index exceeds the maximum");
2172                 return I40E_ERR_PARAM;
2173         }
2174         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2175                         (nb_desc > I40E_MAX_RING_DESC) ||
2176                         (nb_desc < I40E_MIN_RING_DESC)) {
2177                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2178                             "invalid", nb_desc);
2179                 return I40E_ERR_PARAM;
2180         }
2181
2182         /* Free memory if needed */
2183         if (dev->data->rx_queues[queue_idx]) {
2184                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2185                 dev->data->rx_queues[queue_idx] = NULL;
2186         }
2187
2188         /* Allocate the rx queue data structure */
2189         rxq = rte_zmalloc_socket("i40e rx queue",
2190                                  sizeof(struct i40e_rx_queue),
2191                                  RTE_CACHE_LINE_SIZE,
2192                                  socket_id);
2193         if (!rxq) {
2194                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2195                             "rx queue data structure");
2196                 return -ENOMEM;
2197         }
2198         rxq->mp = mp;
2199         rxq->nb_rx_desc = nb_desc;
2200         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2201         rxq->queue_id = queue_idx;
2202         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2203                 rxq->reg_idx = queue_idx;
2204         else /* PF device */
2205                 rxq->reg_idx = vsi->base_queue +
2206                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2207
2208         rxq->port_id = dev->data->port_id;
2209         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2210                                                         0 : ETHER_CRC_LEN);
2211         rxq->drop_en = rx_conf->rx_drop_en;
2212         rxq->vsi = vsi;
2213         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2214
2215         /* Allocate the maximun number of RX ring hardware descriptor. */
2216         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2217         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2218         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2219                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2220         if (!rz) {
2221                 i40e_dev_rx_queue_release(rxq);
2222                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2223                 return -ENOMEM;
2224         }
2225
2226         /* Zero all the descriptors in the ring. */
2227         memset(rz->addr, 0, ring_size);
2228
2229         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2230         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2231
2232 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2233         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2234 #else
2235         len = nb_desc;
2236 #endif
2237
2238         /* Allocate the software ring. */
2239         rxq->sw_ring =
2240                 rte_zmalloc_socket("i40e rx sw ring",
2241                                    sizeof(struct i40e_rx_entry) * len,
2242                                    RTE_CACHE_LINE_SIZE,
2243                                    socket_id);
2244         if (!rxq->sw_ring) {
2245                 i40e_dev_rx_queue_release(rxq);
2246                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2247                 return -ENOMEM;
2248         }
2249
2250         i40e_reset_rx_queue(rxq);
2251         rxq->q_set = TRUE;
2252         dev->data->rx_queues[queue_idx] = rxq;
2253
2254         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2255
2256         if (!use_def_burst_func) {
2257 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2258                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2259                              "satisfied. Rx Burst Bulk Alloc function will be "
2260                              "used on port=%d, queue=%d.",
2261                              rxq->port_id, rxq->queue_id);
2262 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2263         } else {
2264                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2265                              "not satisfied, Scattered Rx is requested, "
2266                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2267                              "not enabled on port=%d, queue=%d.",
2268                              rxq->port_id, rxq->queue_id);
2269                 ad->rx_bulk_alloc_allowed = false;
2270         }
2271
2272         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2273                 if (!(vsi->enabled_tc & (1 << i)))
2274                         continue;
2275                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2276                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2277                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2278                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2279                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2280
2281                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2282                         rxq->dcb_tc = i;
2283         }
2284
2285         return 0;
2286 }
2287
2288 void
2289 i40e_dev_rx_queue_release(void *rxq)
2290 {
2291         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2292
2293         if (!q) {
2294                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2295                 return;
2296         }
2297
2298         i40e_rx_queue_release_mbufs(q);
2299         rte_free(q->sw_ring);
2300         rte_free(q);
2301 }
2302
2303 uint32_t
2304 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2305 {
2306 #define I40E_RXQ_SCAN_INTERVAL 4
2307         volatile union i40e_rx_desc *rxdp;
2308         struct i40e_rx_queue *rxq;
2309         uint16_t desc = 0;
2310
2311         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2312                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2313                 return 0;
2314         }
2315
2316         rxq = dev->data->rx_queues[rx_queue_id];
2317         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2318         while ((desc < rxq->nb_rx_desc) &&
2319                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2320                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2321                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2322                 /**
2323                  * Check the DD bit of a rx descriptor of each 4 in a group,
2324                  * to avoid checking too frequently and downgrading performance
2325                  * too much.
2326                  */
2327                 desc += I40E_RXQ_SCAN_INTERVAL;
2328                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2329                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2330                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2331                                         desc - rxq->nb_rx_desc]);
2332         }
2333
2334         return desc;
2335 }
2336
2337 int
2338 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2339 {
2340         volatile union i40e_rx_desc *rxdp;
2341         struct i40e_rx_queue *rxq = rx_queue;
2342         uint16_t desc;
2343         int ret;
2344
2345         if (unlikely(offset >= rxq->nb_rx_desc)) {
2346                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2347                 return 0;
2348         }
2349
2350         desc = rxq->rx_tail + offset;
2351         if (desc >= rxq->nb_rx_desc)
2352                 desc -= rxq->nb_rx_desc;
2353
2354         rxdp = &(rxq->rx_ring[desc]);
2355
2356         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2357                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2358                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2359
2360         return ret;
2361 }
2362
2363 int
2364 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2365                         uint16_t queue_idx,
2366                         uint16_t nb_desc,
2367                         unsigned int socket_id,
2368                         const struct rte_eth_txconf *tx_conf)
2369 {
2370         struct i40e_vsi *vsi;
2371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2373         struct i40e_tx_queue *txq;
2374         const struct rte_memzone *tz;
2375         uint32_t ring_size;
2376         uint16_t tx_rs_thresh, tx_free_thresh;
2377         uint16_t i, base, bsf, tc_mapping;
2378
2379         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2380                 struct i40e_vf *vf =
2381                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2382                 vsi = &vf->vsi;
2383         } else
2384                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2385
2386         if (vsi == NULL) {
2387                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2388                             "exceeds the maximum", queue_idx);
2389                 return I40E_ERR_PARAM;
2390         }
2391
2392         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2393                         (nb_desc > I40E_MAX_RING_DESC) ||
2394                         (nb_desc < I40E_MIN_RING_DESC)) {
2395                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2396                             "invalid", nb_desc);
2397                 return I40E_ERR_PARAM;
2398         }
2399
2400         /**
2401          * The following two parameters control the setting of the RS bit on
2402          * transmit descriptors. TX descriptors will have their RS bit set
2403          * after txq->tx_rs_thresh descriptors have been used. The TX
2404          * descriptor ring will be cleaned after txq->tx_free_thresh
2405          * descriptors are used or if the number of descriptors required to
2406          * transmit a packet is greater than the number of free TX descriptors.
2407          *
2408          * The following constraints must be satisfied:
2409          *  - tx_rs_thresh must be greater than 0.
2410          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2411          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2412          *  - tx_rs_thresh must be a divisor of the ring size.
2413          *  - tx_free_thresh must be greater than 0.
2414          *  - tx_free_thresh must be less than the size of the ring minus 3.
2415          *
2416          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2417          * race condition, hence the maximum threshold constraints. When set
2418          * to zero use default values.
2419          */
2420         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2421                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2422         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2423                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2424         if (tx_rs_thresh >= (nb_desc - 2)) {
2425                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2426                              "number of TX descriptors minus 2. "
2427                              "(tx_rs_thresh=%u port=%d queue=%d)",
2428                              (unsigned int)tx_rs_thresh,
2429                              (int)dev->data->port_id,
2430                              (int)queue_idx);
2431                 return I40E_ERR_PARAM;
2432         }
2433         if (tx_free_thresh >= (nb_desc - 3)) {
2434                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2435                              "tx_free_thresh must be less than the "
2436                              "number of TX descriptors minus 3. "
2437                              "(tx_free_thresh=%u port=%d queue=%d)",
2438                              (unsigned int)tx_free_thresh,
2439                              (int)dev->data->port_id,
2440                              (int)queue_idx);
2441                 return I40E_ERR_PARAM;
2442         }
2443         if (tx_rs_thresh > tx_free_thresh) {
2444                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2445                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2446                              " tx_rs_thresh=%u port=%d queue=%d)",
2447                              (unsigned int)tx_free_thresh,
2448                              (unsigned int)tx_rs_thresh,
2449                              (int)dev->data->port_id,
2450                              (int)queue_idx);
2451                 return I40E_ERR_PARAM;
2452         }
2453         if ((nb_desc % tx_rs_thresh) != 0) {
2454                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2455                              "number of TX descriptors. (tx_rs_thresh=%u"
2456                              " port=%d queue=%d)",
2457                              (unsigned int)tx_rs_thresh,
2458                              (int)dev->data->port_id,
2459                              (int)queue_idx);
2460                 return I40E_ERR_PARAM;
2461         }
2462         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2463                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2464                              "tx_rs_thresh is greater than 1. "
2465                              "(tx_rs_thresh=%u port=%d queue=%d)",
2466                              (unsigned int)tx_rs_thresh,
2467                              (int)dev->data->port_id,
2468                              (int)queue_idx);
2469                 return I40E_ERR_PARAM;
2470         }
2471
2472         /* Free memory if needed. */
2473         if (dev->data->tx_queues[queue_idx]) {
2474                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2475                 dev->data->tx_queues[queue_idx] = NULL;
2476         }
2477
2478         /* Allocate the TX queue data structure. */
2479         txq = rte_zmalloc_socket("i40e tx queue",
2480                                   sizeof(struct i40e_tx_queue),
2481                                   RTE_CACHE_LINE_SIZE,
2482                                   socket_id);
2483         if (!txq) {
2484                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2485                             "tx queue structure");
2486                 return -ENOMEM;
2487         }
2488
2489         /* Allocate TX hardware ring descriptors. */
2490         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2491         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2492         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2493                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2494         if (!tz) {
2495                 i40e_dev_tx_queue_release(txq);
2496                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2497                 return -ENOMEM;
2498         }
2499
2500         txq->nb_tx_desc = nb_desc;
2501         txq->tx_rs_thresh = tx_rs_thresh;
2502         txq->tx_free_thresh = tx_free_thresh;
2503         txq->pthresh = tx_conf->tx_thresh.pthresh;
2504         txq->hthresh = tx_conf->tx_thresh.hthresh;
2505         txq->wthresh = tx_conf->tx_thresh.wthresh;
2506         txq->queue_id = queue_idx;
2507         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2508                 txq->reg_idx = queue_idx;
2509         else /* PF device */
2510                 txq->reg_idx = vsi->base_queue +
2511                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2512
2513         txq->port_id = dev->data->port_id;
2514         txq->txq_flags = tx_conf->txq_flags;
2515         txq->vsi = vsi;
2516         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2517
2518         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2519         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2520
2521         /* Allocate software ring */
2522         txq->sw_ring =
2523                 rte_zmalloc_socket("i40e tx sw ring",
2524                                    sizeof(struct i40e_tx_entry) * nb_desc,
2525                                    RTE_CACHE_LINE_SIZE,
2526                                    socket_id);
2527         if (!txq->sw_ring) {
2528                 i40e_dev_tx_queue_release(txq);
2529                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2530                 return -ENOMEM;
2531         }
2532
2533         i40e_reset_tx_queue(txq);
2534         txq->q_set = TRUE;
2535         dev->data->tx_queues[queue_idx] = txq;
2536
2537         /* Use a simple TX queue without offloads or multi segs if possible */
2538         i40e_set_tx_function_flag(dev, txq);
2539
2540         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2541                 if (!(vsi->enabled_tc & (1 << i)))
2542                         continue;
2543                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2544                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2545                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2546                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2547                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2548
2549                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2550                         txq->dcb_tc = i;
2551         }
2552
2553         return 0;
2554 }
2555
2556 void
2557 i40e_dev_tx_queue_release(void *txq)
2558 {
2559         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2560
2561         if (!q) {
2562                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2563                 return;
2564         }
2565
2566         i40e_tx_queue_release_mbufs(q);
2567         rte_free(q->sw_ring);
2568         rte_free(q);
2569 }
2570
2571 const struct rte_memzone *
2572 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2573 {
2574         const struct rte_memzone *mz;
2575
2576         mz = rte_memzone_lookup(name);
2577         if (mz)
2578                 return mz;
2579
2580         if (rte_xen_dom0_supported())
2581                 mz = rte_memzone_reserve_bounded(name, len,
2582                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2583         else
2584                 mz = rte_memzone_reserve_aligned(name, len,
2585                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2586         return mz;
2587 }
2588
2589 void
2590 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2591 {
2592         uint16_t i;
2593
2594         /* SSE Vector driver has a different way of releasing mbufs. */
2595         if (rxq->rx_using_sse) {
2596                 i40e_rx_queue_release_mbufs_vec(rxq);
2597                 return;
2598         }
2599
2600         if (!rxq || !rxq->sw_ring) {
2601                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2602                 return;
2603         }
2604
2605         for (i = 0; i < rxq->nb_rx_desc; i++) {
2606                 if (rxq->sw_ring[i].mbuf) {
2607                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2608                         rxq->sw_ring[i].mbuf = NULL;
2609                 }
2610         }
2611 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2612         if (rxq->rx_nb_avail == 0)
2613                 return;
2614         for (i = 0; i < rxq->rx_nb_avail; i++) {
2615                 struct rte_mbuf *mbuf;
2616
2617                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2618                 rte_pktmbuf_free_seg(mbuf);
2619         }
2620         rxq->rx_nb_avail = 0;
2621 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2622 }
2623
2624 void
2625 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2626 {
2627         unsigned i;
2628         uint16_t len;
2629
2630         if (!rxq) {
2631                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2632                 return;
2633         }
2634
2635 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2636         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2637                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2638         else
2639 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2640                 len = rxq->nb_rx_desc;
2641
2642         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2643                 ((volatile char *)rxq->rx_ring)[i] = 0;
2644
2645 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2646         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2647         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2648                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2649
2650         rxq->rx_nb_avail = 0;
2651         rxq->rx_next_avail = 0;
2652         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2653 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2654         rxq->rx_tail = 0;
2655         rxq->nb_rx_hold = 0;
2656         rxq->pkt_first_seg = NULL;
2657         rxq->pkt_last_seg = NULL;
2658
2659         rxq->rxrearm_start = 0;
2660         rxq->rxrearm_nb = 0;
2661 }
2662
2663 void
2664 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2665 {
2666         uint16_t i;
2667
2668         if (!txq || !txq->sw_ring) {
2669                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2670                 return;
2671         }
2672
2673         for (i = 0; i < txq->nb_tx_desc; i++) {
2674                 if (txq->sw_ring[i].mbuf) {
2675                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2676                         txq->sw_ring[i].mbuf = NULL;
2677                 }
2678         }
2679 }
2680
2681 void
2682 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2683 {
2684         struct i40e_tx_entry *txe;
2685         uint16_t i, prev, size;
2686
2687         if (!txq) {
2688                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2689                 return;
2690         }
2691
2692         txe = txq->sw_ring;
2693         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2694         for (i = 0; i < size; i++)
2695                 ((volatile char *)txq->tx_ring)[i] = 0;
2696
2697         prev = (uint16_t)(txq->nb_tx_desc - 1);
2698         for (i = 0; i < txq->nb_tx_desc; i++) {
2699                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2700
2701                 txd->cmd_type_offset_bsz =
2702                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2703                 txe[i].mbuf =  NULL;
2704                 txe[i].last_id = i;
2705                 txe[prev].next_id = i;
2706                 prev = i;
2707         }
2708
2709         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2710         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2711
2712         txq->tx_tail = 0;
2713         txq->nb_tx_used = 0;
2714
2715         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2716         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2717 }
2718
2719 /* Init the TX queue in hardware */
2720 int
2721 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2722 {
2723         enum i40e_status_code err = I40E_SUCCESS;
2724         struct i40e_vsi *vsi = txq->vsi;
2725         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2726         uint16_t pf_q = txq->reg_idx;
2727         struct i40e_hmc_obj_txq tx_ctx;
2728         uint32_t qtx_ctl;
2729
2730         /* clear the context structure first */
2731         memset(&tx_ctx, 0, sizeof(tx_ctx));
2732         tx_ctx.new_context = 1;
2733         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2734         tx_ctx.qlen = txq->nb_tx_desc;
2735
2736 #ifdef RTE_LIBRTE_IEEE1588
2737         tx_ctx.timesync_ena = 1;
2738 #endif
2739         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2740         if (vsi->type == I40E_VSI_FDIR)
2741                 tx_ctx.fd_ena = TRUE;
2742
2743         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2744         if (err != I40E_SUCCESS) {
2745                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2746                 return err;
2747         }
2748
2749         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2750         if (err != I40E_SUCCESS) {
2751                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2752                 return err;
2753         }
2754
2755         /* Now associate this queue with this PCI function */
2756         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2757         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2758                                         I40E_QTX_CTL_PF_INDX_MASK);
2759         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2760         I40E_WRITE_FLUSH(hw);
2761
2762         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2763
2764         return err;
2765 }
2766
2767 int
2768 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2769 {
2770         struct i40e_rx_entry *rxe = rxq->sw_ring;
2771         uint64_t dma_addr;
2772         uint16_t i;
2773
2774         for (i = 0; i < rxq->nb_rx_desc; i++) {
2775                 volatile union i40e_rx_desc *rxd;
2776                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2777
2778                 if (unlikely(!mbuf)) {
2779                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2780                         return -ENOMEM;
2781                 }
2782
2783                 rte_mbuf_refcnt_set(mbuf, 1);
2784                 mbuf->next = NULL;
2785                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2786                 mbuf->nb_segs = 1;
2787                 mbuf->port = rxq->port_id;
2788
2789                 dma_addr =
2790                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2791
2792                 rxd = &rxq->rx_ring[i];
2793                 rxd->read.pkt_addr = dma_addr;
2794                 rxd->read.hdr_addr = 0;
2795 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2796                 rxd->read.rsvd1 = 0;
2797                 rxd->read.rsvd2 = 0;
2798 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2799
2800                 rxe[i].mbuf = mbuf;
2801         }
2802
2803         return 0;
2804 }
2805
2806 /*
2807  * Calculate the buffer length, and check the jumbo frame
2808  * and maximum packet length.
2809  */
2810 static int
2811 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2812 {
2813         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2814         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2815         struct rte_eth_dev_data *data = pf->dev_data;
2816         uint16_t buf_size, len;
2817
2818         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2819                 RTE_PKTMBUF_HEADROOM);
2820
2821         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2822                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2823         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2824                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2825                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2826                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2827                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2828                 rxq->hs_mode = i40e_header_split_enabled;
2829                 break;
2830         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2831         default:
2832                 rxq->rx_hdr_len = 0;
2833                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2834                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2835                 rxq->hs_mode = i40e_header_split_none;
2836                 break;
2837         }
2838
2839         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2840         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2841         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2842                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2843                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2844                         PMD_DRV_LOG(ERR, "maximum packet length must "
2845                                     "be larger than %u and smaller than %u,"
2846                                     "as jumbo frame is enabled",
2847                                     (uint32_t)ETHER_MAX_LEN,
2848                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2849                         return I40E_ERR_CONFIG;
2850                 }
2851         } else {
2852                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2853                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2854                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2855                                     "larger than %u and smaller than %u, "
2856                                     "as jumbo frame is disabled",
2857                                     (uint32_t)ETHER_MIN_LEN,
2858                                     (uint32_t)ETHER_MAX_LEN);
2859                         return I40E_ERR_CONFIG;
2860                 }
2861         }
2862
2863         return 0;
2864 }
2865
2866 /* Init the RX queue in hardware */
2867 int
2868 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2869 {
2870         int err = I40E_SUCCESS;
2871         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2872         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2873         uint16_t pf_q = rxq->reg_idx;
2874         uint16_t buf_size;
2875         struct i40e_hmc_obj_rxq rx_ctx;
2876
2877         err = i40e_rx_queue_config(rxq);
2878         if (err < 0) {
2879                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2880                 return err;
2881         }
2882
2883         /* Clear the context structure first */
2884         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2885         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2886         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2887
2888         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2889         rx_ctx.qlen = rxq->nb_rx_desc;
2890 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2891         rx_ctx.dsize = 1;
2892 #endif
2893         rx_ctx.dtype = rxq->hs_mode;
2894         if (rxq->hs_mode)
2895                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2896         else
2897                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2898         rx_ctx.rxmax = rxq->max_pkt_len;
2899         rx_ctx.tphrdesc_ena = 1;
2900         rx_ctx.tphwdesc_ena = 1;
2901         rx_ctx.tphdata_ena = 1;
2902         rx_ctx.tphhead_ena = 1;
2903         rx_ctx.lrxqthresh = 2;
2904         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2905         rx_ctx.l2tsel = 1;
2906         rx_ctx.showiv = 1;
2907         rx_ctx.prefena = 1;
2908
2909         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2910         if (err != I40E_SUCCESS) {
2911                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2912                 return err;
2913         }
2914         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2915         if (err != I40E_SUCCESS) {
2916                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2917                 return err;
2918         }
2919
2920         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2921
2922         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2923                 RTE_PKTMBUF_HEADROOM);
2924
2925         /* Check if scattered RX needs to be used. */
2926         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2927                 dev_data->scattered_rx = 1;
2928         }
2929
2930         /* Init the RX tail regieter. */
2931         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2932
2933         return 0;
2934 }
2935
2936 void
2937 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2938 {
2939         uint16_t i;
2940
2941         PMD_INIT_FUNC_TRACE();
2942
2943         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2944                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2945                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2946         }
2947
2948         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2949                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2950                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2951         }
2952 }
2953
2954 void
2955 i40e_dev_free_queues(struct rte_eth_dev *dev)
2956 {
2957         uint16_t i;
2958
2959         PMD_INIT_FUNC_TRACE();
2960
2961         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2962                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2963                 dev->data->rx_queues[i] = NULL;
2964         }
2965         dev->data->nb_rx_queues = 0;
2966
2967         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2968                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2969                 dev->data->tx_queues[i] = NULL;
2970         }
2971         dev->data->nb_tx_queues = 0;
2972 }
2973
2974 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2975 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2976
2977 enum i40e_status_code
2978 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2979 {
2980         struct i40e_tx_queue *txq;
2981         const struct rte_memzone *tz = NULL;
2982         uint32_t ring_size;
2983         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2984
2985         if (!pf) {
2986                 PMD_DRV_LOG(ERR, "PF is not available");
2987                 return I40E_ERR_BAD_PTR;
2988         }
2989
2990         /* Allocate the TX queue data structure. */
2991         txq = rte_zmalloc_socket("i40e fdir tx queue",
2992                                   sizeof(struct i40e_tx_queue),
2993                                   RTE_CACHE_LINE_SIZE,
2994                                   SOCKET_ID_ANY);
2995         if (!txq) {
2996                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2997                                         "tx queue structure.");
2998                 return I40E_ERR_NO_MEMORY;
2999         }
3000
3001         /* Allocate TX hardware ring descriptors. */
3002         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3003         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3004
3005         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3006                                       I40E_FDIR_QUEUE_ID, ring_size,
3007                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3008         if (!tz) {
3009                 i40e_dev_tx_queue_release(txq);
3010                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3011                 return I40E_ERR_NO_MEMORY;
3012         }
3013
3014         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3015         txq->queue_id = I40E_FDIR_QUEUE_ID;
3016         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3017         txq->vsi = pf->fdir.fdir_vsi;
3018
3019         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3020         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3021         /*
3022          * don't need to allocate software ring and reset for the fdir
3023          * program queue just set the queue has been configured.
3024          */
3025         txq->q_set = TRUE;
3026         pf->fdir.txq = txq;
3027
3028         return I40E_SUCCESS;
3029 }
3030
3031 enum i40e_status_code
3032 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3033 {
3034         struct i40e_rx_queue *rxq;
3035         const struct rte_memzone *rz = NULL;
3036         uint32_t ring_size;
3037         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3038
3039         if (!pf) {
3040                 PMD_DRV_LOG(ERR, "PF is not available");
3041                 return I40E_ERR_BAD_PTR;
3042         }
3043
3044         /* Allocate the RX queue data structure. */
3045         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3046                                   sizeof(struct i40e_rx_queue),
3047                                   RTE_CACHE_LINE_SIZE,
3048                                   SOCKET_ID_ANY);
3049         if (!rxq) {
3050                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3051                                         "rx queue structure.");
3052                 return I40E_ERR_NO_MEMORY;
3053         }
3054
3055         /* Allocate RX hardware ring descriptors. */
3056         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3057         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3058
3059         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3060                                       I40E_FDIR_QUEUE_ID, ring_size,
3061                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3062         if (!rz) {
3063                 i40e_dev_rx_queue_release(rxq);
3064                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3065                 return I40E_ERR_NO_MEMORY;
3066         }
3067
3068         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3069         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3070         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3071         rxq->vsi = pf->fdir.fdir_vsi;
3072
3073         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3074         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3075
3076         /*
3077          * Don't need to allocate software ring and reset for the fdir
3078          * rx queue, just set the queue has been configured.
3079          */
3080         rxq->q_set = TRUE;
3081         pf->fdir.rxq = rxq;
3082
3083         return I40E_SUCCESS;
3084 }
3085
3086 void
3087 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3088         struct rte_eth_rxq_info *qinfo)
3089 {
3090         struct i40e_rx_queue *rxq;
3091
3092         rxq = dev->data->rx_queues[queue_id];
3093
3094         qinfo->mp = rxq->mp;
3095         qinfo->scattered_rx = dev->data->scattered_rx;
3096         qinfo->nb_desc = rxq->nb_rx_desc;
3097
3098         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3099         qinfo->conf.rx_drop_en = rxq->drop_en;
3100         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3101 }
3102
3103 void
3104 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3105         struct rte_eth_txq_info *qinfo)
3106 {
3107         struct i40e_tx_queue *txq;
3108
3109         txq = dev->data->tx_queues[queue_id];
3110
3111         qinfo->nb_desc = txq->nb_tx_desc;
3112
3113         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3114         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3115         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3116
3117         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3118         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3119         qinfo->conf.txq_flags = txq->txq_flags;
3120         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3121 }
3122
3123 void __attribute__((cold))
3124 i40e_set_rx_function(struct rte_eth_dev *dev)
3125 {
3126         struct i40e_adapter *ad =
3127                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3128         uint16_t rx_using_sse, i;
3129         /* In order to allow Vector Rx there are a few configuration
3130          * conditions to be met and Rx Bulk Allocation should be allowed.
3131          */
3132         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3133                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3134                     !ad->rx_bulk_alloc_allowed) {
3135                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3136                                      " Vector Rx preconditions",
3137                                      dev->data->port_id);
3138
3139                         ad->rx_vec_allowed = false;
3140                 }
3141                 if (ad->rx_vec_allowed) {
3142                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3143                                 struct i40e_rx_queue *rxq =
3144                                         dev->data->rx_queues[i];
3145
3146                                 if (i40e_rxq_vec_setup(rxq)) {
3147                                         ad->rx_vec_allowed = false;
3148                                         break;
3149                                 }
3150                         }
3151                 }
3152         }
3153
3154         if (dev->data->scattered_rx) {
3155                 /* Set the non-LRO scattered callback: there are Vector and
3156                  * single allocation versions.
3157                  */
3158                 if (ad->rx_vec_allowed) {
3159                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3160                                             "callback (port=%d).",
3161                                      dev->data->port_id);
3162
3163                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3164                 } else {
3165                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3166                                            "allocation callback (port=%d).",
3167                                      dev->data->port_id);
3168                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3169                 }
3170         /* If parameters allow we are going to choose between the following
3171          * callbacks:
3172          *    - Vector
3173          *    - Bulk Allocation
3174          *    - Single buffer allocation (the simplest one)
3175          */
3176         } else if (ad->rx_vec_allowed) {
3177                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3178                                     "burst size no less than %d (port=%d).",
3179                              RTE_I40E_DESCS_PER_LOOP,
3180                              dev->data->port_id);
3181
3182                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3183         } else if (ad->rx_bulk_alloc_allowed) {
3184                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3185                                     "satisfied. Rx Burst Bulk Alloc function "
3186                                     "will be used on port=%d.",
3187                              dev->data->port_id);
3188
3189                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3190         } else {
3191                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3192                                     "satisfied, or Scattered Rx is requested "
3193                                     "(port=%d).",
3194                              dev->data->port_id);
3195
3196                 dev->rx_pkt_burst = i40e_recv_pkts;
3197         }
3198
3199         /* Propagate information about RX function choice through all queues. */
3200         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3201                 rx_using_sse =
3202                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3203                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3204
3205                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3206                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3207
3208                         rxq->rx_using_sse = rx_using_sse;
3209                 }
3210         }
3211 }
3212
3213 void __attribute__((cold))
3214 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3215 {
3216         struct i40e_adapter *ad =
3217                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3218
3219         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3220         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3221                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3222                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3223                         PMD_INIT_LOG(DEBUG, "Vector tx"
3224                                      " can be enabled on this txq.");
3225
3226                 } else {
3227                         ad->tx_vec_allowed = false;
3228                 }
3229         } else {
3230                 ad->tx_simple_allowed = false;
3231         }
3232 }
3233
3234 void __attribute__((cold))
3235 i40e_set_tx_function(struct rte_eth_dev *dev)
3236 {
3237         struct i40e_adapter *ad =
3238                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3239         int i;
3240
3241         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3242                 if (ad->tx_vec_allowed) {
3243                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3244                                 struct i40e_tx_queue *txq =
3245                                         dev->data->tx_queues[i];
3246
3247                                 if (i40e_txq_vec_setup(txq)) {
3248                                         ad->tx_vec_allowed = false;
3249                                         break;
3250                                 }
3251                         }
3252                 }
3253         }
3254
3255         if (ad->tx_simple_allowed) {
3256                 if (ad->tx_vec_allowed) {
3257                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3258                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3259                 } else {
3260                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3261                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3262                 }
3263         } else {
3264                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3265                 dev->tx_pkt_burst = i40e_xmit_pkts;
3266         }
3267 }
3268
3269 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3270 int __attribute__((weak))
3271 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3272 {
3273         return -1;
3274 }
3275
3276 uint16_t __attribute__((weak))
3277 i40e_recv_pkts_vec(
3278         void __rte_unused *rx_queue,
3279         struct rte_mbuf __rte_unused **rx_pkts,
3280         uint16_t __rte_unused nb_pkts)
3281 {
3282         return 0;
3283 }
3284
3285 uint16_t __attribute__((weak))
3286 i40e_recv_scattered_pkts_vec(
3287         void __rte_unused *rx_queue,
3288         struct rte_mbuf __rte_unused **rx_pkts,
3289         uint16_t __rte_unused nb_pkts)
3290 {
3291         return 0;
3292 }
3293
3294 int __attribute__((weak))
3295 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3296 {
3297         return -1;
3298 }
3299
3300 int __attribute__((weak))
3301 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3302 {
3303         return -1;
3304 }
3305
3306 void __attribute__((weak))
3307 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3308 {
3309         return;
3310 }
3311
3312 uint16_t __attribute__((weak))
3313 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3314                    struct rte_mbuf __rte_unused **tx_pkts,
3315                    uint16_t __rte_unused nb_pkts)
3316 {
3317         return 0;
3318 }