drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "i40e_logs.h"
  29 #include "base/i40e_prototype.h"
  30 #include "base/i40e_type.h"
  31 #include "i40e_ethdev.h"
  32 #include "i40e_rxtx.h"
  33
  34 #define DEFAULT_TX_RS_THRESH   32
  35 #define DEFAULT_TX_FREE_THRESH 32
  36
  37 #define I40E_TX_MAX_BURST  32
  38
  39 #define I40E_DMA_MEM_ALIGN 4096
  40
  41 /* Base address of the HW descriptor ring should be 128B aligned. */
  42 #define I40E_RING_BASE_ALIGN    128
  43
  44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  45
  46 #ifdef RTE_LIBRTE_IEEE1588
  47 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  48 #else
  49 #define I40E_TX_IEEE1588_TMST 0
  50 #endif
  51
  52 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG |                 \
  56                 PKT_TX_OUTER_IP_CKSUM)
  57
  58 #define I40E_TX_OFFLOAD_MASK (  \
  59                 PKT_TX_OUTER_IPV4 |     \
  60                 PKT_TX_OUTER_IPV6 |     \
  61                 PKT_TX_IPV4 |           \
  62                 PKT_TX_IPV6 |           \
  63                 PKT_TX_IP_CKSUM |       \
  64                 PKT_TX_L4_MASK |        \
  65                 PKT_TX_OUTER_IP_CKSUM | \
  66                 PKT_TX_TCP_SEG |        \
  67                 PKT_TX_QINQ_PKT |       \
  68                 PKT_TX_VLAN_PKT |       \
  69                 PKT_TX_TUNNEL_MASK |    \
  70                 I40E_TX_IEEE1588_TMST)
  71
  72 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  73                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  74
  75 #define I40E_TX_OFFLOAD_SIMPLE_SUP_MASK ( \
  76                 PKT_TX_IPV4 | \
  77                 PKT_TX_IPV6 | \
  78                 PKT_TX_OUTER_IPV4 | \
  79                 PKT_TX_OUTER_IPV6)
  80
  81 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
  82                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
  83
  84 int
  85 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  86 {
  87         struct i40e_rx_queue *rxq = rx_queue;
  88         volatile union i40e_rx_desc *rxdp;
  89         uint16_t desc;
  90
  91         desc = rxq->rx_tail;
  92         rxdp = &rxq->rx_ring[desc];
  93         /* watch for changes in status bit */
  94         pmc->addr = &rxdp->wb.qword1.status_error_len;
  95
  96         /*
  97          * we expect the DD bit to be set to 1 if this descriptor was already
  98          * written to.
  99          */
 100         pmc->val = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 101         pmc->mask = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 102
 103         /* registers are 64-bit */
 104         pmc->size = sizeof(uint64_t);
 105
 106         return 0;
 107 }
 108
 109 static inline void
 110 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 111 {
 112         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 113                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 114                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 115                 mb->vlan_tci =
 116                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 117                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 118                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 119         } else {
 120                 mb->vlan_tci = 0;
 121         }
 122 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 123         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 124                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 125                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
 126                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
 127                 mb->vlan_tci_outer = mb->vlan_tci;
 128                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 129                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 130                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 131                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 132         } else {
 133                 mb->vlan_tci_outer = 0;
 134         }
 135 #endif
 136         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 137                    mb->vlan_tci, mb->vlan_tci_outer);
 138 }
 139
 140 /* Translate the rx descriptor status to pkt flags */
 141 static inline uint64_t
 142 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 143 {
 144         uint64_t flags;
 145
 146         /* Check if RSS_HASH */
 147         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 148                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 149                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 150
 151         /* Check if FDIR Match */
 152         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 153                                                         PKT_RX_FDIR : 0);
 154
 155         return flags;
 156 }
 157
 158 static inline uint64_t
 159 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 160 {
 161         uint64_t flags = 0;
 162         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 163
 164 #define I40E_RX_ERR_BITS 0x3f
 165         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 166                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 167                 return flags;
 168         }
 169
 170         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 171                 flags |= PKT_RX_IP_CKSUM_BAD;
 172         else
 173                 flags |= PKT_RX_IP_CKSUM_GOOD;
 174
 175         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 176                 flags |= PKT_RX_L4_CKSUM_BAD;
 177         else
 178                 flags |= PKT_RX_L4_CKSUM_GOOD;
 179
 180         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 181                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
 182
 183         return flags;
 184 }
 185
 186 /* Function to check and set the ieee1588 timesync index and get the
 187  * appropriate flags.
 188  */
 189 #ifdef RTE_LIBRTE_IEEE1588
 190 static inline uint64_t
 191 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 192 {
 193         uint64_t pkt_flags = 0;
 194         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 195                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 196                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 197
 198         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 199                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 200                 pkt_flags = PKT_RX_IEEE1588_PTP;
 201         if (tsyn & 0x04) {
 202                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 203                 mb->timesync = tsyn & 0x03;
 204         }
 205
 206         return pkt_flags;
 207 }
 208 #endif
 209
 210 static inline uint64_t
 211 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 212 {
 213         uint64_t flags = 0;
 214 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 215         uint16_t flexbh, flexbl;
 216
 217         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 218                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 219                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 220         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 221                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 222                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 223
 224
 225         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 226                 mb->hash.fdir.hi =
 227                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 228                 flags |= PKT_RX_FDIR_ID;
 229         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 230                 mb->hash.fdir.hi =
 231                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 232                 flags |= PKT_RX_FDIR_FLX;
 233         }
 234         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 235                 mb->hash.fdir.lo =
 236                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 237                 flags |= PKT_RX_FDIR_FLX;
 238         }
 239 #else
 240         mb->hash.fdir.hi =
 241                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 242         flags |= PKT_RX_FDIR_ID;
 243 #endif
 244         return flags;
 245 }
 246
 247 static inline void
 248 i40e_parse_tunneling_params(uint64_t ol_flags,
 249                             union i40e_tx_offload tx_offload,
 250                             uint32_t *cd_tunneling)
 251 {
 252         /* EIPT: External (outer) IP header type */
 253         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 254                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 255         else if (ol_flags & PKT_TX_OUTER_IPV4)
 256                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 257         else if (ol_flags & PKT_TX_OUTER_IPV6)
 258                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 259
 260         /* EIPLEN: External (outer) IP header length, in DWords */
 261         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 262                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 263
 264         /* L4TUNT: L4 Tunneling Type */
 265         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 266         case PKT_TX_TUNNEL_IPIP:
 267                 /* for non UDP / GRE tunneling, set to 00b */
 268                 break;
 269         case PKT_TX_TUNNEL_VXLAN:
 270         case PKT_TX_TUNNEL_GENEVE:
 271                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 272                 break;
 273         case PKT_TX_TUNNEL_GRE:
 274                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 275                 break;
 276         default:
 277                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 278                 return;
 279         }
 280
 281         /* L4TUNLEN: L4 Tunneling Length, in Words
 282          *
 283          * We depend on app to set rte_mbuf.l2_len correctly.
 284          * For IP in GRE it should be set to the length of the GRE
 285          * header;
 286          * for MAC in GRE or MAC in UDP it should be set to the length
 287          * of the GRE or UDP headers plus the inner MAC up to including
 288          * its last Ethertype.
 289          */
 290         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 291                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 292 }
 293
 294 static inline void
 295 i40e_txd_enable_checksum(uint64_t ol_flags,
 296                         uint32_t *td_cmd,
 297                         uint32_t *td_offset,
 298                         union i40e_tx_offload tx_offload)
 299 {
 300         /* Set MACLEN */
 301         if (ol_flags & PKT_TX_TUNNEL_MASK)
 302                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 303                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 304         else
 305                 *td_offset |= (tx_offload.l2_len >> 1)
 306                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 307
 308         /* Enable L3 checksum offloads */
 309         if (ol_flags & PKT_TX_IP_CKSUM) {
 310                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 311                 *td_offset |= (tx_offload.l3_len >> 2)
 312                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 313         } else if (ol_flags & PKT_TX_IPV4) {
 314                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 315                 *td_offset |= (tx_offload.l3_len >> 2)
 316                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 317         } else if (ol_flags & PKT_TX_IPV6) {
 318                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 319                 *td_offset |= (tx_offload.l3_len >> 2)
 320                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 321         }
 322
 323         if (ol_flags & PKT_TX_TCP_SEG) {
 324                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 325                 *td_offset |= (tx_offload.l4_len >> 2)
 326                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 327                 return;
 328         }
 329
 330         /* Enable L4 checksum offloads */
 331         switch (ol_flags & PKT_TX_L4_MASK) {
 332         case PKT_TX_TCP_CKSUM:
 333                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 334                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 335                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 336                 break;
 337         case PKT_TX_SCTP_CKSUM:
 338                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 339                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 340                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 341                 break;
 342         case PKT_TX_UDP_CKSUM:
 343                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 344                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 345                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 346                 break;
 347         default:
 348                 break;
 349         }
 350 }
 351
 352 /* Construct the tx flags */
 353 static inline uint64_t
 354 i40e_build_ctob(uint32_t td_cmd,
 355                 uint32_t td_offset,
 356                 unsigned int size,
 357                 uint32_t td_tag)
 358 {
 359         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 360                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 361                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 362                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 363                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 364 }
 365
 366 static inline int
 367 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 368 {
 369         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 370         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 371         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 372         uint16_t nb_tx_desc = txq->nb_tx_desc;
 373         uint16_t desc_to_clean_to;
 374         uint16_t nb_tx_to_clean;
 375
 376         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 377         if (desc_to_clean_to >= nb_tx_desc)
 378                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 379
 380         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 381         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 382                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 383                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 384                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
 385                            "(port=%d queue=%d)", desc_to_clean_to,
 386                            txq->port_id, txq->queue_id);
 387                 return -1;
 388         }
 389
 390         if (last_desc_cleaned > desc_to_clean_to)
 391                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 392                                                         desc_to_clean_to);
 393         else
 394                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 395                                         last_desc_cleaned);
 396
 397         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 398
 399         txq->last_desc_cleaned = desc_to_clean_to;
 400         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 401
 402         return 0;
 403 }
 404
 405 static inline int
 406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 407 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 408 #else
 409 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 410 #endif
 411 {
 412         int ret = 0;
 413
 414 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 415         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 416                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 417                              "rxq->rx_free_thresh=%d, "
 418                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 419                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 420                 ret = -EINVAL;
 421         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 422                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 423                              "rxq->rx_free_thresh=%d, "
 424                              "rxq->nb_rx_desc=%d",
 425                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 426                 ret = -EINVAL;
 427         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 428                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 429                              "rxq->nb_rx_desc=%d, "
 430                              "rxq->rx_free_thresh=%d",
 431                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 432                 ret = -EINVAL;
 433         }
 434 #else
 435         ret = -EINVAL;
 436 #endif
 437
 438         return ret;
 439 }
 440
 441 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 442 #define I40E_LOOK_AHEAD 8
 443 #if (I40E_LOOK_AHEAD != 8)
 444 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 445 #endif
 446 static inline int
 447 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 448 {
 449         volatile union i40e_rx_desc *rxdp;
 450         struct i40e_rx_entry *rxep;
 451         struct rte_mbuf *mb;
 452         uint16_t pkt_len;
 453         uint64_t qword1;
 454         uint32_t rx_status;
 455         int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
 456         int32_t i, j, nb_rx = 0;
 457         uint64_t pkt_flags;
 458         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 459
 460         rxdp = &rxq->rx_ring[rxq->rx_tail];
 461         rxep = &rxq->sw_ring[rxq->rx_tail];
 462
 463         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 464         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 465                                 I40E_RXD_QW1_STATUS_SHIFT;
 466
 467         /* Make sure there is at least 1 packet to receive */
 468         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 469                 return 0;
 470
 471         /**
 472          * Scan LOOK_AHEAD descriptors at a time to determine which
 473          * descriptors reference packets that are ready to be received.
 474          */
 475         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 476                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 477                 /* Read desc statuses backwards to avoid race condition */
 478                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 479                         qword1 = rte_le_to_cpu_64(\
 480                                 rxdp[j].wb.qword1.status_error_len);
 481                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 482                                         I40E_RXD_QW1_STATUS_SHIFT;
 483                 }
 484
 485                 rte_smp_rmb();
 486
 487                 /* Compute how many status bits were set */
 488                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
 489                         var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 490 #ifdef RTE_ARCH_ARM
 491                         /* For Arm platforms, only compute continuous status bits */
 492                         if (var)
 493                                 nb_dd += 1;
 494                         else
 495                                 break;
 496 #else
 497                         nb_dd += var;
 498 #endif
 499                 }
 500
 501                 nb_rx += nb_dd;
 502
 503                 /* Translate descriptor info to mbuf parameters */
 504                 for (j = 0; j < nb_dd; j++) {
 505                         mb = rxep[j].mbuf;
 506                         qword1 = rte_le_to_cpu_64(\
 507                                 rxdp[j].wb.qword1.status_error_len);
 508                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 509                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 510                         mb->data_len = pkt_len;
 511                         mb->pkt_len = pkt_len;
 512                         mb->ol_flags = 0;
 513                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 514                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 515                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 516                         mb->packet_type =
 517                                 ptype_tbl[(uint8_t)((qword1 &
 518                                 I40E_RXD_QW1_PTYPE_MASK) >>
 519                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 520                         if (pkt_flags & PKT_RX_RSS_HASH)
 521                                 mb->hash.rss = rte_le_to_cpu_32(\
 522                                         rxdp[j].wb.qword0.hi_dword.rss);
 523                         if (pkt_flags & PKT_RX_FDIR)
 524                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 525
 526 #ifdef RTE_LIBRTE_IEEE1588
 527                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 528 #endif
 529                         mb->ol_flags |= pkt_flags;
 530
 531                 }
 532
 533                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 534                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 535
 536                 if (nb_dd != I40E_LOOK_AHEAD)
 537                         break;
 538         }
 539
 540         /* Clear software ring entries */
 541         for (i = 0; i < nb_rx; i++)
 542                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 543
 544         return nb_rx;
 545 }
 546
 547 static inline uint16_t
 548 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 549                         struct rte_mbuf **rx_pkts,
 550                         uint16_t nb_pkts)
 551 {
 552         uint16_t i;
 553         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 554
 555         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 556
 557         for (i = 0; i < nb_pkts; i++)
 558                 rx_pkts[i] = stage[i];
 559
 560         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 561         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 562
 563         return nb_pkts;
 564 }
 565
 566 static inline int
 567 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 568 {
 569         volatile union i40e_rx_desc *rxdp;
 570         struct i40e_rx_entry *rxep;
 571         struct rte_mbuf *mb;
 572         uint16_t alloc_idx, i;
 573         uint64_t dma_addr;
 574         int diag;
 575
 576         /* Allocate buffers in bulk */
 577         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 578                                 (rxq->rx_free_thresh - 1));
 579         rxep = &(rxq->sw_ring[alloc_idx]);
 580         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 581                                         rxq->rx_free_thresh);
 582         if (unlikely(diag != 0)) {
 583                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 584                 return -ENOMEM;
 585         }
 586
 587         rxdp = &rxq->rx_ring[alloc_idx];
 588         for (i = 0; i < rxq->rx_free_thresh; i++) {
 589                 if (likely(i < (rxq->rx_free_thresh - 1)))
 590                         /* Prefetch next mbuf */
 591                         rte_prefetch0(rxep[i + 1].mbuf);
 592
 593                 mb = rxep[i].mbuf;
 594                 rte_mbuf_refcnt_set(mb, 1);
 595                 mb->next = NULL;
 596                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 597                 mb->nb_segs = 1;
 598                 mb->port = rxq->port_id;
 599                 dma_addr = rte_cpu_to_le_64(\
 600                         rte_mbuf_data_iova_default(mb));
 601                 rxdp[i].read.hdr_addr = 0;
 602                 rxdp[i].read.pkt_addr = dma_addr;
 603         }
 604
 605         /* Update rx tail regsiter */
 606         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 607
 608         rxq->rx_free_trigger =
 609                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 610         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 611                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 612
 613         return 0;
 614 }
 615
 616 static inline uint16_t
 617 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 618 {
 619         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 620         struct rte_eth_dev *dev;
 621         uint16_t nb_rx = 0;
 622
 623         if (!nb_pkts)
 624                 return 0;
 625
 626         if (rxq->rx_nb_avail)
 627                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 628
 629         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 630         rxq->rx_next_avail = 0;
 631         rxq->rx_nb_avail = nb_rx;
 632         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 633
 634         if (rxq->rx_tail > rxq->rx_free_trigger) {
 635                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 636                         uint16_t i, j;
 637
 638                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 639                         dev->data->rx_mbuf_alloc_failed +=
 640                                 rxq->rx_free_thresh;
 641
 642                         rxq->rx_nb_avail = 0;
 643                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 644                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 645                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 646
 647                         return 0;
 648                 }
 649         }
 650
 651         if (rxq->rx_tail >= rxq->nb_rx_desc)
 652                 rxq->rx_tail = 0;
 653
 654         if (rxq->rx_nb_avail)
 655                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 656
 657         return 0;
 658 }
 659
 660 static uint16_t
 661 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 662                           struct rte_mbuf **rx_pkts,
 663                           uint16_t nb_pkts)
 664 {
 665         uint16_t nb_rx = 0, n, count;
 666
 667         if (unlikely(nb_pkts == 0))
 668                 return 0;
 669
 670         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 671                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 672
 673         while (nb_pkts) {
 674                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 675                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 676                 nb_rx = (uint16_t)(nb_rx + count);
 677                 nb_pkts = (uint16_t)(nb_pkts - count);
 678                 if (count < n)
 679                         break;
 680         }
 681
 682         return nb_rx;
 683 }
 684 #else
 685 static uint16_t
 686 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 687                           struct rte_mbuf __rte_unused **rx_pkts,
 688                           uint16_t __rte_unused nb_pkts)
 689 {
 690         return 0;
 691 }
 692 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 693
 694 uint16_t
 695 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 696 {
 697         struct i40e_rx_queue *rxq;
 698         volatile union i40e_rx_desc *rx_ring;
 699         volatile union i40e_rx_desc *rxdp;
 700         union i40e_rx_desc rxd;
 701         struct i40e_rx_entry *sw_ring;
 702         struct i40e_rx_entry *rxe;
 703         struct rte_eth_dev *dev;
 704         struct rte_mbuf *rxm;
 705         struct rte_mbuf *nmb;
 706         uint16_t nb_rx;
 707         uint32_t rx_status;
 708         uint64_t qword1;
 709         uint16_t rx_packet_len;
 710         uint16_t rx_id, nb_hold;
 711         uint64_t dma_addr;
 712         uint64_t pkt_flags;
 713         uint32_t *ptype_tbl;
 714
 715         nb_rx = 0;
 716         nb_hold = 0;
 717         rxq = rx_queue;
 718         rx_id = rxq->rx_tail;
 719         rx_ring = rxq->rx_ring;
 720         sw_ring = rxq->sw_ring;
 721         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 722
 723         while (nb_rx < nb_pkts) {
 724                 rxdp = &rx_ring[rx_id];
 725                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 726                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 727                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 728
 729                 /* Check the DD bit first */
 730                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 731                         break;
 732
 733                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 734                 if (unlikely(!nmb)) {
 735                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 736                         dev->data->rx_mbuf_alloc_failed++;
 737                         break;
 738                 }
 739
 740                 rxd = *rxdp;
 741                 nb_hold++;
 742                 rxe = &sw_ring[rx_id];
 743                 rx_id++;
 744                 if (unlikely(rx_id == rxq->nb_rx_desc))
 745                         rx_id = 0;
 746
 747                 /* Prefetch next mbuf */
 748                 rte_prefetch0(sw_ring[rx_id].mbuf);
 749
 750                 /**
 751                  * When next RX descriptor is on a cache line boundary,
 752                  * prefetch the next 4 RX descriptors and next 8 pointers
 753                  * to mbufs.
 754                  */
 755                 if ((rx_id & 0x3) == 0) {
 756                         rte_prefetch0(&rx_ring[rx_id]);
 757                         rte_prefetch0(&sw_ring[rx_id]);
 758                 }
 759                 rxm = rxe->mbuf;
 760                 rxe->mbuf = nmb;
 761                 dma_addr =
 762                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 763                 rxdp->read.hdr_addr = 0;
 764                 rxdp->read.pkt_addr = dma_addr;
 765
 766                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 767                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 768
 769                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 770                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 771                 rxm->nb_segs = 1;
 772                 rxm->next = NULL;
 773                 rxm->pkt_len = rx_packet_len;
 774                 rxm->data_len = rx_packet_len;
 775                 rxm->port = rxq->port_id;
 776                 rxm->ol_flags = 0;
 777                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 778                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 779                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 780                 rxm->packet_type =
 781                         ptype_tbl[(uint8_t)((qword1 &
 782                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 783                 if (pkt_flags & PKT_RX_RSS_HASH)
 784                         rxm->hash.rss =
 785                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 786                 if (pkt_flags & PKT_RX_FDIR)
 787                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 788
 789 #ifdef RTE_LIBRTE_IEEE1588
 790                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 791 #endif
 792                 rxm->ol_flags |= pkt_flags;
 793
 794                 rx_pkts[nb_rx++] = rxm;
 795         }
 796         rxq->rx_tail = rx_id;
 797
 798         /**
 799          * If the number of free RX descriptors is greater than the RX free
 800          * threshold of the queue, advance the receive tail register of queue.
 801          * Update that register with the value of the last processed RX
 802          * descriptor minus 1.
 803          */
 804         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 805         if (nb_hold > rxq->rx_free_thresh) {
 806                 rx_id = (uint16_t) ((rx_id == 0) ?
 807                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 808                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 809                 nb_hold = 0;
 810         }
 811         rxq->nb_rx_hold = nb_hold;
 812
 813         return nb_rx;
 814 }
 815
 816 uint16_t
 817 i40e_recv_scattered_pkts(void *rx_queue,
 818                          struct rte_mbuf **rx_pkts,
 819                          uint16_t nb_pkts)
 820 {
 821         struct i40e_rx_queue *rxq = rx_queue;
 822         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 823         volatile union i40e_rx_desc *rxdp;
 824         union i40e_rx_desc rxd;
 825         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 826         struct i40e_rx_entry *rxe;
 827         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 828         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 829         struct rte_mbuf *nmb, *rxm;
 830         uint16_t rx_id = rxq->rx_tail;
 831         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 832         struct rte_eth_dev *dev;
 833         uint32_t rx_status;
 834         uint64_t qword1;
 835         uint64_t dma_addr;
 836         uint64_t pkt_flags;
 837         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 838
 839         while (nb_rx < nb_pkts) {
 840                 rxdp = &rx_ring[rx_id];
 841                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 842                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 843                                         I40E_RXD_QW1_STATUS_SHIFT;
 844
 845                 /* Check the DD bit */
 846                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 847                         break;
 848
 849                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 850                 if (unlikely(!nmb)) {
 851                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 852                         dev->data->rx_mbuf_alloc_failed++;
 853                         break;
 854                 }
 855
 856                 rxd = *rxdp;
 857                 nb_hold++;
 858                 rxe = &sw_ring[rx_id];
 859                 rx_id++;
 860                 if (rx_id == rxq->nb_rx_desc)
 861                         rx_id = 0;
 862
 863                 /* Prefetch next mbuf */
 864                 rte_prefetch0(sw_ring[rx_id].mbuf);
 865
 866                 /**
 867                  * When next RX descriptor is on a cache line boundary,
 868                  * prefetch the next 4 RX descriptors and next 8 pointers
 869                  * to mbufs.
 870                  */
 871                 if ((rx_id & 0x3) == 0) {
 872                         rte_prefetch0(&rx_ring[rx_id]);
 873                         rte_prefetch0(&sw_ring[rx_id]);
 874                 }
 875
 876                 rxm = rxe->mbuf;
 877                 rxe->mbuf = nmb;
 878                 dma_addr =
 879                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 880
 881                 /* Set data buffer address and data length of the mbuf */
 882                 rxdp->read.hdr_addr = 0;
 883                 rxdp->read.pkt_addr = dma_addr;
 884                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 885                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 886                 rxm->data_len = rx_packet_len;
 887                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 888
 889                 /**
 890                  * If this is the first buffer of the received packet, set the
 891                  * pointer to the first mbuf of the packet and initialize its
 892                  * context. Otherwise, update the total length and the number
 893                  * of segments of the current scattered packet, and update the
 894                  * pointer to the last mbuf of the current packet.
 895                  */
 896                 if (!first_seg) {
 897                         first_seg = rxm;
 898                         first_seg->nb_segs = 1;
 899                         first_seg->pkt_len = rx_packet_len;
 900                 } else {
 901                         first_seg->pkt_len =
 902                                 (uint16_t)(first_seg->pkt_len +
 903                                                 rx_packet_len);
 904                         first_seg->nb_segs++;
 905                         last_seg->next = rxm;
 906                 }
 907
 908                 /**
 909                  * If this is not the last buffer of the received packet,
 910                  * update the pointer to the last mbuf of the current scattered
 911                  * packet and continue to parse the RX ring.
 912                  */
 913                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 914                         last_seg = rxm;
 915                         continue;
 916                 }
 917
 918                 /**
 919                  * This is the last buffer of the received packet. If the CRC
 920                  * is not stripped by the hardware:
 921                  *  - Subtract the CRC length from the total packet length.
 922                  *  - If the last buffer only contains the whole CRC or a part
 923                  *  of it, free the mbuf associated to the last buffer. If part
 924                  *  of the CRC is also contained in the previous mbuf, subtract
 925                  *  the length of that CRC part from the data length of the
 926                  *  previous mbuf.
 927                  */
 928                 rxm->next = NULL;
 929                 if (unlikely(rxq->crc_len > 0)) {
 930                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 931                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 932                                 rte_pktmbuf_free_seg(rxm);
 933                                 first_seg->nb_segs--;
 934                                 last_seg->data_len =
 935                                         (uint16_t)(last_seg->data_len -
 936                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 937                                 last_seg->next = NULL;
 938                         } else
 939                                 rxm->data_len = (uint16_t)(rx_packet_len -
 940                                                         RTE_ETHER_CRC_LEN);
 941                 }
 942
 943                 first_seg->port = rxq->port_id;
 944                 first_seg->ol_flags = 0;
 945                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 946                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 947                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 948                 first_seg->packet_type =
 949                         ptype_tbl[(uint8_t)((qword1 &
 950                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 951                 if (pkt_flags & PKT_RX_RSS_HASH)
 952                         first_seg->hash.rss =
 953                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 954                 if (pkt_flags & PKT_RX_FDIR)
 955                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 956
 957 #ifdef RTE_LIBRTE_IEEE1588
 958                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 959 #endif
 960                 first_seg->ol_flags |= pkt_flags;
 961
 962                 /* Prefetch data of first segment, if configured to do so. */
 963                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 964                         first_seg->data_off));
 965                 rx_pkts[nb_rx++] = first_seg;
 966                 first_seg = NULL;
 967         }
 968
 969         /* Record index of the next RX descriptor to probe. */
 970         rxq->rx_tail = rx_id;
 971         rxq->pkt_first_seg = first_seg;
 972         rxq->pkt_last_seg = last_seg;
 973
 974         /**
 975          * If the number of free RX descriptors is greater than the RX free
 976          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 977          * register. Update the RDT with the value of the last processed RX
 978          * descriptor minus 1, to guarantee that the RDT register is never
 979          * equal to the RDH register, which creates a "full" ring situtation
 980          * from the hardware point of view.
 981          */
 982         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 983         if (nb_hold > rxq->rx_free_thresh) {
 984                 rx_id = (uint16_t)(rx_id == 0 ?
 985                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 986                 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 987                 nb_hold = 0;
 988         }
 989         rxq->nb_rx_hold = nb_hold;
 990
 991         return nb_rx;
 992 }
 993
 994 /* Check if the context descriptor is needed for TX offloading */
 995 static inline uint16_t
 996 i40e_calc_context_desc(uint64_t flags)
 997 {
 998         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 999                 PKT_TX_TCP_SEG |
1000                 PKT_TX_QINQ_PKT |
1001                 PKT_TX_TUNNEL_MASK;
1002
1003 #ifdef RTE_LIBRTE_IEEE1588
1004         mask |= PKT_TX_IEEE1588_TMST;
1005 #endif
1006
1007         return (flags & mask) ? 1 : 0;
1008 }
1009
1010 /* set i40e TSO context descriptor */
1011 static inline uint64_t
1012 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1013 {
1014         uint64_t ctx_desc = 0;
1015         uint32_t cd_cmd, hdr_len, cd_tso_len;
1016
1017         if (!tx_offload.l4_len) {
1018                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1019                 return ctx_desc;
1020         }
1021
1022         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1023         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1024                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1025
1026         cd_cmd = I40E_TX_CTX_DESC_TSO;
1027         cd_tso_len = mbuf->pkt_len - hdr_len;
1028         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1029                 ((uint64_t)cd_tso_len <<
1030                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1031                 ((uint64_t)mbuf->tso_segsz <<
1032                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1033
1034         return ctx_desc;
1035 }
1036
1037 /* HW requires that Tx buffer size ranges from 1B up to (16K-1)B. */
1038 #define I40E_MAX_DATA_PER_TXD \
1039         (I40E_TXD_QW1_TX_BUF_SZ_MASK >> I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1040 /* Calculate the number of TX descriptors needed for each pkt */
1041 static inline uint16_t
1042 i40e_calc_pkt_desc(struct rte_mbuf *tx_pkt)
1043 {
1044         struct rte_mbuf *txd = tx_pkt;
1045         uint16_t count = 0;
1046
1047         while (txd != NULL) {
1048                 count += DIV_ROUND_UP(txd->data_len, I40E_MAX_DATA_PER_TXD);
1049                 txd = txd->next;
1050         }
1051
1052         return count;
1053 }
1054
1055 uint16_t
1056 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1057 {
1058         struct i40e_tx_queue *txq;
1059         struct i40e_tx_entry *sw_ring;
1060         struct i40e_tx_entry *txe, *txn;
1061         volatile struct i40e_tx_desc *txd;
1062         volatile struct i40e_tx_desc *txr;
1063         struct rte_mbuf *tx_pkt;
1064         struct rte_mbuf *m_seg;
1065         uint32_t cd_tunneling_params;
1066         uint16_t tx_id;
1067         uint16_t nb_tx;
1068         uint32_t td_cmd;
1069         uint32_t td_offset;
1070         uint32_t td_tag;
1071         uint64_t ol_flags;
1072         uint16_t nb_used;
1073         uint16_t nb_ctx;
1074         uint16_t tx_last;
1075         uint16_t slen;
1076         uint64_t buf_dma_addr;
1077         union i40e_tx_offload tx_offload = {0};
1078
1079         txq = tx_queue;
1080         sw_ring = txq->sw_ring;
1081         txr = txq->tx_ring;
1082         tx_id = txq->tx_tail;
1083         txe = &sw_ring[tx_id];
1084
1085         /* Check if the descriptor ring needs to be cleaned. */
1086         if (txq->nb_tx_free < txq->tx_free_thresh)
1087                 (void)i40e_xmit_cleanup(txq);
1088
1089         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1090                 td_cmd = 0;
1091                 td_tag = 0;
1092                 td_offset = 0;
1093
1094                 tx_pkt = *tx_pkts++;
1095                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1096
1097                 ol_flags = tx_pkt->ol_flags;
1098                 tx_offload.l2_len = tx_pkt->l2_len;
1099                 tx_offload.l3_len = tx_pkt->l3_len;
1100                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1101                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1102                 tx_offload.l4_len = tx_pkt->l4_len;
1103                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1104
1105                 /* Calculate the number of context descriptors needed. */
1106                 nb_ctx = i40e_calc_context_desc(ol_flags);
1107
1108                 /**
1109                  * The number of descriptors that must be allocated for
1110                  * a packet equals to the number of the segments of that
1111                  * packet plus 1 context descriptor if needed.
1112                  * Recalculate the needed tx descs when TSO enabled in case
1113                  * the mbuf data size exceeds max data size that hw allows
1114                  * per tx desc.
1115                  */
1116                 if (ol_flags & PKT_TX_TCP_SEG)
1117                         nb_used = (uint16_t)(i40e_calc_pkt_desc(tx_pkt) +
1118                                              nb_ctx);
1119                 else
1120                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1121                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1122
1123                 /* Circular ring */
1124                 if (tx_last >= txq->nb_tx_desc)
1125                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1126
1127                 if (nb_used > txq->nb_tx_free) {
1128                         if (i40e_xmit_cleanup(txq) != 0) {
1129                                 if (nb_tx == 0)
1130                                         return 0;
1131                                 goto end_of_tx;
1132                         }
1133                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1134                                 while (nb_used > txq->nb_tx_free) {
1135                                         if (i40e_xmit_cleanup(txq) != 0) {
1136                                                 if (nb_tx == 0)
1137                                                         return 0;
1138                                                 goto end_of_tx;
1139                                         }
1140                                 }
1141                         }
1142                 }
1143
1144                 /* Descriptor based VLAN insertion */
1145                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1146                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1147                         td_tag = tx_pkt->vlan_tci;
1148                 }
1149
1150                 /* Always enable CRC offload insertion */
1151                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1152
1153                 /* Fill in tunneling parameters if necessary */
1154                 cd_tunneling_params = 0;
1155                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1156                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1157                                                     &cd_tunneling_params);
1158                 /* Enable checksum offloading */
1159                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1160                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1161                                                  &td_offset, tx_offload);
1162
1163                 if (nb_ctx) {
1164                         /* Setup TX context descriptor if required */
1165                         volatile struct i40e_tx_context_desc *ctx_txd =
1166                                 (volatile struct i40e_tx_context_desc *)\
1167                                                         &txr[tx_id];
1168                         uint16_t cd_l2tag2 = 0;
1169                         uint64_t cd_type_cmd_tso_mss =
1170                                 I40E_TX_DESC_DTYPE_CONTEXT;
1171
1172                         txn = &sw_ring[txe->next_id];
1173                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1174                         if (txe->mbuf != NULL) {
1175                                 rte_pktmbuf_free_seg(txe->mbuf);
1176                                 txe->mbuf = NULL;
1177                         }
1178
1179                         /* TSO enabled means no timestamp */
1180                         if (ol_flags & PKT_TX_TCP_SEG)
1181                                 cd_type_cmd_tso_mss |=
1182                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1183                         else {
1184 #ifdef RTE_LIBRTE_IEEE1588
1185                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1186                                         cd_type_cmd_tso_mss |=
1187                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1188                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1189 #endif
1190                         }
1191
1192                         ctx_txd->tunneling_params =
1193                                 rte_cpu_to_le_32(cd_tunneling_params);
1194                         if (ol_flags & PKT_TX_QINQ_PKT) {
1195                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1196                                 cd_type_cmd_tso_mss |=
1197                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1198                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1199                         }
1200                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1201                         ctx_txd->type_cmd_tso_mss =
1202                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1203
1204                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1205                                 "tunneling_params: %#x;\n"
1206                                 "l2tag2: %#hx;\n"
1207                                 "rsvd: %#hx;\n"
1208                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1209                                 tx_pkt, tx_id,
1210                                 ctx_txd->tunneling_params,
1211                                 ctx_txd->l2tag2,
1212                                 ctx_txd->rsvd,
1213                                 ctx_txd->type_cmd_tso_mss);
1214
1215                         txe->last_id = tx_last;
1216                         tx_id = txe->next_id;
1217                         txe = txn;
1218                 }
1219
1220                 m_seg = tx_pkt;
1221                 do {
1222                         txd = &txr[tx_id];
1223                         txn = &sw_ring[txe->next_id];
1224
1225                         if (txe->mbuf)
1226                                 rte_pktmbuf_free_seg(txe->mbuf);
1227                         txe->mbuf = m_seg;
1228
1229                         /* Setup TX Descriptor */
1230                         slen = m_seg->data_len;
1231                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1232
1233                         while ((ol_flags & PKT_TX_TCP_SEG) &&
1234                                 unlikely(slen > I40E_MAX_DATA_PER_TXD)) {
1235                                 txd->buffer_addr =
1236                                         rte_cpu_to_le_64(buf_dma_addr);
1237                                 txd->cmd_type_offset_bsz =
1238                                         i40e_build_ctob(td_cmd,
1239                                         td_offset, I40E_MAX_DATA_PER_TXD,
1240                                         td_tag);
1241
1242                                 buf_dma_addr += I40E_MAX_DATA_PER_TXD;
1243                                 slen -= I40E_MAX_DATA_PER_TXD;
1244
1245                                 txe->last_id = tx_last;
1246                                 tx_id = txe->next_id;
1247                                 txe = txn;
1248                                 txd = &txr[tx_id];
1249                                 txn = &sw_ring[txe->next_id];
1250                         }
1251                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1252                                 "buf_dma_addr: %#"PRIx64";\n"
1253                                 "td_cmd: %#x;\n"
1254                                 "td_offset: %#x;\n"
1255                                 "td_len: %u;\n"
1256                                 "td_tag: %#x;\n",
1257                                 tx_pkt, tx_id, buf_dma_addr,
1258                                 td_cmd, td_offset, slen, td_tag);
1259
1260                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1261                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1262                                                 td_offset, slen, td_tag);
1263                         txe->last_id = tx_last;
1264                         tx_id = txe->next_id;
1265                         txe = txn;
1266                         m_seg = m_seg->next;
1267                 } while (m_seg != NULL);
1268
1269                 /* The last packet data descriptor needs End Of Packet (EOP) */
1270                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1271                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1272                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1273
1274                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1275                         PMD_TX_LOG(DEBUG,
1276                                    "Setting RS bit on TXD id="
1277                                    "%4u (port=%d queue=%d)",
1278                                    tx_last, txq->port_id, txq->queue_id);
1279
1280                         td_cmd |= I40E_TX_DESC_CMD_RS;
1281
1282                         /* Update txq RS bit counters */
1283                         txq->nb_tx_used = 0;
1284                 }
1285
1286                 txd->cmd_type_offset_bsz |=
1287                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1288                                         I40E_TXD_QW1_CMD_SHIFT);
1289         }
1290
1291 end_of_tx:
1292         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1293                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1294                    (unsigned) tx_id, (unsigned) nb_tx);
1295
1296         rte_io_wmb();
1297         I40E_PCI_REG_WC_WRITE_RELAXED(txq->qtx_tail, tx_id);
1298         txq->tx_tail = tx_id;
1299
1300         return nb_tx;
1301 }
1302
1303 static __rte_always_inline int
1304 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1305 {
1306         struct i40e_tx_entry *txep;
1307         uint16_t tx_rs_thresh = txq->tx_rs_thresh;
1308         uint16_t i = 0, j = 0;
1309         struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
1310         const uint16_t k = RTE_ALIGN_FLOOR(tx_rs_thresh, RTE_I40E_TX_MAX_FREE_BUF_SZ);
1311         const uint16_t m = tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ;
1312
1313         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1314                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1315                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1316                 return 0;
1317
1318         txep = &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)];
1319
1320         for (i = 0; i < tx_rs_thresh; i++)
1321                 rte_prefetch0((txep + i)->mbuf);
1322
1323         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1324                 if (k) {
1325                         for (j = 0; j != k; j += RTE_I40E_TX_MAX_FREE_BUF_SZ) {
1326                                 for (i = 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; ++i, ++txep) {
1327                                         free[i] = txep->mbuf;
1328                                         txep->mbuf = NULL;
1329                                 }
1330                                 rte_mempool_put_bulk(free[0]->pool, (void **)free,
1331                                                 RTE_I40E_TX_MAX_FREE_BUF_SZ);
1332                         }
1333                 }
1334
1335                 if (m) {
1336                         for (i = 0; i < m; ++i, ++txep) {
1337                                 free[i] = txep->mbuf;
1338                                 txep->mbuf = NULL;
1339                         }
1340                         rte_mempool_put_bulk(free[0]->pool, (void **)free, m);
1341                 }
1342         } else {
1343                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1344                         rte_pktmbuf_free_seg(txep->mbuf);
1345                         txep->mbuf = NULL;
1346                 }
1347         }
1348
1349         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1350         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1351         if (txq->tx_next_dd >= txq->nb_tx_desc)
1352                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1353
1354         return txq->tx_rs_thresh;
1355 }
1356
1357 /* Populate 4 descriptors with data from 4 mbufs */
1358 static inline void
1359 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1360 {
1361         uint64_t dma_addr;
1362         uint32_t i;
1363
1364         for (i = 0; i < 4; i++, txdp++, pkts++) {
1365                 dma_addr = rte_mbuf_data_iova(*pkts);
1366                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1367                 txdp->cmd_type_offset_bsz =
1368                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1369                                         (*pkts)->data_len, 0);
1370         }
1371 }
1372
1373 /* Populate 1 descriptor with data from 1 mbuf */
1374 static inline void
1375 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1376 {
1377         uint64_t dma_addr;
1378
1379         dma_addr = rte_mbuf_data_iova(*pkts);
1380         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1381         txdp->cmd_type_offset_bsz =
1382                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1383                                 (*pkts)->data_len, 0);
1384 }
1385
1386 /* Fill hardware descriptor ring with mbuf data */
1387 static inline void
1388 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1389                      struct rte_mbuf **pkts,
1390                      uint16_t nb_pkts)
1391 {
1392         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1393         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1394         const int N_PER_LOOP = 4;
1395         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1396         int mainpart, leftover;
1397         int i, j;
1398
1399         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1400         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1401         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1402                 for (j = 0; j < N_PER_LOOP; ++j) {
1403                         (txep + i + j)->mbuf = *(pkts + i + j);
1404                 }
1405                 tx4(txdp + i, pkts + i);
1406         }
1407         if (unlikely(leftover > 0)) {
1408                 for (i = 0; i < leftover; ++i) {
1409                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1410                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1411                 }
1412         }
1413 }
1414
1415 static inline uint16_t
1416 tx_xmit_pkts(struct i40e_tx_queue *txq,
1417              struct rte_mbuf **tx_pkts,
1418              uint16_t nb_pkts)
1419 {
1420         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1421         uint16_t n = 0;
1422
1423         /**
1424          * Begin scanning the H/W ring for done descriptors when the number
1425          * of available descriptors drops below tx_free_thresh. For each done
1426          * descriptor, free the associated buffer.
1427          */
1428         if (txq->nb_tx_free < txq->tx_free_thresh)
1429                 i40e_tx_free_bufs(txq);
1430
1431         /* Use available descriptor only */
1432         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1433         if (unlikely(!nb_pkts))
1434                 return 0;
1435
1436         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1437         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1438                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1439                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1440                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1441                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1442                                                 I40E_TXD_QW1_CMD_SHIFT);
1443                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1444                 txq->tx_tail = 0;
1445         }
1446
1447         /* Fill hardware descriptor ring with mbuf data */
1448         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1449         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1450
1451         /* Determin if RS bit needs to be set */
1452         if (txq->tx_tail > txq->tx_next_rs) {
1453                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1454                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1455                                                 I40E_TXD_QW1_CMD_SHIFT);
1456                 txq->tx_next_rs =
1457                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1458                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1459                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1460         }
1461
1462         if (txq->tx_tail >= txq->nb_tx_desc)
1463                 txq->tx_tail = 0;
1464
1465         /* Update the tx tail register */
1466         I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1467
1468         return nb_pkts;
1469 }
1470
1471 static uint16_t
1472 i40e_xmit_pkts_simple(void *tx_queue,
1473                       struct rte_mbuf **tx_pkts,
1474                       uint16_t nb_pkts)
1475 {
1476         uint16_t nb_tx = 0;
1477
1478         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1479                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1480                                                 tx_pkts, nb_pkts);
1481
1482         while (nb_pkts) {
1483                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1484                                                 I40E_TX_MAX_BURST);
1485
1486                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1487                                                 &tx_pkts[nb_tx], num);
1488                 nb_tx = (uint16_t)(nb_tx + ret);
1489                 nb_pkts = (uint16_t)(nb_pkts - ret);
1490                 if (ret < num)
1491                         break;
1492         }
1493
1494         return nb_tx;
1495 }
1496
1497 static uint16_t
1498 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1499                    uint16_t nb_pkts)
1500 {
1501         uint16_t nb_tx = 0;
1502         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1503
1504         while (nb_pkts) {
1505                 uint16_t ret, num;
1506
1507                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1508                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1509                                                 num);
1510                 nb_tx += ret;
1511                 nb_pkts -= ret;
1512                 if (ret < num)
1513                         break;
1514         }
1515
1516         return nb_tx;
1517 }
1518
1519 /*********************************************************************
1520  *
1521  *  TX simple prep functions
1522  *
1523  **********************************************************************/
1524 uint16_t
1525 i40e_simple_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1526                       uint16_t nb_pkts)
1527 {
1528         int i;
1529         uint64_t ol_flags;
1530         struct rte_mbuf *m;
1531
1532         for (i = 0; i < nb_pkts; i++) {
1533                 m = tx_pkts[i];
1534                 ol_flags = m->ol_flags;
1535
1536                 if (m->nb_segs != 1) {
1537                         rte_errno = EINVAL;
1538                         return i;
1539                 }
1540
1541                 if (ol_flags & I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK) {
1542                         rte_errno = ENOTSUP;
1543                         return i;
1544                 }
1545
1546                 /* check the size of packet */
1547                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN ||
1548                     m->pkt_len > I40E_FRAME_SIZE_MAX) {
1549                         rte_errno = EINVAL;
1550                         return i;
1551                 }
1552         }
1553         return i;
1554 }
1555
1556 /*********************************************************************
1557  *
1558  *  TX prep functions
1559  *
1560  **********************************************************************/
1561 uint16_t
1562 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1563                 uint16_t nb_pkts)
1564 {
1565         int i, ret;
1566         uint64_t ol_flags;
1567         struct rte_mbuf *m;
1568
1569         for (i = 0; i < nb_pkts; i++) {
1570                 m = tx_pkts[i];
1571                 ol_flags = m->ol_flags;
1572
1573                 /* Check for m->nb_segs to not exceed the limits. */
1574                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1575                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1576                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1577                                 rte_errno = EINVAL;
1578                                 return i;
1579                         }
1580                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1581                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1582                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1583                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1584                         /* MSS outside the range (256B - 9674B) are considered
1585                          * malicious
1586                          */
1587                         rte_errno = EINVAL;
1588                         return i;
1589                 }
1590
1591                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1592                         rte_errno = ENOTSUP;
1593                         return i;
1594                 }
1595
1596                 /* check the size of packet */
1597                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1598                         rte_errno = EINVAL;
1599                         return i;
1600                 }
1601
1602 #ifdef RTE_ETHDEV_DEBUG_TX
1603                 ret = rte_validate_tx_offload(m);
1604                 if (ret != 0) {
1605                         rte_errno = -ret;
1606                         return i;
1607                 }
1608 #endif
1609                 ret = rte_net_intel_cksum_prepare(m);
1610                 if (ret != 0) {
1611                         rte_errno = -ret;
1612                         return i;
1613                 }
1614         }
1615         return i;
1616 }
1617
1618 /*
1619  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1620  * application used, which assume having sequential ones. But from driver's
1621  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1622  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1623  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1624  * use queue_idx from 0 to 95 to access queues, while real queue would be
1625  * different. This function will do a queue mapping to find VSI the queue
1626  * belongs to.
1627  */
1628 static struct i40e_vsi*
1629 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1630 {
1631         /* the queue in MAIN VSI range */
1632         if (queue_idx < pf->main_vsi->nb_qps)
1633                 return pf->main_vsi;
1634
1635         queue_idx -= pf->main_vsi->nb_qps;
1636
1637         /* queue_idx is greater than VMDQ VSIs range */
1638         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1639                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1640                 return NULL;
1641         }
1642
1643         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1644 }
1645
1646 static uint16_t
1647 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1648 {
1649         /* the queue in MAIN VSI range */
1650         if (queue_idx < pf->main_vsi->nb_qps)
1651                 return queue_idx;
1652
1653         /* It's VMDQ queues */
1654         queue_idx -= pf->main_vsi->nb_qps;
1655
1656         if (pf->nb_cfg_vmdq_vsi)
1657                 return queue_idx % pf->vmdq_nb_qps;
1658         else {
1659                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1660                 return (uint16_t)(-1);
1661         }
1662 }
1663
1664 int
1665 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1666 {
1667         struct i40e_rx_queue *rxq;
1668         int err;
1669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670
1671         PMD_INIT_FUNC_TRACE();
1672
1673         rxq = dev->data->rx_queues[rx_queue_id];
1674         if (!rxq || !rxq->q_set) {
1675                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1676                             rx_queue_id);
1677                 return -EINVAL;
1678         }
1679
1680         if (rxq->rx_deferred_start)
1681                 PMD_DRV_LOG(WARNING, "RX queue %u is deferrd start",
1682                             rx_queue_id);
1683
1684         err = i40e_alloc_rx_queue_mbufs(rxq);
1685         if (err) {
1686                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1687                 return err;
1688         }
1689
1690         /* Init the RX tail regieter. */
1691         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1692
1693         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1694         if (err) {
1695                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1696                             rx_queue_id);
1697
1698                 i40e_rx_queue_release_mbufs(rxq);
1699                 i40e_reset_rx_queue(rxq);
1700                 return err;
1701         }
1702         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1703
1704         return 0;
1705 }
1706
1707 int
1708 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1709 {
1710         struct i40e_rx_queue *rxq;
1711         int err;
1712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713
1714         rxq = dev->data->rx_queues[rx_queue_id];
1715         if (!rxq || !rxq->q_set) {
1716                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
1717                                 rx_queue_id);
1718                 return -EINVAL;
1719         }
1720
1721         /*
1722          * rx_queue_id is queue id application refers to, while
1723          * rxq->reg_idx is the real queue index.
1724          */
1725         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1726         if (err) {
1727                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1728                             rx_queue_id);
1729                 return err;
1730         }
1731         i40e_rx_queue_release_mbufs(rxq);
1732         i40e_reset_rx_queue(rxq);
1733         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1734
1735         return 0;
1736 }
1737
1738 int
1739 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1740 {
1741         int err;
1742         struct i40e_tx_queue *txq;
1743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744
1745         PMD_INIT_FUNC_TRACE();
1746
1747         txq = dev->data->tx_queues[tx_queue_id];
1748         if (!txq || !txq->q_set) {
1749                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1750                             tx_queue_id);
1751                 return -EINVAL;
1752         }
1753
1754         if (txq->tx_deferred_start)
1755                 PMD_DRV_LOG(WARNING, "TX queue %u is deferrd start",
1756                             tx_queue_id);
1757
1758         /*
1759          * tx_queue_id is queue id application refers to, while
1760          * rxq->reg_idx is the real queue index.
1761          */
1762         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1763         if (err) {
1764                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1765                             tx_queue_id);
1766                 return err;
1767         }
1768         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1769
1770         return 0;
1771 }
1772
1773 int
1774 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1775 {
1776         struct i40e_tx_queue *txq;
1777         int err;
1778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779
1780         txq = dev->data->tx_queues[tx_queue_id];
1781         if (!txq || !txq->q_set) {
1782                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
1783                         tx_queue_id);
1784                 return -EINVAL;
1785         }
1786
1787         /*
1788          * tx_queue_id is queue id application refers to, while
1789          * txq->reg_idx is the real queue index.
1790          */
1791         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1792         if (err) {
1793                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1794                             tx_queue_id);
1795                 return err;
1796         }
1797
1798         i40e_tx_queue_release_mbufs(txq);
1799         i40e_reset_tx_queue(txq);
1800         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1801
1802         return 0;
1803 }
1804
1805 const uint32_t *
1806 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1807 {
1808         static const uint32_t ptypes[] = {
1809                 /* refers to i40e_rxd_pkt_type_mapping() */
1810                 RTE_PTYPE_L2_ETHER,
1811                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1812                 RTE_PTYPE_L2_ETHER_LLDP,
1813                 RTE_PTYPE_L2_ETHER_ARP,
1814                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1815                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1816                 RTE_PTYPE_L4_FRAG,
1817                 RTE_PTYPE_L4_ICMP,
1818                 RTE_PTYPE_L4_NONFRAG,
1819                 RTE_PTYPE_L4_SCTP,
1820                 RTE_PTYPE_L4_TCP,
1821                 RTE_PTYPE_L4_UDP,
1822                 RTE_PTYPE_TUNNEL_GRENAT,
1823                 RTE_PTYPE_TUNNEL_IP,
1824                 RTE_PTYPE_INNER_L2_ETHER,
1825                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1826                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1827                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1828                 RTE_PTYPE_INNER_L4_FRAG,
1829                 RTE_PTYPE_INNER_L4_ICMP,
1830                 RTE_PTYPE_INNER_L4_NONFRAG,
1831                 RTE_PTYPE_INNER_L4_SCTP,
1832                 RTE_PTYPE_INNER_L4_TCP,
1833                 RTE_PTYPE_INNER_L4_UDP,
1834                 RTE_PTYPE_UNKNOWN
1835         };
1836
1837         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1838 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1839             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1840 #endif
1841             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1842             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1843             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1844 #ifdef CC_AVX512_SUPPORT
1845             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
1846             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
1847 #endif
1848             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1849             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1850                 return ptypes;
1851         return NULL;
1852 }
1853
1854 static int
1855 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1856 {
1857         uint16_t i;
1858
1859         for (i = 0; i < num; i++) {
1860                 if (i != idx && queues[i])
1861                         return 0;
1862         }
1863
1864         return 1;
1865 }
1866
1867 static int
1868 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1869                                 struct i40e_rx_queue *rxq)
1870 {
1871         struct i40e_adapter *ad =
1872                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1873         int use_def_burst_func =
1874                 check_rx_burst_bulk_alloc_preconditions(rxq);
1875         uint16_t buf_size =
1876                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1877                            RTE_PKTMBUF_HEADROOM);
1878         int use_scattered_rx =
1879                 (rxq->max_pkt_len > buf_size);
1880
1881         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1882                 PMD_DRV_LOG(ERR,
1883                             "Failed to do RX queue initialization");
1884                 return -EINVAL;
1885         }
1886
1887         if (i40e_dev_first_queue(rxq->queue_id,
1888                                  dev->data->rx_queues,
1889                                  dev->data->nb_rx_queues)) {
1890                 /**
1891                  * If it is the first queue to setup,
1892                  * set all flags to default and call
1893                  * i40e_set_rx_function.
1894                  */
1895                 ad->rx_bulk_alloc_allowed = true;
1896                 ad->rx_vec_allowed = true;
1897                 dev->data->scattered_rx = use_scattered_rx;
1898                 if (use_def_burst_func)
1899                         ad->rx_bulk_alloc_allowed = false;
1900                 i40e_set_rx_function(dev);
1901                 return 0;
1902         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1903                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1904                             " number %d of queue %d isn't power of 2",
1905                             rxq->nb_rx_desc, rxq->queue_id);
1906                 return -EINVAL;
1907         }
1908
1909         /* check bulk alloc conflict */
1910         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1911                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1912                 return -EINVAL;
1913         }
1914         /* check scatterred conflict */
1915         if (!dev->data->scattered_rx && use_scattered_rx) {
1916                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1917                 return -EINVAL;
1918         }
1919         /* check vector conflict */
1920         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1921                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1922                 return -EINVAL;
1923         }
1924
1925         return 0;
1926 }
1927
1928 int
1929 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1930                         uint16_t queue_idx,
1931                         uint16_t nb_desc,
1932                         unsigned int socket_id,
1933                         const struct rte_eth_rxconf *rx_conf,
1934                         struct rte_mempool *mp)
1935 {
1936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937         struct i40e_adapter *ad =
1938                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1939         struct i40e_vsi *vsi;
1940         struct i40e_pf *pf = NULL;
1941         struct i40e_vf *vf = NULL;
1942         struct i40e_rx_queue *rxq;
1943         const struct rte_memzone *rz;
1944         uint32_t ring_size;
1945         uint16_t len, i;
1946         uint16_t reg_idx, base, bsf, tc_mapping;
1947         int q_offset, use_def_burst_func = 1;
1948         uint64_t offloads;
1949
1950         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1951
1952         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1953                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1954                 vsi = &vf->vsi;
1955                 if (!vsi)
1956                         return -EINVAL;
1957                 reg_idx = queue_idx;
1958         } else {
1959                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1961                 if (!vsi)
1962                         return -EINVAL;
1963                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1964                 if (q_offset < 0)
1965                         return -EINVAL;
1966                 reg_idx = vsi->base_queue + q_offset;
1967         }
1968
1969         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1970             (nb_desc > I40E_MAX_RING_DESC) ||
1971             (nb_desc < I40E_MIN_RING_DESC)) {
1972                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1973                             "invalid", nb_desc);
1974                 return -EINVAL;
1975         }
1976
1977         /* Free memory if needed */
1978         if (dev->data->rx_queues[queue_idx]) {
1979                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1980                 dev->data->rx_queues[queue_idx] = NULL;
1981         }
1982
1983         /* Allocate the rx queue data structure */
1984         rxq = rte_zmalloc_socket("i40e rx queue",
1985                                  sizeof(struct i40e_rx_queue),
1986                                  RTE_CACHE_LINE_SIZE,
1987                                  socket_id);
1988         if (!rxq) {
1989                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1990                             "rx queue data structure");
1991                 return -ENOMEM;
1992         }
1993         rxq->mp = mp;
1994         rxq->nb_rx_desc = nb_desc;
1995         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1996         rxq->queue_id = queue_idx;
1997         rxq->reg_idx = reg_idx;
1998         rxq->port_id = dev->data->port_id;
1999         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
2000                 rxq->crc_len = RTE_ETHER_CRC_LEN;
2001         else
2002                 rxq->crc_len = 0;
2003         rxq->drop_en = rx_conf->rx_drop_en;
2004         rxq->vsi = vsi;
2005         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2006         rxq->offloads = offloads;
2007
2008         /* Allocate the maximun number of RX ring hardware descriptor. */
2009         len = I40E_MAX_RING_DESC;
2010
2011         /**
2012          * Allocating a little more memory because vectorized/bulk_alloc Rx
2013          * functions doesn't check boundaries each time.
2014          */
2015         len += RTE_PMD_I40E_RX_MAX_BURST;
2016
2017         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
2018                               I40E_DMA_MEM_ALIGN);
2019
2020         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2021                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2022         if (!rz) {
2023                 i40e_dev_rx_queue_release(rxq);
2024                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2025                 return -ENOMEM;
2026         }
2027
2028         /* Zero all the descriptors in the ring. */
2029         memset(rz->addr, 0, ring_size);
2030
2031         rxq->rx_ring_phys_addr = rz->iova;
2032         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2033
2034         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2035
2036         /* Allocate the software ring. */
2037         rxq->sw_ring =
2038                 rte_zmalloc_socket("i40e rx sw ring",
2039                                    sizeof(struct i40e_rx_entry) * len,
2040                                    RTE_CACHE_LINE_SIZE,
2041                                    socket_id);
2042         if (!rxq->sw_ring) {
2043                 i40e_dev_rx_queue_release(rxq);
2044                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2045                 return -ENOMEM;
2046         }
2047
2048         i40e_reset_rx_queue(rxq);
2049         rxq->q_set = TRUE;
2050
2051         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2052                 if (!(vsi->enabled_tc & (1 << i)))
2053                         continue;
2054                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2055                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2056                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2057                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2058                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2059
2060                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2061                         rxq->dcb_tc = i;
2062         }
2063
2064         if (dev->data->dev_started) {
2065                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
2066                         i40e_dev_rx_queue_release(rxq);
2067                         return -EINVAL;
2068                 }
2069         } else {
2070                 use_def_burst_func =
2071                         check_rx_burst_bulk_alloc_preconditions(rxq);
2072                 if (!use_def_burst_func) {
2073 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2074                         PMD_INIT_LOG(DEBUG,
2075                           "Rx Burst Bulk Alloc Preconditions are "
2076                           "satisfied. Rx Burst Bulk Alloc function will be "
2077                           "used on port=%d, queue=%d.",
2078                           rxq->port_id, rxq->queue_id);
2079 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2080                 } else {
2081                         PMD_INIT_LOG(DEBUG,
2082                           "Rx Burst Bulk Alloc Preconditions are "
2083                           "not satisfied, Scattered Rx is requested, "
2084                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2085                           "not enabled on port=%d, queue=%d.",
2086                           rxq->port_id, rxq->queue_id);
2087                         ad->rx_bulk_alloc_allowed = false;
2088                 }
2089         }
2090
2091         dev->data->rx_queues[queue_idx] = rxq;
2092         return 0;
2093 }
2094
2095 void
2096 i40e_dev_rx_queue_release(void *rxq)
2097 {
2098         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2099
2100         if (!q) {
2101                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2102                 return;
2103         }
2104
2105         i40e_rx_queue_release_mbufs(q);
2106         rte_free(q->sw_ring);
2107         rte_free(q);
2108 }
2109
2110 uint32_t
2111 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2112 {
2113 #define I40E_RXQ_SCAN_INTERVAL 4
2114         volatile union i40e_rx_desc *rxdp;
2115         struct i40e_rx_queue *rxq;
2116         uint16_t desc = 0;
2117
2118         rxq = dev->data->rx_queues[rx_queue_id];
2119         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2120         while ((desc < rxq->nb_rx_desc) &&
2121                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2122                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2123                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2124                 /**
2125                  * Check the DD bit of a rx descriptor of each 4 in a group,
2126                  * to avoid checking too frequently and downgrading performance
2127                  * too much.
2128                  */
2129                 desc += I40E_RXQ_SCAN_INTERVAL;
2130                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2131                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2132                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2133                                         desc - rxq->nb_rx_desc]);
2134         }
2135
2136         return desc;
2137 }
2138
2139 int
2140 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2141 {
2142         volatile union i40e_rx_desc *rxdp;
2143         struct i40e_rx_queue *rxq = rx_queue;
2144         uint16_t desc;
2145         int ret;
2146
2147         if (unlikely(offset >= rxq->nb_rx_desc)) {
2148                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2149                 return 0;
2150         }
2151
2152         desc = rxq->rx_tail + offset;
2153         if (desc >= rxq->nb_rx_desc)
2154                 desc -= rxq->nb_rx_desc;
2155
2156         rxdp = &(rxq->rx_ring[desc]);
2157
2158         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2159                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2160                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2161
2162         return ret;
2163 }
2164
2165 int
2166 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2167 {
2168         struct i40e_rx_queue *rxq = rx_queue;
2169         volatile uint64_t *status;
2170         uint64_t mask;
2171         uint32_t desc;
2172
2173         if (unlikely(offset >= rxq->nb_rx_desc))
2174                 return -EINVAL;
2175
2176         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2177                 return RTE_ETH_RX_DESC_UNAVAIL;
2178
2179         desc = rxq->rx_tail + offset;
2180         if (desc >= rxq->nb_rx_desc)
2181                 desc -= rxq->nb_rx_desc;
2182
2183         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2184         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2185                 << I40E_RXD_QW1_STATUS_SHIFT);
2186         if (*status & mask)
2187                 return RTE_ETH_RX_DESC_DONE;
2188
2189         return RTE_ETH_RX_DESC_AVAIL;
2190 }
2191
2192 int
2193 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2194 {
2195         struct i40e_tx_queue *txq = tx_queue;
2196         volatile uint64_t *status;
2197         uint64_t mask, expect;
2198         uint32_t desc;
2199
2200         if (unlikely(offset >= txq->nb_tx_desc))
2201                 return -EINVAL;
2202
2203         desc = txq->tx_tail + offset;
2204         /* go to next desc that has the RS bit */
2205         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2206                 txq->tx_rs_thresh;
2207         if (desc >= txq->nb_tx_desc) {
2208                 desc -= txq->nb_tx_desc;
2209                 if (desc >= txq->nb_tx_desc)
2210                         desc -= txq->nb_tx_desc;
2211         }
2212
2213         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2214         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2215         expect = rte_cpu_to_le_64(
2216                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2217         if ((*status & mask) == expect)
2218                 return RTE_ETH_TX_DESC_DONE;
2219
2220         return RTE_ETH_TX_DESC_FULL;
2221 }
2222
2223 static int
2224 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2225                                 struct i40e_tx_queue *txq)
2226 {
2227         struct i40e_adapter *ad =
2228                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2229
2230         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2231                 PMD_DRV_LOG(ERR,
2232                             "Failed to do TX queue initialization");
2233                 return -EINVAL;
2234         }
2235
2236         if (i40e_dev_first_queue(txq->queue_id,
2237                                  dev->data->tx_queues,
2238                                  dev->data->nb_tx_queues)) {
2239                 /**
2240                  * If it is the first queue to setup,
2241                  * set all flags and call
2242                  * i40e_set_tx_function.
2243                  */
2244                 i40e_set_tx_function_flag(dev, txq);
2245                 i40e_set_tx_function(dev);
2246                 return 0;
2247         }
2248
2249         /* check vector conflict */
2250         if (ad->tx_vec_allowed) {
2251                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2252                     i40e_txq_vec_setup(txq)) {
2253                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2254                         return -EINVAL;
2255                 }
2256         }
2257         /* check simple tx conflict */
2258         if (ad->tx_simple_allowed) {
2259                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2260                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2261                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2262                         return -EINVAL;
2263                 }
2264         }
2265
2266         return 0;
2267 }
2268
2269 int
2270 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2271                         uint16_t queue_idx,
2272                         uint16_t nb_desc,
2273                         unsigned int socket_id,
2274                         const struct rte_eth_txconf *tx_conf)
2275 {
2276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277         struct i40e_vsi *vsi;
2278         struct i40e_pf *pf = NULL;
2279         struct i40e_vf *vf = NULL;
2280         struct i40e_tx_queue *txq;
2281         const struct rte_memzone *tz;
2282         uint32_t ring_size;
2283         uint16_t tx_rs_thresh, tx_free_thresh;
2284         uint16_t reg_idx, i, base, bsf, tc_mapping;
2285         int q_offset;
2286         uint64_t offloads;
2287
2288         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2289
2290         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2291                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2292                 vsi = &vf->vsi;
2293                 reg_idx = queue_idx;
2294         } else {
2295                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2297                 if (!vsi)
2298                         return -EINVAL;
2299                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2300                 if (q_offset < 0)
2301                         return -EINVAL;
2302                 reg_idx = vsi->base_queue + q_offset;
2303         }
2304
2305         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2306             (nb_desc > I40E_MAX_RING_DESC) ||
2307             (nb_desc < I40E_MIN_RING_DESC)) {
2308                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2309                             "invalid", nb_desc);
2310                 return -EINVAL;
2311         }
2312
2313         /**
2314          * The following two parameters control the setting of the RS bit on
2315          * transmit descriptors. TX descriptors will have their RS bit set
2316          * after txq->tx_rs_thresh descriptors have been used. The TX
2317          * descriptor ring will be cleaned after txq->tx_free_thresh
2318          * descriptors are used or if the number of descriptors required to
2319          * transmit a packet is greater than the number of free TX descriptors.
2320          *
2321          * The following constraints must be satisfied:
2322          *  - tx_rs_thresh must be greater than 0.
2323          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2324          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2325          *  - tx_rs_thresh must be a divisor of the ring size.
2326          *  - tx_free_thresh must be greater than 0.
2327          *  - tx_free_thresh must be less than the size of the ring minus 3.
2328          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2329          *
2330          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2331          * race condition, hence the maximum threshold constraints. When set
2332          * to zero use default values.
2333          */
2334         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2335                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2336         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2337         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2338                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2339         if (tx_conf->tx_rs_thresh > 0)
2340                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2341         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2342                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2343                                 "exceed nb_desc. (tx_rs_thresh=%u "
2344                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2345                                 (unsigned int)tx_rs_thresh,
2346                                 (unsigned int)tx_free_thresh,
2347                                 (unsigned int)nb_desc,
2348                                 (int)dev->data->port_id,
2349                                 (int)queue_idx);
2350                 return I40E_ERR_PARAM;
2351         }
2352         if (tx_rs_thresh >= (nb_desc - 2)) {
2353                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2354                              "number of TX descriptors minus 2. "
2355                              "(tx_rs_thresh=%u port=%d queue=%d)",
2356                              (unsigned int)tx_rs_thresh,
2357                              (int)dev->data->port_id,
2358                              (int)queue_idx);
2359                 return I40E_ERR_PARAM;
2360         }
2361         if (tx_free_thresh >= (nb_desc - 3)) {
2362                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2363                              "number of TX descriptors minus 3. "
2364                              "(tx_free_thresh=%u port=%d queue=%d)",
2365                              (unsigned int)tx_free_thresh,
2366                              (int)dev->data->port_id,
2367                              (int)queue_idx);
2368                 return I40E_ERR_PARAM;
2369         }
2370         if (tx_rs_thresh > tx_free_thresh) {
2371                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2372                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2373                              " tx_rs_thresh=%u port=%d queue=%d)",
2374                              (unsigned int)tx_free_thresh,
2375                              (unsigned int)tx_rs_thresh,
2376                              (int)dev->data->port_id,
2377                              (int)queue_idx);
2378                 return I40E_ERR_PARAM;
2379         }
2380         if ((nb_desc % tx_rs_thresh) != 0) {
2381                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2382                              "number of TX descriptors. (tx_rs_thresh=%u"
2383                              " port=%d queue=%d)",
2384                              (unsigned int)tx_rs_thresh,
2385                              (int)dev->data->port_id,
2386                              (int)queue_idx);
2387                 return I40E_ERR_PARAM;
2388         }
2389         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2390                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2391                              "tx_rs_thresh is greater than 1. "
2392                              "(tx_rs_thresh=%u port=%d queue=%d)",
2393                              (unsigned int)tx_rs_thresh,
2394                              (int)dev->data->port_id,
2395                              (int)queue_idx);
2396                 return I40E_ERR_PARAM;
2397         }
2398
2399         /* Free memory if needed. */
2400         if (dev->data->tx_queues[queue_idx]) {
2401                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2402                 dev->data->tx_queues[queue_idx] = NULL;
2403         }
2404
2405         /* Allocate the TX queue data structure. */
2406         txq = rte_zmalloc_socket("i40e tx queue",
2407                                   sizeof(struct i40e_tx_queue),
2408                                   RTE_CACHE_LINE_SIZE,
2409                                   socket_id);
2410         if (!txq) {
2411                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2412                             "tx queue structure");
2413                 return -ENOMEM;
2414         }
2415
2416         /* Allocate TX hardware ring descriptors. */
2417         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2418         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2419         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2420                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2421         if (!tz) {
2422                 i40e_dev_tx_queue_release(txq);
2423                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2424                 return -ENOMEM;
2425         }
2426
2427         txq->nb_tx_desc = nb_desc;
2428         txq->tx_rs_thresh = tx_rs_thresh;
2429         txq->tx_free_thresh = tx_free_thresh;
2430         txq->pthresh = tx_conf->tx_thresh.pthresh;
2431         txq->hthresh = tx_conf->tx_thresh.hthresh;
2432         txq->wthresh = tx_conf->tx_thresh.wthresh;
2433         txq->queue_id = queue_idx;
2434         txq->reg_idx = reg_idx;
2435         txq->port_id = dev->data->port_id;
2436         txq->offloads = offloads;
2437         txq->vsi = vsi;
2438         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2439
2440         txq->tx_ring_phys_addr = tz->iova;
2441         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2442
2443         /* Allocate software ring */
2444         txq->sw_ring =
2445                 rte_zmalloc_socket("i40e tx sw ring",
2446                                    sizeof(struct i40e_tx_entry) * nb_desc,
2447                                    RTE_CACHE_LINE_SIZE,
2448                                    socket_id);
2449         if (!txq->sw_ring) {
2450                 i40e_dev_tx_queue_release(txq);
2451                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2452                 return -ENOMEM;
2453         }
2454
2455         i40e_reset_tx_queue(txq);
2456         txq->q_set = TRUE;
2457
2458         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2459                 if (!(vsi->enabled_tc & (1 << i)))
2460                         continue;
2461                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2462                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2463                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2464                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2465                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2466
2467                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2468                         txq->dcb_tc = i;
2469         }
2470
2471         if (dev->data->dev_started) {
2472                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2473                         i40e_dev_tx_queue_release(txq);
2474                         return -EINVAL;
2475                 }
2476         } else {
2477                 /**
2478                  * Use a simple TX queue without offloads or
2479                  * multi segs if possible
2480                  */
2481                 i40e_set_tx_function_flag(dev, txq);
2482         }
2483         dev->data->tx_queues[queue_idx] = txq;
2484
2485         return 0;
2486 }
2487
2488 void
2489 i40e_dev_tx_queue_release(void *txq)
2490 {
2491         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2492
2493         if (!q) {
2494                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2495                 return;
2496         }
2497
2498         i40e_tx_queue_release_mbufs(q);
2499         rte_free(q->sw_ring);
2500         rte_free(q);
2501 }
2502
2503 const struct rte_memzone *
2504 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2505 {
2506         const struct rte_memzone *mz;
2507
2508         mz = rte_memzone_lookup(name);
2509         if (mz)
2510                 return mz;
2511
2512         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2513                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2514         return mz;
2515 }
2516
2517 void
2518 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2519 {
2520         uint16_t i;
2521
2522         /* SSE Vector driver has a different way of releasing mbufs. */
2523         if (rxq->rx_using_sse) {
2524                 i40e_rx_queue_release_mbufs_vec(rxq);
2525                 return;
2526         }
2527
2528         if (!rxq->sw_ring) {
2529                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2530                 return;
2531         }
2532
2533         for (i = 0; i < rxq->nb_rx_desc; i++) {
2534                 if (rxq->sw_ring[i].mbuf) {
2535                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2536                         rxq->sw_ring[i].mbuf = NULL;
2537                 }
2538         }
2539 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2540         if (rxq->rx_nb_avail == 0)
2541                 return;
2542         for (i = 0; i < rxq->rx_nb_avail; i++) {
2543                 struct rte_mbuf *mbuf;
2544
2545                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2546                 rte_pktmbuf_free_seg(mbuf);
2547         }
2548         rxq->rx_nb_avail = 0;
2549 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2550 }
2551
2552 void
2553 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2554 {
2555         unsigned i;
2556         uint16_t len;
2557
2558         if (!rxq) {
2559                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2560                 return;
2561         }
2562
2563 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2564         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2565                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2566         else
2567 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2568                 len = rxq->nb_rx_desc;
2569
2570         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2571                 ((volatile char *)rxq->rx_ring)[i] = 0;
2572
2573         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2574         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2575                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2576
2577 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2578         rxq->rx_nb_avail = 0;
2579         rxq->rx_next_avail = 0;
2580         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2581 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2582         rxq->rx_tail = 0;
2583         rxq->nb_rx_hold = 0;
2584         rxq->pkt_first_seg = NULL;
2585         rxq->pkt_last_seg = NULL;
2586
2587         rxq->rxrearm_start = 0;
2588         rxq->rxrearm_nb = 0;
2589 }
2590
2591 void
2592 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2593 {
2594         struct rte_eth_dev *dev;
2595         uint16_t i;
2596
2597         if (!txq || !txq->sw_ring) {
2598                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2599                 return;
2600         }
2601
2602         dev = &rte_eth_devices[txq->port_id];
2603
2604         /**
2605          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2606          *  so need to free remains more carefully.
2607          */
2608 #ifdef CC_AVX512_SUPPORT
2609         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx512) {
2610                 struct i40e_vec_tx_entry *swr = (void *)txq->sw_ring;
2611
2612                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2613                 if (txq->tx_tail < i) {
2614                         for (; i < txq->nb_tx_desc; i++) {
2615                                 rte_pktmbuf_free_seg(swr[i].mbuf);
2616                                 swr[i].mbuf = NULL;
2617                         }
2618                         i = 0;
2619                 }
2620                 for (; i < txq->tx_tail; i++) {
2621                         rte_pktmbuf_free_seg(swr[i].mbuf);
2622                         swr[i].mbuf = NULL;
2623                 }
2624                 return;
2625         }
2626 #endif
2627         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2628                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2629                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2630                 if (txq->tx_tail < i) {
2631                         for (; i < txq->nb_tx_desc; i++) {
2632                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2633                                 txq->sw_ring[i].mbuf = NULL;
2634                         }
2635                         i = 0;
2636                 }
2637                 for (; i < txq->tx_tail; i++) {
2638                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2639                         txq->sw_ring[i].mbuf = NULL;
2640                 }
2641         } else {
2642                 for (i = 0; i < txq->nb_tx_desc; i++) {
2643                         if (txq->sw_ring[i].mbuf) {
2644                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2645                                 txq->sw_ring[i].mbuf = NULL;
2646                         }
2647                 }
2648         }
2649 }
2650
2651 static int
2652 i40e_tx_done_cleanup_full(struct i40e_tx_queue *txq,
2653                         uint32_t free_cnt)
2654 {
2655         struct i40e_tx_entry *swr_ring = txq->sw_ring;
2656         uint16_t i, tx_last, tx_id;
2657         uint16_t nb_tx_free_last;
2658         uint16_t nb_tx_to_clean;
2659         uint32_t pkt_cnt;
2660
2661         /* Start free mbuf from the next of tx_tail */
2662         tx_last = txq->tx_tail;
2663         tx_id  = swr_ring[tx_last].next_id;
2664
2665         if (txq->nb_tx_free == 0 && i40e_xmit_cleanup(txq))
2666                 return 0;
2667
2668         nb_tx_to_clean = txq->nb_tx_free;
2669         nb_tx_free_last = txq->nb_tx_free;
2670         if (!free_cnt)
2671                 free_cnt = txq->nb_tx_desc;
2672
2673         /* Loop through swr_ring to count the amount of
2674          * freeable mubfs and packets.
2675          */
2676         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2677                 for (i = 0; i < nb_tx_to_clean &&
2678                         pkt_cnt < free_cnt &&
2679                         tx_id != tx_last; i++) {
2680                         if (swr_ring[tx_id].mbuf != NULL) {
2681                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2682                                 swr_ring[tx_id].mbuf = NULL;
2683
2684                                 /*
2685                                  * last segment in the packet,
2686                                  * increment packet count
2687                                  */
2688                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2689                         }
2690
2691                         tx_id = swr_ring[tx_id].next_id;
2692                 }
2693
2694                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2695                         txq->nb_tx_free || tx_id == tx_last)
2696                         break;
2697
2698                 if (pkt_cnt < free_cnt) {
2699                         if (i40e_xmit_cleanup(txq))
2700                                 break;
2701
2702                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2703                         nb_tx_free_last = txq->nb_tx_free;
2704                 }
2705         }
2706
2707         return (int)pkt_cnt;
2708 }
2709
2710 static int
2711 i40e_tx_done_cleanup_simple(struct i40e_tx_queue *txq,
2712                         uint32_t free_cnt)
2713 {
2714         int i, n, cnt;
2715
2716         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2717                 free_cnt = txq->nb_tx_desc;
2718
2719         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2720
2721         for (i = 0; i < cnt; i += n) {
2722                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2723                         break;
2724
2725                 n = i40e_tx_free_bufs(txq);
2726
2727                 if (n == 0)
2728                         break;
2729         }
2730
2731         return i;
2732 }
2733
2734 static int
2735 i40e_tx_done_cleanup_vec(struct i40e_tx_queue *txq __rte_unused,
2736                         uint32_t free_cnt __rte_unused)
2737 {
2738         return -ENOTSUP;
2739 }
2740 int
2741 i40e_tx_done_cleanup(void *txq, uint32_t free_cnt)
2742 {
2743         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2744         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2745         struct i40e_adapter *ad =
2746                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2747
2748         if (ad->tx_simple_allowed) {
2749                 if (ad->tx_vec_allowed)
2750                         return i40e_tx_done_cleanup_vec(q, free_cnt);
2751                 else
2752                         return i40e_tx_done_cleanup_simple(q, free_cnt);
2753         } else {
2754                 return i40e_tx_done_cleanup_full(q, free_cnt);
2755         }
2756 }
2757
2758 void
2759 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2760 {
2761         struct i40e_tx_entry *txe;
2762         uint16_t i, prev, size;
2763
2764         if (!txq) {
2765                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2766                 return;
2767         }
2768
2769         txe = txq->sw_ring;
2770         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2771         for (i = 0; i < size; i++)
2772                 ((volatile char *)txq->tx_ring)[i] = 0;
2773
2774         prev = (uint16_t)(txq->nb_tx_desc - 1);
2775         for (i = 0; i < txq->nb_tx_desc; i++) {
2776                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2777
2778                 txd->cmd_type_offset_bsz =
2779                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2780                 txe[i].mbuf =  NULL;
2781                 txe[i].last_id = i;
2782                 txe[prev].next_id = i;
2783                 prev = i;
2784         }
2785
2786         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2787         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2788
2789         txq->tx_tail = 0;
2790         txq->nb_tx_used = 0;
2791
2792         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2793         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2794 }
2795
2796 /* Init the TX queue in hardware */
2797 int
2798 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2799 {
2800         enum i40e_status_code err = I40E_SUCCESS;
2801         struct i40e_vsi *vsi = txq->vsi;
2802         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2803         uint16_t pf_q = txq->reg_idx;
2804         struct i40e_hmc_obj_txq tx_ctx;
2805         uint32_t qtx_ctl;
2806
2807         /* clear the context structure first */
2808         memset(&tx_ctx, 0, sizeof(tx_ctx));
2809         tx_ctx.new_context = 1;
2810         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2811         tx_ctx.qlen = txq->nb_tx_desc;
2812
2813 #ifdef RTE_LIBRTE_IEEE1588
2814         tx_ctx.timesync_ena = 1;
2815 #endif
2816         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2817         if (vsi->type == I40E_VSI_FDIR)
2818                 tx_ctx.fd_ena = TRUE;
2819
2820         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2821         if (err != I40E_SUCCESS) {
2822                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2823                 return err;
2824         }
2825
2826         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2827         if (err != I40E_SUCCESS) {
2828                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2829                 return err;
2830         }
2831
2832         /* Now associate this queue with this PCI function */
2833         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2834         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2835                                         I40E_QTX_CTL_PF_INDX_MASK);
2836         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2837         I40E_WRITE_FLUSH(hw);
2838
2839         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2840
2841         return err;
2842 }
2843
2844 int
2845 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2846 {
2847         struct i40e_rx_entry *rxe = rxq->sw_ring;
2848         uint64_t dma_addr;
2849         uint16_t i;
2850
2851         for (i = 0; i < rxq->nb_rx_desc; i++) {
2852                 volatile union i40e_rx_desc *rxd;
2853                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2854
2855                 if (unlikely(!mbuf)) {
2856                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2857                         return -ENOMEM;
2858                 }
2859
2860                 rte_mbuf_refcnt_set(mbuf, 1);
2861                 mbuf->next = NULL;
2862                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2863                 mbuf->nb_segs = 1;
2864                 mbuf->port = rxq->port_id;
2865
2866                 dma_addr =
2867                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2868
2869                 rxd = &rxq->rx_ring[i];
2870                 rxd->read.pkt_addr = dma_addr;
2871                 rxd->read.hdr_addr = 0;
2872 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2873                 rxd->read.rsvd1 = 0;
2874                 rxd->read.rsvd2 = 0;
2875 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2876
2877                 rxe[i].mbuf = mbuf;
2878         }
2879
2880         return 0;
2881 }
2882
2883 /*
2884  * Calculate the buffer length, and check the jumbo frame
2885  * and maximum packet length.
2886  */
2887 static int
2888 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2889 {
2890         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2891         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2892         struct rte_eth_dev_data *data = pf->dev_data;
2893         uint16_t buf_size;
2894
2895         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2896                 RTE_PKTMBUF_HEADROOM);
2897
2898         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2899                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2900         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2901                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2902                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2903                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2904                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2905                 rxq->hs_mode = i40e_header_split_enabled;
2906                 break;
2907         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2908         default:
2909                 rxq->rx_hdr_len = 0;
2910                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2911                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2912                 rxq->hs_mode = i40e_header_split_none;
2913                 break;
2914         }
2915
2916         rxq->max_pkt_len =
2917                 RTE_MIN((uint32_t)(hw->func_caps.rx_buf_chain_len *
2918                         rxq->rx_buf_len), data->dev_conf.rxmode.max_rx_pkt_len);
2919         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2920                 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
2921                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2922                         PMD_DRV_LOG(ERR, "maximum packet length must "
2923                                     "be larger than %u and smaller than %u,"
2924                                     "as jumbo frame is enabled",
2925                                     (uint32_t)I40E_ETH_MAX_LEN,
2926                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2927                         return I40E_ERR_CONFIG;
2928                 }
2929         } else {
2930                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2931                         rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
2932                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2933                                     "larger than %u and smaller than %u, "
2934                                     "as jumbo frame is disabled",
2935                                     (uint32_t)RTE_ETHER_MIN_LEN,
2936                                     (uint32_t)I40E_ETH_MAX_LEN);
2937                         return I40E_ERR_CONFIG;
2938                 }
2939         }
2940
2941         return 0;
2942 }
2943
2944 /* Init the RX queue in hardware */
2945 int
2946 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2947 {
2948         int err = I40E_SUCCESS;
2949         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2950         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2951         uint16_t pf_q = rxq->reg_idx;
2952         uint16_t buf_size;
2953         struct i40e_hmc_obj_rxq rx_ctx;
2954
2955         err = i40e_rx_queue_config(rxq);
2956         if (err < 0) {
2957                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2958                 return err;
2959         }
2960
2961         /* Clear the context structure first */
2962         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2963         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2964         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2965
2966         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2967         rx_ctx.qlen = rxq->nb_rx_desc;
2968 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2969         rx_ctx.dsize = 1;
2970 #endif
2971         rx_ctx.dtype = rxq->hs_mode;
2972         if (rxq->hs_mode)
2973                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2974         else
2975                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2976         rx_ctx.rxmax = rxq->max_pkt_len;
2977         rx_ctx.tphrdesc_ena = 1;
2978         rx_ctx.tphwdesc_ena = 1;
2979         rx_ctx.tphdata_ena = 1;
2980         rx_ctx.tphhead_ena = 1;
2981         rx_ctx.lrxqthresh = 2;
2982         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2983         rx_ctx.l2tsel = 1;
2984         /* showiv indicates if inner VLAN is stripped inside of tunnel
2985          * packet. When set it to 1, vlan information is stripped from
2986          * the inner header, but the hardware does not put it in the
2987          * descriptor. So set it zero by default.
2988          */
2989         rx_ctx.showiv = 0;
2990         rx_ctx.prefena = 1;
2991
2992         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2993         if (err != I40E_SUCCESS) {
2994                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2995                 return err;
2996         }
2997         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2998         if (err != I40E_SUCCESS) {
2999                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
3000                 return err;
3001         }
3002
3003         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
3004
3005         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
3006                 RTE_PKTMBUF_HEADROOM);
3007
3008         /* Check if scattered RX needs to be used. */
3009         if (rxq->max_pkt_len > buf_size)
3010                 dev_data->scattered_rx = 1;
3011
3012         /* Init the RX tail regieter. */
3013         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3014
3015         return 0;
3016 }
3017
3018 void
3019 i40e_dev_clear_queues(struct rte_eth_dev *dev)
3020 {
3021         uint16_t i;
3022
3023         PMD_INIT_FUNC_TRACE();
3024
3025         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3026                 if (!dev->data->tx_queues[i])
3027                         continue;
3028                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
3029                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
3030         }
3031
3032         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3033                 if (!dev->data->rx_queues[i])
3034                         continue;
3035                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
3036                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
3037         }
3038 }
3039
3040 void
3041 i40e_dev_free_queues(struct rte_eth_dev *dev)
3042 {
3043         uint16_t i;
3044
3045         PMD_INIT_FUNC_TRACE();
3046
3047         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3048                 if (!dev->data->rx_queues[i])
3049                         continue;
3050                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
3051                 dev->data->rx_queues[i] = NULL;
3052                 rte_eth_dma_zone_free(dev, "rx_ring", i);
3053         }
3054
3055         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3056                 if (!dev->data->tx_queues[i])
3057                         continue;
3058                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
3059                 dev->data->tx_queues[i] = NULL;
3060                 rte_eth_dma_zone_free(dev, "tx_ring", i);
3061         }
3062 }
3063
3064 enum i40e_status_code
3065 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3066 {
3067         struct i40e_tx_queue *txq;
3068         const struct rte_memzone *tz = NULL;
3069         struct rte_eth_dev *dev;
3070         uint32_t ring_size;
3071
3072         if (!pf) {
3073                 PMD_DRV_LOG(ERR, "PF is not available");
3074                 return I40E_ERR_BAD_PTR;
3075         }
3076
3077         dev = &rte_eth_devices[pf->dev_data->port_id];
3078
3079         /* Allocate the TX queue data structure. */
3080         txq = rte_zmalloc_socket("i40e fdir tx queue",
3081                                   sizeof(struct i40e_tx_queue),
3082                                   RTE_CACHE_LINE_SIZE,
3083                                   SOCKET_ID_ANY);
3084         if (!txq) {
3085                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3086                                         "tx queue structure.");
3087                 return I40E_ERR_NO_MEMORY;
3088         }
3089
3090         /* Allocate TX hardware ring descriptors. */
3091         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3092         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3093
3094         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3095                                       I40E_FDIR_QUEUE_ID, ring_size,
3096                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3097         if (!tz) {
3098                 i40e_dev_tx_queue_release(txq);
3099                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3100                 return I40E_ERR_NO_MEMORY;
3101         }
3102
3103         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3104         txq->queue_id = I40E_FDIR_QUEUE_ID;
3105         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3106         txq->vsi = pf->fdir.fdir_vsi;
3107
3108         txq->tx_ring_phys_addr = tz->iova;
3109         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3110
3111         /*
3112          * don't need to allocate software ring and reset for the fdir
3113          * program queue just set the queue has been configured.
3114          */
3115         txq->q_set = TRUE;
3116         pf->fdir.txq = txq;
3117         pf->fdir.txq_available_buf_count = I40E_FDIR_PRG_PKT_CNT;
3118
3119         return I40E_SUCCESS;
3120 }
3121
3122 enum i40e_status_code
3123 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3124 {
3125         struct i40e_rx_queue *rxq;
3126         const struct rte_memzone *rz = NULL;
3127         uint32_t ring_size;
3128         struct rte_eth_dev *dev;
3129
3130         if (!pf) {
3131                 PMD_DRV_LOG(ERR, "PF is not available");
3132                 return I40E_ERR_BAD_PTR;
3133         }
3134
3135         dev = &rte_eth_devices[pf->dev_data->port_id];
3136
3137         /* Allocate the RX queue data structure. */
3138         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3139                                   sizeof(struct i40e_rx_queue),
3140                                   RTE_CACHE_LINE_SIZE,
3141                                   SOCKET_ID_ANY);
3142         if (!rxq) {
3143                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3144                                         "rx queue structure.");
3145                 return I40E_ERR_NO_MEMORY;
3146         }
3147
3148         /* Allocate RX hardware ring descriptors. */
3149         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3150         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3151
3152         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3153                                       I40E_FDIR_QUEUE_ID, ring_size,
3154                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3155         if (!rz) {
3156                 i40e_dev_rx_queue_release(rxq);
3157                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3158                 return I40E_ERR_NO_MEMORY;
3159         }
3160
3161         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3162         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3163         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3164         rxq->vsi = pf->fdir.fdir_vsi;
3165
3166         rxq->rx_ring_phys_addr = rz->iova;
3167         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
3168         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3169
3170         /*
3171          * Don't need to allocate software ring and reset for the fdir
3172          * rx queue, just set the queue has been configured.
3173          */
3174         rxq->q_set = TRUE;
3175         pf->fdir.rxq = rxq;
3176
3177         return I40E_SUCCESS;
3178 }
3179
3180 void
3181 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3182         struct rte_eth_rxq_info *qinfo)
3183 {
3184         struct i40e_rx_queue *rxq;
3185
3186         rxq = dev->data->rx_queues[queue_id];
3187
3188         qinfo->mp = rxq->mp;
3189         qinfo->scattered_rx = dev->data->scattered_rx;
3190         qinfo->nb_desc = rxq->nb_rx_desc;
3191
3192         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3193         qinfo->conf.rx_drop_en = rxq->drop_en;
3194         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3195         qinfo->conf.offloads = rxq->offloads;
3196 }
3197
3198 void
3199 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3200         struct rte_eth_txq_info *qinfo)
3201 {
3202         struct i40e_tx_queue *txq;
3203
3204         txq = dev->data->tx_queues[queue_id];
3205
3206         qinfo->nb_desc = txq->nb_tx_desc;
3207
3208         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3209         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3210         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3211
3212         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3213         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3214         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3215         qinfo->conf.offloads = txq->offloads;
3216 }
3217
3218 static inline bool
3219 get_avx_supported(bool request_avx512)
3220 {
3221 #ifdef RTE_ARCH_X86
3222         if (request_avx512) {
3223                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3224                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3225                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3226 #ifdef CC_AVX512_SUPPORT
3227                         return true;
3228 #else
3229                 PMD_DRV_LOG(NOTICE,
3230                         "AVX512 is not supported in build env");
3231                 return false;
3232 #endif
3233         } else {
3234                 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
3235                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 &&
3236                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3237 #ifdef CC_AVX2_SUPPORT
3238                         return true;
3239 #else
3240                 PMD_DRV_LOG(NOTICE,
3241                         "AVX2 is not supported in build env");
3242                 return false;
3243 #endif
3244         }
3245 #else
3246         RTE_SET_USED(request_avx512);
3247 #endif /* RTE_ARCH_X86 */
3248
3249         return false;
3250 }
3251
3252
3253 void __rte_cold
3254 i40e_set_rx_function(struct rte_eth_dev *dev)
3255 {
3256         struct i40e_adapter *ad =
3257                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3258         uint16_t rx_using_sse, i;
3259         /* In order to allow Vector Rx there are a few configuration
3260          * conditions to be met and Rx Bulk Allocation should be allowed.
3261          */
3262         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3263 #ifdef RTE_ARCH_X86
3264                 ad->rx_use_avx512 = false;
3265                 ad->rx_use_avx2 = false;
3266 #endif
3267                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3268                     !ad->rx_bulk_alloc_allowed) {
3269                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3270                                      " Vector Rx preconditions",
3271                                      dev->data->port_id);
3272
3273                         ad->rx_vec_allowed = false;
3274                 }
3275                 if (ad->rx_vec_allowed) {
3276                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3277                                 struct i40e_rx_queue *rxq =
3278                                         dev->data->rx_queues[i];
3279
3280                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
3281                                         ad->rx_vec_allowed = false;
3282                                         break;
3283                                 }
3284                         }
3285 #ifdef RTE_ARCH_X86
3286                         ad->rx_use_avx512 = get_avx_supported(1);
3287
3288                         if (!ad->rx_use_avx512)
3289                                 ad->rx_use_avx2 = get_avx_supported(0);
3290 #endif
3291                 }
3292         }
3293
3294         if (ad->rx_vec_allowed  &&
3295             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3296 #ifdef RTE_ARCH_X86
3297                 if (dev->data->scattered_rx) {
3298                         if (ad->rx_use_avx512) {
3299 #ifdef CC_AVX512_SUPPORT
3300                                 PMD_DRV_LOG(NOTICE,
3301                                         "Using AVX512 Vector Scattered Rx (port %d).",
3302                                         dev->data->port_id);
3303                                 dev->rx_pkt_burst =
3304                                         i40e_recv_scattered_pkts_vec_avx512;
3305 #endif
3306                         } else {
3307                                 PMD_INIT_LOG(DEBUG,
3308                                         "Using %sVector Scattered Rx (port %d).",
3309                                         ad->rx_use_avx2 ? "avx2 " : "",
3310                                         dev->data->port_id);
3311                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3312                                         i40e_recv_scattered_pkts_vec_avx2 :
3313                                         i40e_recv_scattered_pkts_vec;
3314                         }
3315                 } else {
3316                         if (ad->rx_use_avx512) {
3317 #ifdef CC_AVX512_SUPPORT
3318                                 PMD_DRV_LOG(NOTICE,
3319                                         "Using AVX512 Vector Rx (port %d).",
3320                                         dev->data->port_id);
3321                                 dev->rx_pkt_burst =
3322                                         i40e_recv_pkts_vec_avx512;
3323 #endif
3324                         } else {
3325                                 PMD_INIT_LOG(DEBUG,
3326                                         "Using %sVector Rx (port %d).",
3327                                         ad->rx_use_avx2 ? "avx2 " : "",
3328                                         dev->data->port_id);
3329                                 dev->rx_pkt_burst = ad->rx_use_avx2 ?
3330                                         i40e_recv_pkts_vec_avx2 :
3331                                         i40e_recv_pkts_vec;
3332                         }
3333                 }
3334 #else /* RTE_ARCH_X86 */
3335                 if (dev->data->scattered_rx) {
3336                         PMD_INIT_LOG(DEBUG,
3337                                      "Using Vector Scattered Rx (port %d).",
3338                                      dev->data->port_id);
3339                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3340                 } else {
3341                         PMD_INIT_LOG(DEBUG, "Using Vector Rx (port %d).",
3342                                      dev->data->port_id);
3343                         dev->rx_pkt_burst = i40e_recv_pkts_vec;
3344                 }
3345 #endif /* RTE_ARCH_X86 */
3346         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
3347                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3348                                     "satisfied. Rx Burst Bulk Alloc function "
3349                                     "will be used on port=%d.",
3350                              dev->data->port_id);
3351
3352                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3353         } else {
3354                 /* Simple Rx Path. */
3355                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3356                              dev->data->port_id);
3357                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3358                                         i40e_recv_scattered_pkts :
3359                                         i40e_recv_pkts;
3360         }
3361
3362         /* Propagate information about RX function choice through all queues. */
3363         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3364                 rx_using_sse =
3365                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3366                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3367 #ifdef CC_AVX512_SUPPORT
3368                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx512 ||
3369                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx512 ||
3370 #endif
3371                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3372                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3373
3374                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3375                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3376
3377                         if (rxq)
3378                                 rxq->rx_using_sse = rx_using_sse;
3379                 }
3380         }
3381 }
3382
3383 static const struct {
3384         eth_rx_burst_t pkt_burst;
3385         const char *info;
3386 } i40e_rx_burst_infos[] = {
3387         { i40e_recv_scattered_pkts,          "Scalar Scattered" },
3388         { i40e_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3389         { i40e_recv_pkts,                    "Scalar" },
3390 #ifdef RTE_ARCH_X86
3391 #ifdef CC_AVX512_SUPPORT
3392         { i40e_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3393         { i40e_recv_pkts_vec_avx512,           "Vector AVX512" },
3394 #endif
3395         { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3396         { i40e_recv_pkts_vec_avx2,           "Vector AVX2" },
3397         { i40e_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3398         { i40e_recv_pkts_vec,                "Vector SSE" },
3399 #elif defined(RTE_ARCH_ARM64)
3400         { i40e_recv_scattered_pkts_vec,      "Vector Neon Scattered" },
3401         { i40e_recv_pkts_vec,                "Vector Neon" },
3402 #elif defined(RTE_ARCH_PPC_64)
3403         { i40e_recv_scattered_pkts_vec,      "Vector AltiVec Scattered" },
3404         { i40e_recv_pkts_vec,                "Vector AltiVec" },
3405 #endif
3406 };
3407
3408 int
3409 i40e_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3410                        struct rte_eth_burst_mode *mode)
3411 {
3412         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3413         int ret = -EINVAL;
3414         unsigned int i;
3415
3416         for (i = 0; i < RTE_DIM(i40e_rx_burst_infos); ++i) {
3417                 if (pkt_burst == i40e_rx_burst_infos[i].pkt_burst) {
3418                         snprintf(mode->info, sizeof(mode->info), "%s",
3419                                  i40e_rx_burst_infos[i].info);
3420                         ret = 0;
3421                         break;
3422                 }
3423         }
3424
3425         return ret;
3426 }
3427
3428 void __rte_cold
3429 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3430 {
3431         struct i40e_adapter *ad =
3432                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3433
3434         /* Use a simple Tx queue if possible (only fast free is allowed) */
3435         ad->tx_simple_allowed =
3436                 (txq->offloads ==
3437                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3438                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3439         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3440                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3441
3442         if (ad->tx_vec_allowed)
3443                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3444                                 txq->queue_id);
3445         else if (ad->tx_simple_allowed)
3446                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3447                                 txq->queue_id);
3448         else
3449                 PMD_INIT_LOG(DEBUG,
3450                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3451                                 txq->queue_id);
3452 }
3453
3454 void __rte_cold
3455 i40e_set_tx_function(struct rte_eth_dev *dev)
3456 {
3457         struct i40e_adapter *ad =
3458                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3459         int i;
3460
3461         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3462 #ifdef RTE_ARCH_X86
3463                 ad->tx_use_avx2 = false;
3464                 ad->tx_use_avx512 = false;
3465 #endif
3466                 if (ad->tx_vec_allowed) {
3467                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3468                                 struct i40e_tx_queue *txq =
3469                                         dev->data->tx_queues[i];
3470
3471                                 if (txq && i40e_txq_vec_setup(txq)) {
3472                                         ad->tx_vec_allowed = false;
3473                                         break;
3474                                 }
3475                         }
3476 #ifdef RTE_ARCH_X86
3477                         ad->tx_use_avx512 = get_avx_supported(1);
3478
3479                         if (!ad->tx_use_avx512)
3480                                 ad->tx_use_avx2 = get_avx_supported(0);
3481 #endif
3482                 }
3483         }
3484
3485         if (ad->tx_simple_allowed) {
3486                 if (ad->tx_vec_allowed &&
3487                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3488 #ifdef RTE_ARCH_X86
3489                         if (ad->tx_use_avx512) {
3490 #ifdef CC_AVX512_SUPPORT
3491                                 PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3492                                             dev->data->port_id);
3493                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx512;
3494 #endif
3495                         } else {
3496                                 PMD_INIT_LOG(DEBUG, "Using %sVector Tx (port %d).",
3497                                              ad->tx_use_avx2 ? "avx2 " : "",
3498                                              dev->data->port_id);
3499                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3500                                                     i40e_xmit_pkts_vec_avx2 :
3501                                                     i40e_xmit_pkts_vec;
3502                         }
3503 #else /* RTE_ARCH_X86 */
3504                         PMD_INIT_LOG(DEBUG, "Using Vector Tx (port %d).",
3505                                      dev->data->port_id);
3506                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3507 #endif /* RTE_ARCH_X86 */
3508                 } else {
3509                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3510                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3511                 }
3512                 dev->tx_pkt_prepare = i40e_simple_prep_pkts;
3513         } else {
3514                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3515                 dev->tx_pkt_burst = i40e_xmit_pkts;
3516                 dev->tx_pkt_prepare = i40e_prep_pkts;
3517         }
3518 }
3519
3520 static const struct {
3521         eth_tx_burst_t pkt_burst;
3522         const char *info;
3523 } i40e_tx_burst_infos[] = {
3524         { i40e_xmit_pkts_simple,   "Scalar Simple" },
3525         { i40e_xmit_pkts,          "Scalar" },
3526 #ifdef RTE_ARCH_X86
3527 #ifdef CC_AVX512_SUPPORT
3528         { i40e_xmit_pkts_vec_avx512, "Vector AVX512" },
3529 #endif
3530         { i40e_xmit_pkts_vec_avx2, "Vector AVX2" },
3531         { i40e_xmit_pkts_vec,      "Vector SSE" },
3532 #elif defined(RTE_ARCH_ARM64)
3533         { i40e_xmit_pkts_vec,      "Vector Neon" },
3534 #elif defined(RTE_ARCH_PPC_64)
3535         { i40e_xmit_pkts_vec,      "Vector AltiVec" },
3536 #endif
3537 };
3538
3539 int
3540 i40e_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3541                        struct rte_eth_burst_mode *mode)
3542 {
3543         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3544         int ret = -EINVAL;
3545         unsigned int i;
3546
3547         for (i = 0; i < RTE_DIM(i40e_tx_burst_infos); ++i) {
3548                 if (pkt_burst == i40e_tx_burst_infos[i].pkt_burst) {
3549                         snprintf(mode->info, sizeof(mode->info), "%s",
3550                                  i40e_tx_burst_infos[i].info);
3551                         ret = 0;
3552                         break;
3553                 }
3554         }
3555
3556         return ret;
3557 }
3558
3559 void __rte_cold
3560 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3561 {
3562         struct i40e_adapter *ad =
3563                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3564         int i;
3565
3566         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3567                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3568 }
3569
3570 void __rte_cold
3571 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3572 {
3573         struct i40e_adapter *ad =
3574                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576         int i;
3577
3578         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3579                 ad->pctypes_tbl[i] = 0ULL;
3580         ad->flow_types_mask = 0ULL;
3581         ad->pctypes_mask = 0ULL;
3582
3583         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3584                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3585         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3586                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3587         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3588                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3589         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3590                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3591         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3592                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3593         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3594                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3595         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3596                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3597         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3598                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3599         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3600                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3601         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3602                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3603         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3604                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3605
3606         if (hw->mac.type == I40E_MAC_X722 ||
3607                 hw->mac.type == I40E_MAC_X722_VF) {
3608                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3609                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3610                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3611                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3612                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3613                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3614                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3615                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3616                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3617                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3618                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3619                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3620         }
3621
3622         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3623                 if (ad->pctypes_tbl[i])
3624                         ad->flow_types_mask |= (1ULL << i);
3625                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3626         }
3627 }
3628
3629 #ifndef CC_AVX2_SUPPORT
3630 uint16_t
3631 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3632                         struct rte_mbuf __rte_unused **rx_pkts,
3633                         uint16_t __rte_unused nb_pkts)
3634 {
3635         return 0;
3636 }
3637
3638 uint16_t
3639 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3640                         struct rte_mbuf __rte_unused **rx_pkts,
3641                         uint16_t __rte_unused nb_pkts)
3642 {
3643         return 0;
3644 }
3645
3646 uint16_t
3647 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3648                           struct rte_mbuf __rte_unused **tx_pkts,
3649                           uint16_t __rte_unused nb_pkts)
3650 {
3651         return 0;
3652 }
3653 #endif /* ifndef CC_AVX2_SUPPORT */