1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
6 #include <ethdev_driver.h>
7 #include <rte_malloc.h>
9 #include "base/i40e_prototype.h"
10 #include "base/i40e_type.h"
11 #include "i40e_ethdev.h"
12 #include "i40e_rxtx.h"
13 #include "i40e_rxtx_vec_common.h"
17 #ifndef __INTEL_COMPILER
18 #pragma GCC diagnostic ignored "-Wcast-qual"
21 #define RTE_I40E_DESCS_PER_LOOP_AVX 8
23 static __rte_always_inline void
24 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
28 volatile union i40e_rx_desc *rxdp;
29 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
30 struct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,
33 rxdp = rxq->rx_ring + rxq->rxrearm_start;
36 return i40e_rxq_rearm_common(rxq, true);
38 /* We need to pull 'n' more MBUFs into the software ring from mempool
39 * We inline the mempool function here, so we can vectorize the copy
40 * from the cache into the shadow ring.
43 if (cache->len < RTE_I40E_RXQ_REARM_THRESH) {
44 /* No. Backfill the cache first, and then fill from it */
45 uint32_t req = RTE_I40E_RXQ_REARM_THRESH + (cache->size -
48 /* How many do we require
49 * i.e. number to fill the cache + the request
51 int ret = rte_mempool_ops_dequeue_bulk(rxq->mp,
52 &cache->objs[cache->len], req);
56 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
60 dma_addr0 = _mm_setzero_si128();
61 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
62 rxep[i].mbuf = &rxq->fake_mbuf;
64 ((__m128i *)&rxdp[i].read,
68 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
69 RTE_I40E_RXQ_REARM_THRESH;
74 const __m512i iova_offsets = _mm512_set1_epi64
75 (offsetof(struct rte_mbuf, buf_iova));
76 const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
78 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
79 /* to shuffle the addresses to correct slots. Values 4-7 will contain
80 * zeros, so use 7 for a zero-value.
82 const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
84 const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
87 /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
88 * from mempool cache and populating both shadow and HW rings
90 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH / 8; i++) {
91 const __m512i mbuf_ptrs = _mm512_loadu_si512
92 (&cache->objs[cache->len - 8]);
93 _mm512_store_si512(rxep, mbuf_ptrs);
95 /* gather iova of mbuf0-7 into one zmm reg */
96 const __m512i iova_base_addrs = _mm512_i64gather_epi64
97 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
100 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
102 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
103 const __m512i iovas0 = _mm512_castsi256_si512
104 (_mm512_extracti64x4_epi64(iova_addrs, 0));
105 const __m512i iovas1 = _mm512_castsi256_si512
106 (_mm512_extracti64x4_epi64(iova_addrs, 1));
108 /* permute leaves desc 2-3 addresses in header address slots 0-1
109 * but these are ignored by driver since header split not
110 * enabled. Similarly for desc 4 & 5.
112 const __m512i desc_rd_0_1 = _mm512_permutexvar_epi64
113 (permute_idx, iovas0);
114 const __m512i desc_rd_2_3 = _mm512_bsrli_epi128(desc_rd_0_1, 8);
116 const __m512i desc_rd_4_5 = _mm512_permutexvar_epi64
117 (permute_idx, iovas1);
118 const __m512i desc_rd_6_7 = _mm512_bsrli_epi128(desc_rd_4_5, 8);
120 _mm512_store_si512((void *)rxdp, desc_rd_0_1);
121 _mm512_store_si512((void *)(rxdp + 2), desc_rd_2_3);
122 _mm512_store_si512((void *)(rxdp + 4), desc_rd_4_5);
123 _mm512_store_si512((void *)(rxdp + 6), desc_rd_6_7);
125 /* permute leaves desc 4-7 addresses in header address slots 0-3
126 * but these are ignored by driver since header split not
129 const __m512i desc_rd_0_3 = _mm512_permutexvar_epi64
130 (permute_idx, iova_addrs);
131 const __m512i desc_rd_4_7 = _mm512_bsrli_epi128(desc_rd_0_3, 8);
133 _mm512_store_si512((void *)rxdp, desc_rd_0_3);
134 _mm512_store_si512((void *)(rxdp + 4), desc_rd_4_7);
136 rxep += 8, rxdp += 8, cache->len -= 8;
139 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
140 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
141 rxq->rxrearm_start = 0;
143 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
145 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
146 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
148 /* Update the tail pointer on the NIC */
149 I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
152 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
153 /* Handles 32B descriptor FDIR ID processing:
154 * rxdp: receive descriptor ring, required to load 2nd 16B half of each desc
155 * rx_pkts: required to store metadata back to mbufs
156 * pkt_idx: offset into the burst, increments in vector widths
157 * desc_idx: required to select the correct shift at compile time
159 static inline __m256i
160 desc_fdir_processing_32b(volatile union i40e_rx_desc *rxdp,
161 struct rte_mbuf **rx_pkts,
162 const uint32_t pkt_idx,
163 const uint32_t desc_idx)
165 /* 32B desc path: load rxdp.wb.qword2 for EXT_STATUS and FLEXBH_STAT */
166 __m128i *rxdp_desc_0 = (void *)(&rxdp[desc_idx + 0].wb.qword2);
167 __m128i *rxdp_desc_1 = (void *)(&rxdp[desc_idx + 1].wb.qword2);
168 const __m128i desc_qw2_0 = _mm_load_si128(rxdp_desc_0);
169 const __m128i desc_qw2_1 = _mm_load_si128(rxdp_desc_1);
171 /* Mask for FLEXBH_STAT, and the FDIR_ID value to compare against. The
172 * remaining data is set to all 1's to pass through data.
174 const __m256i flexbh_mask = _mm256_set_epi32(-1, -1, -1, 3 << 4,
176 const __m256i flexbh_id = _mm256_set_epi32(-1, -1, -1, 1 << 4,
179 /* Load descriptor, check for FLEXBH bits, generate a mask for both
180 * packets in the register.
182 __m256i desc_qw2_0_1 =
183 _mm256_inserti128_si256(_mm256_castsi128_si256(desc_qw2_0),
185 __m256i desc_tmp_msk = _mm256_and_si256(flexbh_mask, desc_qw2_0_1);
186 __m256i fdir_mask = _mm256_cmpeq_epi32(flexbh_id, desc_tmp_msk);
187 __m256i fdir_data = _mm256_alignr_epi8(desc_qw2_0_1, desc_qw2_0_1, 12);
188 __m256i desc_fdir_data = _mm256_and_si256(fdir_mask, fdir_data);
190 /* Write data out to the mbuf. There is no store to this area of the
191 * mbuf today, so we cannot combine it with another store.
193 const uint32_t idx_0 = pkt_idx + desc_idx;
194 const uint32_t idx_1 = pkt_idx + desc_idx + 1;
196 rx_pkts[idx_0]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 0);
197 rx_pkts[idx_1]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 4);
199 /* Create mbuf flags as required for mbuf_flags layout
200 * (That's high lane [1,3,5,7, 0,2,4,6] as u32 lanes).
202 * - Mask away bits not required from the fdir_mask
203 * - Leave the PKT_FDIR_ID bit (1 << 13)
204 * - Position that bit correctly based on packet number
205 * - OR in the resulting bit to mbuf_flags
207 RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
208 __m256i mbuf_flag_mask = _mm256_set_epi32(0, 0, 0, 1 << 13,
210 __m256i desc_flag_bit = _mm256_and_si256(mbuf_flag_mask, fdir_mask);
212 /* For static-inline function, this will be stripped out
213 * as the desc_idx is a hard-coded constant.
217 return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 4);
219 return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 8);
221 return _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 12);
223 return desc_flag_bit;
228 /* NOT REACHED, see above switch returns */
229 return _mm256_setzero_si256();
231 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
233 #define PKTLEN_SHIFT 10
235 /* Force inline as some compilers will not inline by default. */
236 static __rte_always_inline uint16_t
237 _recv_raw_pkts_vec_avx512(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
238 uint16_t nb_pkts, uint8_t *split_packet)
240 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
241 const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
242 0, rxq->mbuf_initializer);
243 struct i40e_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
244 volatile union i40e_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
248 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP_AVX */
249 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP_AVX);
251 /* See if we need to rearm the RX queue - gives the prefetch a bit
254 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
257 /* Before we start moving massive data around, check to see if
258 * there is actually a packet available
260 if (!(rxdp->wb.qword1.status_error_len &
261 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
264 /* constants used in processing loop */
265 const __m512i crc_adjust =
267 (0, /* ignore non-length fields */
268 -rxq->crc_len, /* sub crc on data_len */
269 -rxq->crc_len, /* sub crc on pkt_len */
270 0 /* ignore non-length fields */
273 /* 8 packets DD mask, LSB in each 32-bit value */
274 const __m256i dd_check = _mm256_set1_epi32(1);
276 /* 8 packets EOP mask, second-LSB in each 32-bit value */
277 const __m256i eop_check = _mm256_slli_epi32(dd_check,
278 I40E_RX_DESC_STATUS_EOF_SHIFT);
280 /* mask to shuffle from desc. to mbuf (2 descriptors)*/
281 const __m512i shuf_msk =
283 (/* rss hash parsed separately */
284 /* octet 4~7, 32bits rss */
285 7 << 24 | 6 << 16 | 5 << 8 | 4,
286 /* octet 2~3, low 16 bits vlan_macip */
287 /* octet 14~15, 16 bits data_len */
288 3 << 24 | 2 << 16 | 15 << 8 | 14,
289 /* skip hi 16 bits pkt_len, zero out */
290 /* octet 14~15, 16 bits pkt_len */
291 0xFFFF << 16 | 15 << 8 | 14,
292 /* pkt_type set as unknown */
295 /* compile-time check the above crc and shuffle layout is correct.
296 * NOTE: the first field (lowest address) is given last in set_epi
299 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
300 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
301 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
302 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
303 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
304 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
305 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
306 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
308 /* Status/Error flag masks */
309 /* mask everything except RSS, flow director and VLAN flags
310 * bit2 is for VLAN tag, bit11 for flow director indication
311 * bit13:12 for RSS indication. Bits 3-5 of error
312 * field (bits 22-24) are for IP/L4 checksum errors
314 const __m256i flags_mask = _mm256_set1_epi32
315 ((1 << 2) | (1 << 11) | (3 << 12) | (7 << 22));
317 /* data to be shuffled by result of flag mask. If VLAN bit is set,
318 * (bit 2), then position 4 in this array will be used in the
321 const __m256i vlan_flags_shuf = _mm256_set_epi32
322 (0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
323 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
325 /* data to be shuffled by result of flag mask, shifted down 11.
326 * If RSS/FDIR bits are set, shuffle moves appropriate flags in
329 const __m256i rss_flags_shuf = _mm256_set_epi8
330 (0, 0, 0, 0, 0, 0, 0, 0,
331 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
332 0, 0, PKT_RX_FDIR, 0, /* end up 128-bits */
333 0, 0, 0, 0, 0, 0, 0, 0,
334 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
335 0, 0, PKT_RX_FDIR, 0);
337 /* data to be shuffled by the result of the flags mask shifted by 22
338 * bits. This gives use the l3_l4 flags.
340 const __m256i l3_l4_flags_shuf = _mm256_set_epi8
341 (0, 0, 0, 0, 0, 0, 0, 0,
342 /* shift right 1 bit to make sure it not exceed 255 */
343 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
344 PKT_RX_IP_CKSUM_BAD) >> 1,
345 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
346 PKT_RX_L4_CKSUM_BAD) >> 1,
347 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
348 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
349 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
350 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
351 PKT_RX_IP_CKSUM_BAD >> 1,
352 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
353 /* second 128-bits */
354 0, 0, 0, 0, 0, 0, 0, 0,
355 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
356 PKT_RX_IP_CKSUM_BAD) >> 1,
357 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
358 PKT_RX_L4_CKSUM_BAD) >> 1,
359 (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
360 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
361 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
362 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
363 PKT_RX_IP_CKSUM_BAD >> 1,
364 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
366 const __m256i cksum_mask = _mm256_set1_epi32
367 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
368 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
369 PKT_RX_OUTER_IP_CKSUM_BAD);
371 uint16_t i, received;
373 for (i = 0, received = 0; i < nb_pkts;
374 i += RTE_I40E_DESCS_PER_LOOP_AVX,
375 rxdp += RTE_I40E_DESCS_PER_LOOP_AVX) {
376 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
377 _mm256_storeu_si256((void *)&rx_pkts[i],
378 _mm256_loadu_si256((void *)&sw_ring[i]));
379 #ifdef RTE_ARCH_X86_64
380 _mm256_storeu_si256((void *)&rx_pkts[i + 4],
381 _mm256_loadu_si256((void *)&sw_ring[i + 4]));
384 __m512i raw_desc0_3, raw_desc4_7;
385 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
387 /* load in descriptors, in reverse order */
388 const __m128i raw_desc7 =
389 _mm_load_si128((void *)(rxdp + 7));
390 rte_compiler_barrier();
391 const __m128i raw_desc6 =
392 _mm_load_si128((void *)(rxdp + 6));
393 rte_compiler_barrier();
394 const __m128i raw_desc5 =
395 _mm_load_si128((void *)(rxdp + 5));
396 rte_compiler_barrier();
397 const __m128i raw_desc4 =
398 _mm_load_si128((void *)(rxdp + 4));
399 rte_compiler_barrier();
400 const __m128i raw_desc3 =
401 _mm_load_si128((void *)(rxdp + 3));
402 rte_compiler_barrier();
403 const __m128i raw_desc2 =
404 _mm_load_si128((void *)(rxdp + 2));
405 rte_compiler_barrier();
406 const __m128i raw_desc1 =
407 _mm_load_si128((void *)(rxdp + 1));
408 rte_compiler_barrier();
409 const __m128i raw_desc0 =
410 _mm_load_si128((void *)(rxdp + 0));
413 _mm256_inserti128_si256
414 (_mm256_castsi128_si256(raw_desc6),
417 _mm256_inserti128_si256
418 (_mm256_castsi128_si256(raw_desc4),
421 _mm256_inserti128_si256
422 (_mm256_castsi128_si256(raw_desc2),
425 _mm256_inserti128_si256
426 (_mm256_castsi128_si256(raw_desc0),
431 (_mm512_castsi256_si512(raw_desc4_5),
435 (_mm512_castsi256_si512(raw_desc0_1),
441 for (j = 0; j < RTE_I40E_DESCS_PER_LOOP_AVX; j++)
442 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
445 /* convert descriptors 0-7 into mbufs, adjusting length and
446 * re-arranging fields. Then write into the mbuf
448 const __m512i len4_7 = _mm512_slli_epi32
449 (raw_desc4_7, PKTLEN_SHIFT);
450 const __m512i len0_3 = _mm512_slli_epi32
451 (raw_desc0_3, PKTLEN_SHIFT);
452 const __m512i desc4_7 = _mm512_mask_blend_epi16
453 (0x80808080, raw_desc4_7, len4_7);
454 const __m512i desc0_3 = _mm512_mask_blend_epi16
455 (0x80808080, raw_desc0_3, len0_3);
456 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
457 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
459 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
460 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
462 /* to get packet types, shift 64-bit values down 30 bits
463 * and so ptype is in lower 8-bits in each
465 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
466 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
467 const __m256i ptypes6_7 =
468 _mm512_extracti64x4_epi64(ptypes4_7, 1);
469 const __m256i ptypes4_5 =
470 _mm512_extracti64x4_epi64(ptypes4_7, 0);
471 const __m256i ptypes2_3 =
472 _mm512_extracti64x4_epi64(ptypes0_3, 1);
473 const __m256i ptypes0_1 =
474 _mm512_extracti64x4_epi64(ptypes0_3, 0);
475 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
476 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
477 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
478 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
479 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
480 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
481 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
482 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
484 const __m512i ptype4_7 = _mm512_set_epi32
485 (0, 0, 0, ptype_tbl[ptype7],
486 0, 0, 0, ptype_tbl[ptype6],
487 0, 0, 0, ptype_tbl[ptype5],
488 0, 0, 0, ptype_tbl[ptype4]);
489 const __m512i ptype0_3 = _mm512_set_epi32
490 (0, 0, 0, ptype_tbl[ptype3],
491 0, 0, 0, ptype_tbl[ptype2],
492 0, 0, 0, ptype_tbl[ptype1],
493 0, 0, 0, ptype_tbl[ptype0]);
495 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
496 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
498 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
499 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
500 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
501 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
504 * use permute/extract to get status content
505 * After the operations, the packets status flags are in the
506 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
508 /* merge the status bits into one register */
509 const __m512i status_permute_msk = _mm512_set_epi32
514 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
515 (desc4_7, status_permute_msk, desc0_3);
516 __m256i status0_7 = _mm512_extracti64x4_epi64
519 /* now do flag manipulation */
521 /* get only flag/error bits we want */
522 const __m256i flag_bits =
523 _mm256_and_si256(status0_7, flags_mask);
524 /* set vlan and rss flags */
525 const __m256i vlan_flags =
526 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
527 const __m256i rss_fdir_bits = _mm256_srli_epi32(flag_bits, 11);
528 const __m256i rss_flags = _mm256_shuffle_epi8(rss_flags_shuf,
531 /* l3_l4_error flags, shuffle, then shift to correct adjustment
532 * of flags in flags_shuf, and finally mask out extra bits
534 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
535 _mm256_srli_epi32(flag_bits, 22));
536 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
537 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
540 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
541 _mm256_or_si256(rss_flags, vlan_flags));
543 /* If the rxq has FDIR enabled, read and process the FDIR info
544 * from the descriptor. This can cause more loads/stores, so is
545 * not always performed. Branch over the code when not enabled.
547 if (rxq->fdir_enabled) {
548 #ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
549 /* 16B descriptor code path:
550 * RSS and FDIR ID use the same offset in the desc, so
551 * only one can be present at a time. The code below
552 * identifies an FDIR ID match, and zeros the RSS value
553 * in the mbuf on FDIR match to keep mbuf data clean.
555 #define FDIR_BLEND_MASK ((1 << 3) | (1 << 7))
558 * - Take flags, shift bits to null out
559 * - CMPEQ with known FDIR ID, to get 0xFFFF or 0 mask
560 * - Strip bits from mask, leaving 0 or 1 for FDIR ID
561 * - Merge with mbuf_flags
563 /* FLM = 1, FLTSTAT = 0b01, (FLM | FLTSTAT) == 3.
564 * Shift left by 28 to avoid having to mask.
567 _mm256_slli_epi32(rss_fdir_bits, 28);
568 const __m256i fdir_id = _mm256_set1_epi32(3 << 28);
570 /* As above, the fdir_mask to packet mapping is this:
571 * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
572 * Then OR FDIR flags to mbuf_flags on FDIR ID hit.
574 RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
575 const __m256i pkt_fdir_bit = _mm256_set1_epi32(1 << 13);
576 const __m256i fdir_mask =
577 _mm256_cmpeq_epi32(fdir, fdir_id);
579 _mm256_and_si256(fdir_mask, pkt_fdir_bit);
581 mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_bits);
583 /* Based on FDIR_MASK, clear the RSS or FDIR value.
584 * The FDIR ID value is masked to zero if not a hit,
585 * otherwise the mb0_1 register RSS field is zeroed.
587 const __m256i fdir_zero_mask = _mm256_setzero_si256();
588 __m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask,
589 fdir_mask, FDIR_BLEND_MASK);
590 __m256i fdir_mb0_1 = _mm256_and_si256(mb0_1, fdir_mask);
592 mb0_1 = _mm256_andnot_si256(tmp0_1, mb0_1);
594 /* Write to mbuf: no stores to combine with, so just a
595 * scalar store to push data here.
597 rx_pkts[i + 0]->hash.fdir.hi =
598 _mm256_extract_epi32(fdir_mb0_1, 3);
599 rx_pkts[i + 1]->hash.fdir.hi =
600 _mm256_extract_epi32(fdir_mb0_1, 7);
602 /* Same as above, only shift the fdir_mask to align
603 * the packet FDIR mask with the FDIR_ID desc lane.
606 _mm256_alignr_epi8(fdir_mask, fdir_mask, 12);
607 __m256i fdir_mb2_3 = _mm256_and_si256(mb2_3, tmp2_3);
609 tmp2_3 = _mm256_blend_epi32(fdir_zero_mask, tmp2_3,
611 mb2_3 = _mm256_andnot_si256(tmp2_3, mb2_3);
612 rx_pkts[i + 2]->hash.fdir.hi =
613 _mm256_extract_epi32(fdir_mb2_3, 3);
614 rx_pkts[i + 3]->hash.fdir.hi =
615 _mm256_extract_epi32(fdir_mb2_3, 7);
618 _mm256_alignr_epi8(fdir_mask, fdir_mask, 8);
619 __m256i fdir_mb4_5 = _mm256_and_si256(mb4_5, tmp4_5);
621 tmp4_5 = _mm256_blend_epi32(fdir_zero_mask, tmp4_5,
623 mb4_5 = _mm256_andnot_si256(tmp4_5, mb4_5);
624 rx_pkts[i + 4]->hash.fdir.hi =
625 _mm256_extract_epi32(fdir_mb4_5, 3);
626 rx_pkts[i + 5]->hash.fdir.hi =
627 _mm256_extract_epi32(fdir_mb4_5, 7);
630 _mm256_alignr_epi8(fdir_mask, fdir_mask, 4);
631 __m256i fdir_mb6_7 = _mm256_and_si256(mb6_7, tmp6_7);
633 tmp6_7 = _mm256_blend_epi32(fdir_zero_mask, tmp6_7,
635 mb6_7 = _mm256_andnot_si256(tmp6_7, mb6_7);
636 rx_pkts[i + 6]->hash.fdir.hi =
637 _mm256_extract_epi32(fdir_mb6_7, 3);
638 rx_pkts[i + 7]->hash.fdir.hi =
639 _mm256_extract_epi32(fdir_mb6_7, 7);
641 /* End of 16B descriptor handling */
643 /* 32B descriptor FDIR ID mark handling. Returns bits
644 * to be OR-ed into the mbuf olflags.
646 __m256i fdir_add_flags;
649 desc_fdir_processing_32b(rxdp, rx_pkts, i, 0);
651 _mm256_or_si256(mbuf_flags, fdir_add_flags);
654 desc_fdir_processing_32b(rxdp, rx_pkts, i, 2);
656 _mm256_or_si256(mbuf_flags, fdir_add_flags);
659 desc_fdir_processing_32b(rxdp, rx_pkts, i, 4);
661 _mm256_or_si256(mbuf_flags, fdir_add_flags);
664 desc_fdir_processing_32b(rxdp, rx_pkts, i, 6);
666 _mm256_or_si256(mbuf_flags, fdir_add_flags);
667 /* End 32B desc handling */
668 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
670 } /* if() on FDIR enabled */
672 /* At this point, we have the 8 sets of flags in the low 16-bits
673 * of each 32-bit value in vlan0.
674 * We want to extract these, and merge them with the mbuf init data
675 * so we can do a single write to the mbuf to set the flags
676 * and all the other initialization fields. Extracting the
677 * appropriate flags means that we have to do a shift and blend for
678 * each mbuf before we do the write. However, we can also
679 * add in the previously computed rx_descriptor fields to
680 * make a single 256-bit write per mbuf
682 /* check the structure matches expectations */
683 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
684 offsetof(struct rte_mbuf, rearm_data) + 8);
685 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
686 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
687 /* build up data and do writes */
688 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
690 rearm6 = _mm256_blend_epi32
691 (mbuf_init, _mm256_slli_si256(mbuf_flags, 8), 0x04);
692 rearm4 = _mm256_blend_epi32
693 (mbuf_init, _mm256_slli_si256(mbuf_flags, 4), 0x04);
694 rearm2 = _mm256_blend_epi32
695 (mbuf_init, mbuf_flags, 0x04);
696 rearm0 = _mm256_blend_epi32
697 (mbuf_init, _mm256_srli_si256(mbuf_flags, 4), 0x04);
698 /* permute to add in the rx_descriptor e.g. rss fields */
699 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
700 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
701 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
702 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
705 ((__m256i *)&rx_pkts[i + 6]->rearm_data, rearm6);
707 ((__m256i *)&rx_pkts[i + 4]->rearm_data, rearm4);
709 ((__m256i *)&rx_pkts[i + 2]->rearm_data, rearm2);
711 ((__m256i *)&rx_pkts[i + 0]->rearm_data, rearm0);
713 /* repeat for the odd mbufs */
714 const __m256i odd_flags = _mm256_castsi128_si256
715 (_mm256_extracti128_si256(mbuf_flags, 1));
716 rearm7 = _mm256_blend_epi32
717 (mbuf_init, _mm256_slli_si256(odd_flags, 8), 0x04);
718 rearm5 = _mm256_blend_epi32
719 (mbuf_init, _mm256_slli_si256(odd_flags, 4), 0x04);
720 rearm3 = _mm256_blend_epi32
721 (mbuf_init, odd_flags, 0x04);
722 rearm1 = _mm256_blend_epi32
723 (mbuf_init, _mm256_srli_si256(odd_flags, 4), 0x04);
724 /* since odd mbufs are already in hi 128-bits use blend */
725 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
726 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
727 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
728 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
729 /* again write to mbufs */
731 ((__m256i *)&rx_pkts[i + 7]->rearm_data, rearm7);
733 ((__m256i *)&rx_pkts[i + 5]->rearm_data, rearm5);
735 ((__m256i *)&rx_pkts[i + 3]->rearm_data, rearm3);
737 ((__m256i *)&rx_pkts[i + 1]->rearm_data, rearm1);
739 /* extract and record EOP bit */
741 const __m128i eop_mask =
743 (1 << I40E_RX_DESC_STATUS_EOF_SHIFT);
744 const __m256i eop_bits256 =
745 _mm256_and_si256(status0_7, eop_check);
746 /* pack status bits into a single 128-bit register */
747 const __m128i eop_bits =
749 (_mm256_castsi256_si128(eop_bits256),
750 _mm256_extractf128_si256(eop_bits256, 1));
751 /* flip bits, and mask out the EOP bit, which is now
752 * a split-packet bit i.e. !EOP, rather than EOP one.
754 __m128i split_bits = _mm_andnot_si128(eop_bits,
756 /* eop bits are out of order, so we need to shuffle them
757 * back into order again. In doing so, only use low 8
758 * bits, which acts like another pack instruction
759 * The original order is (hi->lo): 1,3,5,7,0,2,4,6
760 * [Since we use epi8, the 16-bit positions are
761 * multiplied by 2 in the eop_shuffle value.]
763 __m128i eop_shuffle = _mm_set_epi8
764 (0xFF, 0xFF, 0xFF, 0xFF, /* zero hi 64b */
765 0xFF, 0xFF, 0xFF, 0xFF,
766 8, 0, 10, 2, /* move values to lo 64b */
768 split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
769 *(uint64_t *)split_packet =
770 _mm_cvtsi128_si64(split_bits);
771 split_packet += RTE_I40E_DESCS_PER_LOOP_AVX;
774 /* perform dd_check */
775 status0_7 = _mm256_and_si256(status0_7, dd_check);
776 status0_7 = _mm256_packs_epi32
777 (status0_7, _mm256_setzero_si256());
779 uint64_t burst = __builtin_popcountll
781 (_mm256_extracti128_si256
783 burst += __builtin_popcountll(_mm_cvtsi128_si64
784 (_mm256_castsi256_si128(status0_7)));
786 if (burst != RTE_I40E_DESCS_PER_LOOP_AVX)
790 /* update tail pointers */
791 rxq->rx_tail += received;
792 rxq->rx_tail &= (rxq->nb_rx_desc - 1);
793 if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
797 rxq->rxrearm_nb += received;
803 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
806 i40e_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
809 return _recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);
813 * vPMD receive routine that reassembles single burst of 32 scattered packets
815 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
818 i40e_recv_scattered_burst_vec_avx512(void *rx_queue,
819 struct rte_mbuf **rx_pkts,
822 struct i40e_rx_queue *rxq = rx_queue;
823 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
825 /* get some new buffers */
826 uint16_t nb_bufs = _recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
831 /* happy day case, full burst + no packets to be joined */
832 const uint64_t *split_fl64 = (uint64_t *)split_flags;
834 if (!rxq->pkt_first_seg &&
835 split_fl64[0] == 0 && split_fl64[1] == 0 &&
836 split_fl64[2] == 0 && split_fl64[3] == 0)
839 /* reassemble any packets that need reassembly*/
842 if (!rxq->pkt_first_seg) {
843 /* find the first split flag, and only reassemble then*/
844 while (i < nb_bufs && !split_flags[i])
848 rxq->pkt_first_seg = rx_pkts[i];
850 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
855 * vPMD receive routine that reassembles scattered packets.
856 * Main receive routine that can handle arbitrary burst sizes
858 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
861 i40e_recv_scattered_pkts_vec_avx512(void *rx_queue,
862 struct rte_mbuf **rx_pkts,
867 while (nb_pkts > RTE_I40E_VPMD_RX_BURST) {
868 uint16_t burst = i40e_recv_scattered_burst_vec_avx512(rx_queue,
869 rx_pkts + retval, RTE_I40E_VPMD_RX_BURST);
872 if (burst < RTE_I40E_VPMD_RX_BURST)
875 return retval + i40e_recv_scattered_burst_vec_avx512(rx_queue,
876 rx_pkts + retval, nb_pkts);
879 static __rte_always_inline int
880 i40e_tx_free_bufs_avx512(struct i40e_tx_queue *txq)
882 struct i40e_vec_tx_entry *txep;
886 struct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
888 /* check DD bits on threshold descriptor */
889 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
890 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
891 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
894 n = txq->tx_rs_thresh;
896 /* first buffer to free from S/W ring is at index
897 * tx_next_dd - (tx_rs_thresh-1)
899 txep = (void *)txq->sw_ring;
900 txep += txq->tx_next_dd - (n - 1);
902 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
903 struct rte_mempool *mp = txep[0].mbuf->pool;
905 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
908 if (!cache || cache->len == 0)
911 cache_objs = &cache->objs[cache->len];
913 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
914 rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
918 /* The cache follows the following algorithm
919 * 1. Add the objects to the cache
920 * 2. Anything greater than the cache min value (if it
921 * crosses the cache flush threshold) is flushed to the ring.
923 /* Add elements back into the cache */
925 /* n is multiple of 32 */
927 const __m512i a = _mm512_load_si512(&txep[copied]);
928 const __m512i b = _mm512_load_si512(&txep[copied + 8]);
929 const __m512i c = _mm512_load_si512(&txep[copied + 16]);
930 const __m512i d = _mm512_load_si512(&txep[copied + 24]);
932 _mm512_storeu_si512(&cache_objs[copied], a);
933 _mm512_storeu_si512(&cache_objs[copied + 8], b);
934 _mm512_storeu_si512(&cache_objs[copied + 16], c);
935 _mm512_storeu_si512(&cache_objs[copied + 24], d);
940 if (cache->len >= cache->flushthresh) {
941 rte_mempool_ops_enqueue_bulk
942 (mp, &cache->objs[cache->size],
943 cache->len - cache->size);
944 cache->len = cache->size;
950 m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
954 for (i = 1; i < n; i++) {
955 rte_prefetch0(&txep[i + 3].mbuf->cacheline1);
956 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
958 if (likely(m->pool == free[0]->pool)) {
961 rte_mempool_put_bulk(free[0]->pool,
969 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
971 for (i = 1; i < n; i++) {
972 m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
974 rte_mempool_put(m->pool, m);
979 /* buffers were freed, update counters */
980 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
981 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
982 if (txq->tx_next_dd >= txq->nb_tx_desc)
983 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
985 return txq->tx_rs_thresh;
989 vtx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
991 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
992 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
993 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
995 __m128i descriptor = _mm_set_epi64x(high_qw,
996 pkt->buf_iova + pkt->data_off);
997 _mm_store_si128((__m128i *)txdp, descriptor);
1001 vtx(volatile struct i40e_tx_desc *txdp,
1002 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
1004 const uint64_t hi_qw_tmpl = (I40E_TX_DESC_DTYPE_DATA |
1005 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT));
1007 for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1010 ((uint64_t)pkt[3]->data_len <<
1011 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
1014 ((uint64_t)pkt[2]->data_len <<
1015 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
1018 ((uint64_t)pkt[1]->data_len <<
1019 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
1022 ((uint64_t)pkt[0]->data_len <<
1023 I40E_TXD_QW1_TX_BUF_SZ_SHIFT);
1027 (hi_qw3, pkt[3]->buf_iova + pkt[3]->data_off,
1028 hi_qw2, pkt[2]->buf_iova + pkt[2]->data_off,
1029 hi_qw1, pkt[1]->buf_iova + pkt[1]->data_off,
1030 hi_qw0, pkt[0]->buf_iova + pkt[0]->data_off);
1031 _mm512_storeu_si512((void *)txdp, desc0_3);
1034 /* do any last ones */
1036 vtx1(txdp, *pkt, flags);
1037 txdp++, pkt++, nb_pkts--;
1041 static __rte_always_inline void
1042 tx_backlog_entry_avx512(struct i40e_vec_tx_entry *txep,
1043 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1047 for (i = 0; i < (int)nb_pkts; ++i)
1048 txep[i].mbuf = tx_pkts[i];
1051 static inline uint16_t
1052 i40e_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1055 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1056 volatile struct i40e_tx_desc *txdp;
1057 struct i40e_vec_tx_entry *txep;
1058 uint16_t n, nb_commit, tx_id;
1059 uint64_t flags = I40E_TD_CMD;
1060 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
1062 /* cross rx_thresh boundary is not allowed */
1063 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1065 if (txq->nb_tx_free < txq->tx_free_thresh)
1066 i40e_tx_free_bufs_avx512(txq);
1068 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1069 if (unlikely(nb_pkts == 0))
1072 tx_id = txq->tx_tail;
1073 txdp = &txq->tx_ring[tx_id];
1074 txep = (void *)txq->sw_ring;
1077 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1079 n = (uint16_t)(txq->nb_tx_desc - tx_id);
1080 if (nb_commit >= n) {
1081 tx_backlog_entry_avx512(txep, tx_pkts, n);
1083 vtx(txdp, tx_pkts, n - 1, flags);
1087 vtx1(txdp, *tx_pkts++, rs);
1089 nb_commit = (uint16_t)(nb_commit - n);
1092 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1094 /* avoid reach the end of ring */
1095 txdp = txq->tx_ring;
1096 txep = (void *)txq->sw_ring;
1099 tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1101 vtx(txdp, tx_pkts, nb_commit, flags);
1103 tx_id = (uint16_t)(tx_id + nb_commit);
1104 if (tx_id > txq->tx_next_rs) {
1105 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
1106 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1107 I40E_TXD_QW1_CMD_SHIFT);
1109 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1112 txq->tx_tail = tx_id;
1114 I40E_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1120 i40e_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1124 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1129 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1130 ret = i40e_xmit_fixed_burst_vec_avx512
1131 (tx_queue, &tx_pkts[nb_tx], num);