drivers/net/iavf/base/iavf_adminq_cmd.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013 - 2015 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_ADMINQ_CMD_H_
   6 #define _IAVF_ADMINQ_CMD_H_
   7
   8 /* This header file defines the iavf Admin Queue commands and is shared between
   9  * iavf Firmware and Software.
  10  *
  11  * This file needs to comply with the Linux Kernel coding style.
  12  */
  13
  14
  15 #define IAVF_FW_API_VERSION_MAJOR       0x0001
  16 #define IAVF_FW_API_VERSION_MINOR_X722  0x0005
  17 #define IAVF_FW_API_VERSION_MINOR_X710  0x0007
  18
  19 #define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \
  20                                         IAVF_FW_API_VERSION_MINOR_X710 : \
  21                                         IAVF_FW_API_VERSION_MINOR_X722)
  22
  23 /* API version 1.7 implements additional link and PHY-specific APIs  */
  24 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
  25
  26 struct iavf_aq_desc {
  27         __le16 flags;
  28         __le16 opcode;
  29         __le16 datalen;
  30         __le16 retval;
  31         __le32 cookie_high;
  32         __le32 cookie_low;
  33         union {
  34                 struct {
  35                         __le32 param0;
  36                         __le32 param1;
  37                         __le32 param2;
  38                         __le32 param3;
  39                 } internal;
  40                 struct {
  41                         __le32 param0;
  42                         __le32 param1;
  43                         __le32 addr_high;
  44                         __le32 addr_low;
  45                 } external;
  46                 u8 raw[16];
  47         } params;
  48 };
  49
  50 /* Flags sub-structure
  51  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  52  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  53  */
  54
  55 /* command flags and offsets*/
  56 #define IAVF_AQ_FLAG_DD_SHIFT   0
  57 #define IAVF_AQ_FLAG_CMP_SHIFT  1
  58 #define IAVF_AQ_FLAG_ERR_SHIFT  2
  59 #define IAVF_AQ_FLAG_VFE_SHIFT  3
  60 #define IAVF_AQ_FLAG_LB_SHIFT   9
  61 #define IAVF_AQ_FLAG_RD_SHIFT   10
  62 #define IAVF_AQ_FLAG_VFC_SHIFT  11
  63 #define IAVF_AQ_FLAG_BUF_SHIFT  12
  64 #define IAVF_AQ_FLAG_SI_SHIFT   13
  65 #define IAVF_AQ_FLAG_EI_SHIFT   14
  66 #define IAVF_AQ_FLAG_FE_SHIFT   15
  67
  68 #define IAVF_AQ_FLAG_DD         (1 << IAVF_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  69 #define IAVF_AQ_FLAG_CMP        (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  70 #define IAVF_AQ_FLAG_ERR        (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4    */
  71 #define IAVF_AQ_FLAG_VFE        (1 << IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8    */
  72 #define IAVF_AQ_FLAG_LB         (1 << IAVF_AQ_FLAG_LB_SHIFT)  /* 0x200  */
  73 #define IAVF_AQ_FLAG_RD         (1 << IAVF_AQ_FLAG_RD_SHIFT)  /* 0x400  */
  74 #define IAVF_AQ_FLAG_VFC        (1 << IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800  */
  75 #define IAVF_AQ_FLAG_BUF        (1 << IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  76 #define IAVF_AQ_FLAG_SI         (1 << IAVF_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
  77 #define IAVF_AQ_FLAG_EI         (1 << IAVF_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
  78 #define IAVF_AQ_FLAG_FE         (1 << IAVF_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
  79
  80 /* error codes */
  81 enum iavf_admin_queue_err {
  82         IAVF_AQ_RC_OK           = 0,  /* success */
  83         IAVF_AQ_RC_EPERM        = 1,  /* Operation not permitted */
  84         IAVF_AQ_RC_ENOENT       = 2,  /* No such element */
  85         IAVF_AQ_RC_ESRCH        = 3,  /* Bad opcode */
  86         IAVF_AQ_RC_EINTR        = 4,  /* operation interrupted */
  87         IAVF_AQ_RC_EIO          = 5,  /* I/O error */
  88         IAVF_AQ_RC_ENXIO        = 6,  /* No such resource */
  89         IAVF_AQ_RC_E2BIG        = 7,  /* Arg too long */
  90         IAVF_AQ_RC_EAGAIN       = 8,  /* Try again */
  91         IAVF_AQ_RC_ENOMEM       = 9,  /* Out of memory */
  92         IAVF_AQ_RC_EACCES       = 10, /* Permission denied */
  93         IAVF_AQ_RC_EFAULT       = 11, /* Bad address */
  94         IAVF_AQ_RC_EBUSY        = 12, /* Device or resource busy */
  95         IAVF_AQ_RC_EEXIST       = 13, /* object already exists */
  96         IAVF_AQ_RC_EINVAL       = 14, /* Invalid argument */
  97         IAVF_AQ_RC_ENOTTY       = 15, /* Not a typewriter */
  98         IAVF_AQ_RC_ENOSPC       = 16, /* No space left or alloc failure */
  99         IAVF_AQ_RC_ENOSYS       = 17, /* Function not implemented */
 100         IAVF_AQ_RC_ERANGE       = 18, /* Parameter out of range */
 101         IAVF_AQ_RC_EFLUSHED     = 19, /* Cmd flushed due to prev cmd error */
 102         IAVF_AQ_RC_BAD_ADDR     = 20, /* Descriptor contains a bad pointer */
 103         IAVF_AQ_RC_EMODE        = 21, /* Op not allowed in current dev mode */
 104         IAVF_AQ_RC_EFBIG        = 22, /* File too large */
 105 };
 106
 107 /* Admin Queue command opcodes */
 108 enum iavf_admin_queue_opc {
 109         /* aq commands */
 110         iavf_aqc_opc_get_version        = 0x0001,
 111         iavf_aqc_opc_driver_version     = 0x0002,
 112         iavf_aqc_opc_queue_shutdown     = 0x0003,
 113         iavf_aqc_opc_set_pf_context     = 0x0004,
 114
 115         /* resource ownership */
 116         iavf_aqc_opc_request_resource   = 0x0008,
 117         iavf_aqc_opc_release_resource   = 0x0009,
 118
 119         iavf_aqc_opc_list_func_capabilities     = 0x000A,
 120         iavf_aqc_opc_list_dev_capabilities      = 0x000B,
 121
 122         /* Proxy commands */
 123         iavf_aqc_opc_set_proxy_config           = 0x0104,
 124         iavf_aqc_opc_set_ns_proxy_table_entry   = 0x0105,
 125
 126         /* LAA */
 127         iavf_aqc_opc_mac_address_read   = 0x0107,
 128         iavf_aqc_opc_mac_address_write  = 0x0108,
 129
 130         /* PXE */
 131         iavf_aqc_opc_clear_pxe_mode     = 0x0110,
 132
 133         /* WoL commands */
 134         iavf_aqc_opc_set_wol_filter     = 0x0120,
 135         iavf_aqc_opc_get_wake_reason    = 0x0121,
 136         iavf_aqc_opc_clear_all_wol_filters = 0x025E,
 137
 138         /* internal switch commands */
 139         iavf_aqc_opc_get_switch_config          = 0x0200,
 140         iavf_aqc_opc_add_statistics             = 0x0201,
 141         iavf_aqc_opc_remove_statistics          = 0x0202,
 142         iavf_aqc_opc_set_port_parameters        = 0x0203,
 143         iavf_aqc_opc_get_switch_resource_alloc  = 0x0204,
 144         iavf_aqc_opc_set_switch_config          = 0x0205,
 145         iavf_aqc_opc_rx_ctl_reg_read            = 0x0206,
 146         iavf_aqc_opc_rx_ctl_reg_write           = 0x0207,
 147
 148         iavf_aqc_opc_add_vsi                    = 0x0210,
 149         iavf_aqc_opc_update_vsi_parameters      = 0x0211,
 150         iavf_aqc_opc_get_vsi_parameters         = 0x0212,
 151
 152         iavf_aqc_opc_add_pv                     = 0x0220,
 153         iavf_aqc_opc_update_pv_parameters       = 0x0221,
 154         iavf_aqc_opc_get_pv_parameters          = 0x0222,
 155
 156         iavf_aqc_opc_add_veb                    = 0x0230,
 157         iavf_aqc_opc_update_veb_parameters      = 0x0231,
 158         iavf_aqc_opc_get_veb_parameters         = 0x0232,
 159
 160         iavf_aqc_opc_delete_element             = 0x0243,
 161
 162         iavf_aqc_opc_add_macvlan                = 0x0250,
 163         iavf_aqc_opc_remove_macvlan             = 0x0251,
 164         iavf_aqc_opc_add_vlan                   = 0x0252,
 165         iavf_aqc_opc_remove_vlan                = 0x0253,
 166         iavf_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
 167         iavf_aqc_opc_add_tag                    = 0x0255,
 168         iavf_aqc_opc_remove_tag                 = 0x0256,
 169         iavf_aqc_opc_add_multicast_etag         = 0x0257,
 170         iavf_aqc_opc_remove_multicast_etag      = 0x0258,
 171         iavf_aqc_opc_update_tag                 = 0x0259,
 172         iavf_aqc_opc_add_control_packet_filter  = 0x025A,
 173         iavf_aqc_opc_remove_control_packet_filter       = 0x025B,
 174         iavf_aqc_opc_add_cloud_filters          = 0x025C,
 175         iavf_aqc_opc_remove_cloud_filters       = 0x025D,
 176         iavf_aqc_opc_clear_wol_switch_filters   = 0x025E,
 177         iavf_aqc_opc_replace_cloud_filters      = 0x025F,
 178
 179         iavf_aqc_opc_add_mirror_rule    = 0x0260,
 180         iavf_aqc_opc_delete_mirror_rule = 0x0261,
 181
 182         /* Dynamic Device Personalization */
 183         iavf_aqc_opc_write_personalization_profile      = 0x0270,
 184         iavf_aqc_opc_get_personalization_profile_list   = 0x0271,
 185
 186         /* DCB commands */
 187         iavf_aqc_opc_dcb_ignore_pfc     = 0x0301,
 188         iavf_aqc_opc_dcb_updated        = 0x0302,
 189         iavf_aqc_opc_set_dcb_parameters = 0x0303,
 190
 191         /* TX scheduler */
 192         iavf_aqc_opc_configure_vsi_bw_limit             = 0x0400,
 193         iavf_aqc_opc_configure_vsi_ets_sla_bw_limit     = 0x0406,
 194         iavf_aqc_opc_configure_vsi_tc_bw                = 0x0407,
 195         iavf_aqc_opc_query_vsi_bw_config                = 0x0408,
 196         iavf_aqc_opc_query_vsi_ets_sla_config           = 0x040A,
 197         iavf_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
 198
 199         iavf_aqc_opc_enable_switching_comp_ets                  = 0x0413,
 200         iavf_aqc_opc_modify_switching_comp_ets                  = 0x0414,
 201         iavf_aqc_opc_disable_switching_comp_ets                 = 0x0415,
 202         iavf_aqc_opc_configure_switching_comp_ets_bw_limit      = 0x0416,
 203         iavf_aqc_opc_configure_switching_comp_bw_config         = 0x0417,
 204         iavf_aqc_opc_query_switching_comp_ets_config            = 0x0418,
 205         iavf_aqc_opc_query_port_ets_config                      = 0x0419,
 206         iavf_aqc_opc_query_switching_comp_bw_config             = 0x041A,
 207         iavf_aqc_opc_suspend_port_tx                            = 0x041B,
 208         iavf_aqc_opc_resume_port_tx                             = 0x041C,
 209         iavf_aqc_opc_configure_partition_bw                     = 0x041D,
 210         /* hmc */
 211         iavf_aqc_opc_query_hmc_resource_profile = 0x0500,
 212         iavf_aqc_opc_set_hmc_resource_profile   = 0x0501,
 213
 214         /* phy commands*/
 215
 216         /* phy commands*/
 217         iavf_aqc_opc_get_phy_abilities          = 0x0600,
 218         iavf_aqc_opc_set_phy_config             = 0x0601,
 219         iavf_aqc_opc_set_mac_config             = 0x0603,
 220         iavf_aqc_opc_set_link_restart_an        = 0x0605,
 221         iavf_aqc_opc_get_link_status            = 0x0607,
 222         iavf_aqc_opc_set_phy_int_mask           = 0x0613,
 223         iavf_aqc_opc_get_local_advt_reg         = 0x0614,
 224         iavf_aqc_opc_set_local_advt_reg         = 0x0615,
 225         iavf_aqc_opc_get_partner_advt           = 0x0616,
 226         iavf_aqc_opc_set_lb_modes               = 0x0618,
 227         iavf_aqc_opc_get_phy_wol_caps           = 0x0621,
 228         iavf_aqc_opc_set_phy_debug              = 0x0622,
 229         iavf_aqc_opc_upload_ext_phy_fm          = 0x0625,
 230         iavf_aqc_opc_run_phy_activity           = 0x0626,
 231         iavf_aqc_opc_set_phy_register           = 0x0628,
 232         iavf_aqc_opc_get_phy_register           = 0x0629,
 233
 234         /* NVM commands */
 235         iavf_aqc_opc_nvm_read                   = 0x0701,
 236         iavf_aqc_opc_nvm_erase                  = 0x0702,
 237         iavf_aqc_opc_nvm_update                 = 0x0703,
 238         iavf_aqc_opc_nvm_config_read            = 0x0704,
 239         iavf_aqc_opc_nvm_config_write           = 0x0705,
 240         iavf_aqc_opc_nvm_progress               = 0x0706,
 241         iavf_aqc_opc_oem_post_update            = 0x0720,
 242         iavf_aqc_opc_thermal_sensor             = 0x0721,
 243
 244         /* virtualization commands */
 245         iavf_aqc_opc_send_msg_to_pf             = 0x0801,
 246         iavf_aqc_opc_send_msg_to_vf             = 0x0802,
 247         iavf_aqc_opc_send_msg_to_peer           = 0x0803,
 248
 249         /* alternate structure */
 250         iavf_aqc_opc_alternate_write            = 0x0900,
 251         iavf_aqc_opc_alternate_write_indirect   = 0x0901,
 252         iavf_aqc_opc_alternate_read             = 0x0902,
 253         iavf_aqc_opc_alternate_read_indirect    = 0x0903,
 254         iavf_aqc_opc_alternate_write_done       = 0x0904,
 255         iavf_aqc_opc_alternate_set_mode         = 0x0905,
 256         iavf_aqc_opc_alternate_clear_port       = 0x0906,
 257
 258         /* LLDP commands */
 259         iavf_aqc_opc_lldp_get_mib       = 0x0A00,
 260         iavf_aqc_opc_lldp_update_mib    = 0x0A01,
 261         iavf_aqc_opc_lldp_add_tlv       = 0x0A02,
 262         iavf_aqc_opc_lldp_update_tlv    = 0x0A03,
 263         iavf_aqc_opc_lldp_delete_tlv    = 0x0A04,
 264         iavf_aqc_opc_lldp_stop          = 0x0A05,
 265         iavf_aqc_opc_lldp_start         = 0x0A06,
 266         iavf_aqc_opc_get_cee_dcb_cfg    = 0x0A07,
 267         iavf_aqc_opc_lldp_set_local_mib = 0x0A08,
 268         iavf_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
 269
 270         /* Tunnel commands */
 271         iavf_aqc_opc_add_udp_tunnel     = 0x0B00,
 272         iavf_aqc_opc_del_udp_tunnel     = 0x0B01,
 273         iavf_aqc_opc_set_rss_key        = 0x0B02,
 274         iavf_aqc_opc_set_rss_lut        = 0x0B03,
 275         iavf_aqc_opc_get_rss_key        = 0x0B04,
 276         iavf_aqc_opc_get_rss_lut        = 0x0B05,
 277
 278         /* Async Events */
 279         iavf_aqc_opc_event_lan_overflow         = 0x1001,
 280
 281         /* OEM commands */
 282         iavf_aqc_opc_oem_parameter_change       = 0xFE00,
 283         iavf_aqc_opc_oem_device_status_change   = 0xFE01,
 284         iavf_aqc_opc_oem_ocsd_initialize        = 0xFE02,
 285         iavf_aqc_opc_oem_ocbb_initialize        = 0xFE03,
 286
 287         /* debug commands */
 288         iavf_aqc_opc_debug_read_reg             = 0xFF03,
 289         iavf_aqc_opc_debug_write_reg            = 0xFF04,
 290         iavf_aqc_opc_debug_modify_reg           = 0xFF07,
 291         iavf_aqc_opc_debug_dump_internals       = 0xFF08,
 292 };
 293
 294 /* command structures and indirect data structures */
 295
 296 /* Structure naming conventions:
 297  * - no suffix for direct command descriptor structures
 298  * - _data for indirect sent data
 299  * - _resp for indirect return data (data which is both will use _data)
 300  * - _completion for direct return data
 301  * - _element_ for repeated elements (may also be _data or _resp)
 302  *
 303  * Command structures are expected to overlay the params.raw member of the basic
 304  * descriptor, and as such cannot exceed 16 bytes in length.
 305  */
 306
 307 /* This macro is used to generate a compilation error if a structure
 308  * is not exactly the correct length. It gives a divide by zero error if the
 309  * structure is not of the correct size, otherwise it creates an enum that is
 310  * never used.
 311  */
 312 #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \
 313         { iavf_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 314
 315 /* This macro is used extensively to ensure that command structures are 16
 316  * bytes in length as they have to map to the raw array of that size.
 317  */
 318 #define IAVF_CHECK_CMD_LENGTH(X)        IAVF_CHECK_STRUCT_LEN(16, X)
 319
 320 /* internal (0x00XX) commands */
 321
 322 /* Get version (direct 0x0001) */
 323 struct iavf_aqc_get_version {
 324         __le32 rom_ver;
 325         __le32 fw_build;
 326         __le16 fw_major;
 327         __le16 fw_minor;
 328         __le16 api_major;
 329         __le16 api_minor;
 330 };
 331
 332 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_version);
 333
 334 /* Send driver version (indirect 0x0002) */
 335 struct iavf_aqc_driver_version {
 336         u8      driver_major_ver;
 337         u8      driver_minor_ver;
 338         u8      driver_build_ver;
 339         u8      driver_subbuild_ver;
 340         u8      reserved[4];
 341         __le32  address_high;
 342         __le32  address_low;
 343 };
 344
 345 IAVF_CHECK_CMD_LENGTH(iavf_aqc_driver_version);
 346
 347 /* Queue Shutdown (direct 0x0003) */
 348 struct iavf_aqc_queue_shutdown {
 349         __le32  driver_unloading;
 350 #define IAVF_AQ_DRIVER_UNLOADING        0x1
 351         u8      reserved[12];
 352 };
 353
 354 IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
 355
 356 /* Set PF context (0x0004, direct) */
 357 struct iavf_aqc_set_pf_context {
 358         u8      pf_id;
 359         u8      reserved[15];
 360 };
 361
 362 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_pf_context);
 363
 364 /* Request resource ownership (direct 0x0008)
 365  * Release resource ownership (direct 0x0009)
 366  */
 367 #define IAVF_AQ_RESOURCE_NVM                    1
 368 #define IAVF_AQ_RESOURCE_SDP                    2
 369 #define IAVF_AQ_RESOURCE_ACCESS_READ            1
 370 #define IAVF_AQ_RESOURCE_ACCESS_WRITE           2
 371 #define IAVF_AQ_RESOURCE_NVM_READ_TIMEOUT       3000
 372 #define IAVF_AQ_RESOURCE_NVM_WRITE_TIMEOUT      180000
 373
 374 struct iavf_aqc_request_resource {
 375         __le16  resource_id;
 376         __le16  access_type;
 377         __le32  timeout;
 378         __le32  resource_number;
 379         u8      reserved[4];
 380 };
 381
 382 IAVF_CHECK_CMD_LENGTH(iavf_aqc_request_resource);
 383
 384 /* Get function capabilities (indirect 0x000A)
 385  * Get device capabilities (indirect 0x000B)
 386  */
 387 struct iavf_aqc_list_capabilites {
 388         u8 command_flags;
 389 #define IAVF_AQ_LIST_CAP_PF_INDEX_EN    1
 390         u8 pf_index;
 391         u8 reserved[2];
 392         __le32 count;
 393         __le32 addr_high;
 394         __le32 addr_low;
 395 };
 396
 397 IAVF_CHECK_CMD_LENGTH(iavf_aqc_list_capabilites);
 398
 399 struct iavf_aqc_list_capabilities_element_resp {
 400         __le16  id;
 401         u8      major_rev;
 402         u8      minor_rev;
 403         __le32  number;
 404         __le32  logical_id;
 405         __le32  phys_id;
 406         u8      reserved[16];
 407 };
 408
 409 /* list of caps */
 410
 411 #define IAVF_AQ_CAP_ID_SWITCH_MODE      0x0001
 412 #define IAVF_AQ_CAP_ID_MNG_MODE         0x0002
 413 #define IAVF_AQ_CAP_ID_NPAR_ACTIVE      0x0003
 414 #define IAVF_AQ_CAP_ID_OS2BMC_CAP       0x0004
 415 #define IAVF_AQ_CAP_ID_FUNCTIONS_VALID  0x0005
 416 #define IAVF_AQ_CAP_ID_ALTERNATE_RAM    0x0006
 417 #define IAVF_AQ_CAP_ID_WOL_AND_PROXY    0x0008
 418 #define IAVF_AQ_CAP_ID_SRIOV            0x0012
 419 #define IAVF_AQ_CAP_ID_VF               0x0013
 420 #define IAVF_AQ_CAP_ID_VMDQ             0x0014
 421 #define IAVF_AQ_CAP_ID_8021QBG          0x0015
 422 #define IAVF_AQ_CAP_ID_8021QBR          0x0016
 423 #define IAVF_AQ_CAP_ID_VSI              0x0017
 424 #define IAVF_AQ_CAP_ID_DCB              0x0018
 425 #define IAVF_AQ_CAP_ID_FCOE             0x0021
 426 #define IAVF_AQ_CAP_ID_ISCSI            0x0022
 427 #define IAVF_AQ_CAP_ID_RSS              0x0040
 428 #define IAVF_AQ_CAP_ID_RXQ              0x0041
 429 #define IAVF_AQ_CAP_ID_TXQ              0x0042
 430 #define IAVF_AQ_CAP_ID_MSIX             0x0043
 431 #define IAVF_AQ_CAP_ID_VF_MSIX          0x0044
 432 #define IAVF_AQ_CAP_ID_FLOW_DIRECTOR    0x0045
 433 #define IAVF_AQ_CAP_ID_1588             0x0046
 434 #define IAVF_AQ_CAP_ID_IWARP            0x0051
 435 #define IAVF_AQ_CAP_ID_LED              0x0061
 436 #define IAVF_AQ_CAP_ID_SDP              0x0062
 437 #define IAVF_AQ_CAP_ID_MDIO             0x0063
 438 #define IAVF_AQ_CAP_ID_WSR_PROT         0x0064
 439 #define IAVF_AQ_CAP_ID_NVM_MGMT         0x0080
 440 #define IAVF_AQ_CAP_ID_FLEX10           0x00F1
 441 #define IAVF_AQ_CAP_ID_CEM              0x00F2
 442
 443 /* Set CPPM Configuration (direct 0x0103) */
 444 struct iavf_aqc_cppm_configuration {
 445         __le16  command_flags;
 446 #define IAVF_AQ_CPPM_EN_LTRC    0x0800
 447 #define IAVF_AQ_CPPM_EN_DMCTH   0x1000
 448 #define IAVF_AQ_CPPM_EN_DMCTLX  0x2000
 449 #define IAVF_AQ_CPPM_EN_HPTC    0x4000
 450 #define IAVF_AQ_CPPM_EN_DMARC   0x8000
 451         __le16  ttlx;
 452         __le32  dmacr;
 453         __le16  dmcth;
 454         u8      hptc;
 455         u8      reserved;
 456         __le32  pfltrc;
 457 };
 458
 459 IAVF_CHECK_CMD_LENGTH(iavf_aqc_cppm_configuration);
 460
 461 /* Set ARP Proxy command / response (indirect 0x0104) */
 462 struct iavf_aqc_arp_proxy_data {
 463         __le16  command_flags;
 464 #define IAVF_AQ_ARP_INIT_IPV4   0x0800
 465 #define IAVF_AQ_ARP_UNSUP_CTL   0x1000
 466 #define IAVF_AQ_ARP_ENA         0x2000
 467 #define IAVF_AQ_ARP_ADD_IPV4    0x4000
 468 #define IAVF_AQ_ARP_DEL_IPV4    0x8000
 469         __le16  table_id;
 470         __le32  enabled_offloads;
 471 #define IAVF_AQ_ARP_DIRECTED_OFFLOAD_ENABLE     0x00000020
 472 #define IAVF_AQ_ARP_OFFLOAD_ENABLE              0x00000800
 473         __le32  ip_addr;
 474         u8      mac_addr[6];
 475         u8      reserved[2];
 476 };
 477
 478 IAVF_CHECK_STRUCT_LEN(0x14, iavf_aqc_arp_proxy_data);
 479
 480 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
 481 struct iavf_aqc_ns_proxy_data {
 482         __le16  table_idx_mac_addr_0;
 483         __le16  table_idx_mac_addr_1;
 484         __le16  table_idx_ipv6_0;
 485         __le16  table_idx_ipv6_1;
 486         __le16  control;
 487 #define IAVF_AQ_NS_PROXY_ADD_0          0x0001
 488 #define IAVF_AQ_NS_PROXY_DEL_0          0x0002
 489 #define IAVF_AQ_NS_PROXY_ADD_1          0x0004
 490 #define IAVF_AQ_NS_PROXY_DEL_1          0x0008
 491 #define IAVF_AQ_NS_PROXY_ADD_IPV6_0     0x0010
 492 #define IAVF_AQ_NS_PROXY_DEL_IPV6_0     0x0020
 493 #define IAVF_AQ_NS_PROXY_ADD_IPV6_1     0x0040
 494 #define IAVF_AQ_NS_PROXY_DEL_IPV6_1     0x0080
 495 #define IAVF_AQ_NS_PROXY_COMMAND_SEQ    0x0100
 496 #define IAVF_AQ_NS_PROXY_INIT_IPV6_TBL  0x0200
 497 #define IAVF_AQ_NS_PROXY_INIT_MAC_TBL   0x0400
 498 #define IAVF_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
 499 #define IAVF_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE        0x1000
 500         u8      mac_addr_0[6];
 501         u8      mac_addr_1[6];
 502         u8      local_mac_addr[6];
 503         u8      ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
 504         u8      ipv6_addr_1[16];
 505 };
 506
 507 IAVF_CHECK_STRUCT_LEN(0x3c, iavf_aqc_ns_proxy_data);
 508
 509 /* Manage LAA Command (0x0106) - obsolete */
 510 struct iavf_aqc_mng_laa {
 511         __le16  command_flags;
 512 #define IAVF_AQ_LAA_FLAG_WR     0x8000
 513         u8      reserved[2];
 514         __le32  sal;
 515         __le16  sah;
 516         u8      reserved2[6];
 517 };
 518
 519 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mng_laa);
 520
 521 /* Manage MAC Address Read Command (indirect 0x0107) */
 522 struct iavf_aqc_mac_address_read {
 523         __le16  command_flags;
 524 #define IAVF_AQC_LAN_ADDR_VALID         0x10
 525 #define IAVF_AQC_SAN_ADDR_VALID         0x20
 526 #define IAVF_AQC_PORT_ADDR_VALID        0x40
 527 #define IAVF_AQC_WOL_ADDR_VALID         0x80
 528 #define IAVF_AQC_MC_MAG_EN_VALID        0x100
 529 #define IAVF_AQC_WOL_PRESERVE_STATUS    0x200
 530 #define IAVF_AQC_ADDR_VALID_MASK        0x3F0
 531         u8      reserved[6];
 532         __le32  addr_high;
 533         __le32  addr_low;
 534 };
 535
 536 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_read);
 537
 538 struct iavf_aqc_mac_address_read_data {
 539         u8 pf_lan_mac[6];
 540         u8 pf_san_mac[6];
 541         u8 port_mac[6];
 542         u8 pf_wol_mac[6];
 543 };
 544
 545 IAVF_CHECK_STRUCT_LEN(24, iavf_aqc_mac_address_read_data);
 546
 547 /* Manage MAC Address Write Command (0x0108) */
 548 struct iavf_aqc_mac_address_write {
 549         __le16  command_flags;
 550 #define IAVF_AQC_MC_MAG_EN              0x0100
 551 #define IAVF_AQC_WOL_PRESERVE_ON_PFR    0x0200
 552 #define IAVF_AQC_WRITE_TYPE_LAA_ONLY    0x0000
 553 #define IAVF_AQC_WRITE_TYPE_LAA_WOL     0x4000
 554 #define IAVF_AQC_WRITE_TYPE_PORT        0x8000
 555 #define IAVF_AQC_WRITE_TYPE_UPDATE_MC_MAG       0xC000
 556 #define IAVF_AQC_WRITE_TYPE_MASK        0xC000
 557
 558         __le16  mac_sah;
 559         __le32  mac_sal;
 560         u8      reserved[8];
 561 };
 562
 563 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_write);
 564
 565 /* PXE commands (0x011x) */
 566
 567 /* Clear PXE Command and response  (direct 0x0110) */
 568 struct iavf_aqc_clear_pxe {
 569         u8      rx_cnt;
 570         u8      reserved[15];
 571 };
 572
 573 IAVF_CHECK_CMD_LENGTH(iavf_aqc_clear_pxe);
 574
 575 /* Set WoL Filter (0x0120) */
 576
 577 struct iavf_aqc_set_wol_filter {
 578         __le16 filter_index;
 579 #define IAVF_AQC_MAX_NUM_WOL_FILTERS    8
 580 #define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT        15
 581 #define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
 582                 IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
 583
 584 #define IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT             0
 585 #define IAVF_AQC_SET_WOL_FILTER_INDEX_MASK      (0x7 << \
 586                 IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT)
 587         __le16 cmd_flags;
 588 #define IAVF_AQC_SET_WOL_FILTER                         0x8000
 589 #define IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL              0x4000
 590 #define IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR     0x2000
 591 #define IAVF_AQC_SET_WOL_FILTER_ACTION_CLEAR            0
 592 #define IAVF_AQC_SET_WOL_FILTER_ACTION_SET              1
 593         __le16 valid_flags;
 594 #define IAVF_AQC_SET_WOL_FILTER_ACTION_VALID            0x8000
 595 #define IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID     0x4000
 596         u8 reserved[2];
 597         __le32  address_high;
 598         __le32  address_low;
 599 };
 600
 601 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_wol_filter);
 602
 603 struct iavf_aqc_set_wol_filter_data {
 604         u8 filter[128];
 605         u8 mask[16];
 606 };
 607
 608 IAVF_CHECK_STRUCT_LEN(0x90, iavf_aqc_set_wol_filter_data);
 609
 610 /* Get Wake Reason (0x0121) */
 611
 612 struct iavf_aqc_get_wake_reason_completion {
 613         u8 reserved_1[2];
 614         __le16 wake_reason;
 615 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT      0
 616 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
 617                 IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
 618 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT   8
 619 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK    (0xFF << \
 620                 IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
 621         u8 reserved_2[12];
 622 };
 623
 624 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_wake_reason_completion);
 625
 626 /* Switch configuration commands (0x02xx) */
 627
 628 /* Used by many indirect commands that only pass an seid and a buffer in the
 629  * command
 630  */
 631 struct iavf_aqc_switch_seid {
 632         __le16  seid;
 633         u8      reserved[6];
 634         __le32  addr_high;
 635         __le32  addr_low;
 636 };
 637
 638 IAVF_CHECK_CMD_LENGTH(iavf_aqc_switch_seid);
 639
 640 /* Get Switch Configuration command (indirect 0x0200)
 641  * uses iavf_aqc_switch_seid for the descriptor
 642  */
 643 struct iavf_aqc_get_switch_config_header_resp {
 644         __le16  num_reported;
 645         __le16  num_total;
 646         u8      reserved[12];
 647 };
 648
 649 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_config_header_resp);
 650
 651 struct iavf_aqc_switch_config_element_resp {
 652         u8      element_type;
 653 #define IAVF_AQ_SW_ELEM_TYPE_MAC        1
 654 #define IAVF_AQ_SW_ELEM_TYPE_PF         2
 655 #define IAVF_AQ_SW_ELEM_TYPE_VF         3
 656 #define IAVF_AQ_SW_ELEM_TYPE_EMP        4
 657 #define IAVF_AQ_SW_ELEM_TYPE_BMC        5
 658 #define IAVF_AQ_SW_ELEM_TYPE_PV         16
 659 #define IAVF_AQ_SW_ELEM_TYPE_VEB        17
 660 #define IAVF_AQ_SW_ELEM_TYPE_PA         18
 661 #define IAVF_AQ_SW_ELEM_TYPE_VSI        19
 662         u8      revision;
 663 #define IAVF_AQ_SW_ELEM_REV_1           1
 664         __le16  seid;
 665         __le16  uplink_seid;
 666         __le16  downlink_seid;
 667         u8      reserved[3];
 668         u8      connection_type;
 669 #define IAVF_AQ_CONN_TYPE_REGULAR       0x1
 670 #define IAVF_AQ_CONN_TYPE_DEFAULT       0x2
 671 #define IAVF_AQ_CONN_TYPE_CASCADED      0x3
 672         __le16  scheduler_id;
 673         __le16  element_info;
 674 };
 675
 676 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_config_element_resp);
 677
 678 /* Get Switch Configuration (indirect 0x0200)
 679  *    an array of elements are returned in the response buffer
 680  *    the first in the array is the header, remainder are elements
 681  */
 682 struct iavf_aqc_get_switch_config_resp {
 683         struct iavf_aqc_get_switch_config_header_resp   header;
 684         struct iavf_aqc_switch_config_element_resp      element[1];
 685 };
 686
 687 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_switch_config_resp);
 688
 689 /* Add Statistics (direct 0x0201)
 690  * Remove Statistics (direct 0x0202)
 691  */
 692 struct iavf_aqc_add_remove_statistics {
 693         __le16  seid;
 694         __le16  vlan;
 695         __le16  stat_index;
 696         u8      reserved[10];
 697 };
 698
 699 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_statistics);
 700
 701 /* Set Port Parameters command (direct 0x0203) */
 702 struct iavf_aqc_set_port_parameters {
 703         __le16  command_flags;
 704 #define IAVF_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS   1
 705 #define IAVF_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS  2 /* must set! */
 706 #define IAVF_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA    4
 707         __le16  bad_frame_vsi;
 708 #define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT  0x0
 709 #define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_MASK   0x3FF
 710         __le16  default_seid;        /* reserved for command */
 711         u8      reserved[10];
 712 };
 713
 714 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_port_parameters);
 715
 716 /* Get Switch Resource Allocation (indirect 0x0204) */
 717 struct iavf_aqc_get_switch_resource_alloc {
 718         u8      num_entries;         /* reserved for command */
 719         u8      reserved[7];
 720         __le32  addr_high;
 721         __le32  addr_low;
 722 };
 723
 724 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_resource_alloc);
 725
 726 /* expect an array of these structs in the response buffer */
 727 struct iavf_aqc_switch_resource_alloc_element_resp {
 728         u8      resource_type;
 729 #define IAVF_AQ_RESOURCE_TYPE_VEB               0x0
 730 #define IAVF_AQ_RESOURCE_TYPE_VSI               0x1
 731 #define IAVF_AQ_RESOURCE_TYPE_MACADDR           0x2
 732 #define IAVF_AQ_RESOURCE_TYPE_STAG              0x3
 733 #define IAVF_AQ_RESOURCE_TYPE_ETAG              0x4
 734 #define IAVF_AQ_RESOURCE_TYPE_MULTICAST_HASH    0x5
 735 #define IAVF_AQ_RESOURCE_TYPE_UNICAST_HASH      0x6
 736 #define IAVF_AQ_RESOURCE_TYPE_VLAN              0x7
 737 #define IAVF_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY    0x8
 738 #define IAVF_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY   0x9
 739 #define IAVF_AQ_RESOURCE_TYPE_VLAN_STAT_POOL    0xA
 740 #define IAVF_AQ_RESOURCE_TYPE_MIRROR_RULE       0xB
 741 #define IAVF_AQ_RESOURCE_TYPE_QUEUE_SETS        0xC
 742 #define IAVF_AQ_RESOURCE_TYPE_VLAN_FILTERS      0xD
 743 #define IAVF_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
 744 #define IAVF_AQ_RESOURCE_TYPE_IP_FILTERS        0x10
 745 #define IAVF_AQ_RESOURCE_TYPE_GRE_VN_KEYS       0x11
 746 #define IAVF_AQ_RESOURCE_TYPE_VN2_KEYS          0x12
 747 #define IAVF_AQ_RESOURCE_TYPE_TUNNEL_PORTS      0x13
 748         u8      reserved1;
 749         __le16  guaranteed;
 750         __le16  total;
 751         __le16  used;
 752         __le16  total_unalloced;
 753         u8      reserved2[6];
 754 };
 755
 756 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_resource_alloc_element_resp);
 757
 758 /* Set Switch Configuration (direct 0x0205) */
 759 struct iavf_aqc_set_switch_config {
 760         __le16  flags;
 761 /* flags used for both fields below */
 762 #define IAVF_AQ_SET_SWITCH_CFG_PROMISC          0x0001
 763 #define IAVF_AQ_SET_SWITCH_CFG_L2_FILTER        0x0002
 764 #define IAVF_AQ_SET_SWITCH_CFG_HW_ATR_EVICT     0x0004
 765         __le16  valid_flags;
 766         /* The ethertype in switch_tag is dropped on ingress and used
 767          * internally by the switch. Set this to zero for the default
 768          * of 0x88a8 (802.1ad). Should be zero for firmware API
 769          * versions lower than 1.7.
 770          */
 771         __le16  switch_tag;
 772         /* The ethertypes in first_tag and second_tag are used to
 773          * match the outer and inner VLAN tags (respectively) when HW
 774          * double VLAN tagging is enabled via the set port parameters
 775          * AQ command. Otherwise these are both ignored. Set them to
 776          * zero for their defaults of 0x8100 (802.1Q). Should be zero
 777          * for firmware API versions lower than 1.7.
 778          */
 779         __le16  first_tag;
 780         __le16  second_tag;
 781         u8      reserved[6];
 782 };
 783
 784 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_switch_config);
 785
 786 /* Read Receive control registers  (direct 0x0206)
 787  * Write Receive control registers (direct 0x0207)
 788  *     used for accessing Rx control registers that can be
 789  *     slow and need special handling when under high Rx load
 790  */
 791 struct iavf_aqc_rx_ctl_reg_read_write {
 792         __le32 reserved1;
 793         __le32 address;
 794         __le32 reserved2;
 795         __le32 value;
 796 };
 797
 798 IAVF_CHECK_CMD_LENGTH(iavf_aqc_rx_ctl_reg_read_write);
 799
 800 /* Add VSI (indirect 0x0210)
 801  *    this indirect command uses struct iavf_aqc_vsi_properties_data
 802  *    as the indirect buffer (128 bytes)
 803  *
 804  * Update VSI (indirect 0x211)
 805  *     uses the same data structure as Add VSI
 806  *
 807  * Get VSI (indirect 0x0212)
 808  *     uses the same completion and data structure as Add VSI
 809  */
 810 struct iavf_aqc_add_get_update_vsi {
 811         __le16  uplink_seid;
 812         u8      connection_type;
 813 #define IAVF_AQ_VSI_CONN_TYPE_NORMAL    0x1
 814 #define IAVF_AQ_VSI_CONN_TYPE_DEFAULT   0x2
 815 #define IAVF_AQ_VSI_CONN_TYPE_CASCADED  0x3
 816         u8      reserved1;
 817         u8      vf_id;
 818         u8      reserved2;
 819         __le16  vsi_flags;
 820 #define IAVF_AQ_VSI_TYPE_SHIFT          0x0
 821 #define IAVF_AQ_VSI_TYPE_MASK           (0x3 << IAVF_AQ_VSI_TYPE_SHIFT)
 822 #define IAVF_AQ_VSI_TYPE_VF             0x0
 823 #define IAVF_AQ_VSI_TYPE_VMDQ2          0x1
 824 #define IAVF_AQ_VSI_TYPE_PF             0x2
 825 #define IAVF_AQ_VSI_TYPE_EMP_MNG        0x3
 826 #define IAVF_AQ_VSI_FLAG_CASCADED_PV    0x4
 827         __le32  addr_high;
 828         __le32  addr_low;
 829 };
 830
 831 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi);
 832
 833 struct iavf_aqc_add_get_update_vsi_completion {
 834         __le16 seid;
 835         __le16 vsi_number;
 836         __le16 vsi_used;
 837         __le16 vsi_free;
 838         __le32 addr_high;
 839         __le32 addr_low;
 840 };
 841
 842 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi_completion);
 843
 844 struct iavf_aqc_vsi_properties_data {
 845         /* first 96 byte are written by SW */
 846         __le16  valid_sections;
 847 #define IAVF_AQ_VSI_PROP_SWITCH_VALID           0x0001
 848 #define IAVF_AQ_VSI_PROP_SECURITY_VALID         0x0002
 849 #define IAVF_AQ_VSI_PROP_VLAN_VALID             0x0004
 850 #define IAVF_AQ_VSI_PROP_CAS_PV_VALID           0x0008
 851 #define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID       0x0010
 852 #define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID        0x0020
 853 #define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID        0x0040
 854 #define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID        0x0080
 855 #define IAVF_AQ_VSI_PROP_OUTER_UP_VALID         0x0100
 856 #define IAVF_AQ_VSI_PROP_SCHED_VALID            0x0200
 857         /* switch section */
 858         __le16  switch_id; /* 12bit id combined with flags below */
 859 #define IAVF_AQ_VSI_SW_ID_SHIFT         0x0000
 860 #define IAVF_AQ_VSI_SW_ID_MASK          (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT)
 861 #define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
 862 #define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
 863 #define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
 864         u8      sw_reserved[2];
 865         /* security section */
 866         u8      sec_flags;
 867 #define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
 868 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
 869 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04
 870         u8      sec_reserved;
 871         /* VLAN section */
 872         __le16  pvid; /* VLANS include priority bits */
 873         __le16  fcoe_pvid;
 874         u8      port_vlan_flags;
 875 #define IAVF_AQ_VSI_PVLAN_MODE_SHIFT    0x00
 876 #define IAVF_AQ_VSI_PVLAN_MODE_MASK     (0x03 << \
 877                                          IAVF_AQ_VSI_PVLAN_MODE_SHIFT)
 878 #define IAVF_AQ_VSI_PVLAN_MODE_TAGGED   0x01
 879 #define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
 880 #define IAVF_AQ_VSI_PVLAN_MODE_ALL      0x03
 881 #define IAVF_AQ_VSI_PVLAN_INSERT_PVID   0x04
 882 #define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
 883 #define IAVF_AQ_VSI_PVLAN_EMOD_MASK     (0x3 << \
 884                                          IAVF_AQ_VSI_PVLAN_EMOD_SHIFT)
 885 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
 886 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
 887 #define IAVF_AQ_VSI_PVLAN_EMOD_STR      0x10
 888 #define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
 889         u8      pvlan_reserved[3];
 890         /* ingress egress up sections */
 891         __le32  ingress_table; /* bitmap, 3 bits per up */
 892 #define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT  0
 893 #define IAVF_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
 894                                          IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT)
 895 #define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT  3
 896 #define IAVF_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
 897                                          IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT)
 898 #define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT  6
 899 #define IAVF_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
 900                                          IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT)
 901 #define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT  9
 902 #define IAVF_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
 903                                          IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT)
 904 #define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT  12
 905 #define IAVF_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
 906                                          IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT)
 907 #define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT  15
 908 #define IAVF_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
 909                                          IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT)
 910 #define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT  18
 911 #define IAVF_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
 912                                          IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT)
 913 #define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT  21
 914 #define IAVF_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
 915                                          IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT)
 916         __le32  egress_table;   /* same defines as for ingress table */
 917         /* cascaded PV section */
 918         __le16  cas_pv_tag;
 919         u8      cas_pv_flags;
 920 #define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT           0x00
 921 #define IAVF_AQ_VSI_CAS_PV_TAGX_MASK            (0x03 << \
 922                                                  IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT)
 923 #define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE           0x00
 924 #define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE          0x01
 925 #define IAVF_AQ_VSI_CAS_PV_TAGX_COPY            0x02
 926 #define IAVF_AQ_VSI_CAS_PV_INSERT_TAG           0x10
 927 #define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE           0x20
 928 #define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG      0x40
 929         u8      cas_pv_reserved;
 930         /* queue mapping section */
 931         __le16  mapping_flags;
 932 #define IAVF_AQ_VSI_QUE_MAP_CONTIG      0x0
 933 #define IAVF_AQ_VSI_QUE_MAP_NONCONTIG   0x1
 934         __le16  queue_mapping[16];
 935 #define IAVF_AQ_VSI_QUEUE_SHIFT         0x0
 936 #define IAVF_AQ_VSI_QUEUE_MASK          (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT)
 937         __le16  tc_mapping[8];
 938 #define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
 939 #define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
 940                                          IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 941 #define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
 942 #define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
 943                                          IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 944         /* queueing option section */
 945         u8      queueing_opt_flags;
 946 #define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
 947 #define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA     0x08
 948 #define IAVF_AQ_VSI_QUE_OPT_TCP_ENA     0x10
 949 #define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
 950 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
 951 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
 952         u8      queueing_opt_reserved[3];
 953         /* scheduler section */
 954         u8      up_enable_bits;
 955         u8      sched_reserved;
 956         /* outer up section */
 957         __le32  outer_up_table; /* same structure and defines as ingress tbl */
 958         u8      cmd_reserved[8];
 959         /* last 32 bytes are written by FW */
 960         __le16  qs_handle[8];
 961 #define IAVF_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
 962         __le16  stat_counter_idx;
 963         __le16  sched_id;
 964         u8      resp_reserved[12];
 965 };
 966
 967 IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
 968
 969 /* Add Port Virtualizer (direct 0x0220)
 970  * also used for update PV (direct 0x0221) but only flags are used
 971  * (IS_CTRL_PORT only works on add PV)
 972  */
 973 struct iavf_aqc_add_update_pv {
 974         __le16  command_flags;
 975 #define IAVF_AQC_PV_FLAG_PV_TYPE                0x1
 976 #define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN    0x2
 977 #define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN    0x4
 978 #define IAVF_AQC_PV_FLAG_IS_CTRL_PORT           0x8
 979         __le16  uplink_seid;
 980         __le16  connected_seid;
 981         u8      reserved[10];
 982 };
 983
 984 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv);
 985
 986 struct iavf_aqc_add_update_pv_completion {
 987         /* reserved for update; for add also encodes error if rc == ENOSPC */
 988         __le16  pv_seid;
 989 #define IAVF_AQC_PV_ERR_FLAG_NO_PV      0x1
 990 #define IAVF_AQC_PV_ERR_FLAG_NO_SCHED   0x2
 991 #define IAVF_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
 992 #define IAVF_AQC_PV_ERR_FLAG_NO_ENTRY   0x8
 993         u8      reserved[14];
 994 };
 995
 996 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv_completion);
 997
 998 /* Get PV Params (direct 0x0222)
 999  * uses iavf_aqc_switch_seid for the descriptor
1000  */
1001
1002 struct iavf_aqc_get_pv_params_completion {
1003         __le16  seid;
1004         __le16  default_stag;
1005         __le16  pv_flags; /* same flags as add_pv */
1006 #define IAVF_AQC_GET_PV_PV_TYPE                 0x1
1007 #define IAVF_AQC_GET_PV_FRWD_UNKNOWN_STAG       0x2
1008 #define IAVF_AQC_GET_PV_FRWD_UNKNOWN_ETAG       0x4
1009         u8      reserved[8];
1010         __le16  default_port_seid;
1011 };
1012
1013 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_pv_params_completion);
1014
1015 /* Add VEB (direct 0x0230) */
1016 struct iavf_aqc_add_veb {
1017         __le16  uplink_seid;
1018         __le16  downlink_seid;
1019         __le16  veb_flags;
1020 #define IAVF_AQC_ADD_VEB_FLOATING               0x1
1021 #define IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT        1
1022 #define IAVF_AQC_ADD_VEB_PORT_TYPE_MASK         (0x3 << \
1023                                         IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1024 #define IAVF_AQC_ADD_VEB_PORT_TYPE_DEFAULT      0x2
1025 #define IAVF_AQC_ADD_VEB_PORT_TYPE_DATA         0x4
1026 #define IAVF_AQC_ADD_VEB_ENABLE_L2_FILTER       0x8     /* deprecated */
1027 #define IAVF_AQC_ADD_VEB_ENABLE_DISABLE_STATS   0x10
1028         u8      enable_tcs;
1029         u8      reserved[9];
1030 };
1031
1032 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb);
1033
1034 struct iavf_aqc_add_veb_completion {
1035         u8      reserved[6];
1036         __le16  switch_seid;
1037         /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1038         __le16  veb_seid;
1039 #define IAVF_AQC_VEB_ERR_FLAG_NO_VEB            0x1
1040 #define IAVF_AQC_VEB_ERR_FLAG_NO_SCHED          0x2
1041 #define IAVF_AQC_VEB_ERR_FLAG_NO_COUNTER        0x4
1042 #define IAVF_AQC_VEB_ERR_FLAG_NO_ENTRY          0x8
1043         __le16  statistic_index;
1044         __le16  vebs_used;
1045         __le16  vebs_free;
1046 };
1047
1048 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb_completion);
1049
1050 /* Get VEB Parameters (direct 0x0232)
1051  * uses iavf_aqc_switch_seid for the descriptor
1052  */
1053 struct iavf_aqc_get_veb_parameters_completion {
1054         __le16  seid;
1055         __le16  switch_id;
1056         __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
1057         __le16  statistic_index;
1058         __le16  vebs_used;
1059         __le16  vebs_free;
1060         u8      reserved[4];
1061 };
1062
1063 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
1064
1065 /* Delete Element (direct 0x0243)
1066  * uses the generic iavf_aqc_switch_seid
1067  */
1068
1069 /* Add MAC-VLAN (indirect 0x0250) */
1070
1071 /* used for the command for most vlan commands */
1072 struct iavf_aqc_macvlan {
1073         __le16  num_addresses;
1074         __le16  seid[3];
1075 #define IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT     0
1076 #define IAVF_AQC_MACVLAN_CMD_SEID_NUM_MASK      (0x3FF << \
1077                                         IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1078 #define IAVF_AQC_MACVLAN_CMD_SEID_VALID         0x8000
1079         __le32  addr_high;
1080         __le32  addr_low;
1081 };
1082
1083 IAVF_CHECK_CMD_LENGTH(iavf_aqc_macvlan);
1084
1085 /* indirect data for command and response */
1086 struct iavf_aqc_add_macvlan_element_data {
1087         u8      mac_addr[6];
1088         __le16  vlan_tag;
1089         __le16  flags;
1090 #define IAVF_AQC_MACVLAN_ADD_PERFECT_MATCH      0x0001
1091 #define IAVF_AQC_MACVLAN_ADD_HASH_MATCH         0x0002
1092 #define IAVF_AQC_MACVLAN_ADD_IGNORE_VLAN        0x0004
1093 #define IAVF_AQC_MACVLAN_ADD_TO_QUEUE           0x0008
1094 #define IAVF_AQC_MACVLAN_ADD_USE_SHARED_MAC     0x0010
1095         __le16  queue_number;
1096 #define IAVF_AQC_MACVLAN_CMD_QUEUE_SHIFT        0
1097 #define IAVF_AQC_MACVLAN_CMD_QUEUE_MASK         (0x7FF << \
1098                                         IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1099         /* response section */
1100         u8      match_method;
1101 #define IAVF_AQC_MM_PERFECT_MATCH       0x01
1102 #define IAVF_AQC_MM_HASH_MATCH          0x02
1103 #define IAVF_AQC_MM_ERR_NO_RES          0xFF
1104         u8      reserved1[3];
1105 };
1106
1107 struct iavf_aqc_add_remove_macvlan_completion {
1108         __le16 perfect_mac_used;
1109         __le16 perfect_mac_free;
1110         __le16 unicast_hash_free;
1111         __le16 multicast_hash_free;
1112         __le32 addr_high;
1113         __le32 addr_low;
1114 };
1115
1116 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_macvlan_completion);
1117
1118 /* Remove MAC-VLAN (indirect 0x0251)
1119  * uses iavf_aqc_macvlan for the descriptor
1120  * data points to an array of num_addresses of elements
1121  */
1122
1123 struct iavf_aqc_remove_macvlan_element_data {
1124         u8      mac_addr[6];
1125         __le16  vlan_tag;
1126         u8      flags;
1127 #define IAVF_AQC_MACVLAN_DEL_PERFECT_MATCH      0x01
1128 #define IAVF_AQC_MACVLAN_DEL_HASH_MATCH         0x02
1129 #define IAVF_AQC_MACVLAN_DEL_IGNORE_VLAN        0x08
1130 #define IAVF_AQC_MACVLAN_DEL_ALL_VSIS           0x10
1131         u8      reserved[3];
1132         /* reply section */
1133         u8      error_code;
1134 #define IAVF_AQC_REMOVE_MACVLAN_SUCCESS         0x0
1135 #define IAVF_AQC_REMOVE_MACVLAN_FAIL            0xFF
1136         u8      reply_reserved[3];
1137 };
1138
1139 /* Add VLAN (indirect 0x0252)
1140  * Remove VLAN (indirect 0x0253)
1141  * use the generic iavf_aqc_macvlan for the command
1142  */
1143 struct iavf_aqc_add_remove_vlan_element_data {
1144         __le16  vlan_tag;
1145         u8      vlan_flags;
1146 /* flags for add VLAN */
1147 #define IAVF_AQC_ADD_VLAN_LOCAL                 0x1
1148 #define IAVF_AQC_ADD_PVLAN_TYPE_SHIFT           1
1149 #define IAVF_AQC_ADD_PVLAN_TYPE_MASK    (0x3 << IAVF_AQC_ADD_PVLAN_TYPE_SHIFT)
1150 #define IAVF_AQC_ADD_PVLAN_TYPE_REGULAR         0x0
1151 #define IAVF_AQC_ADD_PVLAN_TYPE_PRIMARY         0x2
1152 #define IAVF_AQC_ADD_PVLAN_TYPE_SECONDARY       0x4
1153 #define IAVF_AQC_VLAN_PTYPE_SHIFT               3
1154 #define IAVF_AQC_VLAN_PTYPE_MASK        (0x3 << IAVF_AQC_VLAN_PTYPE_SHIFT)
1155 #define IAVF_AQC_VLAN_PTYPE_REGULAR_VSI         0x0
1156 #define IAVF_AQC_VLAN_PTYPE_PROMISC_VSI         0x8
1157 #define IAVF_AQC_VLAN_PTYPE_COMMUNITY_VSI       0x10
1158 #define IAVF_AQC_VLAN_PTYPE_ISOLATED_VSI        0x18
1159 /* flags for remove VLAN */
1160 #define IAVF_AQC_REMOVE_VLAN_ALL        0x1
1161         u8      reserved;
1162         u8      result;
1163 /* flags for add VLAN */
1164 #define IAVF_AQC_ADD_VLAN_SUCCESS       0x0
1165 #define IAVF_AQC_ADD_VLAN_FAIL_REQUEST  0xFE
1166 #define IAVF_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1167 /* flags for remove VLAN */
1168 #define IAVF_AQC_REMOVE_VLAN_SUCCESS    0x0
1169 #define IAVF_AQC_REMOVE_VLAN_FAIL       0xFF
1170         u8      reserved1[3];
1171 };
1172
1173 struct iavf_aqc_add_remove_vlan_completion {
1174         u8      reserved[4];
1175         __le16  vlans_used;
1176         __le16  vlans_free;
1177         __le32  addr_high;
1178         __le32  addr_low;
1179 };
1180
1181 /* Set VSI Promiscuous Modes (direct 0x0254) */
1182 struct iavf_aqc_set_vsi_promiscuous_modes {
1183         __le16  promiscuous_flags;
1184         __le16  valid_flags;
1185 /* flags used for both fields above */
1186 #define IAVF_AQC_SET_VSI_PROMISC_UNICAST        0x01
1187 #define IAVF_AQC_SET_VSI_PROMISC_MULTICAST      0x02
1188 #define IAVF_AQC_SET_VSI_PROMISC_BROADCAST      0x04
1189 #define IAVF_AQC_SET_VSI_DEFAULT                0x08
1190 #define IAVF_AQC_SET_VSI_PROMISC_VLAN           0x10
1191 #define IAVF_AQC_SET_VSI_PROMISC_TX             0x8000
1192         __le16  seid;
1193 #define IAVF_AQC_VSI_PROM_CMD_SEID_MASK         0x3FF
1194         __le16  vlan_tag;
1195 #define IAVF_AQC_SET_VSI_VLAN_MASK              0x0FFF
1196 #define IAVF_AQC_SET_VSI_VLAN_VALID             0x8000
1197         u8      reserved[8];
1198 };
1199
1200 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_vsi_promiscuous_modes);
1201
1202 /* Add S/E-tag command (direct 0x0255)
1203  * Uses generic iavf_aqc_add_remove_tag_completion for completion
1204  */
1205 struct iavf_aqc_add_tag {
1206         __le16  flags;
1207 #define IAVF_AQC_ADD_TAG_FLAG_TO_QUEUE          0x0001
1208         __le16  seid;
1209 #define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT     0
1210 #define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_MASK      (0x3FF << \
1211                                         IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1212         __le16  tag;
1213         __le16  queue_number;
1214         u8      reserved[8];
1215 };
1216
1217 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_tag);
1218
1219 struct iavf_aqc_add_remove_tag_completion {
1220         u8      reserved[12];
1221         __le16  tags_used;
1222         __le16  tags_free;
1223 };
1224
1225 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_tag_completion);
1226
1227 /* Remove S/E-tag command (direct 0x0256)
1228  * Uses generic iavf_aqc_add_remove_tag_completion for completion
1229  */
1230 struct iavf_aqc_remove_tag {
1231         __le16  seid;
1232 #define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT  0
1233 #define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1234                                         IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1235         __le16  tag;
1236         u8      reserved[12];
1237 };
1238
1239 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);
1240
1241 /* Add multicast E-Tag (direct 0x0257)
1242  * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1243  * and no external data
1244  */
1245 struct iavf_aqc_add_remove_mcast_etag {
1246         __le16  pv_seid;
1247         __le16  etag;
1248         u8      num_unicast_etags;
1249         u8      reserved[3];
1250         __le32  addr_high;          /* address of array of 2-byte s-tags */
1251         __le32  addr_low;
1252 };
1253
1254 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);
1255
1256 struct iavf_aqc_add_remove_mcast_etag_completion {
1257         u8      reserved[4];
1258         __le16  mcast_etags_used;
1259         __le16  mcast_etags_free;
1260         __le32  addr_high;
1261         __le32  addr_low;
1262
1263 };
1264
1265 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);
1266
1267 /* Update S/E-Tag (direct 0x0259) */
1268 struct iavf_aqc_update_tag {
1269         __le16  seid;
1270 #define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT  0
1271 #define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1272                                         IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1273         __le16  old_tag;
1274         __le16  new_tag;
1275         u8      reserved[10];
1276 };
1277
1278 IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);
1279
1280 struct iavf_aqc_update_tag_completion {
1281         u8      reserved[12];
1282         __le16  tags_used;
1283         __le16  tags_free;
1284 };
1285
1286 IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);
1287
1288 /* Add Control Packet filter (direct 0x025A)
1289  * Remove Control Packet filter (direct 0x025B)
1290  * uses the iavf_aqc_add_oveb_cloud,
1291  * and the generic direct completion structure
1292  */
1293 struct iavf_aqc_add_remove_control_packet_filter {
1294         u8      mac[6];
1295         __le16  etype;
1296         __le16  flags;
1297 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC    0x0001
1298 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP          0x0002
1299 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE      0x0004
1300 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX            0x0008
1301 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX            0x0000
1302         __le16  seid;
1303 #define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT  0
1304 #define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK   (0x3FF << \
1305                                 IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1306         __le16  queue;
1307         u8      reserved[2];
1308 };
1309
1310 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);
1311
1312 struct iavf_aqc_add_remove_control_packet_filter_completion {
1313         __le16  mac_etype_used;
1314         __le16  etype_used;
1315         __le16  mac_etype_free;
1316         __le16  etype_free;
1317         u8      reserved[8];
1318 };
1319
1320 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);
1321
1322 /* Add Cloud filters (indirect 0x025C)
1323  * Remove Cloud filters (indirect 0x025D)
1324  * uses the iavf_aqc_add_remove_cloud_filters,
1325  * and the generic indirect completion structure
1326  */
1327 struct iavf_aqc_add_remove_cloud_filters {
1328         u8      num_filters;
1329         u8      reserved;
1330         __le16  seid;
1331 #define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT   0
1332 #define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK    (0x3FF << \
1333                                         IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1334         u8      big_buffer_flag;
1335 #define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER   1
1336         u8      reserved2[3];
1337         __le32  addr_high;
1338         __le32  addr_low;
1339 };
1340
1341 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);
1342
1343 struct iavf_aqc_add_remove_cloud_filters_element_data {
1344         u8      outer_mac[6];
1345         u8      inner_mac[6];
1346         __le16  inner_vlan;
1347         union {
1348                 struct {
1349                         u8 reserved[12];
1350                         u8 data[4];
1351                 } v4;
1352                 struct {
1353                         u8 data[16];
1354                 } v6;
1355         } ipaddr;
1356         __le16  flags;
1357 #define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT                 0
1358 #define IAVF_AQC_ADD_CLOUD_FILTER_MASK  (0x3F << \
1359                                         IAVF_AQC_ADD_CLOUD_FILTER_SHIFT)
1360 /* 0x0000 reserved */
1361 #define IAVF_AQC_ADD_CLOUD_FILTER_OIP                   0x0001
1362 /* 0x0002 reserved */
1363 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN            0x0003
1364 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID     0x0004
1365 /* 0x0005 reserved */
1366 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID           0x0006
1367 /* 0x0007 reserved */
1368 /* 0x0008 reserved */
1369 #define IAVF_AQC_ADD_CLOUD_FILTER_OMAC                  0x0009
1370 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC                  0x000A
1371 #define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC      0x000B
1372 #define IAVF_AQC_ADD_CLOUD_FILTER_IIP                   0x000C
1373 /* 0x0010 to 0x0017 is for custom filters */
1374
1375 #define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE               0x0080
1376 #define IAVF_AQC_ADD_CLOUD_VNK_SHIFT                    6
1377 #define IAVF_AQC_ADD_CLOUD_VNK_MASK                     0x00C0
1378 #define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4                   0
1379 #define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6                   0x0100
1380
1381 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT               9
1382 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK                0x1E00
1383 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN               0
1384 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC          1
1385 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE              2
1386 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP                  3
1387 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED            4
1388 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE           5
1389
1390 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC       0x2000
1391 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC       0x4000
1392 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP        0x8000
1393
1394         __le32  tenant_id;
1395         u8      reserved[4];
1396         __le16  queue_number;
1397 #define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT          0
1398 #define IAVF_AQC_ADD_CLOUD_QUEUE_MASK           (0x7FF << \
1399                                                  IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)
1400         u8      reserved2[14];
1401         /* response section */
1402         u8      allocation_result;
1403 #define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS       0x0
1404 #define IAVF_AQC_ADD_CLOUD_FILTER_FAIL          0xFF
1405         u8      response_reserved[7];
1406 };
1407
1408 /* iavf_aqc_add_rm_cloud_filt_elem_ext is used when
1409  * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1410  */
1411 struct iavf_aqc_add_rm_cloud_filt_elem_ext {
1412         struct iavf_aqc_add_remove_cloud_filters_element_data element;
1413         u16     general_fields[32];
1414 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0    0
1415 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1    1
1416 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2    2
1417 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0    3
1418 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1    4
1419 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2    5
1420 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0    6
1421 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1    7
1422 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2    8
1423 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0    9
1424 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1    10
1425 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2    11
1426 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0    12
1427 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1    13
1428 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2    14
1429 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0    15
1430 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1    16
1431 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2    17
1432 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3    18
1433 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4    19
1434 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5    20
1435 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6    21
1436 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7    22
1437 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0    23
1438 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1    24
1439 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2    25
1440 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3    26
1441 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4    27
1442 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5    28
1443 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6    29
1444 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7    30
1445 };
1446
1447 struct iavf_aqc_remove_cloud_filters_completion {
1448         __le16 perfect_ovlan_used;
1449         __le16 perfect_ovlan_free;
1450         __le16 vlan_used;
1451         __le16 vlan_free;
1452         __le32 addr_high;
1453         __le32 addr_low;
1454 };
1455
1456 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);
1457
1458 /* Replace filter Command 0x025F
1459  * uses the iavf_aqc_replace_cloud_filters,
1460  * and the generic indirect completion structure
1461  */
1462 struct iavf_filter_data {
1463         u8 filter_type;
1464         u8 input[3];
1465 };
1466
1467 struct iavf_aqc_replace_cloud_filters_cmd {
1468         u8      valid_flags;
1469 #define IAVF_AQC_REPLACE_L1_FILTER              0x0
1470 #define IAVF_AQC_REPLACE_CLOUD_FILTER           0x1
1471 #define IAVF_AQC_GET_CLOUD_FILTERS              0x2
1472 #define IAVF_AQC_MIRROR_CLOUD_FILTER            0x4
1473 #define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER     0x8
1474         u8      old_filter_type;
1475         u8      new_filter_type;
1476         u8      tr_bit;
1477         u8      reserved[4];
1478         __le32 addr_high;
1479         __le32 addr_low;
1480 };
1481
1482 struct iavf_aqc_replace_cloud_filters_cmd_buf {
1483         u8      data[32];
1484 /* Filter type INPUT codes*/
1485 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX    3
1486 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED      (1 << 7UL)
1487
1488 /* Field Vector offsets */
1489 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA              0
1490 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH            6
1491 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG                7
1492 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN                8
1493 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN          9
1494 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN          10
1495 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY          11
1496 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC                12
1497 /* big FLU */
1498 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA               14
1499 /* big FLU */
1500 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA              15
1501
1502 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN          37
1503         struct iavf_filter_data filters[8];
1504 };
1505
1506 /* Add Mirror Rule (indirect or direct 0x0260)
1507  * Delete Mirror Rule (indirect or direct 0x0261)
1508  * note: some rule types (4,5) do not use an external buffer.
1509  *       take care to set the flags correctly.
1510  */
1511 struct iavf_aqc_add_delete_mirror_rule {
1512         __le16 seid;
1513         __le16 rule_type;
1514 #define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT         0
1515 #define IAVF_AQC_MIRROR_RULE_TYPE_MASK          (0x7 << \
1516                                                 IAVF_AQC_MIRROR_RULE_TYPE_SHIFT)
1517 #define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1518 #define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS  2
1519 #define IAVF_AQC_MIRROR_RULE_TYPE_VLAN          3
1520 #define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS   4
1521 #define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS    5
1522         __le16 num_entries;
1523         __le16 destination;  /* VSI for add, rule id for delete */
1524         __le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1525         __le32 addr_low;
1526 };
1527
1528 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);
1529
1530 struct iavf_aqc_add_delete_mirror_rule_completion {
1531         u8      reserved[2];
1532         __le16  rule_id;  /* only used on add */
1533         __le16  mirror_rules_used;
1534         __le16  mirror_rules_free;
1535         __le32  addr_high;
1536         __le32  addr_low;
1537 };
1538
1539 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);
1540
1541 /* Dynamic Device Personalization */
1542 struct iavf_aqc_write_personalization_profile {
1543         u8      flags;
1544         u8      reserved[3];
1545         __le32  profile_track_id;
1546         __le32  addr_high;
1547         __le32  addr_low;
1548 };
1549
1550 IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);
1551
1552 struct iavf_aqc_write_ddp_resp {
1553         __le32 error_offset;
1554         __le32 error_info;
1555         __le32 addr_high;
1556         __le32 addr_low;
1557 };
1558
1559 struct iavf_aqc_get_applied_profiles {
1560         u8      flags;
1561 #define IAVF_AQC_GET_DDP_GET_CONF       0x1
1562 #define IAVF_AQC_GET_DDP_GET_RDPU_CONF  0x2
1563         u8      rsv[3];
1564         __le32  reserved;
1565         __le32  addr_high;
1566         __le32  addr_low;
1567 };
1568
1569 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);
1570
1571 /* DCB 0x03xx*/
1572
1573 /* PFC Ignore (direct 0x0301)
1574  *    the command and response use the same descriptor structure
1575  */
1576 struct iavf_aqc_pfc_ignore {
1577         u8      tc_bitmap;
1578         u8      command_flags; /* unused on response */
1579 #define IAVF_AQC_PFC_IGNORE_SET         0x80
1580 #define IAVF_AQC_PFC_IGNORE_CLEAR       0x0
1581         u8      reserved[14];
1582 };
1583
1584 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);
1585
1586 /* DCB Update (direct 0x0302) uses the iavf_aq_desc structure
1587  * with no parameters
1588  */
1589
1590 /* TX scheduler 0x04xx */
1591
1592 /* Almost all the indirect commands use
1593  * this generic struct to pass the SEID in param0
1594  */
1595 struct iavf_aqc_tx_sched_ind {
1596         __le16  vsi_seid;
1597         u8      reserved[6];
1598         __le32  addr_high;
1599         __le32  addr_low;
1600 };
1601
1602 IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);
1603
1604 /* Several commands respond with a set of queue set handles */
1605 struct iavf_aqc_qs_handles_resp {
1606         __le16 qs_handles[8];
1607 };
1608
1609 /* Configure VSI BW limits (direct 0x0400) */
1610 struct iavf_aqc_configure_vsi_bw_limit {
1611         __le16  vsi_seid;
1612         u8      reserved[2];
1613         __le16  credit;
1614         u8      reserved1[2];
1615         u8      max_credit; /* 0-3, limit = 2^max */
1616         u8      reserved2[7];
1617 };
1618
1619 IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);
1620
1621 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1622  *    responds with iavf_aqc_qs_handles_resp
1623  */
1624 struct iavf_aqc_configure_vsi_ets_sla_bw_data {
1625         u8      tc_valid_bits;
1626         u8      reserved[15];
1627         __le16  tc_bw_credits[8]; /* FW writesback QS handles here */
1628
1629         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1630         __le16  tc_bw_max[2];
1631         u8      reserved1[28];
1632 };
1633
1634 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);
1635
1636 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1637  *    responds with iavf_aqc_qs_handles_resp
1638  */
1639 struct iavf_aqc_configure_vsi_tc_bw_data {
1640         u8      tc_valid_bits;
1641         u8      reserved[3];
1642         u8      tc_bw_credits[8];
1643         u8      reserved1[4];
1644         __le16  qs_handles[8];
1645 };
1646
1647 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);
1648
1649 /* Query vsi bw configuration (indirect 0x0408) */
1650 struct iavf_aqc_query_vsi_bw_config_resp {
1651         u8      tc_valid_bits;
1652         u8      tc_suspended_bits;
1653         u8      reserved[14];
1654         __le16  qs_handles[8];
1655         u8      reserved1[4];
1656         __le16  port_bw_limit;
1657         u8      reserved2[2];
1658         u8      max_bw; /* 0-3, limit = 2^max */
1659         u8      reserved3[23];
1660 };
1661
1662 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);
1663
1664 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1665 struct iavf_aqc_query_vsi_ets_sla_config_resp {
1666         u8      tc_valid_bits;
1667         u8      reserved[3];
1668         u8      share_credits[8];
1669         __le16  credits[8];
1670
1671         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1672         __le16  tc_bw_max[2];
1673 };
1674
1675 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);
1676
1677 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1678 struct iavf_aqc_configure_switching_comp_bw_limit {
1679         __le16  seid;
1680         u8      reserved[2];
1681         __le16  credit;
1682         u8      reserved1[2];
1683         u8      max_bw; /* 0-3, limit = 2^max */
1684         u8      reserved2[7];
1685 };
1686
1687 IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);
1688
1689 /* Enable  Physical Port ETS (indirect 0x0413)
1690  * Modify  Physical Port ETS (indirect 0x0414)
1691  * Disable Physical Port ETS (indirect 0x0415)
1692  */
1693 struct iavf_aqc_configure_switching_comp_ets_data {
1694         u8      reserved[4];
1695         u8      tc_valid_bits;
1696         u8      seepage;
1697 #define IAVF_AQ_ETS_SEEPAGE_EN_MASK     0x1
1698         u8      tc_strict_priority_flags;
1699         u8      reserved1[17];
1700         u8      tc_bw_share_credits[8];
1701         u8      reserved2[96];
1702 };
1703
1704 IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);
1705
1706 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1707 struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {
1708         u8      tc_valid_bits;
1709         u8      reserved[15];
1710         __le16  tc_bw_credit[8];
1711
1712         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1713         __le16  tc_bw_max[2];
1714         u8      reserved1[28];
1715 };
1716
1717 IAVF_CHECK_STRUCT_LEN(0x40,
1718                       iavf_aqc_configure_switching_comp_ets_bw_limit_data);
1719
1720 /* Configure Switching Component Bandwidth Allocation per Tc
1721  * (indirect 0x0417)
1722  */
1723 struct iavf_aqc_configure_switching_comp_bw_config_data {
1724         u8      tc_valid_bits;
1725         u8      reserved[2];
1726         u8      absolute_credits; /* bool */
1727         u8      tc_bw_share_credits[8];
1728         u8      reserved1[20];
1729 };
1730
1731 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);
1732
1733 /* Query Switching Component Configuration (indirect 0x0418) */
1734 struct iavf_aqc_query_switching_comp_ets_config_resp {
1735         u8      tc_valid_bits;
1736         u8      reserved[35];
1737         __le16  port_bw_limit;
1738         u8      reserved1[2];
1739         u8      tc_bw_max; /* 0-3, limit = 2^max */
1740         u8      reserved2[23];
1741 };
1742
1743 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);
1744
1745 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1746 struct iavf_aqc_query_port_ets_config_resp {
1747         u8      reserved[4];
1748         u8      tc_valid_bits;
1749         u8      reserved1;
1750         u8      tc_strict_priority_bits;
1751         u8      reserved2;
1752         u8      tc_bw_share_credits[8];
1753         __le16  tc_bw_limits[8];
1754
1755         /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1756         __le16  tc_bw_max[2];
1757         u8      reserved3[32];
1758 };
1759
1760 IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);
1761
1762 /* Query Switching Component Bandwidth Allocation per Traffic Type
1763  * (indirect 0x041A)
1764  */
1765 struct iavf_aqc_query_switching_comp_bw_config_resp {
1766         u8      tc_valid_bits;
1767         u8      reserved[2];
1768         u8      absolute_credits_enable; /* bool */
1769         u8      tc_bw_share_credits[8];
1770         __le16  tc_bw_limits[8];
1771
1772         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1773         __le16  tc_bw_max[2];
1774 };
1775
1776 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);
1777
1778 /* Suspend/resume port TX traffic
1779  * (direct 0x041B and 0x041C) uses the generic SEID struct
1780  */
1781
1782 /* Configure partition BW
1783  * (indirect 0x041D)
1784  */
1785 struct iavf_aqc_configure_partition_bw_data {
1786         __le16  pf_valid_bits;
1787         u8      min_bw[16];      /* guaranteed bandwidth */
1788         u8      max_bw[16];      /* bandwidth limit */
1789 };
1790
1791 IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);
1792
1793 /* Get and set the active HMC resource profile and status.
1794  * (direct 0x0500) and (direct 0x0501)
1795  */
1796 struct iavf_aq_get_set_hmc_resource_profile {
1797         u8      pm_profile;
1798         u8      pe_vf_enabled;
1799         u8      reserved[14];
1800 };
1801
1802 IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);
1803
1804 enum iavf_aq_hmc_profile {
1805         /* IAVF_HMC_PROFILE_NO_CHANGE   = 0, reserved */
1806         IAVF_HMC_PROFILE_DEFAULT        = 1,
1807         IAVF_HMC_PROFILE_FAVOR_VF       = 2,
1808         IAVF_HMC_PROFILE_EQUAL          = 3,
1809 };
1810
1811 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1812
1813 /* set in param0 for get phy abilities to report qualified modules */
1814 #define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES    0x0001
1815 #define IAVF_AQ_PHY_REPORT_INITIAL_VALUES       0x0002
1816
1817 enum iavf_aq_phy_type {
1818         IAVF_PHY_TYPE_SGMII                     = 0x0,
1819         IAVF_PHY_TYPE_1000BASE_KX               = 0x1,
1820         IAVF_PHY_TYPE_10GBASE_KX4               = 0x2,
1821         IAVF_PHY_TYPE_10GBASE_KR                = 0x3,
1822         IAVF_PHY_TYPE_40GBASE_KR4               = 0x4,
1823         IAVF_PHY_TYPE_XAUI                      = 0x5,
1824         IAVF_PHY_TYPE_XFI                       = 0x6,
1825         IAVF_PHY_TYPE_SFI                       = 0x7,
1826         IAVF_PHY_TYPE_XLAUI                     = 0x8,
1827         IAVF_PHY_TYPE_XLPPI                     = 0x9,
1828         IAVF_PHY_TYPE_40GBASE_CR4_CU            = 0xA,
1829         IAVF_PHY_TYPE_10GBASE_CR1_CU            = 0xB,
1830         IAVF_PHY_TYPE_10GBASE_AOC               = 0xC,
1831         IAVF_PHY_TYPE_40GBASE_AOC               = 0xD,
1832         IAVF_PHY_TYPE_UNRECOGNIZED              = 0xE,
1833         IAVF_PHY_TYPE_UNSUPPORTED               = 0xF,
1834         IAVF_PHY_TYPE_100BASE_TX                = 0x11,
1835         IAVF_PHY_TYPE_1000BASE_T                = 0x12,
1836         IAVF_PHY_TYPE_10GBASE_T                 = 0x13,
1837         IAVF_PHY_TYPE_10GBASE_SR                = 0x14,
1838         IAVF_PHY_TYPE_10GBASE_LR                = 0x15,
1839         IAVF_PHY_TYPE_10GBASE_SFPP_CU           = 0x16,
1840         IAVF_PHY_TYPE_10GBASE_CR1               = 0x17,
1841         IAVF_PHY_TYPE_40GBASE_CR4               = 0x18,
1842         IAVF_PHY_TYPE_40GBASE_SR4               = 0x19,
1843         IAVF_PHY_TYPE_40GBASE_LR4               = 0x1A,
1844         IAVF_PHY_TYPE_1000BASE_SX               = 0x1B,
1845         IAVF_PHY_TYPE_1000BASE_LX               = 0x1C,
1846         IAVF_PHY_TYPE_1000BASE_T_OPTICAL        = 0x1D,
1847         IAVF_PHY_TYPE_20GBASE_KR2               = 0x1E,
1848         IAVF_PHY_TYPE_25GBASE_KR                = 0x1F,
1849         IAVF_PHY_TYPE_25GBASE_CR                = 0x20,
1850         IAVF_PHY_TYPE_25GBASE_SR                = 0x21,
1851         IAVF_PHY_TYPE_25GBASE_LR                = 0x22,
1852         IAVF_PHY_TYPE_25GBASE_AOC               = 0x23,
1853         IAVF_PHY_TYPE_25GBASE_ACC               = 0x24,
1854         IAVF_PHY_TYPE_MAX,
1855         IAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP   = 0xFD,
1856         IAVF_PHY_TYPE_EMPTY                     = 0xFE,
1857         IAVF_PHY_TYPE_DEFAULT                   = 0xFF,
1858 };
1859
1860 #define IAVF_LINK_SPEED_100MB_SHIFT     0x1
1861 #define IAVF_LINK_SPEED_1000MB_SHIFT    0x2
1862 #define IAVF_LINK_SPEED_10GB_SHIFT      0x3
1863 #define IAVF_LINK_SPEED_40GB_SHIFT      0x4
1864 #define IAVF_LINK_SPEED_20GB_SHIFT      0x5
1865 #define IAVF_LINK_SPEED_25GB_SHIFT      0x6
1866
1867 enum iavf_aq_link_speed {
1868         IAVF_LINK_SPEED_UNKNOWN = 0,
1869         IAVF_LINK_SPEED_100MB   = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
1870         IAVF_LINK_SPEED_1GB     = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
1871         IAVF_LINK_SPEED_10GB    = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
1872         IAVF_LINK_SPEED_40GB    = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
1873         IAVF_LINK_SPEED_20GB    = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
1874         IAVF_LINK_SPEED_25GB    = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
1875 };
1876
1877 struct iavf_aqc_module_desc {
1878         u8 oui[3];
1879         u8 reserved1;
1880         u8 part_number[16];
1881         u8 revision[4];
1882         u8 reserved2[8];
1883 };
1884
1885 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);
1886
1887 struct iavf_aq_get_phy_abilities_resp {
1888         __le32  phy_type;       /* bitmap using the above enum for offsets */
1889         u8      link_speed;     /* bitmap using the above enum bit patterns */
1890         u8      abilities;
1891 #define IAVF_AQ_PHY_FLAG_PAUSE_TX       0x01
1892 #define IAVF_AQ_PHY_FLAG_PAUSE_RX       0x02
1893 #define IAVF_AQ_PHY_FLAG_LOW_POWER      0x04
1894 #define IAVF_AQ_PHY_LINK_ENABLED        0x08
1895 #define IAVF_AQ_PHY_AN_ENABLED          0x10
1896 #define IAVF_AQ_PHY_FLAG_MODULE_QUAL    0x20
1897 #define IAVF_AQ_PHY_FEC_ABILITY_KR      0x40
1898 #define IAVF_AQ_PHY_FEC_ABILITY_RS      0x80
1899         __le16  eee_capability;
1900 #define IAVF_AQ_EEE_100BASE_TX          0x0002
1901 #define IAVF_AQ_EEE_1000BASE_T          0x0004
1902 #define IAVF_AQ_EEE_10GBASE_T           0x0008
1903 #define IAVF_AQ_EEE_1000BASE_KX         0x0010
1904 #define IAVF_AQ_EEE_10GBASE_KX4         0x0020
1905 #define IAVF_AQ_EEE_10GBASE_KR          0x0040
1906         __le32  eeer_val;
1907         u8      d3_lpan;
1908 #define IAVF_AQ_SET_PHY_D3_LPAN_ENA     0x01
1909         u8      phy_type_ext;
1910 #define IAVF_AQ_PHY_TYPE_EXT_25G_KR     0x01
1911 #define IAVF_AQ_PHY_TYPE_EXT_25G_CR     0x02
1912 #define IAVF_AQ_PHY_TYPE_EXT_25G_SR     0x04
1913 #define IAVF_AQ_PHY_TYPE_EXT_25G_LR     0x08
1914 #define IAVF_AQ_PHY_TYPE_EXT_25G_AOC    0x10
1915 #define IAVF_AQ_PHY_TYPE_EXT_25G_ACC    0x20
1916         u8      fec_cfg_curr_mod_ext_info;
1917 #define IAVF_AQ_ENABLE_FEC_KR           0x01
1918 #define IAVF_AQ_ENABLE_FEC_RS           0x02
1919 #define IAVF_AQ_REQUEST_FEC_KR          0x04
1920 #define IAVF_AQ_REQUEST_FEC_RS          0x08
1921 #define IAVF_AQ_ENABLE_FEC_AUTO         0x10
1922 #define IAVF_AQ_FEC
1923 #define IAVF_AQ_MODULE_TYPE_EXT_MASK    0xE0
1924 #define IAVF_AQ_MODULE_TYPE_EXT_SHIFT   5
1925
1926         u8      ext_comp_code;
1927         u8      phy_id[4];
1928         u8      module_type[3];
1929         u8      qualified_module_count;
1930 #define IAVF_AQ_PHY_MAX_QMS             16
1931         struct iavf_aqc_module_desc     qualified_module[IAVF_AQ_PHY_MAX_QMS];
1932 };
1933
1934 IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);
1935
1936 /* Set PHY Config (direct 0x0601) */
1937 struct iavf_aq_set_phy_config { /* same bits as above in all */
1938         __le32  phy_type;
1939         u8      link_speed;
1940         u8      abilities;
1941 /* bits 0-2 use the values from get_phy_abilities_resp */
1942 #define IAVF_AQ_PHY_ENABLE_LINK         0x08
1943 #define IAVF_AQ_PHY_ENABLE_AN           0x10
1944 #define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK  0x20
1945         __le16  eee_capability;
1946         __le32  eeer;
1947         u8      low_power_ctrl;
1948         u8      phy_type_ext;
1949         u8      fec_config;
1950 #define IAVF_AQ_SET_FEC_ABILITY_KR      BIT(0)
1951 #define IAVF_AQ_SET_FEC_ABILITY_RS      BIT(1)
1952 #define IAVF_AQ_SET_FEC_REQUEST_KR      BIT(2)
1953 #define IAVF_AQ_SET_FEC_REQUEST_RS      BIT(3)
1954 #define IAVF_AQ_SET_FEC_AUTO            BIT(4)
1955 #define IAVF_AQ_PHY_FEC_CONFIG_SHIFT    0x0
1956 #define IAVF_AQ_PHY_FEC_CONFIG_MASK     (0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)
1957         u8      reserved;
1958 };
1959
1960 IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);
1961
1962 /* Set MAC Config command data structure (direct 0x0603) */
1963 struct iavf_aq_set_mac_config {
1964         __le16  max_frame_size;
1965         u8      params;
1966 #define IAVF_AQ_SET_MAC_CONFIG_CRC_EN           0x04
1967 #define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK      0x78
1968 #define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT     3
1969 #define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE      0x0
1970 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX   0xF
1971 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX   0x9
1972 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX   0x8
1973 #define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX   0x7
1974 #define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX   0x6
1975 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX   0x5
1976 #define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX   0x4
1977 #define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX   0x3
1978 #define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX   0x2
1979 #define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX   0x1
1980         u8      tx_timer_priority; /* bitmap */
1981         __le16  tx_timer_value;
1982         __le16  fc_refresh_threshold;
1983         u8      reserved[8];
1984 };
1985
1986 IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);
1987
1988 /* Restart Auto-Negotiation (direct 0x605) */
1989 struct iavf_aqc_set_link_restart_an {
1990         u8      command;
1991 #define IAVF_AQ_PHY_RESTART_AN  0x02
1992 #define IAVF_AQ_PHY_LINK_ENABLE 0x04
1993         u8      reserved[15];
1994 };
1995
1996 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);
1997
1998 /* Get Link Status cmd & response data structure (direct 0x0607) */
1999 struct iavf_aqc_get_link_status {
2000         __le16  command_flags; /* only field set on command */
2001 #define IAVF_AQ_LSE_MASK                0x3
2002 #define IAVF_AQ_LSE_NOP                 0x0
2003 #define IAVF_AQ_LSE_DISABLE             0x2
2004 #define IAVF_AQ_LSE_ENABLE              0x3
2005 /* only response uses this flag */
2006 #define IAVF_AQ_LSE_IS_ENABLED          0x1
2007         u8      phy_type;    /* iavf_aq_phy_type   */
2008         u8      link_speed;  /* iavf_aq_link_speed */
2009         u8      link_info;
2010 #define IAVF_AQ_LINK_UP                 0x01    /* obsolete */
2011 #define IAVF_AQ_LINK_UP_FUNCTION        0x01
2012 #define IAVF_AQ_LINK_FAULT              0x02
2013 #define IAVF_AQ_LINK_FAULT_TX           0x04
2014 #define IAVF_AQ_LINK_FAULT_RX           0x08
2015 #define IAVF_AQ_LINK_FAULT_REMOTE       0x10
2016 #define IAVF_AQ_LINK_UP_PORT            0x20
2017 #define IAVF_AQ_MEDIA_AVAILABLE         0x40
2018 #define IAVF_AQ_SIGNAL_DETECT           0x80
2019         u8      an_info;
2020 #define IAVF_AQ_AN_COMPLETED            0x01
2021 #define IAVF_AQ_LP_AN_ABILITY           0x02
2022 #define IAVF_AQ_PD_FAULT                0x04
2023 #define IAVF_AQ_FEC_EN                  0x08
2024 #define IAVF_AQ_PHY_LOW_POWER           0x10
2025 #define IAVF_AQ_LINK_PAUSE_TX           0x20
2026 #define IAVF_AQ_LINK_PAUSE_RX           0x40
2027 #define IAVF_AQ_QUALIFIED_MODULE        0x80
2028         u8      ext_info;
2029 #define IAVF_AQ_LINK_PHY_TEMP_ALARM     0x01
2030 #define IAVF_AQ_LINK_XCESSIVE_ERRORS    0x02
2031 #define IAVF_AQ_LINK_TX_SHIFT           0x02
2032 #define IAVF_AQ_LINK_TX_MASK            (0x03 << IAVF_AQ_LINK_TX_SHIFT)
2033 #define IAVF_AQ_LINK_TX_ACTIVE          0x00
2034 #define IAVF_AQ_LINK_TX_DRAINED         0x01
2035 #define IAVF_AQ_LINK_TX_FLUSHED         0x03
2036 #define IAVF_AQ_LINK_FORCED_40G         0x10
2037 /* 25G Error Codes */
2038 #define IAVF_AQ_25G_NO_ERR              0X00
2039 #define IAVF_AQ_25G_NOT_PRESENT         0X01
2040 #define IAVF_AQ_25G_NVM_CRC_ERR         0X02
2041 #define IAVF_AQ_25G_SBUS_UCODE_ERR      0X03
2042 #define IAVF_AQ_25G_SERDES_UCODE_ERR    0X04
2043 #define IAVF_AQ_25G_NIMB_UCODE_ERR      0X05
2044         u8      loopback; /* use defines from iavf_aqc_set_lb_mode */
2045 /* Since firmware API 1.7 loopback field keeps power class info as well */
2046 #define IAVF_AQ_LOOPBACK_MASK           0x07
2047 #define IAVF_AQ_PWR_CLASS_SHIFT_LB      6
2048 #define IAVF_AQ_PWR_CLASS_MASK_LB       (0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)
2049         __le16  max_frame_size;
2050         u8      config;
2051 #define IAVF_AQ_CONFIG_FEC_KR_ENA       0x01
2052 #define IAVF_AQ_CONFIG_FEC_RS_ENA       0x02
2053 #define IAVF_AQ_CONFIG_CRC_ENA          0x04
2054 #define IAVF_AQ_CONFIG_PACING_MASK      0x78
2055         union {
2056                 struct {
2057                         u8      power_desc;
2058 #define IAVF_AQ_LINK_POWER_CLASS_1      0x00
2059 #define IAVF_AQ_LINK_POWER_CLASS_2      0x01
2060 #define IAVF_AQ_LINK_POWER_CLASS_3      0x02
2061 #define IAVF_AQ_LINK_POWER_CLASS_4      0x03
2062 #define IAVF_AQ_PWR_CLASS_MASK          0x03
2063                         u8      reserved[4];
2064                 };
2065                 struct {
2066                         u8      link_type[4];
2067                         u8      link_type_ext;
2068                 };
2069         };
2070 };
2071
2072 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);
2073
2074 /* Set event mask command (direct 0x613) */
2075 struct iavf_aqc_set_phy_int_mask {
2076         u8      reserved[8];
2077         __le16  event_mask;
2078 #define IAVF_AQ_EVENT_LINK_UPDOWN       0x0002
2079 #define IAVF_AQ_EVENT_MEDIA_NA          0x0004
2080 #define IAVF_AQ_EVENT_LINK_FAULT        0x0008
2081 #define IAVF_AQ_EVENT_PHY_TEMP_ALARM    0x0010
2082 #define IAVF_AQ_EVENT_EXCESSIVE_ERRORS  0x0020
2083 #define IAVF_AQ_EVENT_SIGNAL_DETECT     0x0040
2084 #define IAVF_AQ_EVENT_AN_COMPLETED      0x0080
2085 #define IAVF_AQ_EVENT_MODULE_QUAL_FAIL  0x0100
2086 #define IAVF_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2087         u8      reserved1[6];
2088 };
2089
2090 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);
2091
2092 /* Get Local AN advt register (direct 0x0614)
2093  * Set Local AN advt register (direct 0x0615)
2094  * Get Link Partner AN advt register (direct 0x0616)
2095  */
2096 struct iavf_aqc_an_advt_reg {
2097         __le32  local_an_reg0;
2098         __le16  local_an_reg1;
2099         u8      reserved[10];
2100 };
2101
2102 IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);
2103
2104 /* Set Loopback mode (0x0618) */
2105 struct iavf_aqc_set_lb_mode {
2106         u8      lb_level;
2107 #define IAVF_AQ_LB_NONE 0
2108 #define IAVF_AQ_LB_MAC  1
2109 #define IAVF_AQ_LB_SERDES       2
2110 #define IAVF_AQ_LB_PHY_INT      3
2111 #define IAVF_AQ_LB_PHY_EXT      4
2112 #define IAVF_AQ_LB_CPVL_PCS     5
2113 #define IAVF_AQ_LB_CPVL_EXT     6
2114 #define IAVF_AQ_LB_PHY_LOCAL    0x01
2115 #define IAVF_AQ_LB_PHY_REMOTE   0x02
2116 #define IAVF_AQ_LB_MAC_LOCAL    0x04
2117         u8      lb_type;
2118 #define IAVF_AQ_LB_LOCAL        0
2119 #define IAVF_AQ_LB_FAR  0x01
2120         u8      speed;
2121 #define IAVF_AQ_LB_SPEED_NONE   0
2122 #define IAVF_AQ_LB_SPEED_1G     1
2123 #define IAVF_AQ_LB_SPEED_10G    2
2124 #define IAVF_AQ_LB_SPEED_40G    3
2125 #define IAVF_AQ_LB_SPEED_20G    4
2126         u8      force_speed;
2127         u8      reserved[12];
2128 };
2129
2130 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);
2131
2132 /* Set PHY Debug command (0x0622) */
2133 struct iavf_aqc_set_phy_debug {
2134         u8      command_flags;
2135 #define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL        0x02
2136 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT  2
2137 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK   (0x03 << \
2138                                         IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2139 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE   0x00
2140 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD   0x01
2141 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT   0x02
2142 /* Disable link manageability on a single port */
2143 #define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW       0x10
2144 /* Disable link manageability on all ports needs both bits 4 and 5 */
2145 #define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW   0x20
2146         u8      reserved[15];
2147 };
2148
2149 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);
2150
2151 enum iavf_aq_phy_reg_type {
2152         IAVF_AQC_PHY_REG_INTERNAL       = 0x1,
2153         IAVF_AQC_PHY_REG_EXERNAL_BASET  = 0x2,
2154         IAVF_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2155 };
2156
2157 /* Run PHY Activity (0x0626) */
2158 struct iavf_aqc_run_phy_activity {
2159         __le16  activity_id;
2160         u8      flags;
2161         u8      reserved1;
2162         __le32  control;
2163         __le32  data;
2164         u8      reserved2[4];
2165 };
2166
2167 IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);
2168
2169 /* Set PHY Register command (0x0628) */
2170 /* Get PHY Register command (0x0629) */
2171 struct iavf_aqc_phy_register_access {
2172         u8      phy_interface;
2173 #define IAVF_AQ_PHY_REG_ACCESS_INTERNAL 0
2174 #define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL 1
2175 #define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE  2
2176         u8      dev_addres;
2177         u8      reserved1[2];
2178         __le32  reg_address;
2179         __le32  reg_value;
2180         u8      reserved2[4];
2181 };
2182
2183 IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);
2184
2185 /* NVM Read command (indirect 0x0701)
2186  * NVM Erase commands (direct 0x0702)
2187  * NVM Update commands (indirect 0x0703)
2188  */
2189 struct iavf_aqc_nvm_update {
2190         u8      command_flags;
2191 #define IAVF_AQ_NVM_LAST_CMD                    0x01
2192 #define IAVF_AQ_NVM_FLASH_ONLY                  0x80
2193 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT    1
2194 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK     0x03
2195 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2196 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL      0x01
2197         u8      module_pointer;
2198         __le16  length;
2199         __le32  offset;
2200         __le32  addr_high;
2201         __le32  addr_low;
2202 };
2203
2204 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);
2205
2206 /* NVM Config Read (indirect 0x0704) */
2207 struct iavf_aqc_nvm_config_read {
2208         __le16  cmd_flags;
2209 #define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK   1
2210 #define IAVF_AQ_ANVM_READ_SINGLE_FEATURE                0
2211 #define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES             1
2212         __le16  element_count;
2213         __le16  element_id;     /* Feature/field ID */
2214         __le16  element_id_msw; /* MSWord of field ID */
2215         __le32  address_high;
2216         __le32  address_low;
2217 };
2218
2219 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);
2220
2221 /* NVM Config Write (indirect 0x0705) */
2222 struct iavf_aqc_nvm_config_write {
2223         __le16  cmd_flags;
2224         __le16  element_count;
2225         u8      reserved[4];
2226         __le32  address_high;
2227         __le32  address_low;
2228 };
2229
2230 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);
2231
2232 /* Used for 0x0704 as well as for 0x0705 commands */
2233 #define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT         1
2234 #define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2235                                 (1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2236 #define IAVF_AQ_ANVM_FEATURE            0
2237 #define IAVF_AQ_ANVM_IMMEDIATE_FIELD    (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2238 struct iavf_aqc_nvm_config_data_feature {
2239         __le16 feature_id;
2240 #define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY            0x01
2241 #define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP           0x08
2242 #define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR             0x10
2243         __le16 feature_options;
2244         __le16 feature_selection;
2245 };
2246
2247 IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);
2248
2249 struct iavf_aqc_nvm_config_data_immediate_field {
2250         __le32 field_id;
2251         __le32 field_value;
2252         __le16 field_options;
2253         __le16 reserved;
2254 };
2255
2256 IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);
2257
2258 /* OEM Post Update (indirect 0x0720)
2259  * no command data struct used
2260  */
2261 struct iavf_aqc_nvm_oem_post_update {
2262 #define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA       0x01
2263         u8 sel_data;
2264         u8 reserved[7];
2265 };
2266
2267 IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);
2268
2269 struct iavf_aqc_nvm_oem_post_update_buffer {
2270         u8 str_len;
2271         u8 dev_addr;
2272         __le16 eeprom_addr;
2273         u8 data[36];
2274 };
2275
2276 IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);
2277
2278 /* Thermal Sensor (indirect 0x0721)
2279  *     read or set thermal sensor configs and values
2280  *     takes a sensor and command specific data buffer, not detailed here
2281  */
2282 struct iavf_aqc_thermal_sensor {
2283         u8 sensor_action;
2284 #define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG      0
2285 #define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG       1
2286 #define IAVF_AQ_THERMAL_SENSOR_READ_TEMP        2
2287         u8 reserved[7];
2288         __le32  addr_high;
2289         __le32  addr_low;
2290 };
2291
2292 IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);
2293
2294 /* Send to PF command (indirect 0x0801) id is only used by PF
2295  * Send to VF command (indirect 0x0802) id is only used by PF
2296  * Send to Peer PF command (indirect 0x0803)
2297  */
2298 struct iavf_aqc_pf_vf_message {
2299         __le32  id;
2300         u8      reserved[4];
2301         __le32  addr_high;
2302         __le32  addr_low;
2303 };
2304
2305 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
2306
2307 /* Alternate structure */
2308
2309 /* Direct write (direct 0x0900)
2310  * Direct read (direct 0x0902)
2311  */
2312 struct iavf_aqc_alternate_write {
2313         __le32 address0;
2314         __le32 data0;
2315         __le32 address1;
2316         __le32 data1;
2317 };
2318
2319 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);
2320
2321 /* Indirect write (indirect 0x0901)
2322  * Indirect read (indirect 0x0903)
2323  */
2324
2325 struct iavf_aqc_alternate_ind_write {
2326         __le32 address;
2327         __le32 length;
2328         __le32 addr_high;
2329         __le32 addr_low;
2330 };
2331
2332 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);
2333
2334 /* Done alternate write (direct 0x0904)
2335  * uses iavf_aq_desc
2336  */
2337 struct iavf_aqc_alternate_write_done {
2338         __le16  cmd_flags;
2339 #define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK        1
2340 #define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY      0
2341 #define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI        1
2342 #define IAVF_AQ_ALTERNATE_RESET_NEEDED          2
2343         u8      reserved[14];
2344 };
2345
2346 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);
2347
2348 /* Set OEM mode (direct 0x0905) */
2349 struct iavf_aqc_alternate_set_mode {
2350         __le32  mode;
2351 #define IAVF_AQ_ALTERNATE_MODE_NONE     0
2352 #define IAVF_AQ_ALTERNATE_MODE_OEM      1
2353         u8      reserved[12];
2354 };
2355
2356 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);
2357
2358 /* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */
2359
2360 /* async events 0x10xx */
2361
2362 /* Lan Queue Overflow Event (direct, 0x1001) */
2363 struct iavf_aqc_lan_overflow {
2364         __le32  prtdcb_rupto;
2365         __le32  otx_ctl;
2366         u8      reserved[8];
2367 };
2368
2369 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);
2370
2371 /* Get LLDP MIB (indirect 0x0A00) */
2372 struct iavf_aqc_lldp_get_mib {
2373         u8      type;
2374         u8      reserved1;
2375 #define IAVF_AQ_LLDP_MIB_TYPE_MASK              0x3
2376 #define IAVF_AQ_LLDP_MIB_LOCAL                  0x0
2377 #define IAVF_AQ_LLDP_MIB_REMOTE                 0x1
2378 #define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE       0x2
2379 #define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK           0xC
2380 #define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT          0x2
2381 #define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2382 #define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR       0x1
2383 #define IAVF_AQ_LLDP_TX_SHIFT                   0x4
2384 #define IAVF_AQ_LLDP_TX_MASK                    (0x03 << IAVF_AQ_LLDP_TX_SHIFT)
2385 /* TX pause flags use IAVF_AQ_LINK_TX_* above */
2386         __le16  local_len;
2387         __le16  remote_len;
2388         u8      reserved2[2];
2389         __le32  addr_high;
2390         __le32  addr_low;
2391 };
2392
2393 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);
2394
2395 /* Configure LLDP MIB Change Event (direct 0x0A01)
2396  * also used for the event (with type in the command field)
2397  */
2398 struct iavf_aqc_lldp_update_mib {
2399         u8      command;
2400 #define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE  0x0
2401 #define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2402         u8      reserved[7];
2403         __le32  addr_high;
2404         __le32  addr_low;
2405 };
2406
2407 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);
2408
2409 /* Add LLDP TLV (indirect 0x0A02)
2410  * Delete LLDP TLV (indirect 0x0A04)
2411  */
2412 struct iavf_aqc_lldp_add_tlv {
2413         u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2414         u8      reserved1[1];
2415         __le16  len;
2416         u8      reserved2[4];
2417         __le32  addr_high;
2418         __le32  addr_low;
2419 };
2420
2421 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);
2422
2423 /* Update LLDP TLV (indirect 0x0A03) */
2424 struct iavf_aqc_lldp_update_tlv {
2425         u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2426         u8      reserved;
2427         __le16  old_len;
2428         __le16  new_offset;
2429         __le16  new_len;
2430         __le32  addr_high;
2431         __le32  addr_low;
2432 };
2433
2434 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);
2435
2436 /* Stop LLDP (direct 0x0A05) */
2437 struct iavf_aqc_lldp_stop {
2438         u8      command;
2439 #define IAVF_AQ_LLDP_AGENT_STOP         0x0
2440 #define IAVF_AQ_LLDP_AGENT_SHUTDOWN     0x1
2441         u8      reserved[15];
2442 };
2443
2444 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);
2445
2446 /* Start LLDP (direct 0x0A06) */
2447
2448 struct iavf_aqc_lldp_start {
2449         u8      command;
2450 #define IAVF_AQ_LLDP_AGENT_START        0x1
2451         u8      reserved[15];
2452 };
2453
2454 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);
2455
2456 /* Set DCB (direct 0x0303) */
2457 struct iavf_aqc_set_dcb_parameters {
2458         u8 command;
2459 #define IAVF_AQ_DCB_SET_AGENT   0x1
2460 #define IAVF_DCB_VALID          0x1
2461         u8 valid_flags;
2462         u8 reserved[14];
2463 };
2464
2465 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);
2466
2467 /* Get CEE DCBX Oper Config (0x0A07)
2468  * uses the generic descriptor struct
2469  * returns below as indirect response
2470  */
2471
2472 #define IAVF_AQC_CEE_APP_FCOE_SHIFT     0x0
2473 #define IAVF_AQC_CEE_APP_FCOE_MASK      (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
2474 #define IAVF_AQC_CEE_APP_ISCSI_SHIFT    0x3
2475 #define IAVF_AQC_CEE_APP_ISCSI_MASK     (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
2476 #define IAVF_AQC_CEE_APP_FIP_SHIFT      0x8
2477 #define IAVF_AQC_CEE_APP_FIP_MASK       (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
2478
2479 #define IAVF_AQC_CEE_PG_STATUS_SHIFT    0x0
2480 #define IAVF_AQC_CEE_PG_STATUS_MASK     (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
2481 #define IAVF_AQC_CEE_PFC_STATUS_SHIFT   0x3
2482 #define IAVF_AQC_CEE_PFC_STATUS_MASK    (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
2483 #define IAVF_AQC_CEE_APP_STATUS_SHIFT   0x8
2484 #define IAVF_AQC_CEE_APP_STATUS_MASK    (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
2485 #define IAVF_AQC_CEE_FCOE_STATUS_SHIFT  0x8
2486 #define IAVF_AQC_CEE_FCOE_STATUS_MASK   (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
2487 #define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2488 #define IAVF_AQC_CEE_ISCSI_STATUS_MASK  (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
2489 #define IAVF_AQC_CEE_FIP_STATUS_SHIFT   0x10
2490 #define IAVF_AQC_CEE_FIP_STATUS_MASK    (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
2491
2492 /* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2493  * word boundary layout issues, which the Linux compilers silently deal
2494  * with by adding padding, making the actual struct larger than designed.
2495  * However, the FW compiler for the NIC is less lenient and complains
2496  * about the struct.  Hence, the struct defined here has an extra byte in
2497  * fields reserved3 and reserved4 to directly acknowledge that padding,
2498  * and the new length is used in the length check macro.
2499  */
2500 struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
2501         u8      reserved1;
2502         u8      oper_num_tc;
2503         u8      oper_prio_tc[4];
2504         u8      reserved2;
2505         u8      oper_tc_bw[8];
2506         u8      oper_pfc_en;
2507         u8      reserved3[2];
2508         __le16  oper_app_prio;
2509         u8      reserved4[2];
2510         __le16  tlv_status;
2511 };
2512
2513 IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
2514
2515 struct iavf_aqc_get_cee_dcb_cfg_resp {
2516         u8      oper_num_tc;
2517         u8      oper_prio_tc[4];
2518         u8      oper_tc_bw[8];
2519         u8      oper_pfc_en;
2520         __le16  oper_app_prio;
2521         __le32  tlv_status;
2522         u8      reserved[12];
2523 };
2524
2525 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
2526
2527 /*      Set Local LLDP MIB (indirect 0x0A08)
2528  *      Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2529  */
2530 struct iavf_aqc_lldp_set_local_mib {
2531 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT        0
2532 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2533                                         SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2534 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2535 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT    (1)
2536 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK     (1 << \
2537                                 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2538 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS          0x1
2539         u8      type;
2540         u8      reserved0;
2541         __le16  length;
2542         u8      reserved1[4];
2543         __le32  address_high;
2544         __le32  address_low;
2545 };
2546
2547 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_set_local_mib);
2548
2549 struct iavf_aqc_lldp_set_local_mib_resp {
2550 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK      0x01
2551         u8  status;
2552         u8  reserved[15];
2553 };
2554
2555 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_lldp_set_local_mib_resp);
2556
2557 /*      Stop/Start LLDP Agent (direct 0x0A09)
2558  *      Used for stopping/starting specific LLDP agent. e.g. DCBx
2559  */
2560 struct iavf_aqc_lldp_stop_start_specific_agent {
2561 #define IAVF_AQC_START_SPECIFIC_AGENT_SHIFT     0
2562 #define IAVF_AQC_START_SPECIFIC_AGENT_MASK \
2563                                 (1 << IAVF_AQC_START_SPECIFIC_AGENT_SHIFT)
2564         u8      command;
2565         u8      reserved[15];
2566 };
2567
2568 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop_start_specific_agent);
2569
2570 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2571 struct iavf_aqc_add_udp_tunnel {
2572         __le16  udp_port;
2573         u8      reserved0[3];
2574         u8      protocol_type;
2575 #define IAVF_AQC_TUNNEL_TYPE_VXLAN      0x00
2576 #define IAVF_AQC_TUNNEL_TYPE_NGE        0x01
2577 #define IAVF_AQC_TUNNEL_TYPE_TEREDO     0x10
2578 #define IAVF_AQC_TUNNEL_TYPE_VXLAN_GPE  0x11
2579         u8      reserved1[10];
2580 };
2581
2582 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel);
2583
2584 struct iavf_aqc_add_udp_tunnel_completion {
2585         __le16  udp_port;
2586         u8      filter_entry_index;
2587         u8      multiple_pfs;
2588 #define IAVF_AQC_SINGLE_PF              0x0
2589 #define IAVF_AQC_MULTIPLE_PFS           0x1
2590         u8      total_filters;
2591         u8      reserved[11];
2592 };
2593
2594 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel_completion);
2595
2596 /* remove UDP Tunnel command (0x0B01) */
2597 struct iavf_aqc_remove_udp_tunnel {
2598         u8      reserved[2];
2599         u8      index; /* 0 to 15 */
2600         u8      reserved2[13];
2601 };
2602
2603 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_udp_tunnel);
2604
2605 struct iavf_aqc_del_udp_tunnel_completion {
2606         __le16  udp_port;
2607         u8      index; /* 0 to 15 */
2608         u8      multiple_pfs;
2609         u8      total_filters_used;
2610         u8      reserved1[11];
2611 };
2612
2613 IAVF_CHECK_CMD_LENGTH(iavf_aqc_del_udp_tunnel_completion);
2614
2615 struct iavf_aqc_get_set_rss_key {
2616 #define IAVF_AQC_SET_RSS_KEY_VSI_VALID          (0x1 << 15)
2617 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT       0
2618 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK        (0x3FF << \
2619                                         IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2620         __le16  vsi_id;
2621         u8      reserved[6];
2622         __le32  addr_high;
2623         __le32  addr_low;
2624 };
2625
2626 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key);
2627
2628 struct iavf_aqc_get_set_rss_key_data {
2629         u8 standard_rss_key[0x28];
2630         u8 extended_hash_key[0xc];
2631 };
2632
2633 IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data);
2634
2635 struct  iavf_aqc_get_set_rss_lut {
2636 #define IAVF_AQC_SET_RSS_LUT_VSI_VALID          (0x1 << 15)
2637 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT       0
2638 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK        (0x3FF << \
2639                                         IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2640         __le16  vsi_id;
2641 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
2642 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK    (0x1 << \
2643                                         IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2644
2645 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI     0
2646 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF      1
2647         __le16  flags;
2648         u8      reserved[4];
2649         __le32  addr_high;
2650         __le32  addr_low;
2651 };
2652
2653 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
2654
2655 /* tunnel key structure 0x0B10 */
2656
2657 struct iavf_aqc_tunnel_key_structure {
2658         u8      key1_off;
2659         u8      key2_off;
2660         u8      key1_len;  /* 0 to 15 */
2661         u8      key2_len;  /* 0 to 15 */
2662         u8      flags;
2663 #define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDE     0x01
2664 /* response flags */
2665 #define IAVF_AQC_TUNNEL_KEY_STRUCT_SUCCESS      0x01
2666 #define IAVF_AQC_TUNNEL_KEY_STRUCT_MODIFIED     0x02
2667 #define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN   0x03
2668         u8      network_key_index;
2669 #define IAVF_AQC_NETWORK_KEY_INDEX_VXLAN                0x0
2670 #define IAVF_AQC_NETWORK_KEY_INDEX_NGE                  0x1
2671 #define IAVF_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP      0x2
2672 #define IAVF_AQC_NETWORK_KEY_INDEX_GRE                  0x3
2673         u8      reserved[10];
2674 };
2675
2676 IAVF_CHECK_CMD_LENGTH(iavf_aqc_tunnel_key_structure);
2677
2678 /* OEM mode commands (direct 0xFE0x) */
2679 struct iavf_aqc_oem_param_change {
2680         __le32  param_type;
2681 #define IAVF_AQ_OEM_PARAM_TYPE_PF_CTL   0
2682 #define IAVF_AQ_OEM_PARAM_TYPE_BW_CTL   1
2683 #define IAVF_AQ_OEM_PARAM_MAC           2
2684         __le32  param_value1;
2685         __le16  param_value2;
2686         u8      reserved[6];
2687 };
2688
2689 IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_param_change);
2690
2691 struct iavf_aqc_oem_state_change {
2692         __le32  state;
2693 #define IAVF_AQ_OEM_STATE_LINK_DOWN     0x0
2694 #define IAVF_AQ_OEM_STATE_LINK_UP       0x1
2695         u8      reserved[12];
2696 };
2697
2698 IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_state_change);
2699
2700 /* Initialize OCSD (0xFE02, direct) */
2701 struct iavf_aqc_opc_oem_ocsd_initialize {
2702         u8 type_status;
2703         u8 reserved1[3];
2704         __le32 ocsd_memory_block_addr_high;
2705         __le32 ocsd_memory_block_addr_low;
2706         __le32 requested_update_interval;
2707 };
2708
2709 IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocsd_initialize);
2710
2711 /* Initialize OCBB  (0xFE03, direct) */
2712 struct iavf_aqc_opc_oem_ocbb_initialize {
2713         u8 type_status;
2714         u8 reserved1[3];
2715         __le32 ocbb_memory_block_addr_high;
2716         __le32 ocbb_memory_block_addr_low;
2717         u8 reserved2[4];
2718 };
2719
2720 IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocbb_initialize);
2721
2722 /* debug commands */
2723
2724 /* get device id (0xFF00) uses the generic structure */
2725
2726 /* set test more (0xFF01, internal) */
2727
2728 struct iavf_acq_set_test_mode {
2729         u8      mode;
2730 #define IAVF_AQ_TEST_PARTIAL    0
2731 #define IAVF_AQ_TEST_FULL       1
2732 #define IAVF_AQ_TEST_NVM        2
2733         u8      reserved[3];
2734         u8      command;
2735 #define IAVF_AQ_TEST_OPEN       0
2736 #define IAVF_AQ_TEST_CLOSE      1
2737 #define IAVF_AQ_TEST_INC        2
2738         u8      reserved2[3];
2739         __le32  address_high;
2740         __le32  address_low;
2741 };
2742
2743 IAVF_CHECK_CMD_LENGTH(iavf_acq_set_test_mode);
2744
2745 /* Debug Read Register command (0xFF03)
2746  * Debug Write Register command (0xFF04)
2747  */
2748 struct iavf_aqc_debug_reg_read_write {
2749         __le32 reserved;
2750         __le32 address;
2751         __le32 value_high;
2752         __le32 value_low;
2753 };
2754
2755 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_reg_read_write);
2756
2757 /* Scatter/gather Reg Read  (indirect 0xFF05)
2758  * Scatter/gather Reg Write (indirect 0xFF06)
2759  */
2760
2761 /* iavf_aq_desc is used for the command */
2762 struct iavf_aqc_debug_reg_sg_element_data {
2763         __le32 address;
2764         __le32 value;
2765 };
2766
2767 /* Debug Modify register (direct 0xFF07) */
2768 struct iavf_aqc_debug_modify_reg {
2769         __le32 address;
2770         __le32 value;
2771         __le32 clear_mask;
2772         __le32 set_mask;
2773 };
2774
2775 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_reg);
2776
2777 /* dump internal data (0xFF08, indirect) */
2778
2779 #define IAVF_AQ_CLUSTER_ID_AUX          0
2780 #define IAVF_AQ_CLUSTER_ID_SWITCH_FLU   1
2781 #define IAVF_AQ_CLUSTER_ID_TXSCHED      2
2782 #define IAVF_AQ_CLUSTER_ID_HMC          3
2783 #define IAVF_AQ_CLUSTER_ID_MAC0         4
2784 #define IAVF_AQ_CLUSTER_ID_MAC1         5
2785 #define IAVF_AQ_CLUSTER_ID_MAC2         6
2786 #define IAVF_AQ_CLUSTER_ID_MAC3         7
2787 #define IAVF_AQ_CLUSTER_ID_DCB          8
2788 #define IAVF_AQ_CLUSTER_ID_EMP_MEM      9
2789 #define IAVF_AQ_CLUSTER_ID_PKT_BUF      10
2790 #define IAVF_AQ_CLUSTER_ID_ALTRAM       11
2791
2792 struct iavf_aqc_debug_dump_internals {
2793         u8      cluster_id;
2794         u8      table_id;
2795         __le16  data_size;
2796         __le32  idx;
2797         __le32  address_high;
2798         __le32  address_low;
2799 };
2800
2801 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_dump_internals);
2802
2803 struct iavf_aqc_debug_modify_internals {
2804         u8      cluster_id;
2805         u8      cluster_specific_params[7];
2806         __le32  address_high;
2807         __le32  address_low;
2808 };
2809
2810 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_internals);
2811
2812 #endif /* _IAVF_ADMINQ_CMD_H_ */