drivers/net/iavf/base/iavf_register.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013 - 2015 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_REGISTER_H_
   6 #define _IAVF_REGISTER_H_
   7
   8
   9 #define IAVFMSIX_PBA1(_i)          (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
  10 #define IAVFMSIX_PBA1_MAX_INDEX    19
  11 #define IAVFMSIX_PBA1_PENBIT_SHIFT 0
  12 #define IAVFMSIX_PBA1_PENBIT_MASK  IAVF_MASK(0xFFFFFFFF, IAVFMSIX_PBA1_PENBIT_SHIFT)
  13 #define IAVFMSIX_TADD1(_i)              (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
  14 #define IAVFMSIX_TADD1_MAX_INDEX        639
  15 #define IAVFMSIX_TADD1_MSIXTADD10_SHIFT 0
  16 #define IAVFMSIX_TADD1_MSIXTADD10_MASK  IAVF_MASK(0x3, IAVFMSIX_TADD1_MSIXTADD10_SHIFT)
  17 #define IAVFMSIX_TADD1_MSIXTADD_SHIFT   2
  18 #define IAVFMSIX_TADD1_MSIXTADD_MASK    IAVF_MASK(0x3FFFFFFF, IAVFMSIX_TADD1_MSIXTADD_SHIFT)
  19 #define IAVFMSIX_TMSG1(_i)            (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
  20 #define IAVFMSIX_TMSG1_MAX_INDEX      639
  21 #define IAVFMSIX_TMSG1_MSIXTMSG_SHIFT 0
  22 #define IAVFMSIX_TMSG1_MSIXTMSG_MASK  IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TMSG1_MSIXTMSG_SHIFT)
  23 #define IAVFMSIX_TUADD1(_i)             (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
  24 #define IAVFMSIX_TUADD1_MAX_INDEX       639
  25 #define IAVFMSIX_TUADD1_MSIXTUADD_SHIFT 0
  26 #define IAVFMSIX_TUADD1_MSIXTUADD_MASK  IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TUADD1_MSIXTUADD_SHIFT)
  27 #define IAVFMSIX_TVCTRL1(_i)        (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
  28 #define IAVFMSIX_TVCTRL1_MAX_INDEX  639
  29 #define IAVFMSIX_TVCTRL1_MASK_SHIFT 0
  30 #define IAVFMSIX_TVCTRL1_MASK_MASK  IAVF_MASK(0x1, IAVFMSIX_TVCTRL1_MASK_SHIFT)
  31 #define IAVF_ARQBAH1              0x00006000 /* Reset: EMPR */
  32 #define IAVF_ARQBAH1_ARQBAH_SHIFT 0
  33 #define IAVF_ARQBAH1_ARQBAH_MASK  IAVF_MASK(0xFFFFFFFF, IAVF_ARQBAH1_ARQBAH_SHIFT)
  34 #define IAVF_ARQBAL1              0x00006C00 /* Reset: EMPR */
  35 #define IAVF_ARQBAL1_ARQBAL_SHIFT 0
  36 #define IAVF_ARQBAL1_ARQBAL_MASK  IAVF_MASK(0xFFFFFFFF, IAVF_ARQBAL1_ARQBAL_SHIFT)
  37 #define IAVF_ARQH1            0x00007400 /* Reset: EMPR */
  38 #define IAVF_ARQH1_ARQH_SHIFT 0
  39 #define IAVF_ARQH1_ARQH_MASK  IAVF_MASK(0x3FF, IAVF_ARQH1_ARQH_SHIFT)
  40 #define IAVF_ARQLEN1                 0x00008000 /* Reset: EMPR */
  41 #define IAVF_ARQLEN1_ARQLEN_SHIFT    0
  42 #define IAVF_ARQLEN1_ARQLEN_MASK     IAVF_MASK(0x3FF, IAVF_ARQLEN1_ARQLEN_SHIFT)
  43 #define IAVF_ARQLEN1_ARQVFE_SHIFT    28
  44 #define IAVF_ARQLEN1_ARQVFE_MASK     IAVF_MASK(0x1, IAVF_ARQLEN1_ARQVFE_SHIFT)
  45 #define IAVF_ARQLEN1_ARQOVFL_SHIFT   29
  46 #define IAVF_ARQLEN1_ARQOVFL_MASK    IAVF_MASK(0x1, IAVF_ARQLEN1_ARQOVFL_SHIFT)
  47 #define IAVF_ARQLEN1_ARQCRIT_SHIFT   30
  48 #define IAVF_ARQLEN1_ARQCRIT_MASK    IAVF_MASK(0x1, IAVF_ARQLEN1_ARQCRIT_SHIFT)
  49 #define IAVF_ARQLEN1_ARQENABLE_SHIFT 31
  50 #define IAVF_ARQLEN1_ARQENABLE_MASK  IAVF_MASK(0x1U, IAVF_ARQLEN1_ARQENABLE_SHIFT)
  51 #define IAVF_ARQT1            0x00007000 /* Reset: EMPR */
  52 #define IAVF_ARQT1_ARQT_SHIFT 0
  53 #define IAVF_ARQT1_ARQT_MASK  IAVF_MASK(0x3FF, IAVF_ARQT1_ARQT_SHIFT)
  54 #define IAVF_ATQBAH1              0x00007800 /* Reset: EMPR */
  55 #define IAVF_ATQBAH1_ATQBAH_SHIFT 0
  56 #define IAVF_ATQBAH1_ATQBAH_MASK  IAVF_MASK(0xFFFFFFFF, IAVF_ATQBAH1_ATQBAH_SHIFT)
  57 #define IAVF_ATQBAL1              0x00007C00 /* Reset: EMPR */
  58 #define IAVF_ATQBAL1_ATQBAL_SHIFT 0
  59 #define IAVF_ATQBAL1_ATQBAL_MASK  IAVF_MASK(0xFFFFFFFF, IAVF_ATQBAL1_ATQBAL_SHIFT)
  60 #define IAVF_ATQH1            0x00006400 /* Reset: EMPR */
  61 #define IAVF_ATQH1_ATQH_SHIFT 0
  62 #define IAVF_ATQH1_ATQH_MASK  IAVF_MASK(0x3FF, IAVF_ATQH1_ATQH_SHIFT)
  63 #define IAVF_ATQLEN1                 0x00006800 /* Reset: EMPR */
  64 #define IAVF_ATQLEN1_ATQLEN_SHIFT    0
  65 #define IAVF_ATQLEN1_ATQLEN_MASK     IAVF_MASK(0x3FF, IAVF_ATQLEN1_ATQLEN_SHIFT)
  66 #define IAVF_ATQLEN1_ATQVFE_SHIFT    28
  67 #define IAVF_ATQLEN1_ATQVFE_MASK     IAVF_MASK(0x1, IAVF_ATQLEN1_ATQVFE_SHIFT)
  68 #define IAVF_ATQLEN1_ATQOVFL_SHIFT   29
  69 #define IAVF_ATQLEN1_ATQOVFL_MASK    IAVF_MASK(0x1, IAVF_ATQLEN1_ATQOVFL_SHIFT)
  70 #define IAVF_ATQLEN1_ATQCRIT_SHIFT   30
  71 #define IAVF_ATQLEN1_ATQCRIT_MASK    IAVF_MASK(0x1, IAVF_ATQLEN1_ATQCRIT_SHIFT)
  72 #define IAVF_ATQLEN1_ATQENABLE_SHIFT 31
  73 #define IAVF_ATQLEN1_ATQENABLE_MASK  IAVF_MASK(0x1U, IAVF_ATQLEN1_ATQENABLE_SHIFT)
  74 #define IAVF_ATQT1            0x00008400 /* Reset: EMPR */
  75 #define IAVF_ATQT1_ATQT_SHIFT 0
  76 #define IAVF_ATQT1_ATQT_MASK  IAVF_MASK(0x3FF, IAVF_ATQT1_ATQT_SHIFT)
  77 #define IAVFGEN_RSTAT                 0x00008800 /* Reset: VFR */
  78 #define IAVFGEN_RSTAT_VFR_STATE_SHIFT 0
  79 #define IAVFGEN_RSTAT_VFR_STATE_MASK  IAVF_MASK(0x3, IAVFGEN_RSTAT_VFR_STATE_SHIFT)
  80 #define IAVFINT_DYN_CTL01                       0x00005C00 /* Reset: VFR */
  81 #define IAVFINT_DYN_CTL01_INTENA_SHIFT          0
  82 #define IAVFINT_DYN_CTL01_INTENA_MASK           IAVF_MASK(0x1, IAVFINT_DYN_CTL01_INTENA_SHIFT)
  83 #define IAVFINT_DYN_CTL01_CLEARPBA_SHIFT        1
  84 #define IAVFINT_DYN_CTL01_CLEARPBA_MASK         IAVF_MASK(0x1, IAVFINT_DYN_CTL01_CLEARPBA_SHIFT)
  85 #define IAVFINT_DYN_CTL01_SWINT_TRIG_SHIFT      2
  86 #define IAVFINT_DYN_CTL01_SWINT_TRIG_MASK       IAVF_MASK(0x1, IAVFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
  87 #define IAVFINT_DYN_CTL01_ITR_INDX_SHIFT        3
  88 #define IAVFINT_DYN_CTL01_ITR_INDX_MASK         IAVF_MASK(0x3, IAVFINT_DYN_CTL01_ITR_INDX_SHIFT)
  89 #define IAVFINT_DYN_CTL01_INTERVAL_SHIFT        5
  90 #define IAVFINT_DYN_CTL01_INTERVAL_MASK         IAVF_MASK(0xFFF, IAVFINT_DYN_CTL01_INTERVAL_SHIFT)
  91 #define IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
  92 #define IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK  IAVF_MASK(0x1, IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
  93 #define IAVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT     25
  94 #define IAVFINT_DYN_CTL01_SW_ITR_INDX_MASK      IAVF_MASK(0x3, IAVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
  95 #define IAVFINT_DYN_CTL01_INTENA_MSK_SHIFT      31
  96 #define IAVFINT_DYN_CTL01_INTENA_MSK_MASK       IAVF_MASK(0x1, IAVFINT_DYN_CTL01_INTENA_MSK_SHIFT)
  97 #define IAVFINT_DYN_CTLN1(_INTVF)               (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
  98 #define IAVFINT_DYN_CTLN1_MAX_INDEX             15
  99 #define IAVFINT_DYN_CTLN1_INTENA_SHIFT          0
 100 #define IAVFINT_DYN_CTLN1_INTENA_MASK           IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_INTENA_SHIFT)
 101 #define IAVFINT_DYN_CTLN1_CLEARPBA_SHIFT        1
 102 #define IAVFINT_DYN_CTLN1_CLEARPBA_MASK         IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_CLEARPBA_SHIFT)
 103 #define IAVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT      2
 104 #define IAVFINT_DYN_CTLN1_SWINT_TRIG_MASK       IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
 105 #define IAVFINT_DYN_CTLN1_ITR_INDX_SHIFT        3
 106 #define IAVFINT_DYN_CTLN1_ITR_INDX_MASK         IAVF_MASK(0x3, IAVFINT_DYN_CTLN1_ITR_INDX_SHIFT)
 107 #define IAVFINT_DYN_CTLN1_INTERVAL_SHIFT        5
 108 #define IAVFINT_DYN_CTLN1_INTERVAL_MASK         IAVF_MASK(0xFFF, IAVFINT_DYN_CTLN1_INTERVAL_SHIFT)
 109 #define IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
 110 #define IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK  IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
 111 #define IAVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT     25
 112 #define IAVFINT_DYN_CTLN1_SW_ITR_INDX_MASK      IAVF_MASK(0x3, IAVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
 113 #define IAVFINT_DYN_CTLN1_INTENA_MSK_SHIFT      31
 114 #define IAVFINT_DYN_CTLN1_INTENA_MSK_MASK       IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
 115 #define IAVFINT_ICR0_ENA1                        0x00005000 /* Reset: CORER */
 116 #define IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
 117 #define IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK  IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
 118 #define IAVFINT_ICR0_ENA1_ADMINQ_SHIFT           30
 119 #define IAVFINT_ICR0_ENA1_ADMINQ_MASK            IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_ADMINQ_SHIFT)
 120 #define IAVFINT_ICR0_ENA1_RSVD_SHIFT             31
 121 #define IAVFINT_ICR0_ENA1_RSVD_MASK              IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_RSVD_SHIFT)
 122 #define IAVFINT_ICR01                        0x00004800 /* Reset: CORER */
 123 #define IAVFINT_ICR01_INTEVENT_SHIFT         0
 124 #define IAVFINT_ICR01_INTEVENT_MASK          IAVF_MASK(0x1, IAVFINT_ICR01_INTEVENT_SHIFT)
 125 #define IAVFINT_ICR01_QUEUE_0_SHIFT          1
 126 #define IAVFINT_ICR01_QUEUE_0_MASK           IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_0_SHIFT)
 127 #define IAVFINT_ICR01_QUEUE_1_SHIFT          2
 128 #define IAVFINT_ICR01_QUEUE_1_MASK           IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_1_SHIFT)
 129 #define IAVFINT_ICR01_QUEUE_2_SHIFT          3
 130 #define IAVFINT_ICR01_QUEUE_2_MASK           IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_2_SHIFT)
 131 #define IAVFINT_ICR01_QUEUE_3_SHIFT          4
 132 #define IAVFINT_ICR01_QUEUE_3_MASK           IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_3_SHIFT)
 133 #define IAVFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
 134 #define IAVFINT_ICR01_LINK_STAT_CHANGE_MASK  IAVF_MASK(0x1, IAVFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
 135 #define IAVFINT_ICR01_ADMINQ_SHIFT           30
 136 #define IAVFINT_ICR01_ADMINQ_MASK            IAVF_MASK(0x1, IAVFINT_ICR01_ADMINQ_SHIFT)
 137 #define IAVFINT_ICR01_SWINT_SHIFT            31
 138 #define IAVFINT_ICR01_SWINT_MASK             IAVF_MASK(0x1, IAVFINT_ICR01_SWINT_SHIFT)
 139 #define IAVFINT_ITR01(_i)            (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
 140 #define IAVFINT_ITR01_MAX_INDEX      2
 141 #define IAVFINT_ITR01_INTERVAL_SHIFT 0
 142 #define IAVFINT_ITR01_INTERVAL_MASK  IAVF_MASK(0xFFF, IAVFINT_ITR01_INTERVAL_SHIFT)
 143 #define IAVFINT_ITRN1(_i, _INTVF)     (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
 144 #define IAVFINT_ITRN1_MAX_INDEX      2
 145 #define IAVFINT_ITRN1_INTERVAL_SHIFT 0
 146 #define IAVFINT_ITRN1_INTERVAL_MASK  IAVF_MASK(0xFFF, IAVFINT_ITRN1_INTERVAL_SHIFT)
 147 #define IAVFINT_STAT_CTL01                      0x00005400 /* Reset: CORER */
 148 #define IAVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
 149 #define IAVFINT_STAT_CTL01_OTHER_ITR_INDX_MASK  IAVF_MASK(0x3, IAVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
 150 #define IAVF_QRX_TAIL1(_Q)        (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
 151 #define IAVF_QRX_TAIL1_MAX_INDEX  15
 152 #define IAVF_QRX_TAIL1_TAIL_SHIFT 0
 153 #define IAVF_QRX_TAIL1_TAIL_MASK  IAVF_MASK(0x1FFF, IAVF_QRX_TAIL1_TAIL_SHIFT)
 154 #define IAVF_QTX_TAIL1(_Q)        (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
 155 #define IAVF_QTX_TAIL1_MAX_INDEX  15
 156 #define IAVF_QTX_TAIL1_TAIL_SHIFT 0
 157 #define IAVF_QTX_TAIL1_TAIL_MASK  IAVF_MASK(0x1FFF, IAVF_QTX_TAIL1_TAIL_SHIFT)
 158 #define IAVFMSIX_PBA              0x00002000 /* Reset: VFLR */
 159 #define IAVFMSIX_PBA_PENBIT_SHIFT 0
 160 #define IAVFMSIX_PBA_PENBIT_MASK  IAVF_MASK(0xFFFFFFFF, IAVFMSIX_PBA_PENBIT_SHIFT)
 161 #define IAVFMSIX_TADD(_i)              (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 162 #define IAVFMSIX_TADD_MAX_INDEX        16
 163 #define IAVFMSIX_TADD_MSIXTADD10_SHIFT 0
 164 #define IAVFMSIX_TADD_MSIXTADD10_MASK  IAVF_MASK(0x3, IAVFMSIX_TADD_MSIXTADD10_SHIFT)
 165 #define IAVFMSIX_TADD_MSIXTADD_SHIFT   2
 166 #define IAVFMSIX_TADD_MSIXTADD_MASK    IAVF_MASK(0x3FFFFFFF, IAVFMSIX_TADD_MSIXTADD_SHIFT)
 167 #define IAVFMSIX_TMSG(_i)            (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 168 #define IAVFMSIX_TMSG_MAX_INDEX      16
 169 #define IAVFMSIX_TMSG_MSIXTMSG_SHIFT 0
 170 #define IAVFMSIX_TMSG_MSIXTMSG_MASK  IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TMSG_MSIXTMSG_SHIFT)
 171 #define IAVFMSIX_TUADD(_i)             (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 172 #define IAVFMSIX_TUADD_MAX_INDEX       16
 173 #define IAVFMSIX_TUADD_MSIXTUADD_SHIFT 0
 174 #define IAVFMSIX_TUADD_MSIXTUADD_MASK  IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TUADD_MSIXTUADD_SHIFT)
 175 #define IAVFMSIX_TVCTRL(_i)        (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 176 #define IAVFMSIX_TVCTRL_MAX_INDEX  16
 177 #define IAVFMSIX_TVCTRL_MASK_SHIFT 0
 178 #define IAVFMSIX_TVCTRL_MASK_MASK  IAVF_MASK(0x1, IAVFMSIX_TVCTRL_MASK_SHIFT)
 179 #define IAVFCM_PE_ERRDATA                  0x0000DC00 /* Reset: VFR */
 180 #define IAVFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
 181 #define IAVFCM_PE_ERRDATA_ERROR_CODE_MASK  IAVF_MASK(0xF, IAVFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
 182 #define IAVFCM_PE_ERRDATA_Q_TYPE_SHIFT     4
 183 #define IAVFCM_PE_ERRDATA_Q_TYPE_MASK      IAVF_MASK(0x7, IAVFCM_PE_ERRDATA_Q_TYPE_SHIFT)
 184 #define IAVFCM_PE_ERRDATA_Q_NUM_SHIFT      8
 185 #define IAVFCM_PE_ERRDATA_Q_NUM_MASK       IAVF_MASK(0x3FFFF, IAVFCM_PE_ERRDATA_Q_NUM_SHIFT)
 186 #define IAVFCM_PE_ERRINFO                     0x0000D800 /* Reset: VFR */
 187 #define IAVFCM_PE_ERRINFO_ERROR_VALID_SHIFT   0
 188 #define IAVFCM_PE_ERRINFO_ERROR_VALID_MASK    IAVF_MASK(0x1, IAVFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
 189 #define IAVFCM_PE_ERRINFO_ERROR_INST_SHIFT    4
 190 #define IAVFCM_PE_ERRINFO_ERROR_INST_MASK     IAVF_MASK(0x7, IAVFCM_PE_ERRINFO_ERROR_INST_SHIFT)
 191 #define IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
 192 #define IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK  IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
 193 #define IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
 194 #define IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK  IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
 195 #define IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
 196 #define IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK  IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
 197 #define IAVFQF_HENA(_i)             (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 198 #define IAVFQF_HENA_MAX_INDEX       1
 199 #define IAVFQF_HENA_PTYPE_ENA_SHIFT 0
 200 #define IAVFQF_HENA_PTYPE_ENA_MASK  IAVF_MASK(0xFFFFFFFF, IAVFQF_HENA_PTYPE_ENA_SHIFT)
 201 #define IAVFQF_HKEY(_i)         (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
 202 #define IAVFQF_HKEY_MAX_INDEX   12
 203 #define IAVFQF_HKEY_KEY_0_SHIFT 0
 204 #define IAVFQF_HKEY_KEY_0_MASK  IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_0_SHIFT)
 205 #define IAVFQF_HKEY_KEY_1_SHIFT 8
 206 #define IAVFQF_HKEY_KEY_1_MASK  IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_1_SHIFT)
 207 #define IAVFQF_HKEY_KEY_2_SHIFT 16
 208 #define IAVFQF_HKEY_KEY_2_MASK  IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_2_SHIFT)
 209 #define IAVFQF_HKEY_KEY_3_SHIFT 24
 210 #define IAVFQF_HKEY_KEY_3_MASK  IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_3_SHIFT)
 211 #define IAVFQF_HLUT(_i)        (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 212 #define IAVFQF_HLUT_MAX_INDEX  15
 213 #define IAVFQF_HLUT_LUT0_SHIFT 0
 214 #define IAVFQF_HLUT_LUT0_MASK  IAVF_MASK(0xF, IAVFQF_HLUT_LUT0_SHIFT)
 215 #define IAVFQF_HLUT_LUT1_SHIFT 8
 216 #define IAVFQF_HLUT_LUT1_MASK  IAVF_MASK(0xF, IAVFQF_HLUT_LUT1_SHIFT)
 217 #define IAVFQF_HLUT_LUT2_SHIFT 16
 218 #define IAVFQF_HLUT_LUT2_MASK  IAVF_MASK(0xF, IAVFQF_HLUT_LUT2_SHIFT)
 219 #define IAVFQF_HLUT_LUT3_SHIFT 24
 220 #define IAVFQF_HLUT_LUT3_MASK  IAVF_MASK(0xF, IAVFQF_HLUT_LUT3_SHIFT)
 221 #define IAVFQF_HREGION(_i)                  (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 222 #define IAVFQF_HREGION_MAX_INDEX            7
 223 #define IAVFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
 224 #define IAVFQF_HREGION_OVERRIDE_ENA_0_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
 225 #define IAVFQF_HREGION_REGION_0_SHIFT       1
 226 #define IAVFQF_HREGION_REGION_0_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_0_SHIFT)
 227 #define IAVFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
 228 #define IAVFQF_HREGION_OVERRIDE_ENA_1_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
 229 #define IAVFQF_HREGION_REGION_1_SHIFT       5
 230 #define IAVFQF_HREGION_REGION_1_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_1_SHIFT)
 231 #define IAVFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
 232 #define IAVFQF_HREGION_OVERRIDE_ENA_2_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
 233 #define IAVFQF_HREGION_REGION_2_SHIFT       9
 234 #define IAVFQF_HREGION_REGION_2_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_2_SHIFT)
 235 #define IAVFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
 236 #define IAVFQF_HREGION_OVERRIDE_ENA_3_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
 237 #define IAVFQF_HREGION_REGION_3_SHIFT       13
 238 #define IAVFQF_HREGION_REGION_3_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_3_SHIFT)
 239 #define IAVFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
 240 #define IAVFQF_HREGION_OVERRIDE_ENA_4_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
 241 #define IAVFQF_HREGION_REGION_4_SHIFT       17
 242 #define IAVFQF_HREGION_REGION_4_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_4_SHIFT)
 243 #define IAVFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
 244 #define IAVFQF_HREGION_OVERRIDE_ENA_5_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
 245 #define IAVFQF_HREGION_REGION_5_SHIFT       21
 246 #define IAVFQF_HREGION_REGION_5_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_5_SHIFT)
 247 #define IAVFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
 248 #define IAVFQF_HREGION_OVERRIDE_ENA_6_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
 249 #define IAVFQF_HREGION_REGION_6_SHIFT       25
 250 #define IAVFQF_HREGION_REGION_6_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_6_SHIFT)
 251 #define IAVFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
 252 #define IAVFQF_HREGION_OVERRIDE_ENA_7_MASK  IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
 253 #define IAVFQF_HREGION_REGION_7_SHIFT       29
 254 #define IAVFQF_HREGION_REGION_7_MASK        IAVF_MASK(0x7, IAVFQF_HREGION_REGION_7_SHIFT)
 255
 256 #define IAVFINT_DYN_CTL01_WB_ON_ITR_SHIFT       30
 257 #define IAVFINT_DYN_CTL01_WB_ON_ITR_MASK        IAVF_MASK(0x1, IAVFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
 258 #define IAVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT       30
 259 #define IAVFINT_DYN_CTLN1_WB_ON_ITR_MASK        IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
 260 #define IAVFPE_AEQALLOC1               0x0000A400 /* Reset: VFR */
 261 #define IAVFPE_AEQALLOC1_AECOUNT_SHIFT 0
 262 #define IAVFPE_AEQALLOC1_AECOUNT_MASK  IAVF_MASK(0xFFFFFFFF, IAVFPE_AEQALLOC1_AECOUNT_SHIFT)
 263 #define IAVFPE_CCQPHIGH1                  0x00009800 /* Reset: VFR */
 264 #define IAVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
 265 #define IAVFPE_CCQPHIGH1_PECCQPHIGH_MASK  IAVF_MASK(0xFFFFFFFF, IAVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
 266 #define IAVFPE_CCQPLOW1                 0x0000AC00 /* Reset: VFR */
 267 #define IAVFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
 268 #define IAVFPE_CCQPLOW1_PECCQPLOW_MASK  IAVF_MASK(0xFFFFFFFF, IAVFPE_CCQPLOW1_PECCQPLOW_SHIFT)
 269 #define IAVFPE_CCQPSTATUS1                   0x0000B800 /* Reset: VFR */
 270 #define IAVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT   0
 271 #define IAVFPE_CCQPSTATUS1_CCQP_DONE_MASK    IAVF_MASK(0x1, IAVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
 272 #define IAVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
 273 #define IAVFPE_CCQPSTATUS1_HMC_PROFILE_MASK  IAVF_MASK(0x7, IAVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
 274 #define IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
 275 #define IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK  IAVF_MASK(0x3F, IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
 276 #define IAVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT    31
 277 #define IAVFPE_CCQPSTATUS1_CCQP_ERR_MASK     IAVF_MASK(0x1, IAVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
 278 #define IAVFPE_CQACK1              0x0000B000 /* Reset: VFR */
 279 #define IAVFPE_CQACK1_PECQID_SHIFT 0
 280 #define IAVFPE_CQACK1_PECQID_MASK  IAVF_MASK(0x1FFFF, IAVFPE_CQACK1_PECQID_SHIFT)
 281 #define IAVFPE_CQARM1              0x0000B400 /* Reset: VFR */
 282 #define IAVFPE_CQARM1_PECQID_SHIFT 0
 283 #define IAVFPE_CQARM1_PECQID_MASK  IAVF_MASK(0x1FFFF, IAVFPE_CQARM1_PECQID_SHIFT)
 284 #define IAVFPE_CQPDB1              0x0000BC00 /* Reset: VFR */
 285 #define IAVFPE_CQPDB1_WQHEAD_SHIFT 0
 286 #define IAVFPE_CQPDB1_WQHEAD_MASK  IAVF_MASK(0x7FF, IAVFPE_CQPDB1_WQHEAD_SHIFT)
 287 #define IAVFPE_CQPERRCODES1                      0x00009C00 /* Reset: VFR */
 288 #define IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
 289 #define IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK  IAVF_MASK(0xFFFF, IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
 290 #define IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
 291 #define IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK  IAVF_MASK(0xFFFF, IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
 292 #define IAVFPE_CQPTAIL1                  0x0000A000 /* Reset: VFR */
 293 #define IAVFPE_CQPTAIL1_WQTAIL_SHIFT     0
 294 #define IAVFPE_CQPTAIL1_WQTAIL_MASK      IAVF_MASK(0x7FF, IAVFPE_CQPTAIL1_WQTAIL_SHIFT)
 295 #define IAVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
 296 #define IAVFPE_CQPTAIL1_CQP_OP_ERR_MASK  IAVF_MASK(0x1, IAVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
 297 #define IAVFPE_IPCONFIG01                        0x00008C00 /* Reset: VFR */
 298 #define IAVFPE_IPCONFIG01_PEIPID_SHIFT           0
 299 #define IAVFPE_IPCONFIG01_PEIPID_MASK            IAVF_MASK(0xFFFF, IAVFPE_IPCONFIG01_PEIPID_SHIFT)
 300 #define IAVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
 301 #define IAVFPE_IPCONFIG01_USEENTIREIDRANGE_MASK  IAVF_MASK(0x1, IAVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
 302 #define IAVFPE_MRTEIDXMASK1                       0x00009000 /* Reset: VFR */
 303 #define IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
 304 #define IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK  IAVF_MASK(0x1F, IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
 305 #define IAVFPE_RCVUNEXPECTEDERROR1                        0x00009400 /* Reset: VFR */
 306 #define IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
 307 #define IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK  IAVF_MASK(0xFFFFFF, IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
 308 #define IAVFPE_TCPNOWTIMER1               0x0000A800 /* Reset: VFR */
 309 #define IAVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
 310 #define IAVFPE_TCPNOWTIMER1_TCP_NOW_MASK  IAVF_MASK(0xFFFFFFFF, IAVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
 311 #define IAVFPE_WQEALLOC1                      0x0000C000 /* Reset: VFR */
 312 #define IAVFPE_WQEALLOC1_PEQPID_SHIFT         0
 313 #define IAVFPE_WQEALLOC1_PEQPID_MASK          IAVF_MASK(0x3FFFF, IAVFPE_WQEALLOC1_PEQPID_SHIFT)
 314 #define IAVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
 315 #define IAVFPE_WQEALLOC1_WQE_DESC_INDEX_MASK  IAVF_MASK(0xFFF, IAVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
 316
 317 #endif /* _IAVF_REGISTER_H_ */