drivers/net/iavf/base/iavf_type.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013 - 2015 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_TYPE_H_
   6 #define _IAVF_TYPE_H_
   7
   8 #include "iavf_status.h"
   9 #include "iavf_osdep.h"
  10 #include "iavf_register.h"
  11 #include "iavf_adminq.h"
  12 #include "iavf_devids.h"
  13
  14 #define IAVF_RXQ_CTX_DBUFF_SHIFT        7
  15
  16 #define UNREFERENCED_XPARAMETER
  17 #define UNREFERENCED_1PARAMETER(_p) (_p);
  18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  22
  23 #ifndef LINUX_MACROS
  24 #ifndef BIT
  25 #define BIT(a) (1UL << (a))
  26 #endif /* BIT */
  27 #ifndef BIT_ULL
  28 #define BIT_ULL(a) (1ULL << (a))
  29 #endif /* BIT_ULL */
  30 #endif /* LINUX_MACROS */
  31
  32 #ifndef IAVF_MASK
  33 /* IAVF_MASK is a macro used on 32 bit registers */
  34 #define IAVF_MASK(mask, shift) (mask << shift)
  35 #endif
  36
  37 #define IAVF_MAX_PF                     16
  38 #define IAVF_MAX_PF_VSI                 64
  39 #define IAVF_MAX_PF_QP                  128
  40 #define IAVF_MAX_VSI_QP                 16
  41 #define IAVF_MAX_VF_VSI                 3
  42 #define IAVF_MAX_CHAINED_RX_BUFFERS     5
  43 #define IAVF_MAX_PF_UDP_OFFLOAD_PORTS   16
  44
  45 /* something less than 1 minute */
  46 #define IAVF_HEARTBEAT_TIMEOUT          (HZ * 50)
  47
  48 /* Max default timeout in ms, */
  49 #define IAVF_MAX_NVM_TIMEOUT            18000
  50
  51 /* Max timeout in ms for the phy to respond */
  52 #define IAVF_MAX_PHY_TIMEOUT            500
  53
  54 /* Check whether address is multicast. */
  55 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  56
  57 /* Check whether an address is broadcast. */
  58 #define IAVF_IS_BROADCAST(address)      \
  59         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  60         (((u8 *)(address))[1] == ((u8)0xff)))
  61
  62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  63 #define IAVF_MS_TO_GTIME(time)          ((time) * 1000)
  64
  65 /* forward declaration */
  66 struct iavf_hw;
  67 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
  68
  69 #ifndef ETH_ALEN
  70 #define ETH_ALEN        6
  71 #endif
  72 /* Data type manipulation macros. */
  73 #define IAVF_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  74 #define IAVF_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  75
  76 #define IAVF_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  77 #define IAVF_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  78
  79 #define IAVF_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  80 #define IAVF_LO_BYTE(x)         ((u8)((x) & 0xFF))
  81
  82 /* Number of Transmit Descriptors must be a multiple of 8. */
  83 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8
  84 /* Number of Receive Descriptors must be a multiple of 32 if
  85  * the number of descriptors is greater than 32.
  86  */
  87 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32
  88
  89 #define IAVF_DESC_UNUSED(R)     \
  90         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  91         (R)->next_to_clean - (R)->next_to_use - 1)
  92
  93 /* bitfields for Tx queue mapping in QTX_CTL */
  94 #define IAVF_QTX_CTL_VF_QUEUE   0x0
  95 #define IAVF_QTX_CTL_VM_QUEUE   0x1
  96 #define IAVF_QTX_CTL_PF_QUEUE   0x2
  97
  98 /* debug masks - set these bits in hw->debug_mask to control output */
  99 enum iavf_debug_mask {
 100         IAVF_DEBUG_INIT                 = 0x00000001,
 101         IAVF_DEBUG_RELEASE              = 0x00000002,
 102
 103         IAVF_DEBUG_LINK                 = 0x00000010,
 104         IAVF_DEBUG_PHY                  = 0x00000020,
 105         IAVF_DEBUG_HMC                  = 0x00000040,
 106         IAVF_DEBUG_NVM                  = 0x00000080,
 107         IAVF_DEBUG_LAN                  = 0x00000100,
 108         IAVF_DEBUG_FLOW                 = 0x00000200,
 109         IAVF_DEBUG_DCB                  = 0x00000400,
 110         IAVF_DEBUG_DIAG                 = 0x00000800,
 111         IAVF_DEBUG_FD                   = 0x00001000,
 112         IAVF_DEBUG_PACKAGE              = 0x00002000,
 113
 114         IAVF_DEBUG_AQ_MESSAGE           = 0x01000000,
 115         IAVF_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 116         IAVF_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 117         IAVF_DEBUG_AQ_COMMAND           = 0x06000000,
 118         IAVF_DEBUG_AQ                   = 0x0F000000,
 119
 120         IAVF_DEBUG_USER                 = 0xF0000000,
 121
 122         IAVF_DEBUG_ALL                  = 0xFFFFFFFF
 123 };
 124
 125 /* PCI Bus Info */
 126 #define IAVF_PCI_LINK_STATUS            0xB2
 127 #define IAVF_PCI_LINK_WIDTH             0x3F0
 128 #define IAVF_PCI_LINK_WIDTH_1           0x10
 129 #define IAVF_PCI_LINK_WIDTH_2           0x20
 130 #define IAVF_PCI_LINK_WIDTH_4           0x40
 131 #define IAVF_PCI_LINK_WIDTH_8           0x80
 132 #define IAVF_PCI_LINK_SPEED             0xF
 133 #define IAVF_PCI_LINK_SPEED_2500        0x1
 134 #define IAVF_PCI_LINK_SPEED_5000        0x2
 135 #define IAVF_PCI_LINK_SPEED_8000        0x3
 136
 137 #define IAVF_MDIO_CLAUSE22_STCODE_MASK  IAVF_MASK(1, \
 138                                                   IAVF_GLGEN_MSCA_STCODE_SHIFT)
 139 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK    IAVF_MASK(1, \
 140                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 141 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK     IAVF_MASK(2, \
 142                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 143
 144 #define IAVF_MDIO_CLAUSE45_STCODE_MASK  IAVF_MASK(0, \
 145                                                   IAVF_GLGEN_MSCA_STCODE_SHIFT)
 146 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  IAVF_MASK(0, \
 147                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 148 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK    IAVF_MASK(1, \
 149                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 150 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    IAVF_MASK(2, \
 151                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 152 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK     IAVF_MASK(3, \
 153                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 154
 155 #define IAVF_PHY_COM_REG_PAGE                   0x1E
 156 #define IAVF_PHY_LED_LINK_MODE_MASK             0xF0
 157 #define IAVF_PHY_LED_MANUAL_ON                  0x100
 158 #define IAVF_PHY_LED_PROV_REG_1                 0xC430
 159 #define IAVF_PHY_LED_MODE_MASK                  0xFFFF
 160 #define IAVF_PHY_LED_MODE_ORIG                  0x80000000
 161
 162 /* Memory types */
 163 enum iavf_memset_type {
 164         IAVF_NONDMA_MEM = 0,
 165         IAVF_DMA_MEM
 166 };
 167
 168 /* Memcpy types */
 169 enum iavf_memcpy_type {
 170         IAVF_NONDMA_TO_NONDMA = 0,
 171         IAVF_NONDMA_TO_DMA,
 172         IAVF_DMA_TO_DMA,
 173         IAVF_DMA_TO_NONDMA
 174 };
 175
 176 /* These are structs for managing the hardware information and the operations.
 177  * The structures of function pointers are filled out at init time when we
 178  * know for sure exactly which hardware we're working with.  This gives us the
 179  * flexibility of using the same main driver code but adapting to slightly
 180  * different hardware needs as new parts are developed.  For this architecture,
 181  * the Firmware and AdminQ are intended to insulate the driver from most of the
 182  * future changes, but these structures will also do part of the job.
 183  */
 184 enum iavf_mac_type {
 185         IAVF_MAC_UNKNOWN = 0,
 186         IAVF_MAC_XL710,
 187         IAVF_MAC_VF,
 188         IAVF_MAC_X722,
 189         IAVF_MAC_X722_VF,
 190         IAVF_MAC_GENERIC,
 191 };
 192
 193 enum iavf_media_type {
 194         IAVF_MEDIA_TYPE_UNKNOWN = 0,
 195         IAVF_MEDIA_TYPE_FIBER,
 196         IAVF_MEDIA_TYPE_BASET,
 197         IAVF_MEDIA_TYPE_BACKPLANE,
 198         IAVF_MEDIA_TYPE_CX4,
 199         IAVF_MEDIA_TYPE_DA,
 200         IAVF_MEDIA_TYPE_VIRTUAL
 201 };
 202
 203 enum iavf_fc_mode {
 204         IAVF_FC_NONE = 0,
 205         IAVF_FC_RX_PAUSE,
 206         IAVF_FC_TX_PAUSE,
 207         IAVF_FC_FULL,
 208         IAVF_FC_PFC,
 209         IAVF_FC_DEFAULT
 210 };
 211
 212 enum iavf_set_fc_aq_failures {
 213         IAVF_SET_FC_AQ_FAIL_NONE = 0,
 214         IAVF_SET_FC_AQ_FAIL_GET = 1,
 215         IAVF_SET_FC_AQ_FAIL_SET = 2,
 216         IAVF_SET_FC_AQ_FAIL_UPDATE = 4,
 217         IAVF_SET_FC_AQ_FAIL_SET_UPDATE = 6
 218 };
 219
 220 enum iavf_vsi_type {
 221         IAVF_VSI_MAIN   = 0,
 222         IAVF_VSI_VMDQ1  = 1,
 223         IAVF_VSI_VMDQ2  = 2,
 224         IAVF_VSI_CTRL   = 3,
 225         IAVF_VSI_FCOE   = 4,
 226         IAVF_VSI_MIRROR = 5,
 227         IAVF_VSI_SRIOV  = 6,
 228         IAVF_VSI_FDIR   = 7,
 229         IAVF_VSI_TYPE_UNKNOWN
 230 };
 231
 232 enum iavf_queue_type {
 233         IAVF_QUEUE_TYPE_RX = 0,
 234         IAVF_QUEUE_TYPE_TX,
 235         IAVF_QUEUE_TYPE_PE_CEQ,
 236         IAVF_QUEUE_TYPE_UNKNOWN
 237 };
 238
 239 struct iavf_link_status {
 240         enum iavf_aq_phy_type phy_type;
 241         enum iavf_aq_link_speed link_speed;
 242         u8 link_info;
 243         u8 an_info;
 244         u8 req_fec_info;
 245         u8 fec_info;
 246         u8 ext_info;
 247         u8 loopback;
 248         /* is Link Status Event notification to SW enabled */
 249         bool lse_enable;
 250         u16 max_frame_size;
 251         bool crc_enable;
 252         u8 pacing;
 253         u8 requested_speeds;
 254         u8 module_type[3];
 255         /* 1st byte: module identifier */
 256 #define IAVF_MODULE_TYPE_SFP            0x03
 257 #define IAVF_MODULE_TYPE_QSFP           0x0D
 258         /* 2nd byte: ethernet compliance codes for 10/40G */
 259 #define IAVF_MODULE_TYPE_40G_ACTIVE     0x01
 260 #define IAVF_MODULE_TYPE_40G_LR4        0x02
 261 #define IAVF_MODULE_TYPE_40G_SR4        0x04
 262 #define IAVF_MODULE_TYPE_40G_CR4        0x08
 263 #define IAVF_MODULE_TYPE_10G_BASE_SR    0x10
 264 #define IAVF_MODULE_TYPE_10G_BASE_LR    0x20
 265 #define IAVF_MODULE_TYPE_10G_BASE_LRM   0x40
 266 #define IAVF_MODULE_TYPE_10G_BASE_ER    0x80
 267         /* 3rd byte: ethernet compliance codes for 1G */
 268 #define IAVF_MODULE_TYPE_1000BASE_SX    0x01
 269 #define IAVF_MODULE_TYPE_1000BASE_LX    0x02
 270 #define IAVF_MODULE_TYPE_1000BASE_CX    0x04
 271 #define IAVF_MODULE_TYPE_1000BASE_T     0x08
 272 };
 273
 274 struct iavf_phy_info {
 275         struct iavf_link_status link_info;
 276         struct iavf_link_status link_info_old;
 277         bool get_link_info;
 278         enum iavf_media_type media_type;
 279         /* all the phy types the NVM is capable of */
 280         u64 phy_types;
 281 };
 282
 283 #define IAVF_CAP_PHY_TYPE_SGMII BIT_ULL(IAVF_PHY_TYPE_SGMII)
 284 #define IAVF_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(IAVF_PHY_TYPE_1000BASE_KX)
 285 #define IAVF_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(IAVF_PHY_TYPE_10GBASE_KX4)
 286 #define IAVF_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(IAVF_PHY_TYPE_10GBASE_KR)
 287 #define IAVF_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_KR4)
 288 #define IAVF_CAP_PHY_TYPE_XAUI BIT_ULL(IAVF_PHY_TYPE_XAUI)
 289 #define IAVF_CAP_PHY_TYPE_XFI BIT_ULL(IAVF_PHY_TYPE_XFI)
 290 #define IAVF_CAP_PHY_TYPE_SFI BIT_ULL(IAVF_PHY_TYPE_SFI)
 291 #define IAVF_CAP_PHY_TYPE_XLAUI BIT_ULL(IAVF_PHY_TYPE_XLAUI)
 292 #define IAVF_CAP_PHY_TYPE_XLPPI BIT_ULL(IAVF_PHY_TYPE_XLPPI)
 293 #define IAVF_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4_CU)
 294 #define IAVF_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1_CU)
 295 #define IAVF_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_10GBASE_AOC)
 296 #define IAVF_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_40GBASE_AOC)
 297 #define IAVF_CAP_PHY_TYPE_100BASE_TX BIT_ULL(IAVF_PHY_TYPE_100BASE_TX)
 298 #define IAVF_CAP_PHY_TYPE_1000BASE_T BIT_ULL(IAVF_PHY_TYPE_1000BASE_T)
 299 #define IAVF_CAP_PHY_TYPE_10GBASE_T BIT_ULL(IAVF_PHY_TYPE_10GBASE_T)
 300 #define IAVF_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(IAVF_PHY_TYPE_10GBASE_SR)
 301 #define IAVF_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(IAVF_PHY_TYPE_10GBASE_LR)
 302 #define IAVF_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_SFPP_CU)
 303 #define IAVF_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1)
 304 #define IAVF_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4)
 305 #define IAVF_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_SR4)
 306 #define IAVF_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_LR4)
 307 #define IAVF_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(IAVF_PHY_TYPE_1000BASE_SX)
 308 #define IAVF_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(IAVF_PHY_TYPE_1000BASE_LX)
 309 #define IAVF_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 310                                 BIT_ULL(IAVF_PHY_TYPE_1000BASE_T_OPTICAL)
 311 #define IAVF_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(IAVF_PHY_TYPE_20GBASE_KR2)
 312 /*
 313  * Defining the macro IAVF_TYPE_OFFSET to implement a bit shift for some
 314  * PHY types. There is an unused bit (31) in the IAVF_CAP_PHY_TYPE_* bit
 315  * fields but no corresponding gap in the iavf_aq_phy_type enumeration. So,
 316  * a shift is needed to adjust for this with values larger than 31. The
 317  * only affected values are IAVF_PHY_TYPE_25GBASE_*.
 318  */
 319 #define IAVF_PHY_TYPE_OFFSET 1
 320 #define IAVF_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(IAVF_PHY_TYPE_25GBASE_KR + \
 321                                              IAVF_PHY_TYPE_OFFSET)
 322 #define IAVF_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(IAVF_PHY_TYPE_25GBASE_CR + \
 323                                              IAVF_PHY_TYPE_OFFSET)
 324 #define IAVF_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(IAVF_PHY_TYPE_25GBASE_SR + \
 325                                              IAVF_PHY_TYPE_OFFSET)
 326 #define IAVF_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(IAVF_PHY_TYPE_25GBASE_LR + \
 327                                              IAVF_PHY_TYPE_OFFSET)
 328 #define IAVF_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_25GBASE_AOC + \
 329                                              IAVF_PHY_TYPE_OFFSET)
 330 #define IAVF_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(IAVF_PHY_TYPE_25GBASE_ACC + \
 331                                              IAVF_PHY_TYPE_OFFSET)
 332 #define IAVF_HW_CAP_MAX_GPIO                    30
 333 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO         0
 334 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C          1
 335
 336 enum iavf_acpi_programming_method {
 337         IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 338         IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 339 };
 340
 341 #define IAVF_WOL_SUPPORT_MASK                   0x1
 342 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK       0x2
 343 #define IAVF_PROXY_SUPPORT_MASK                 0x4
 344
 345 /* Capabilities of a PF or a VF or the whole device */
 346 struct iavf_hw_capabilities {
 347         u32  switch_mode;
 348 #define IAVF_NVM_IMAGE_TYPE_EVB         0x0
 349 #define IAVF_NVM_IMAGE_TYPE_CLOUD       0x2
 350 #define IAVF_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 351
 352         u32  management_mode;
 353         u32  mng_protocols_over_mctp;
 354 #define IAVF_MNG_PROTOCOL_PLDM          0x2
 355 #define IAVF_MNG_PROTOCOL_OEM_COMMANDS  0x4
 356 #define IAVF_MNG_PROTOCOL_NCSI          0x8
 357         u32  npar_enable;
 358         u32  os2bmc;
 359         u32  valid_functions;
 360         bool sr_iov_1_1;
 361         bool vmdq;
 362         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 363         bool evb_802_1_qbh; /* Bridge Port Extension */
 364         bool dcb;
 365         bool fcoe;
 366         bool iscsi; /* Indicates iSCSI enabled */
 367         bool flex10_enable;
 368         bool flex10_capable;
 369         u32  flex10_mode;
 370 #define IAVF_FLEX10_MODE_UNKNOWN        0x0
 371 #define IAVF_FLEX10_MODE_DCC            0x1
 372 #define IAVF_FLEX10_MODE_DCI            0x2
 373
 374         u32 flex10_status;
 375 #define IAVF_FLEX10_STATUS_DCC_ERROR    0x1
 376 #define IAVF_FLEX10_STATUS_VC_MODE      0x2
 377
 378         bool sec_rev_disabled;
 379         bool update_disabled;
 380 #define IAVF_NVM_MGMT_SEC_REV_DISABLED  0x1
 381 #define IAVF_NVM_MGMT_UPDATE_DISABLED   0x2
 382
 383         bool mgmt_cem;
 384         bool ieee_1588;
 385         bool iwarp;
 386         bool fd;
 387         u32 fd_filters_guaranteed;
 388         u32 fd_filters_best_effort;
 389         bool rss;
 390         u32 rss_table_size;
 391         u32 rss_table_entry_width;
 392         bool led[IAVF_HW_CAP_MAX_GPIO];
 393         bool sdp[IAVF_HW_CAP_MAX_GPIO];
 394         u32 nvm_image_type;
 395         u32 num_flow_director_filters;
 396         u32 num_vfs;
 397         u32 vf_base_id;
 398         u32 num_vsis;
 399         u32 num_rx_qp;
 400         u32 num_tx_qp;
 401         u32 base_queue;
 402         u32 num_msix_vectors;
 403         u32 num_msix_vectors_vf;
 404         u32 led_pin_num;
 405         u32 sdp_pin_num;
 406         u32 mdio_port_num;
 407         u32 mdio_port_mode;
 408         u8 rx_buf_chain_len;
 409         u32 enabled_tcmap;
 410         u32 maxtc;
 411         u64 wr_csr_prot;
 412         bool apm_wol_support;
 413         enum iavf_acpi_programming_method acpi_prog_method;
 414         bool proxy_support;
 415 };
 416
 417 struct iavf_mac_info {
 418         enum iavf_mac_type type;
 419         u8 addr[ETH_ALEN];
 420         u8 perm_addr[ETH_ALEN];
 421         u8 san_addr[ETH_ALEN];
 422         u8 port_addr[ETH_ALEN];
 423         u16 max_fcoeq;
 424 };
 425
 426 enum iavf_aq_resources_ids {
 427         IAVF_NVM_RESOURCE_ID = 1
 428 };
 429
 430 enum iavf_aq_resource_access_type {
 431         IAVF_RESOURCE_READ = 1,
 432         IAVF_RESOURCE_WRITE
 433 };
 434
 435 struct iavf_nvm_info {
 436         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 437         u32 timeout;              /* [ms] */
 438         u16 sr_size;              /* Shadow RAM size in words */
 439         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 440         u16 version;              /* NVM package version */
 441         u32 eetrack;              /* NVM data version */
 442         u32 oem_ver;              /* OEM version info */
 443 };
 444
 445 /* definitions used in NVM update support */
 446
 447 enum iavf_nvmupd_cmd {
 448         IAVF_NVMUPD_INVALID,
 449         IAVF_NVMUPD_READ_CON,
 450         IAVF_NVMUPD_READ_SNT,
 451         IAVF_NVMUPD_READ_LCB,
 452         IAVF_NVMUPD_READ_SA,
 453         IAVF_NVMUPD_WRITE_ERA,
 454         IAVF_NVMUPD_WRITE_CON,
 455         IAVF_NVMUPD_WRITE_SNT,
 456         IAVF_NVMUPD_WRITE_LCB,
 457         IAVF_NVMUPD_WRITE_SA,
 458         IAVF_NVMUPD_CSUM_CON,
 459         IAVF_NVMUPD_CSUM_SA,
 460         IAVF_NVMUPD_CSUM_LCB,
 461         IAVF_NVMUPD_STATUS,
 462         IAVF_NVMUPD_EXEC_AQ,
 463         IAVF_NVMUPD_GET_AQ_RESULT,
 464         IAVF_NVMUPD_GET_AQ_EVENT,
 465 };
 466
 467 enum iavf_nvmupd_state {
 468         IAVF_NVMUPD_STATE_INIT,
 469         IAVF_NVMUPD_STATE_READING,
 470         IAVF_NVMUPD_STATE_WRITING,
 471         IAVF_NVMUPD_STATE_INIT_WAIT,
 472         IAVF_NVMUPD_STATE_WRITE_WAIT,
 473         IAVF_NVMUPD_STATE_ERROR
 474 };
 475
 476 /* nvm_access definition and its masks/shifts need to be accessible to
 477  * application, core driver, and shared code.  Where is the right file?
 478  */
 479 #define IAVF_NVM_READ   0xB
 480 #define IAVF_NVM_WRITE  0xC
 481
 482 #define IAVF_NVM_MOD_PNT_MASK 0xFF
 483
 484 #define IAVF_NVM_TRANS_SHIFT                    8
 485 #define IAVF_NVM_TRANS_MASK                     (0xf << IAVF_NVM_TRANS_SHIFT)
 486 #define IAVF_NVM_PRESERVATION_FLAGS_SHIFT       12
 487 #define IAVF_NVM_PRESERVATION_FLAGS_MASK \
 488                                 (0x3 << IAVF_NVM_PRESERVATION_FLAGS_SHIFT)
 489 #define IAVF_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 490 #define IAVF_NVM_PRESERVATION_FLAGS_ALL         0x02
 491 #define IAVF_NVM_CON                            0x0
 492 #define IAVF_NVM_SNT                            0x1
 493 #define IAVF_NVM_LCB                            0x2
 494 #define IAVF_NVM_SA                             (IAVF_NVM_SNT | IAVF_NVM_LCB)
 495 #define IAVF_NVM_ERA                            0x4
 496 #define IAVF_NVM_CSUM                           0x8
 497 #define IAVF_NVM_AQE                            0xe
 498 #define IAVF_NVM_EXEC                           0xf
 499
 500 #define IAVF_NVM_ADAPT_SHIFT    16
 501 #define IAVF_NVM_ADAPT_MASK     (0xffffULL << IAVF_NVM_ADAPT_SHIFT)
 502
 503 #define IAVF_NVMUPD_MAX_DATA    4096
 504 #define IAVF_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 505
 506 struct iavf_nvm_access {
 507         u32 command;
 508         u32 config;
 509         u32 offset;     /* in bytes */
 510         u32 data_size;  /* in bytes */
 511         u8 data[1];
 512 };
 513
 514 /* (Q)SFP module access definitions */
 515 #define IAVF_I2C_EEPROM_DEV_ADDR        0xA0
 516 #define IAVF_I2C_EEPROM_DEV_ADDR2       0xA2
 517 #define IAVF_MODULE_TYPE_ADDR           0x00
 518 #define IAVF_MODULE_REVISION_ADDR       0x01
 519 #define IAVF_MODULE_SFF_8472_COMP       0x5E
 520 #define IAVF_MODULE_SFF_8472_SWAP       0x5C
 521 #define IAVF_MODULE_SFF_ADDR_MODE       0x04
 522 #define IAVF_MODULE_SFF_DIAG_CAPAB      0x40
 523 #define IAVF_MODULE_TYPE_QSFP_PLUS      0x0D
 524 #define IAVF_MODULE_TYPE_QSFP28         0x11
 525 #define IAVF_MODULE_QSFP_MAX_LEN        640
 526
 527 /* PCI bus types */
 528 enum iavf_bus_type {
 529         iavf_bus_type_unknown = 0,
 530         iavf_bus_type_pci,
 531         iavf_bus_type_pcix,
 532         iavf_bus_type_pci_express,
 533         iavf_bus_type_reserved
 534 };
 535
 536 /* PCI bus speeds */
 537 enum iavf_bus_speed {
 538         iavf_bus_speed_unknown  = 0,
 539         iavf_bus_speed_33       = 33,
 540         iavf_bus_speed_66       = 66,
 541         iavf_bus_speed_100      = 100,
 542         iavf_bus_speed_120      = 120,
 543         iavf_bus_speed_133      = 133,
 544         iavf_bus_speed_2500     = 2500,
 545         iavf_bus_speed_5000     = 5000,
 546         iavf_bus_speed_8000     = 8000,
 547         iavf_bus_speed_reserved
 548 };
 549
 550 /* PCI bus widths */
 551 enum iavf_bus_width {
 552         iavf_bus_width_unknown  = 0,
 553         iavf_bus_width_pcie_x1  = 1,
 554         iavf_bus_width_pcie_x2  = 2,
 555         iavf_bus_width_pcie_x4  = 4,
 556         iavf_bus_width_pcie_x8  = 8,
 557         iavf_bus_width_32       = 32,
 558         iavf_bus_width_64       = 64,
 559         iavf_bus_width_reserved
 560 };
 561
 562 /* Bus parameters */
 563 struct iavf_bus_info {
 564         enum iavf_bus_speed speed;
 565         enum iavf_bus_width width;
 566         enum iavf_bus_type type;
 567
 568         u16 func;
 569         u16 device;
 570         u16 lan_id;
 571         u16 bus_id;
 572 };
 573
 574 /* Flow control (FC) parameters */
 575 struct iavf_fc_info {
 576         enum iavf_fc_mode current_mode; /* FC mode in effect */
 577         enum iavf_fc_mode requested_mode; /* FC mode requested by caller */
 578 };
 579
 580 #define IAVF_MAX_TRAFFIC_CLASS          8
 581 #define IAVF_MAX_USER_PRIORITY          8
 582 #define IAVF_DCBX_MAX_APPS              32
 583 #define IAVF_LLDPDU_SIZE                1500
 584 #define IAVF_TLV_STATUS_OPER            0x1
 585 #define IAVF_TLV_STATUS_SYNC            0x2
 586 #define IAVF_TLV_STATUS_ERR             0x4
 587 #define IAVF_CEE_OPER_MAX_APPS          3
 588 #define IAVF_APP_PROTOID_FCOE           0x8906
 589 #define IAVF_APP_PROTOID_ISCSI          0x0cbc
 590 #define IAVF_APP_PROTOID_FIP            0x8914
 591 #define IAVF_APP_SEL_ETHTYPE            0x1
 592 #define IAVF_APP_SEL_TCPIP              0x2
 593 #define IAVF_CEE_APP_SEL_ETHTYPE        0x0
 594 #define IAVF_CEE_APP_SEL_TCPIP          0x1
 595
 596 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 597 struct iavf_dcb_ets_config {
 598         u8 willing;
 599         u8 cbs;
 600         u8 maxtcs;
 601         u8 prioritytable[IAVF_MAX_TRAFFIC_CLASS];
 602         u8 tcbwtable[IAVF_MAX_TRAFFIC_CLASS];
 603         u8 tsatable[IAVF_MAX_TRAFFIC_CLASS];
 604 };
 605
 606 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 607 struct iavf_dcb_pfc_config {
 608         u8 willing;
 609         u8 mbc;
 610         u8 pfccap;
 611         u8 pfcenable;
 612 };
 613
 614 /* CEE or IEEE 802.1Qaz Application Priority data */
 615 struct iavf_dcb_app_priority_table {
 616         u8  priority;
 617         u8  selector;
 618         u16 protocolid;
 619 };
 620
 621 struct iavf_dcbx_config {
 622         u8  dcbx_mode;
 623 #define IAVF_DCBX_MODE_CEE      0x1
 624 #define IAVF_DCBX_MODE_IEEE     0x2
 625         u8  app_mode;
 626 #define IAVF_DCBX_APPS_NON_WILLING      0x1
 627         u32 numapps;
 628         u32 tlv_status; /* CEE mode TLV status */
 629         struct iavf_dcb_ets_config etscfg;
 630         struct iavf_dcb_ets_config etsrec;
 631         struct iavf_dcb_pfc_config pfc;
 632         struct iavf_dcb_app_priority_table app[IAVF_DCBX_MAX_APPS];
 633 };
 634
 635 /* Port hardware description */
 636 struct iavf_hw {
 637         u8 *hw_addr;
 638         void *back;
 639
 640         /* subsystem structs */
 641         struct iavf_phy_info phy;
 642         struct iavf_mac_info mac;
 643         struct iavf_bus_info bus;
 644         struct iavf_nvm_info nvm;
 645         struct iavf_fc_info fc;
 646
 647         /* pci info */
 648         u16 device_id;
 649         u16 vendor_id;
 650         u16 subsystem_device_id;
 651         u16 subsystem_vendor_id;
 652         u8 revision_id;
 653         u8 port;
 654         bool adapter_stopped;
 655
 656         /* capabilities for entire device and PCI func */
 657         struct iavf_hw_capabilities dev_caps;
 658         struct iavf_hw_capabilities func_caps;
 659
 660         /* Flow Director shared filter space */
 661         u16 fdir_shared_filter_count;
 662
 663         /* device profile info */
 664         u8  pf_id;
 665         u16 main_vsi_seid;
 666
 667         /* for multi-function MACs */
 668         u16 partition_id;
 669         u16 num_partitions;
 670         u16 num_ports;
 671
 672         /* Closest numa node to the device */
 673         u16 numa_node;
 674
 675         /* Admin Queue info */
 676         struct iavf_adminq_info aq;
 677
 678         /* state of nvm update process */
 679         enum iavf_nvmupd_state nvmupd_state;
 680         struct iavf_aq_desc nvm_wb_desc;
 681         struct iavf_aq_desc nvm_aq_event_desc;
 682         struct iavf_virt_mem nvm_buff;
 683         bool nvm_release_on_done;
 684         u16 nvm_wait_opcode;
 685
 686         /* LLDP/DCBX Status */
 687         u16 dcbx_status;
 688
 689         /* DCBX info */
 690         struct iavf_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 691         struct iavf_dcbx_config remote_dcbx_config; /* Peer Cfg */
 692         struct iavf_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 693
 694         /* WoL and proxy support */
 695         u16 num_wol_proxy_filters;
 696         u16 wol_proxy_vsi_seid;
 697
 698 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 699 #define IAVF_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 700 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 701 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 702         u64 flags;
 703
 704         /* Used in set switch config AQ command */
 705         u16 switch_tag;
 706         u16 first_tag;
 707         u16 second_tag;
 708
 709         /* debug mask */
 710         u32 debug_mask;
 711         char err_str[16];
 712 };
 713
 714 STATIC INLINE bool iavf_is_vf(struct iavf_hw *hw)
 715 {
 716         return (hw->mac.type == IAVF_MAC_VF ||
 717                 hw->mac.type == IAVF_MAC_X722_VF);
 718 }
 719
 720 struct iavf_driver_version {
 721         u8 major_version;
 722         u8 minor_version;
 723         u8 build_version;
 724         u8 subbuild_version;
 725         u8 driver_string[32];
 726 };
 727
 728 /* RX Descriptors */
 729 union iavf_16byte_rx_desc {
 730         struct {
 731                 __le64 pkt_addr; /* Packet buffer address */
 732                 __le64 hdr_addr; /* Header buffer address */
 733         } read;
 734         struct {
 735                 struct {
 736                         struct {
 737                                 union {
 738                                         __le16 mirroring_status;
 739                                         __le16 fcoe_ctx_id;
 740                                 } mirr_fcoe;
 741                                 __le16 l2tag1;
 742                         } lo_dword;
 743                         union {
 744                                 __le32 rss; /* RSS Hash */
 745                                 __le32 fd_id; /* Flow director filter id */
 746                                 __le32 fcoe_param; /* FCoE DDP Context id */
 747                         } hi_dword;
 748                 } qword0;
 749                 struct {
 750                         /* ext status/error/pktype/length */
 751                         __le64 status_error_len;
 752                 } qword1;
 753         } wb;  /* writeback */
 754 };
 755
 756 union iavf_32byte_rx_desc {
 757         struct {
 758                 __le64  pkt_addr; /* Packet buffer address */
 759                 __le64  hdr_addr; /* Header buffer address */
 760                         /* bit 0 of hdr_buffer_addr is DD bit */
 761                 __le64  rsvd1;
 762                 __le64  rsvd2;
 763         } read;
 764         struct {
 765                 struct {
 766                         struct {
 767                                 union {
 768                                         __le16 mirroring_status;
 769                                         __le16 fcoe_ctx_id;
 770                                 } mirr_fcoe;
 771                                 __le16 l2tag1;
 772                         } lo_dword;
 773                         union {
 774                                 __le32 rss; /* RSS Hash */
 775                                 __le32 fcoe_param; /* FCoE DDP Context id */
 776                                 /* Flow director filter id in case of
 777                                  * Programming status desc WB
 778                                  */
 779                                 __le32 fd_id;
 780                         } hi_dword;
 781                 } qword0;
 782                 struct {
 783                         /* status/error/pktype/length */
 784                         __le64 status_error_len;
 785                 } qword1;
 786                 struct {
 787                         __le16 ext_status; /* extended status */
 788                         __le16 rsvd;
 789                         __le16 l2tag2_1;
 790                         __le16 l2tag2_2;
 791                 } qword2;
 792                 struct {
 793                         union {
 794                                 __le32 flex_bytes_lo;
 795                                 __le32 pe_status;
 796                         } lo_dword;
 797                         union {
 798                                 __le32 flex_bytes_hi;
 799                                 __le32 fd_id;
 800                         } hi_dword;
 801                 } qword3;
 802         } wb;  /* writeback */
 803 };
 804
 805 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT        8
 806 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 807                                          IAVF_RXD_QW0_MIRROR_STATUS_SHIFT)
 808 #define IAVF_RXD_QW0_FCOEINDX_SHIFT     0
 809 #define IAVF_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 810                                          IAVF_RXD_QW0_FCOEINDX_SHIFT)
 811
 812 enum iavf_rx_desc_status_bits {
 813         /* Note: These are predefined bit offsets */
 814         IAVF_RX_DESC_STATUS_DD_SHIFT            = 0,
 815         IAVF_RX_DESC_STATUS_EOF_SHIFT           = 1,
 816         IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 817         IAVF_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 818         IAVF_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 819         IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 820         IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 821         IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 822
 823         IAVF_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 824         IAVF_RX_DESC_STATUS_FLM_SHIFT           = 11,
 825         IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 826         IAVF_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 827         IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 828         IAVF_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 829         IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 830         IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 831 };
 832
 833 #define IAVF_RXD_QW1_STATUS_SHIFT       0
 834 #define IAVF_RXD_QW1_STATUS_MASK        ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) << \
 835                                          IAVF_RXD_QW1_STATUS_SHIFT)
 836
 837 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT   IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
 838 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 839                                              IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 840
 841 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT  IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
 842 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 843
 844 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT       IAVF_RX_DESC_STATUS_UMBCAST
 845 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 846                                          IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT)
 847
 848 enum iavf_rx_desc_fltstat_values {
 849         IAVF_RX_DESC_FLTSTAT_NO_DATA    = 0,
 850         IAVF_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 851         IAVF_RX_DESC_FLTSTAT_RSV        = 2,
 852         IAVF_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 853 };
 854
 855 #define IAVF_RXD_PACKET_TYPE_UNICAST    0
 856 #define IAVF_RXD_PACKET_TYPE_MULTICAST  1
 857 #define IAVF_RXD_PACKET_TYPE_BROADCAST  2
 858 #define IAVF_RXD_PACKET_TYPE_MIRRORED   3
 859
 860 #define IAVF_RXD_QW1_ERROR_SHIFT        19
 861 #define IAVF_RXD_QW1_ERROR_MASK         (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT)
 862
 863 enum iavf_rx_desc_error_bits {
 864         /* Note: These are predefined bit offsets */
 865         IAVF_RX_DESC_ERROR_RXE_SHIFT            = 0,
 866         IAVF_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 867         IAVF_RX_DESC_ERROR_HBO_SHIFT            = 2,
 868         IAVF_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 869         IAVF_RX_DESC_ERROR_IPE_SHIFT            = 3,
 870         IAVF_RX_DESC_ERROR_L4E_SHIFT            = 4,
 871         IAVF_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 872         IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 873         IAVF_RX_DESC_ERROR_PPRS_SHIFT           = 7
 874 };
 875
 876 enum iavf_rx_desc_error_l3l4e_fcoe_masks {
 877         IAVF_RX_DESC_ERROR_L3L4E_NONE           = 0,
 878         IAVF_RX_DESC_ERROR_L3L4E_PROT           = 1,
 879         IAVF_RX_DESC_ERROR_L3L4E_FC             = 2,
 880         IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 881         IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 882 };
 883
 884 #define IAVF_RXD_QW1_PTYPE_SHIFT        30
 885 #define IAVF_RXD_QW1_PTYPE_MASK         (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT)
 886
 887 /* Packet type non-ip values */
 888 enum iavf_rx_l2_ptype {
 889         IAVF_RX_PTYPE_L2_RESERVED                       = 0,
 890         IAVF_RX_PTYPE_L2_MAC_PAY2                       = 1,
 891         IAVF_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 892         IAVF_RX_PTYPE_L2_FIP_PAY2                       = 3,
 893         IAVF_RX_PTYPE_L2_OUI_PAY2                       = 4,
 894         IAVF_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 895         IAVF_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 896         IAVF_RX_PTYPE_L2_ECP_PAY2                       = 7,
 897         IAVF_RX_PTYPE_L2_EVB_PAY2                       = 8,
 898         IAVF_RX_PTYPE_L2_QCN_PAY2                       = 9,
 899         IAVF_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 900         IAVF_RX_PTYPE_L2_ARP                            = 11,
 901         IAVF_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 902         IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 903         IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 904         IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 905         IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 906         IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 907         IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 908         IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 909         IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 910         IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 911         IAVF_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 912         IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 913         IAVF_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 914         IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 915 };
 916
 917 struct iavf_rx_ptype_decoded {
 918         u32 ptype:8;
 919         u32 known:1;
 920         u32 outer_ip:1;
 921         u32 outer_ip_ver:1;
 922         u32 outer_frag:1;
 923         u32 tunnel_type:3;
 924         u32 tunnel_end_prot:2;
 925         u32 tunnel_end_frag:1;
 926         u32 inner_prot:4;
 927         u32 payload_layer:3;
 928 };
 929
 930 enum iavf_rx_ptype_outer_ip {
 931         IAVF_RX_PTYPE_OUTER_L2  = 0,
 932         IAVF_RX_PTYPE_OUTER_IP  = 1
 933 };
 934
 935 enum iavf_rx_ptype_outer_ip_ver {
 936         IAVF_RX_PTYPE_OUTER_NONE        = 0,
 937         IAVF_RX_PTYPE_OUTER_IPV4        = 0,
 938         IAVF_RX_PTYPE_OUTER_IPV6        = 1
 939 };
 940
 941 enum iavf_rx_ptype_outer_fragmented {
 942         IAVF_RX_PTYPE_NOT_FRAG  = 0,
 943         IAVF_RX_PTYPE_FRAG      = 1
 944 };
 945
 946 enum iavf_rx_ptype_tunnel_type {
 947         IAVF_RX_PTYPE_TUNNEL_NONE               = 0,
 948         IAVF_RX_PTYPE_TUNNEL_IP_IP              = 1,
 949         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 950         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 951         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 952 };
 953
 954 enum iavf_rx_ptype_tunnel_end_prot {
 955         IAVF_RX_PTYPE_TUNNEL_END_NONE   = 0,
 956         IAVF_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 957         IAVF_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 958 };
 959
 960 enum iavf_rx_ptype_inner_prot {
 961         IAVF_RX_PTYPE_INNER_PROT_NONE           = 0,
 962         IAVF_RX_PTYPE_INNER_PROT_UDP            = 1,
 963         IAVF_RX_PTYPE_INNER_PROT_TCP            = 2,
 964         IAVF_RX_PTYPE_INNER_PROT_SCTP           = 3,
 965         IAVF_RX_PTYPE_INNER_PROT_ICMP           = 4,
 966         IAVF_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 967 };
 968
 969 enum iavf_rx_ptype_payload_layer {
 970         IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 971         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 972         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 973         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 974 };
 975
 976 #define IAVF_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 977 #define IAVF_RX_PTYPE_SHIFT             56
 978
 979 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT  38
 980 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 981                                          IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)
 982
 983 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT  52
 984 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 985                                          IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
 986
 987 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT   63
 988 #define IAVF_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
 989
 990 #define IAVF_RXD_QW1_NEXTP_SHIFT        38
 991 #define IAVF_RXD_QW1_NEXTP_MASK         (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT)
 992
 993 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT   0
 994 #define IAVF_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 995                                          IAVF_RXD_QW2_EXT_STATUS_SHIFT)
 996
 997 enum iavf_rx_desc_ext_status_bits {
 998         /* Note: These are predefined bit offsets */
 999         IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1000         IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1001         IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1002         IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1003         IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1004         IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1005         IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1006 };
1007
1008 #define IAVF_RXD_QW2_L2TAG2_SHIFT       0
1009 #define IAVF_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT)
1010
1011 #define IAVF_RXD_QW2_L2TAG3_SHIFT       16
1012 #define IAVF_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT)
1013
1014 enum iavf_rx_desc_pe_status_bits {
1015         /* Note: These are predefined bit offsets */
1016         IAVF_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1017         IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1018         IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1019         IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1020         IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1021         IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1022         IAVF_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1023         IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1024         IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1025 };
1026
1027 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1028 #define IAVF_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1029
1030 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1031 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1032                                 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1033
1034 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1035 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1036                                 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1037
1038 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1039 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1040                                 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1041
1042 enum iavf_rx_prog_status_desc_status_bits {
1043         /* Note: These are predefined bit offsets */
1044         IAVF_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1045         IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1046 };
1047
1048 enum iavf_rx_prog_status_desc_prog_id_masks {
1049         IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1050         IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1051         IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1052 };
1053
1054 enum iavf_rx_prog_status_desc_error_bits {
1055         /* Note: These are predefined bit offsets */
1056         IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1057         IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1058         IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1059         IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1060 };
1061
1062 #define IAVF_TWO_BIT_MASK       0x3
1063 #define IAVF_THREE_BIT_MASK     0x7
1064 #define IAVF_FOUR_BIT_MASK      0xF
1065 #define IAVF_EIGHTEEN_BIT_MASK  0x3FFFF
1066
1067 /* TX Descriptor */
1068 struct iavf_tx_desc {
1069         __le64 buffer_addr; /* Address of descriptor's data buf */
1070         __le64 cmd_type_offset_bsz;
1071 };
1072
1073 #define IAVF_TXD_QW1_DTYPE_SHIFT        0
1074 #define IAVF_TXD_QW1_DTYPE_MASK         (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
1075
1076 enum iavf_tx_desc_dtype_value {
1077         IAVF_TX_DESC_DTYPE_DATA         = 0x0,
1078         IAVF_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1079         IAVF_TX_DESC_DTYPE_CONTEXT      = 0x1,
1080         IAVF_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1081         IAVF_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1082         IAVF_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1083         IAVF_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1084         IAVF_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1085         IAVF_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1086         IAVF_TX_DESC_DTYPE_DESC_DONE    = 0xF
1087 };
1088
1089 #define IAVF_TXD_QW1_CMD_SHIFT  4
1090 #define IAVF_TXD_QW1_CMD_MASK   (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
1091
1092 enum iavf_tx_desc_cmd_bits {
1093         IAVF_TX_DESC_CMD_EOP                    = 0x0001,
1094         IAVF_TX_DESC_CMD_RS                     = 0x0002,
1095         IAVF_TX_DESC_CMD_ICRC                   = 0x0004,
1096         IAVF_TX_DESC_CMD_IL2TAG1                = 0x0008,
1097         IAVF_TX_DESC_CMD_DUMMY                  = 0x0010,
1098         IAVF_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1099         IAVF_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1100         IAVF_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1101         IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1102         IAVF_TX_DESC_CMD_FCOET                  = 0x0080,
1103         IAVF_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1104         IAVF_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1105         IAVF_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1106         IAVF_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1107         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1108         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1109         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1110         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1111 };
1112
1113 #define IAVF_TXD_QW1_OFFSET_SHIFT       16
1114 #define IAVF_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1115                                          IAVF_TXD_QW1_OFFSET_SHIFT)
1116
1117 enum iavf_tx_desc_length_fields {
1118         /* Note: These are predefined bit offsets */
1119         IAVF_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1120         IAVF_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1121         IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1122 };
1123
1124 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
1125 #define IAVF_TXD_QW1_IPLEN_MASK  (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
1126 #define IAVF_TXD_QW1_L4LEN_MASK  (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1127 #define IAVF_TXD_QW1_FCLEN_MASK  (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1128
1129 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT    34
1130 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1131                                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
1132
1133 #define IAVF_TXD_QW1_L2TAG1_SHIFT       48
1134 #define IAVF_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
1135
1136 /* Context descriptors */
1137 struct iavf_tx_context_desc {
1138         __le32 tunneling_params;
1139         __le16 l2tag2;
1140         __le16 rsvd;
1141         __le64 type_cmd_tso_mss;
1142 };
1143
1144 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT    0
1145 #define IAVF_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT)
1146
1147 #define IAVF_TXD_CTX_QW1_CMD_SHIFT      4
1148 #define IAVF_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
1149
1150 enum iavf_tx_ctx_desc_cmd_bits {
1151         IAVF_TX_CTX_DESC_TSO            = 0x01,
1152         IAVF_TX_CTX_DESC_TSYN           = 0x02,
1153         IAVF_TX_CTX_DESC_IL2TAG2        = 0x04,
1154         IAVF_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1155         IAVF_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1156         IAVF_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1157         IAVF_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1158         IAVF_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1159         IAVF_TX_CTX_DESC_SWPE           = 0x40
1160 };
1161
1162 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1163 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1164                                          IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
1165
1166 #define IAVF_TXD_CTX_QW1_MSS_SHIFT      50
1167 #define IAVF_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1168                                          IAVF_TXD_CTX_QW1_MSS_SHIFT)
1169
1170 #define IAVF_TXD_CTX_QW1_VSI_SHIFT      50
1171 #define IAVF_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
1172
1173 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT   0
1174 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1175                                          IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
1176
1177 enum iavf_tx_ctx_desc_eipt_offload {
1178         IAVF_TX_CTX_EXT_IP_NONE         = 0x0,
1179         IAVF_TX_CTX_EXT_IP_IPV6         = 0x1,
1180         IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1181         IAVF_TX_CTX_EXT_IP_IPV4         = 0x3
1182 };
1183
1184 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1185 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1186                                          IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1187
1188 #define IAVF_TXD_CTX_QW0_NATT_SHIFT     9
1189 #define IAVF_TXD_CTX_QW0_NATT_MASK      (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
1190
1191 #define IAVF_TXD_CTX_UDP_TUNNELING      BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
1192 #define IAVF_TXD_CTX_GRE_TUNNELING      (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
1193
1194 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1195 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1196
1197 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST       IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
1198
1199 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT   12
1200 #define IAVF_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1201                                          IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
1202
1203 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT   19
1204 #define IAVF_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1205                                          IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
1206
1207 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT   23
1208 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
1209 struct iavf_nop_desc {
1210         __le64 rsvd;
1211         __le64 dtype_cmd;
1212 };
1213
1214 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT    0
1215 #define IAVF_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT)
1216
1217 #define IAVF_TXD_NOP_QW1_CMD_SHIFT      4
1218 #define IAVF_TXD_NOP_QW1_CMD_MASK       (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT)
1219
1220 enum iavf_tx_nop_desc_cmd_bits {
1221         /* Note: These are predefined bit offsets */
1222         IAVF_TX_NOP_DESC_EOP_SHIFT      = 0,
1223         IAVF_TX_NOP_DESC_RS_SHIFT       = 1,
1224         IAVF_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1225 };
1226
1227 struct iavf_filter_program_desc {
1228         __le32 qindex_flex_ptype_vsi;
1229         __le32 rsvd;
1230         __le32 dtype_cmd_cntindex;
1231         __le32 fd_id;
1232 };
1233 #define IAVF_TXD_FLTR_QW0_QINDEX_SHIFT  0
1234 #define IAVF_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1235                                          IAVF_TXD_FLTR_QW0_QINDEX_SHIFT)
1236 #define IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1237 #define IAVF_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1238                                          IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1239 #define IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1240 #define IAVF_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1241                                          IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT)
1242
1243 /* Packet Classifier Types for filters */
1244 enum iavf_filter_pctype {
1245         /* Note: Values 0-28 are reserved for future use.
1246          * Value 29, 30, 32 are not supported on XL710 and X710.
1247          */
1248         IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1249         IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1250         IAVF_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1251         IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1252         IAVF_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1253         IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1254         IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1255         IAVF_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1256         /* Note: Values 37-38 are reserved for future use.
1257          * Value 39, 40, 42 are not supported on XL710 and X710.
1258          */
1259         IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1260         IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1261         IAVF_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1262         IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1263         IAVF_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1264         IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1265         IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1266         IAVF_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1267         /* Note: Value 47 is reserved for future use */
1268         IAVF_FILTER_PCTYPE_FCOE_OX                      = 48,
1269         IAVF_FILTER_PCTYPE_FCOE_RX                      = 49,
1270         IAVF_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1271         /* Note: Values 51-62 are reserved for future use */
1272         IAVF_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1273 };
1274
1275 enum iavf_filter_program_desc_dest {
1276         IAVF_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1277         IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1278         IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1279 };
1280
1281 enum iavf_filter_program_desc_fd_status {
1282         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1283         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1284         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1285         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1286 };
1287
1288 #define IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1289 #define IAVF_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1290                                          IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1291
1292 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT   0
1293 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)
1294
1295 #define IAVF_TXD_FLTR_QW1_CMD_SHIFT     4
1296 #define IAVF_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1297                                          IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1298
1299 #define IAVF_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1300 #define IAVF_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << IAVF_TXD_FLTR_QW1_PCMD_SHIFT)
1301
1302 enum iavf_filter_program_desc_pcmd {
1303         IAVF_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1304         IAVF_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1305 };
1306
1307 #define IAVF_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1308 #define IAVF_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << IAVF_TXD_FLTR_QW1_DEST_SHIFT)
1309
1310 #define IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1311 #define IAVF_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1312
1313 #define IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1314                                                  IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1315 #define IAVF_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1316                                           IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1317
1318 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1319                                          IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1320 #define IAVF_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
1321
1322 #define IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1323 #define IAVF_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1324                                          IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1325
1326 enum iavf_filter_type {
1327         IAVF_FLOW_DIRECTOR_FLTR = 0,
1328         IAVF_PE_QUAD_HASH_FLTR = 1,
1329         IAVF_ETHERTYPE_FLTR,
1330         IAVF_FCOE_CTX_FLTR,
1331         IAVF_MAC_VLAN_FLTR,
1332         IAVF_HASH_FLTR
1333 };
1334
1335 struct iavf_vsi_context {
1336         u16 seid;
1337         u16 uplink_seid;
1338         u16 vsi_number;
1339         u16 vsis_allocated;
1340         u16 vsis_unallocated;
1341         u16 flags;
1342         u8 pf_num;
1343         u8 vf_num;
1344         u8 connection_type;
1345         struct iavf_aqc_vsi_properties_data info;
1346 };
1347
1348 struct iavf_veb_context {
1349         u16 seid;
1350         u16 uplink_seid;
1351         u16 veb_number;
1352         u16 vebs_allocated;
1353         u16 vebs_unallocated;
1354         u16 flags;
1355         struct iavf_aqc_get_veb_parameters_completion info;
1356 };
1357
1358 /* Statistics collected by each port, VSI, VEB, and S-channel */
1359 struct iavf_eth_stats {
1360         u64 rx_bytes;                   /* gorc */
1361         u64 rx_unicast;                 /* uprc */
1362         u64 rx_multicast;               /* mprc */
1363         u64 rx_broadcast;               /* bprc */
1364         u64 rx_discards;                /* rdpc */
1365         u64 rx_unknown_protocol;        /* rupp */
1366         u64 tx_bytes;                   /* gotc */
1367         u64 tx_unicast;                 /* uptc */
1368         u64 tx_multicast;               /* mptc */
1369         u64 tx_broadcast;               /* bptc */
1370         u64 tx_discards;                /* tdpc */
1371         u64 tx_errors;                  /* tepc */
1372 };
1373
1374 /* Statistics collected per VEB per TC */
1375 struct iavf_veb_tc_stats {
1376         u64 tc_rx_packets[IAVF_MAX_TRAFFIC_CLASS];
1377         u64 tc_rx_bytes[IAVF_MAX_TRAFFIC_CLASS];
1378         u64 tc_tx_packets[IAVF_MAX_TRAFFIC_CLASS];
1379         u64 tc_tx_bytes[IAVF_MAX_TRAFFIC_CLASS];
1380 };
1381
1382 /* Statistics collected per function for FCoE */
1383 struct iavf_fcoe_stats {
1384         u64 rx_fcoe_packets;            /* fcoeprc */
1385         u64 rx_fcoe_dwords;             /* focedwrc */
1386         u64 rx_fcoe_dropped;            /* fcoerpdc */
1387         u64 tx_fcoe_packets;            /* fcoeptc */
1388         u64 tx_fcoe_dwords;             /* focedwtc */
1389         u64 fcoe_bad_fccrc;             /* fcoecrc */
1390         u64 fcoe_last_error;            /* fcoelast */
1391         u64 fcoe_ddp_count;             /* fcoeddpc */
1392 };
1393
1394 /* offset to per function FCoE statistics block */
1395 #define IAVF_FCOE_VF_STAT_OFFSET        0
1396 #define IAVF_FCOE_PF_STAT_OFFSET        128
1397 #define IAVF_FCOE_STAT_MAX              (IAVF_FCOE_PF_STAT_OFFSET + IAVF_MAX_PF)
1398
1399 /* Statistics collected by the MAC */
1400 struct iavf_hw_port_stats {
1401         /* eth stats collected by the port */
1402         struct iavf_eth_stats eth;
1403
1404         /* additional port specific stats */
1405         u64 tx_dropped_link_down;       /* tdold */
1406         u64 crc_errors;                 /* crcerrs */
1407         u64 illegal_bytes;              /* illerrc */
1408         u64 error_bytes;                /* errbc */
1409         u64 mac_local_faults;           /* mlfc */
1410         u64 mac_remote_faults;          /* mrfc */
1411         u64 rx_length_errors;           /* rlec */
1412         u64 link_xon_rx;                /* lxonrxc */
1413         u64 link_xoff_rx;               /* lxoffrxc */
1414         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1415         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1416         u64 link_xon_tx;                /* lxontxc */
1417         u64 link_xoff_tx;               /* lxofftxc */
1418         u64 priority_xon_tx[8];         /* pxontxc[8] */
1419         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1420         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1421         u64 rx_size_64;                 /* prc64 */
1422         u64 rx_size_127;                /* prc127 */
1423         u64 rx_size_255;                /* prc255 */
1424         u64 rx_size_511;                /* prc511 */
1425         u64 rx_size_1023;               /* prc1023 */
1426         u64 rx_size_1522;               /* prc1522 */
1427         u64 rx_size_big;                /* prc9522 */
1428         u64 rx_undersize;               /* ruc */
1429         u64 rx_fragments;               /* rfc */
1430         u64 rx_oversize;                /* roc */
1431         u64 rx_jabber;                  /* rjc */
1432         u64 tx_size_64;                 /* ptc64 */
1433         u64 tx_size_127;                /* ptc127 */
1434         u64 tx_size_255;                /* ptc255 */
1435         u64 tx_size_511;                /* ptc511 */
1436         u64 tx_size_1023;               /* ptc1023 */
1437         u64 tx_size_1522;               /* ptc1522 */
1438         u64 tx_size_big;                /* ptc9522 */
1439         u64 mac_short_packet_dropped;   /* mspdc */
1440         u64 checksum_error;             /* xec */
1441         /* flow director stats */
1442         u64 fd_atr_match;
1443         u64 fd_sb_match;
1444         u64 fd_atr_tunnel_match;
1445         u32 fd_atr_status;
1446         u32 fd_sb_status;
1447         /* EEE LPI */
1448         u32 tx_lpi_status;
1449         u32 rx_lpi_status;
1450         u64 tx_lpi_count;               /* etlpic */
1451         u64 rx_lpi_count;               /* erlpic */
1452 };
1453
1454 /* Checksum and Shadow RAM pointers */
1455 #define IAVF_SR_NVM_CONTROL_WORD                0x00
1456 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1457 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR           0x04
1458 #define IAVF_SR_OPTION_ROM_PTR                  0x05
1459 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1460 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1461 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1462 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR           0x09
1463 #define IAVF_SR_RO_PCIE_LCB_PTR                 0x0A
1464 #define IAVF_SR_EMP_IMAGE_PTR                   0x0B
1465 #define IAVF_SR_PE_IMAGE_PTR                    0x0C
1466 #define IAVF_SR_CSR_PROTECTED_LIST_PTR          0x0D
1467 #define IAVF_SR_MNG_CONFIG_PTR                  0x0E
1468 #define IAVF_EMP_MODULE_PTR                     0x0F
1469 #define IAVF_SR_EMP_MODULE_PTR                  0x48
1470 #define IAVF_SR_PBA_FLAGS                       0x15
1471 #define IAVF_SR_PBA_BLOCK_PTR                   0x16
1472 #define IAVF_SR_BOOT_CONFIG_PTR                 0x17
1473 #define IAVF_NVM_OEM_VER_OFF                    0x83
1474 #define IAVF_SR_NVM_DEV_STARTER_VERSION         0x18
1475 #define IAVF_SR_NVM_WAKE_ON_LAN                 0x19
1476 #define IAVF_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1477 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1478 #define IAVF_SR_NVM_MAP_VERSION                 0x29
1479 #define IAVF_SR_NVM_IMAGE_VERSION               0x2A
1480 #define IAVF_SR_NVM_STRUCTURE_VERSION           0x2B
1481 #define IAVF_SR_NVM_EETRACK_LO                  0x2D
1482 #define IAVF_SR_NVM_EETRACK_HI                  0x2E
1483 #define IAVF_SR_VPD_PTR                         0x2F
1484 #define IAVF_SR_PXE_SETUP_PTR                   0x30
1485 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1486 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1487 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1488 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1489 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1490 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1491 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1492 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1493 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1494 #define IAVF_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1495 #define IAVF_SR_SW_CHECKSUM_WORD                0x3F
1496 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1497 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1498 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1499 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1500 #define IAVF_SR_EMP_SR_SETTINGS_PTR             0x48
1501 #define IAVF_SR_FEATURE_CONFIGURATION_PTR       0x49
1502 #define IAVF_SR_CONFIGURATION_METADATA_PTR      0x4D
1503 #define IAVF_SR_IMMEDIATE_VALUES_PTR            0x4E
1504
1505 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1506 #define IAVF_SR_VPD_MODULE_MAX_SIZE             1024
1507 #define IAVF_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1508 #define IAVF_SR_CONTROL_WORD_1_SHIFT            0x06
1509 #define IAVF_SR_CONTROL_WORD_1_MASK     (0x03 << IAVF_SR_CONTROL_WORD_1_SHIFT)
1510 #define IAVF_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1511 #define IAVF_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1512 #define IAVF_PTR_TYPE                           BIT(15)
1513
1514 /* Shadow RAM related */
1515 #define IAVF_SR_SECTOR_SIZE_IN_WORDS    0x800
1516 #define IAVF_SR_BUF_ALIGNMENT           4096
1517 #define IAVF_SR_WORDS_IN_1KB            512
1518 /* Checksum should be calculated such that after adding all the words,
1519  * including the checksum word itself, the sum should be 0xBABA.
1520  */
1521 #define IAVF_SR_SW_CHECKSUM_BASE        0xBABA
1522
1523 #define IAVF_SRRD_SRCTL_ATTEMPTS        100000
1524
1525 /* FCoE Tx context descriptor - Use the iavf_tx_context_desc struct */
1526
1527 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1528         IAVF_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1529         IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1530         IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1531         IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1532         IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1533         IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1534         IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1535         IAVF_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1536         IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1537         IAVF_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1538         IAVF_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1539         IAVF_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1540         IAVF_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1541 };
1542
1543 /* FCoE DIF/DIX Context descriptor */
1544 struct iavf_fcoe_difdix_context_desc {
1545         __le64 flags_buff0_buff1_ref;
1546         __le64 difapp_msk_bias;
1547 };
1548
1549 #define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1550 #define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1551                                         IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1552
1553 enum iavf_fcoe_difdix_ctx_desc_flags_bits {
1554         /* 2 BITS */
1555         IAVF_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1556         /* 1 BIT  */
1557         IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1558         /* 1 BIT  */
1559         IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1560         /* 2 BITS */
1561         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1562         /* 2 BITS */
1563         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1564         /* 2 BITS */
1565         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1566         /* 2 BITS */
1567         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1568         /* 2 BITS */
1569         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1570         /* 2 BITS */
1571         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1572         /* 2 BITS */
1573         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1574         /* 2 BITS */
1575         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1576         /* 1 BIT  */
1577         IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1578         /* 1 BIT  */
1579         IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1580         /* 2 BITS */
1581         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1582         /* 2 BITS */
1583         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1584         /* 2 BITS */
1585         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1586         /* 2 BITS */
1587         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1588         /* 1 BIT  */
1589         IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1590         /* 1 BIT  */
1591         IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1592         /* 1 BIT */
1593         IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1594         /* 1 BIT */
1595         IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1596 };
1597
1598 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1599 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1600                                         IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1601
1602 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1603 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1604                                         IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1605
1606 #define IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1607 #define IAVF_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1608                                         IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1609
1610 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1611 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1612                                         IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1613
1614 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1615 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1616                                         IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1617
1618 #define IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1619 #define IAVF_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1620                                         IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1621
1622 /* FCoE DIF/DIX Buffers descriptor */
1623 struct iavf_fcoe_difdix_buffers_desc {
1624         __le64 buff_addr0;
1625         __le64 buff_addr1;
1626 };
1627
1628 /* FCoE DDP Context descriptor */
1629 struct iavf_fcoe_ddp_context_desc {
1630         __le64 rsvd;
1631         __le64 type_cmd_foff_lsize;
1632 };
1633
1634 #define IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1635 #define IAVF_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1636                                         IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1637
1638 #define IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1639 #define IAVF_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1640                                          IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1641
1642 enum iavf_fcoe_ddp_ctx_desc_cmd_bits {
1643         IAVF_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1644         IAVF_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1645         IAVF_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1646         IAVF_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1647         IAVF_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1648         IAVF_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1649 };
1650
1651 #define IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1652 #define IAVF_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1653                                          IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1654
1655 #define IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1656 #define IAVF_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1657                                         IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1658
1659 /* FCoE DDP/DWO Queue Context descriptor */
1660 struct iavf_fcoe_queue_context_desc {
1661         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1662         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1663 };
1664
1665 #define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1666 #define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1667                                         IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1668
1669 #define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1670 #define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1671                                         IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1672
1673 #define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1674 #define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1675                                         IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1676
1677 #define IAVF_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1678 #define IAVF_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1679                                         IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1680
1681 enum iavf_fcoe_queue_ctx_desc_tph_bits {
1682         IAVF_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1683         IAVF_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1684 };
1685
1686 #define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1687 #define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1688                                         IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1689
1690 /* FCoE DDP/DWO Filter Context descriptor */
1691 struct iavf_fcoe_filter_context_desc {
1692         __le32 param;
1693         __le16 seqn;
1694
1695         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1696         __le16 rsvd_dmaindx;
1697
1698         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1699         __le64 flags_rsvd_lanq;
1700 };
1701
1702 #define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1703 #define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1704                                         IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1705
1706 enum iavf_fcoe_filter_ctx_desc_flags_bits {
1707         IAVF_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1708         IAVF_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1709         IAVF_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1710         IAVF_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1711         IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1712         IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1713 };
1714
1715 #define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1716 #define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1717                                         IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1718
1719 #define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1720 #define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1721                         IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1722
1723 #define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1724 #define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1725                         IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1726
1727 enum iavf_switch_element_types {
1728         IAVF_SWITCH_ELEMENT_TYPE_MAC    = 1,
1729         IAVF_SWITCH_ELEMENT_TYPE_PF     = 2,
1730         IAVF_SWITCH_ELEMENT_TYPE_VF     = 3,
1731         IAVF_SWITCH_ELEMENT_TYPE_EMP    = 4,
1732         IAVF_SWITCH_ELEMENT_TYPE_BMC    = 6,
1733         IAVF_SWITCH_ELEMENT_TYPE_PE     = 16,
1734         IAVF_SWITCH_ELEMENT_TYPE_VEB    = 17,
1735         IAVF_SWITCH_ELEMENT_TYPE_PA     = 18,
1736         IAVF_SWITCH_ELEMENT_TYPE_VSI    = 19,
1737 };
1738
1739 /* Supported EtherType filters */
1740 enum iavf_ether_type_index {
1741         IAVF_ETHER_TYPE_1588            = 0,
1742         IAVF_ETHER_TYPE_FIP             = 1,
1743         IAVF_ETHER_TYPE_OUI_EXTENDED    = 2,
1744         IAVF_ETHER_TYPE_MAC_CONTROL     = 3,
1745         IAVF_ETHER_TYPE_LLDP            = 4,
1746         IAVF_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1747         IAVF_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1748         IAVF_ETHER_TYPE_QCN_CNM         = 7,
1749         IAVF_ETHER_TYPE_8021X           = 8,
1750         IAVF_ETHER_TYPE_ARP             = 9,
1751         IAVF_ETHER_TYPE_RSV1            = 10,
1752         IAVF_ETHER_TYPE_RSV2            = 11,
1753 };
1754
1755 /* Filter context base size is 1K */
1756 #define IAVF_HASH_FILTER_BASE_SIZE      1024
1757 /* Supported Hash filter values */
1758 enum iavf_hash_filter_size {
1759         IAVF_HASH_FILTER_SIZE_1K        = 0,
1760         IAVF_HASH_FILTER_SIZE_2K        = 1,
1761         IAVF_HASH_FILTER_SIZE_4K        = 2,
1762         IAVF_HASH_FILTER_SIZE_8K        = 3,
1763         IAVF_HASH_FILTER_SIZE_16K       = 4,
1764         IAVF_HASH_FILTER_SIZE_32K       = 5,
1765         IAVF_HASH_FILTER_SIZE_64K       = 6,
1766         IAVF_HASH_FILTER_SIZE_128K      = 7,
1767         IAVF_HASH_FILTER_SIZE_256K      = 8,
1768         IAVF_HASH_FILTER_SIZE_512K      = 9,
1769         IAVF_HASH_FILTER_SIZE_1M        = 10,
1770 };
1771
1772 /* DMA context base size is 0.5K */
1773 #define IAVF_DMA_CNTX_BASE_SIZE         512
1774 /* Supported DMA context values */
1775 enum iavf_dma_cntx_size {
1776         IAVF_DMA_CNTX_SIZE_512          = 0,
1777         IAVF_DMA_CNTX_SIZE_1K           = 1,
1778         IAVF_DMA_CNTX_SIZE_2K           = 2,
1779         IAVF_DMA_CNTX_SIZE_4K           = 3,
1780         IAVF_DMA_CNTX_SIZE_8K           = 4,
1781         IAVF_DMA_CNTX_SIZE_16K          = 5,
1782         IAVF_DMA_CNTX_SIZE_32K          = 6,
1783         IAVF_DMA_CNTX_SIZE_64K          = 7,
1784         IAVF_DMA_CNTX_SIZE_128K         = 8,
1785         IAVF_DMA_CNTX_SIZE_256K         = 9,
1786 };
1787
1788 /* Supported Hash look up table (LUT) sizes */
1789 enum iavf_hash_lut_size {
1790         IAVF_HASH_LUT_SIZE_128          = 0,
1791         IAVF_HASH_LUT_SIZE_512          = 1,
1792 };
1793
1794 /* Structure to hold a per PF filter control settings */
1795 struct iavf_filter_control_settings {
1796         /* number of PE Quad Hash filter buckets */
1797         enum iavf_hash_filter_size pe_filt_num;
1798         /* number of PE Quad Hash contexts */
1799         enum iavf_dma_cntx_size pe_cntx_num;
1800         /* number of FCoE filter buckets */
1801         enum iavf_hash_filter_size fcoe_filt_num;
1802         /* number of FCoE DDP contexts */
1803         enum iavf_dma_cntx_size fcoe_cntx_num;
1804         /* size of the Hash LUT */
1805         enum iavf_hash_lut_size hash_lut_size;
1806         /* enable FDIR filters for PF and its VFs */
1807         bool enable_fdir;
1808         /* enable Ethertype filters for PF and its VFs */
1809         bool enable_ethtype;
1810         /* enable MAC/VLAN filters for PF and its VFs */
1811         bool enable_macvlan;
1812 };
1813
1814 /* Structure to hold device level control filter counts */
1815 struct iavf_control_filter_stats {
1816         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1817         u16 etype_used;       /* Used perfect EtherType filters */
1818         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1819         u16 etype_free;       /* Un-used perfect EtherType filters */
1820 };
1821
1822 enum iavf_reset_type {
1823         IAVF_RESET_POR          = 0,
1824         IAVF_RESET_CORER        = 1,
1825         IAVF_RESET_GLOBR        = 2,
1826         IAVF_RESET_EMPR         = 3,
1827 };
1828
1829 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1830 #define IAVF_NVM_LLDP_CFG_PTR   0x06
1831 #define IAVF_SR_LLDP_CFG_PTR    0x31
1832 struct iavf_lldp_variables {
1833         u16 length;
1834         u16 adminstatus;
1835         u16 msgfasttx;
1836         u16 msgtxinterval;
1837         u16 txparams;
1838         u16 timers;
1839         u16 crc8;
1840 };
1841
1842 /* Offsets into Alternate Ram */
1843 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1844 #define IAVF_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1845 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1846 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1847 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1848 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1849
1850 /* Alternate Ram Bandwidth Masks */
1851 #define IAVF_ALT_BW_VALUE_MASK          0xFF
1852 #define IAVF_ALT_BW_RELATIVE_MASK       0x40000000
1853 #define IAVF_ALT_BW_VALID_MASK          0x80000000
1854
1855 /* RSS Hash Table Size */
1856 #define IAVF_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1857
1858 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1859 #define IAVF_L3_SRC_SHIFT               47
1860 #define IAVF_L3_SRC_MASK                (0x3ULL << IAVF_L3_SRC_SHIFT)
1861 #define IAVF_L3_V6_SRC_SHIFT            43
1862 #define IAVF_L3_V6_SRC_MASK             (0xFFULL << IAVF_L3_V6_SRC_SHIFT)
1863 #define IAVF_L3_DST_SHIFT               35
1864 #define IAVF_L3_DST_MASK                (0x3ULL << IAVF_L3_DST_SHIFT)
1865 #define IAVF_L3_V6_DST_SHIFT            35
1866 #define IAVF_L3_V6_DST_MASK             (0xFFULL << IAVF_L3_V6_DST_SHIFT)
1867 #define IAVF_L4_SRC_SHIFT               34
1868 #define IAVF_L4_SRC_MASK                (0x1ULL << IAVF_L4_SRC_SHIFT)
1869 #define IAVF_L4_DST_SHIFT               33
1870 #define IAVF_L4_DST_MASK                (0x1ULL << IAVF_L4_DST_SHIFT)
1871 #define IAVF_VERIFY_TAG_SHIFT           31
1872 #define IAVF_VERIFY_TAG_MASK            (0x3ULL << IAVF_VERIFY_TAG_SHIFT)
1873
1874 #define IAVF_FLEX_50_SHIFT              13
1875 #define IAVF_FLEX_50_MASK               (0x1ULL << IAVF_FLEX_50_SHIFT)
1876 #define IAVF_FLEX_51_SHIFT              12
1877 #define IAVF_FLEX_51_MASK               (0x1ULL << IAVF_FLEX_51_SHIFT)
1878 #define IAVF_FLEX_52_SHIFT              11
1879 #define IAVF_FLEX_52_MASK               (0x1ULL << IAVF_FLEX_52_SHIFT)
1880 #define IAVF_FLEX_53_SHIFT              10
1881 #define IAVF_FLEX_53_MASK               (0x1ULL << IAVF_FLEX_53_SHIFT)
1882 #define IAVF_FLEX_54_SHIFT              9
1883 #define IAVF_FLEX_54_MASK               (0x1ULL << IAVF_FLEX_54_SHIFT)
1884 #define IAVF_FLEX_55_SHIFT              8
1885 #define IAVF_FLEX_55_MASK               (0x1ULL << IAVF_FLEX_55_SHIFT)
1886 #define IAVF_FLEX_56_SHIFT              7
1887 #define IAVF_FLEX_56_MASK               (0x1ULL << IAVF_FLEX_56_SHIFT)
1888 #define IAVF_FLEX_57_SHIFT              6
1889 #define IAVF_FLEX_57_MASK               (0x1ULL << IAVF_FLEX_57_SHIFT)
1890
1891 /* Version format for Dynamic Device Personalization(DDP) */
1892 struct iavf_ddp_version {
1893         u8 major;
1894         u8 minor;
1895         u8 update;
1896         u8 draft;
1897 };
1898
1899 #define IAVF_DDP_NAME_SIZE      32
1900
1901 /* Package header */
1902 struct iavf_package_header {
1903         struct iavf_ddp_version version;
1904         u32 segment_count;
1905         u32 segment_offset[1];
1906 };
1907
1908 /* Generic segment header */
1909 struct iavf_generic_seg_header {
1910 #define SEGMENT_TYPE_METADATA   0x00000001
1911 #define SEGMENT_TYPE_NOTES      0x00000002
1912 #define SEGMENT_TYPE_IAVF       0x00000011
1913 #define SEGMENT_TYPE_X722       0x00000012
1914         u32 type;
1915         struct iavf_ddp_version version;
1916         u32 size;
1917         char name[IAVF_DDP_NAME_SIZE];
1918 };
1919
1920 struct iavf_metadata_segment {
1921         struct iavf_generic_seg_header header;
1922         struct iavf_ddp_version version;
1923 #define IAVF_DDP_TRACKID_RDONLY         0
1924 #define IAVF_DDP_TRACKID_INVALID        0xFFFFFFFF
1925         u32 track_id;
1926         char name[IAVF_DDP_NAME_SIZE];
1927 };
1928
1929 struct iavf_device_id_entry {
1930         u32 vendor_dev_id;
1931         u32 sub_vendor_dev_id;
1932 };
1933
1934 struct iavf_profile_segment {
1935         struct iavf_generic_seg_header header;
1936         struct iavf_ddp_version version;
1937         char name[IAVF_DDP_NAME_SIZE];
1938         u32 device_table_count;
1939         struct iavf_device_id_entry device_table[1];
1940 };
1941
1942 struct iavf_section_table {
1943         u32 section_count;
1944         u32 section_offset[1];
1945 };
1946
1947 struct iavf_profile_section_header {
1948         u16 tbl_size;
1949         u16 data_end;
1950         struct {
1951 #define SECTION_TYPE_INFO       0x00000010
1952 #define SECTION_TYPE_MMIO       0x00000800
1953 #define SECTION_TYPE_RB_MMIO    0x00001800
1954 #define SECTION_TYPE_AQ         0x00000801
1955 #define SECTION_TYPE_RB_AQ      0x00001801
1956 #define SECTION_TYPE_NOTE       0x80000000
1957 #define SECTION_TYPE_NAME       0x80000001
1958 #define SECTION_TYPE_PROTO      0x80000002
1959 #define SECTION_TYPE_PCTYPE     0x80000003
1960 #define SECTION_TYPE_PTYPE      0x80000004
1961                 u32 type;
1962                 u32 offset;
1963                 u32 size;
1964         } section;
1965 };
1966
1967 struct iavf_profile_tlv_section_record {
1968         u8 rtype;
1969         u8 type;
1970         u16 len;
1971         u8 data[12];
1972 };
1973
1974 /* Generic AQ section in proflie */
1975 struct iavf_profile_aq_section {
1976         u16 opcode;
1977         u16 flags;
1978         u8  param[16];
1979         u16 datalen;
1980         u8  data[1];
1981 };
1982
1983 struct iavf_profile_info {
1984         u32 track_id;
1985         struct iavf_ddp_version version;
1986         u8 op;
1987 #define IAVF_DDP_ADD_TRACKID            0x01
1988 #define IAVF_DDP_REMOVE_TRACKID 0x02
1989         u8 reserved[7];
1990         u8 name[IAVF_DDP_NAME_SIZE];
1991 };
1992 #endif /* _IAVF_TYPE_H_ */