drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26 #include <rte_vect.h>
  27
  28 #include "iavf.h"
  29 #include "iavf_rxtx.h"
  30 #include "rte_pmd_iavf.h"
  31
  32 /* Offset of mbuf dynamic field for protocol extraction's metadata */
  33 int rte_pmd_ifd_dynfield_proto_xtr_metadata_offs = -1;
  34
  35 /* Mask of mbuf dynamic flags for protocol extraction's type */
  36 uint64_t rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
  37 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
  38 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
  39 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
  40 uint64_t rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
  41 uint64_t rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
  42
  43 uint8_t
  44 iavf_proto_xtr_type_to_rxdid(uint8_t flex_type)
  45 {
  46         static uint8_t rxdid_map[] = {
  47                 [IAVF_PROTO_XTR_NONE]      = IAVF_RXDID_COMMS_OVS_1,
  48                 [IAVF_PROTO_XTR_VLAN]      = IAVF_RXDID_COMMS_AUX_VLAN,
  49                 [IAVF_PROTO_XTR_IPV4]      = IAVF_RXDID_COMMS_AUX_IPV4,
  50                 [IAVF_PROTO_XTR_IPV6]      = IAVF_RXDID_COMMS_AUX_IPV6,
  51                 [IAVF_PROTO_XTR_IPV6_FLOW] = IAVF_RXDID_COMMS_AUX_IPV6_FLOW,
  52                 [IAVF_PROTO_XTR_TCP]       = IAVF_RXDID_COMMS_AUX_TCP,
  53                 [IAVF_PROTO_XTR_IP_OFFSET] = IAVF_RXDID_COMMS_AUX_IP_OFFSET,
  54         };
  55
  56         return flex_type < RTE_DIM(rxdid_map) ?
  57                                 rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
  58 }
  59
  60 int
  61 iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  62 {
  63         struct iavf_rx_queue *rxq = rx_queue;
  64         volatile union iavf_rx_desc *rxdp;
  65         uint16_t desc;
  66
  67         desc = rxq->rx_tail;
  68         rxdp = &rxq->rx_ring[desc];
  69         /* watch for changes in status bit */
  70         pmc->addr = &rxdp->wb.qword1.status_error_len;
  71
  72         /*
  73          * we expect the DD bit to be set to 1 if this descriptor was already
  74          * written to.
  75          */
  76         pmc->val = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  77         pmc->mask = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
  78
  79         /* registers are 64-bit */
  80         pmc->size = sizeof(uint64_t);
  81
  82         return 0;
  83 }
  84
  85 static inline int
  86 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  87 {
  88         /* The following constraints must be satisfied:
  89          *   thresh < rxq->nb_rx_desc
  90          */
  91         if (thresh >= nb_desc) {
  92                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  93                              thresh, nb_desc);
  94                 return -EINVAL;
  95         }
  96         return 0;
  97 }
  98
  99 static inline int
 100 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
 101                 uint16_t tx_free_thresh)
 102 {
 103         /* TX descriptors will have their RS bit set after tx_rs_thresh
 104          * descriptors have been used. The TX descriptor ring will be cleaned
 105          * after tx_free_thresh descriptors are used or if the number of
 106          * descriptors required to transmit a packet is greater than the
 107          * number of free TX descriptors.
 108          *
 109          * The following constraints must be satisfied:
 110          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 111          *  - tx_free_thresh must be less than the size of the ring minus 3.
 112          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 113          *  - tx_rs_thresh must be a divisor of the ring size.
 114          *
 115          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 116          * race condition, hence the maximum threshold constraints. When set
 117          * to zero use default values.
 118          */
 119         if (tx_rs_thresh >= (nb_desc - 2)) {
 120                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
 121                              "number of TX descriptors (%u) minus 2",
 122                              tx_rs_thresh, nb_desc);
 123                 return -EINVAL;
 124         }
 125         if (tx_free_thresh >= (nb_desc - 3)) {
 126                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
 127                              "number of TX descriptors (%u) minus 3.",
 128                              tx_free_thresh, nb_desc);
 129                 return -EINVAL;
 130         }
 131         if (tx_rs_thresh > tx_free_thresh) {
 132                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
 133                              "equal to tx_free_thresh (%u).",
 134                              tx_rs_thresh, tx_free_thresh);
 135                 return -EINVAL;
 136         }
 137         if ((nb_desc % tx_rs_thresh) != 0) {
 138                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
 139                              "number of TX descriptors (%u).",
 140                              tx_rs_thresh, nb_desc);
 141                 return -EINVAL;
 142         }
 143
 144         return 0;
 145 }
 146
 147 static inline bool
 148 check_rx_vec_allow(struct iavf_rx_queue *rxq)
 149 {
 150         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
 151             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 152                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 153                 return true;
 154         }
 155
 156         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 157         return false;
 158 }
 159
 160 static inline bool
 161 check_tx_vec_allow(struct iavf_tx_queue *txq)
 162 {
 163         if (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&
 164             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 165             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 166                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 167                 return true;
 168         }
 169         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 170         return false;
 171 }
 172
 173 static inline bool
 174 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 175 {
 176         int ret = true;
 177
 178         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 179                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 180                              "rxq->rx_free_thresh=%d, "
 181                              "IAVF_RX_MAX_BURST=%d",
 182                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 183                 ret = false;
 184         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 185                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 186                              "rxq->nb_rx_desc=%d, "
 187                              "rxq->rx_free_thresh=%d",
 188                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 189                 ret = false;
 190         }
 191         return ret;
 192 }
 193
 194 static inline void
 195 reset_rx_queue(struct iavf_rx_queue *rxq)
 196 {
 197         uint16_t len;
 198         uint32_t i;
 199
 200         if (!rxq)
 201                 return;
 202
 203         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 204
 205         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 206                 ((volatile char *)rxq->rx_ring)[i] = 0;
 207
 208         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 209
 210         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 211                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 212
 213         /* for rx bulk */
 214         rxq->rx_nb_avail = 0;
 215         rxq->rx_next_avail = 0;
 216         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 217
 218         rxq->rx_tail = 0;
 219         rxq->nb_rx_hold = 0;
 220         rxq->pkt_first_seg = NULL;
 221         rxq->pkt_last_seg = NULL;
 222         rxq->rxrearm_nb = 0;
 223         rxq->rxrearm_start = 0;
 224 }
 225
 226 static inline void
 227 reset_tx_queue(struct iavf_tx_queue *txq)
 228 {
 229         struct iavf_tx_entry *txe;
 230         uint32_t i, size;
 231         uint16_t prev;
 232
 233         if (!txq) {
 234                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 235                 return;
 236         }
 237
 238         txe = txq->sw_ring;
 239         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 240         for (i = 0; i < size; i++)
 241                 ((volatile char *)txq->tx_ring)[i] = 0;
 242
 243         prev = (uint16_t)(txq->nb_tx_desc - 1);
 244         for (i = 0; i < txq->nb_tx_desc; i++) {
 245                 txq->tx_ring[i].cmd_type_offset_bsz =
 246                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 247                 txe[i].mbuf =  NULL;
 248                 txe[i].last_id = i;
 249                 txe[prev].next_id = i;
 250                 prev = i;
 251         }
 252
 253         txq->tx_tail = 0;
 254         txq->nb_used = 0;
 255
 256         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 257         txq->nb_free = txq->nb_tx_desc - 1;
 258
 259         txq->next_dd = txq->rs_thresh - 1;
 260         txq->next_rs = txq->rs_thresh - 1;
 261 }
 262
 263 static int
 264 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 265 {
 266         volatile union iavf_rx_desc *rxd;
 267         struct rte_mbuf *mbuf = NULL;
 268         uint64_t dma_addr;
 269         uint16_t i;
 270
 271         for (i = 0; i < rxq->nb_rx_desc; i++) {
 272                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 273                 if (unlikely(!mbuf)) {
 274                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 275                         return -ENOMEM;
 276                 }
 277
 278                 rte_mbuf_refcnt_set(mbuf, 1);
 279                 mbuf->next = NULL;
 280                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 281                 mbuf->nb_segs = 1;
 282                 mbuf->port = rxq->port_id;
 283
 284                 dma_addr =
 285                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 286
 287                 rxd = &rxq->rx_ring[i];
 288                 rxd->read.pkt_addr = dma_addr;
 289                 rxd->read.hdr_addr = 0;
 290 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 291                 rxd->read.rsvd1 = 0;
 292                 rxd->read.rsvd2 = 0;
 293 #endif
 294
 295                 rxq->sw_ring[i] = mbuf;
 296         }
 297
 298         return 0;
 299 }
 300
 301 static inline void
 302 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 303 {
 304         uint16_t i;
 305
 306         if (!rxq->sw_ring)
 307                 return;
 308
 309         for (i = 0; i < rxq->nb_rx_desc; i++) {
 310                 if (rxq->sw_ring[i]) {
 311                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 312                         rxq->sw_ring[i] = NULL;
 313                 }
 314         }
 315
 316         /* for rx bulk */
 317         if (rxq->rx_nb_avail == 0)
 318                 return;
 319         for (i = 0; i < rxq->rx_nb_avail; i++) {
 320                 struct rte_mbuf *mbuf;
 321
 322                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 323                 rte_pktmbuf_free_seg(mbuf);
 324         }
 325         rxq->rx_nb_avail = 0;
 326 }
 327
 328 static inline void
 329 release_txq_mbufs(struct iavf_tx_queue *txq)
 330 {
 331         uint16_t i;
 332
 333         if (!txq || !txq->sw_ring) {
 334                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 335                 return;
 336         }
 337
 338         for (i = 0; i < txq->nb_tx_desc; i++) {
 339                 if (txq->sw_ring[i].mbuf) {
 340                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 341                         txq->sw_ring[i].mbuf = NULL;
 342                 }
 343         }
 344 }
 345
 346 static const struct iavf_rxq_ops def_rxq_ops = {
 347         .release_mbufs = release_rxq_mbufs,
 348 };
 349
 350 static const struct iavf_txq_ops def_txq_ops = {
 351         .release_mbufs = release_txq_mbufs,
 352 };
 353
 354 static inline void
 355 iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue *rxq,
 356                                     struct rte_mbuf *mb,
 357                                     volatile union iavf_rx_flex_desc *rxdp)
 358 {
 359         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 360                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 361 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 362         uint16_t stat_err;
 363 #endif
 364
 365         if (desc->flow_id != 0xFFFFFFFF) {
 366                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 367                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 368         }
 369
 370 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 371         stat_err = rte_le_to_cpu_16(desc->status_error0);
 372         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 373                 mb->ol_flags |= PKT_RX_RSS_HASH;
 374                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 375         }
 376 #endif
 377 }
 378
 379 static inline void
 380 iavf_rxd_to_pkt_fields_by_comms_aux_v1(struct iavf_rx_queue *rxq,
 381                                        struct rte_mbuf *mb,
 382                                        volatile union iavf_rx_flex_desc *rxdp)
 383 {
 384         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 385                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 386         uint16_t stat_err;
 387
 388         stat_err = rte_le_to_cpu_16(desc->status_error0);
 389         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 390                 mb->ol_flags |= PKT_RX_RSS_HASH;
 391                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 392         }
 393
 394 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 395         if (desc->flow_id != 0xFFFFFFFF) {
 396                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 397                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 398         }
 399
 400         if (rxq->xtr_ol_flag) {
 401                 uint32_t metadata = 0;
 402
 403                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 404
 405                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 406                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 407
 408                 if (stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 409                         metadata |=
 410                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 411
 412                 if (metadata) {
 413                         mb->ol_flags |= rxq->xtr_ol_flag;
 414
 415                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 416                 }
 417         }
 418 #endif
 419 }
 420
 421 static inline void
 422 iavf_rxd_to_pkt_fields_by_comms_aux_v2(struct iavf_rx_queue *rxq,
 423                                        struct rte_mbuf *mb,
 424                                        volatile union iavf_rx_flex_desc *rxdp)
 425 {
 426         volatile struct iavf_32b_rx_flex_desc_comms *desc =
 427                         (volatile struct iavf_32b_rx_flex_desc_comms *)rxdp;
 428         uint16_t stat_err;
 429
 430         stat_err = rte_le_to_cpu_16(desc->status_error0);
 431         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 432                 mb->ol_flags |= PKT_RX_RSS_HASH;
 433                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 434         }
 435
 436 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 437         if (desc->flow_id != 0xFFFFFFFF) {
 438                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 439                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 440         }
 441
 442         if (rxq->xtr_ol_flag) {
 443                 uint32_t metadata = 0;
 444
 445                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 446                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 447                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 448                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 449
 450                 if (metadata) {
 451                         mb->ol_flags |= rxq->xtr_ol_flag;
 452
 453                         *RTE_PMD_IFD_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 454                 }
 455         }
 456 #endif
 457 }
 458
 459 static void
 460 iavf_select_rxd_to_pkt_fields_handler(struct iavf_rx_queue *rxq, uint32_t rxdid)
 461 {
 462         switch (rxdid) {
 463         case IAVF_RXDID_COMMS_AUX_VLAN:
 464                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_vlan_mask;
 465                 rxq->rxd_to_pkt_fields =
 466                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 467                 break;
 468         case IAVF_RXDID_COMMS_AUX_IPV4:
 469                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv4_mask;
 470                 rxq->rxd_to_pkt_fields =
 471                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 472                 break;
 473         case IAVF_RXDID_COMMS_AUX_IPV6:
 474                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_ipv6_mask;
 475                 rxq->rxd_to_pkt_fields =
 476                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 477                 break;
 478         case IAVF_RXDID_COMMS_AUX_IPV6_FLOW:
 479                 rxq->xtr_ol_flag =
 480                         rte_pmd_ifd_dynflag_proto_xtr_ipv6_flow_mask;
 481                 rxq->rxd_to_pkt_fields =
 482                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 483                 break;
 484         case IAVF_RXDID_COMMS_AUX_TCP:
 485                 rxq->xtr_ol_flag = rte_pmd_ifd_dynflag_proto_xtr_tcp_mask;
 486                 rxq->rxd_to_pkt_fields =
 487                         iavf_rxd_to_pkt_fields_by_comms_aux_v1;
 488                 break;
 489         case IAVF_RXDID_COMMS_AUX_IP_OFFSET:
 490                 rxq->xtr_ol_flag =
 491                         rte_pmd_ifd_dynflag_proto_xtr_ip_offset_mask;
 492                 rxq->rxd_to_pkt_fields =
 493                         iavf_rxd_to_pkt_fields_by_comms_aux_v2;
 494                 break;
 495         case IAVF_RXDID_COMMS_OVS_1:
 496                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 497                 break;
 498         default:
 499                 /* update this according to the RXDID for FLEX_DESC_NONE */
 500                 rxq->rxd_to_pkt_fields = iavf_rxd_to_pkt_fields_by_comms_ovs;
 501                 break;
 502         }
 503
 504         if (!rte_pmd_ifd_dynf_proto_xtr_metadata_avail())
 505                 rxq->xtr_ol_flag = 0;
 506 }
 507
 508 int
 509 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 510                        uint16_t nb_desc, unsigned int socket_id,
 511                        const struct rte_eth_rxconf *rx_conf,
 512                        struct rte_mempool *mp)
 513 {
 514         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 515         struct iavf_adapter *ad =
 516                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 517         struct iavf_info *vf =
 518                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 519         struct iavf_vsi *vsi = &vf->vsi;
 520         struct iavf_rx_queue *rxq;
 521         const struct rte_memzone *mz;
 522         uint32_t ring_size;
 523         uint8_t proto_xtr;
 524         uint16_t len;
 525         uint16_t rx_free_thresh;
 526         uint64_t offloads;
 527
 528         PMD_INIT_FUNC_TRACE();
 529
 530         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
 531
 532         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 533             nb_desc > IAVF_MAX_RING_DESC ||
 534             nb_desc < IAVF_MIN_RING_DESC) {
 535                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 536                              "invalid", nb_desc);
 537                 return -EINVAL;
 538         }
 539
 540         /* Check free threshold */
 541         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 542                          IAVF_DEFAULT_RX_FREE_THRESH :
 543                          rx_conf->rx_free_thresh;
 544         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 545                 return -EINVAL;
 546
 547         /* Free memory if needed */
 548         if (dev->data->rx_queues[queue_idx]) {
 549                 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 550                 dev->data->rx_queues[queue_idx] = NULL;
 551         }
 552
 553         /* Allocate the rx queue data structure */
 554         rxq = rte_zmalloc_socket("iavf rxq",
 555                                  sizeof(struct iavf_rx_queue),
 556                                  RTE_CACHE_LINE_SIZE,
 557                                  socket_id);
 558         if (!rxq) {
 559                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 560                              "rx queue data structure");
 561                 return -ENOMEM;
 562         }
 563
 564         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
 565                 proto_xtr = vf->proto_xtr ? vf->proto_xtr[queue_idx] :
 566                                 IAVF_PROTO_XTR_NONE;
 567                 rxq->rxdid = iavf_proto_xtr_type_to_rxdid(proto_xtr);
 568                 rxq->proto_xtr = proto_xtr;
 569         } else {
 570                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 571                 rxq->proto_xtr = IAVF_PROTO_XTR_NONE;
 572         }
 573
 574         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 575                 struct virtchnl_vlan_supported_caps *stripping_support =
 576                                 &vf->vlan_v2_caps.offloads.stripping_support;
 577                 uint32_t stripping_cap;
 578
 579                 if (stripping_support->outer)
 580                         stripping_cap = stripping_support->outer;
 581                 else
 582                         stripping_cap = stripping_support->inner;
 583
 584                 if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 585                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 586                 else if (stripping_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2_2)
 587                         rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2;
 588         } else {
 589                 rxq->rx_flags = IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 590         }
 591
 592         iavf_select_rxd_to_pkt_fields_handler(rxq, rxq->rxdid);
 593
 594         rxq->mp = mp;
 595         rxq->nb_rx_desc = nb_desc;
 596         rxq->rx_free_thresh = rx_free_thresh;
 597         rxq->queue_id = queue_idx;
 598         rxq->port_id = dev->data->port_id;
 599         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 600         rxq->rx_hdr_len = 0;
 601         rxq->vsi = vsi;
 602         rxq->offloads = offloads;
 603
 604         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 605                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 606         else
 607                 rxq->crc_len = 0;
 608
 609         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 610         rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 611
 612         /* Allocate the software ring. */
 613         len = nb_desc + IAVF_RX_MAX_BURST;
 614         rxq->sw_ring =
 615                 rte_zmalloc_socket("iavf rx sw ring",
 616                                    sizeof(struct rte_mbuf *) * len,
 617                                    RTE_CACHE_LINE_SIZE,
 618                                    socket_id);
 619         if (!rxq->sw_ring) {
 620                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 621                 rte_free(rxq);
 622                 return -ENOMEM;
 623         }
 624
 625         /* Allocate the maximun number of RX ring hardware descriptor with
 626          * a liitle more to support bulk allocate.
 627          */
 628         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 629         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 630                               IAVF_DMA_MEM_ALIGN);
 631         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 632                                       ring_size, IAVF_RING_BASE_ALIGN,
 633                                       socket_id);
 634         if (!mz) {
 635                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 636                 rte_free(rxq->sw_ring);
 637                 rte_free(rxq);
 638                 return -ENOMEM;
 639         }
 640         /* Zero all the descriptors in the ring. */
 641         memset(mz->addr, 0, ring_size);
 642         rxq->rx_ring_phys_addr = mz->iova;
 643         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 644
 645         rxq->mz = mz;
 646         reset_rx_queue(rxq);
 647         rxq->q_set = true;
 648         dev->data->rx_queues[queue_idx] = rxq;
 649         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 650         rxq->ops = &def_rxq_ops;
 651
 652         if (check_rx_bulk_allow(rxq) == true) {
 653                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 654                              "satisfied. Rx Burst Bulk Alloc function will be "
 655                              "used on port=%d, queue=%d.",
 656                              rxq->port_id, rxq->queue_id);
 657         } else {
 658                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 659                              "not satisfied, Scattered Rx is requested "
 660                              "on port=%d, queue=%d.",
 661                              rxq->port_id, rxq->queue_id);
 662                 ad->rx_bulk_alloc_allowed = false;
 663         }
 664
 665         if (check_rx_vec_allow(rxq) == false)
 666                 ad->rx_vec_allowed = false;
 667
 668         return 0;
 669 }
 670
 671 int
 672 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 673                        uint16_t queue_idx,
 674                        uint16_t nb_desc,
 675                        unsigned int socket_id,
 676                        const struct rte_eth_txconf *tx_conf)
 677 {
 678         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 679         struct iavf_info *vf =
 680                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 681         struct iavf_tx_queue *txq;
 682         const struct rte_memzone *mz;
 683         uint32_t ring_size;
 684         uint16_t tx_rs_thresh, tx_free_thresh;
 685         uint64_t offloads;
 686
 687         PMD_INIT_FUNC_TRACE();
 688
 689         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 690
 691         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 692             nb_desc > IAVF_MAX_RING_DESC ||
 693             nb_desc < IAVF_MIN_RING_DESC) {
 694                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 695                             "invalid", nb_desc);
 696                 return -EINVAL;
 697         }
 698
 699         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 700                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 701         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 702                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 703         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 704
 705         /* Free memory if needed. */
 706         if (dev->data->tx_queues[queue_idx]) {
 707                 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 708                 dev->data->tx_queues[queue_idx] = NULL;
 709         }
 710
 711         /* Allocate the TX queue data structure. */
 712         txq = rte_zmalloc_socket("iavf txq",
 713                                  sizeof(struct iavf_tx_queue),
 714                                  RTE_CACHE_LINE_SIZE,
 715                                  socket_id);
 716         if (!txq) {
 717                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 718                              "tx queue structure");
 719                 return -ENOMEM;
 720         }
 721
 722         if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN_V2) {
 723                 struct virtchnl_vlan_supported_caps *insertion_support =
 724                         &vf->vlan_v2_caps.offloads.insertion_support;
 725                 uint32_t insertion_cap;
 726
 727                 if (insertion_support->outer)
 728                         insertion_cap = insertion_support->outer;
 729                 else
 730                         insertion_cap = insertion_support->inner;
 731
 732                 if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG1)
 733                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 734                 else if (insertion_cap & VIRTCHNL_VLAN_TAG_LOCATION_L2TAG2)
 735                         txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2;
 736         } else {
 737                 txq->vlan_flag = IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1;
 738         }
 739
 740         txq->nb_tx_desc = nb_desc;
 741         txq->rs_thresh = tx_rs_thresh;
 742         txq->free_thresh = tx_free_thresh;
 743         txq->queue_id = queue_idx;
 744         txq->port_id = dev->data->port_id;
 745         txq->offloads = offloads;
 746         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 747
 748         /* Allocate software ring */
 749         txq->sw_ring =
 750                 rte_zmalloc_socket("iavf tx sw ring",
 751                                    sizeof(struct iavf_tx_entry) * nb_desc,
 752                                    RTE_CACHE_LINE_SIZE,
 753                                    socket_id);
 754         if (!txq->sw_ring) {
 755                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 756                 rte_free(txq);
 757                 return -ENOMEM;
 758         }
 759
 760         /* Allocate TX hardware ring descriptors. */
 761         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 762         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 763         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 764                                       ring_size, IAVF_RING_BASE_ALIGN,
 765                                       socket_id);
 766         if (!mz) {
 767                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 768                 rte_free(txq->sw_ring);
 769                 rte_free(txq);
 770                 return -ENOMEM;
 771         }
 772         txq->tx_ring_phys_addr = mz->iova;
 773         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 774
 775         txq->mz = mz;
 776         reset_tx_queue(txq);
 777         txq->q_set = true;
 778         dev->data->tx_queues[queue_idx] = txq;
 779         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 780         txq->ops = &def_txq_ops;
 781
 782         if (check_tx_vec_allow(txq) == false) {
 783                 struct iavf_adapter *ad =
 784                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 785                 ad->tx_vec_allowed = false;
 786         }
 787
 788         return 0;
 789 }
 790
 791 int
 792 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 793 {
 794         struct iavf_adapter *adapter =
 795                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 796         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 797         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798         struct iavf_rx_queue *rxq;
 799         int err = 0;
 800
 801         PMD_DRV_FUNC_TRACE();
 802
 803         if (rx_queue_id >= dev->data->nb_rx_queues)
 804                 return -EINVAL;
 805
 806         rxq = dev->data->rx_queues[rx_queue_id];
 807
 808         err = alloc_rxq_mbufs(rxq);
 809         if (err) {
 810                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 811                 return err;
 812         }
 813
 814         rte_wmb();
 815
 816         /* Init the RX tail register. */
 817         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 818         IAVF_WRITE_FLUSH(hw);
 819
 820         /* Ready to switch the queue on */
 821         if (!vf->lv_enabled)
 822                 err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 823         else
 824                 err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
 825
 826         if (err)
 827                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 828                             rx_queue_id);
 829         else
 830                 dev->data->rx_queue_state[rx_queue_id] =
 831                         RTE_ETH_QUEUE_STATE_STARTED;
 832
 833         return err;
 834 }
 835
 836 int
 837 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 838 {
 839         struct iavf_adapter *adapter =
 840                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 841         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 842         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 843         struct iavf_tx_queue *txq;
 844         int err = 0;
 845
 846         PMD_DRV_FUNC_TRACE();
 847
 848         if (tx_queue_id >= dev->data->nb_tx_queues)
 849                 return -EINVAL;
 850
 851         txq = dev->data->tx_queues[tx_queue_id];
 852
 853         /* Init the RX tail register. */
 854         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 855         IAVF_WRITE_FLUSH(hw);
 856
 857         /* Ready to switch the queue on */
 858         if (!vf->lv_enabled)
 859                 err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 860         else
 861                 err = iavf_switch_queue_lv(adapter, tx_queue_id, false, true);
 862
 863         if (err)
 864                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 865                             tx_queue_id);
 866         else
 867                 dev->data->tx_queue_state[tx_queue_id] =
 868                         RTE_ETH_QUEUE_STATE_STARTED;
 869
 870         return err;
 871 }
 872
 873 int
 874 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 875 {
 876         struct iavf_adapter *adapter =
 877                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 878         struct iavf_rx_queue *rxq;
 879         int err;
 880
 881         PMD_DRV_FUNC_TRACE();
 882
 883         if (rx_queue_id >= dev->data->nb_rx_queues)
 884                 return -EINVAL;
 885
 886         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 887         if (err) {
 888                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 889                             rx_queue_id);
 890                 return err;
 891         }
 892
 893         rxq = dev->data->rx_queues[rx_queue_id];
 894         rxq->ops->release_mbufs(rxq);
 895         reset_rx_queue(rxq);
 896         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 897
 898         return 0;
 899 }
 900
 901 int
 902 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 903 {
 904         struct iavf_adapter *adapter =
 905                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 906         struct iavf_tx_queue *txq;
 907         int err;
 908
 909         PMD_DRV_FUNC_TRACE();
 910
 911         if (tx_queue_id >= dev->data->nb_tx_queues)
 912                 return -EINVAL;
 913
 914         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 915         if (err) {
 916                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 917                             tx_queue_id);
 918                 return err;
 919         }
 920
 921         txq = dev->data->tx_queues[tx_queue_id];
 922         txq->ops->release_mbufs(txq);
 923         reset_tx_queue(txq);
 924         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 925
 926         return 0;
 927 }
 928
 929 void
 930 iavf_dev_rx_queue_release(void *rxq)
 931 {
 932         struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
 933
 934         if (!q)
 935                 return;
 936
 937         q->ops->release_mbufs(q);
 938         rte_free(q->sw_ring);
 939         rte_memzone_free(q->mz);
 940         rte_free(q);
 941 }
 942
 943 void
 944 iavf_dev_tx_queue_release(void *txq)
 945 {
 946         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
 947
 948         if (!q)
 949                 return;
 950
 951         q->ops->release_mbufs(q);
 952         rte_free(q->sw_ring);
 953         rte_memzone_free(q->mz);
 954         rte_free(q);
 955 }
 956
 957 void
 958 iavf_stop_queues(struct rte_eth_dev *dev)
 959 {
 960         struct iavf_adapter *adapter =
 961                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 962         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 963         struct iavf_rx_queue *rxq;
 964         struct iavf_tx_queue *txq;
 965         int ret, i;
 966
 967         /* Stop All queues */
 968         if (!vf->lv_enabled) {
 969                 ret = iavf_disable_queues(adapter);
 970                 if (ret)
 971                         PMD_DRV_LOG(WARNING, "Fail to stop queues");
 972         } else {
 973                 ret = iavf_disable_queues_lv(adapter);
 974                 if (ret)
 975                         PMD_DRV_LOG(WARNING, "Fail to stop queues for large VF");
 976         }
 977
 978         if (ret)
 979                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 980
 981         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 982                 txq = dev->data->tx_queues[i];
 983                 if (!txq)
 984                         continue;
 985                 txq->ops->release_mbufs(txq);
 986                 reset_tx_queue(txq);
 987                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 988         }
 989         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 990                 rxq = dev->data->rx_queues[i];
 991                 if (!rxq)
 992                         continue;
 993                 rxq->ops->release_mbufs(rxq);
 994                 reset_rx_queue(rxq);
 995                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 996         }
 997 }
 998
 999 #define IAVF_RX_FLEX_ERR0_BITS  \
1000         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1001          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1002          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1003          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1004          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1005          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1006
1007 static inline void
1008 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
1009 {
1010         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1011                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1012                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1013                 mb->vlan_tci =
1014                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1015         } else {
1016                 mb->vlan_tci = 0;
1017         }
1018 }
1019
1020 static inline void
1021 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
1022                           volatile union iavf_rx_flex_desc *rxdp,
1023                           uint8_t rx_flags)
1024 {
1025         uint16_t vlan_tci = 0;
1026
1027         if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1 &&
1028             rte_le_to_cpu_64(rxdp->wb.status_error0) &
1029             (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S))
1030                 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag1);
1031
1032 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1033         if (rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2 &&
1034             rte_le_to_cpu_16(rxdp->wb.status_error1) &
1035             (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S))
1036                 vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1037 #endif
1038
1039         if (vlan_tci) {
1040                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1041                 mb->vlan_tci = vlan_tci;
1042         }
1043 }
1044
1045 /* Translate the rx descriptor status and error fields to pkt flags */
1046 static inline uint64_t
1047 iavf_rxd_to_pkt_flags(uint64_t qword)
1048 {
1049         uint64_t flags;
1050         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
1051
1052 #define IAVF_RX_ERR_BITS 0x3f
1053
1054         /* Check if RSS_HASH */
1055         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
1056                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
1057                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1058
1059         /* Check if FDIR Match */
1060         flags |= (qword & (1 << IAVF_RX_DESC_STATUS_FLM_SHIFT) ?
1061                                 PKT_RX_FDIR : 0);
1062
1063         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
1064                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1065                 return flags;
1066         }
1067
1068         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
1069                 flags |= PKT_RX_IP_CKSUM_BAD;
1070         else
1071                 flags |= PKT_RX_IP_CKSUM_GOOD;
1072
1073         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
1074                 flags |= PKT_RX_L4_CKSUM_BAD;
1075         else
1076                 flags |= PKT_RX_L4_CKSUM_GOOD;
1077
1078         /* TODO: Oversize error bit is not processed here */
1079
1080         return flags;
1081 }
1082
1083 static inline uint64_t
1084 iavf_rxd_build_fdir(volatile union iavf_rx_desc *rxdp, struct rte_mbuf *mb)
1085 {
1086         uint64_t flags = 0;
1087 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1088         uint16_t flexbh;
1089
1090         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
1091                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
1092                 IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK;
1093
1094         if (flexbh == IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
1095                 mb->hash.fdir.hi =
1096                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
1097                 flags |= PKT_RX_FDIR_ID;
1098         }
1099 #else
1100         mb->hash.fdir.hi =
1101                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
1102         flags |= PKT_RX_FDIR_ID;
1103 #endif
1104         return flags;
1105 }
1106
1107 #define IAVF_RX_FLEX_ERR0_BITS  \
1108         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
1109          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
1110          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
1111          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1112          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
1113          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
1114
1115 /* Rx L3/L4 checksum */
1116 static inline uint64_t
1117 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
1118 {
1119         uint64_t flags = 0;
1120
1121         /* check if HW has decoded the packet and checksum */
1122         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1123                 return 0;
1124
1125         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
1126                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1127                 return flags;
1128         }
1129
1130         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1131                 flags |= PKT_RX_IP_CKSUM_BAD;
1132         else
1133                 flags |= PKT_RX_IP_CKSUM_GOOD;
1134
1135         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1136                 flags |= PKT_RX_L4_CKSUM_BAD;
1137         else
1138                 flags |= PKT_RX_L4_CKSUM_GOOD;
1139
1140         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1141                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1142
1143         return flags;
1144 }
1145
1146 /* If the number of free RX descriptors is greater than the RX free
1147  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1148  * register. Update the RDT with the value of the last processed RX
1149  * descriptor minus 1, to guarantee that the RDT register is never
1150  * equal to the RDH register, which creates a "full" ring situation
1151  * from the hardware point of view.
1152  */
1153 static inline void
1154 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
1155 {
1156         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1157
1158         if (nb_hold > rxq->rx_free_thresh) {
1159                 PMD_RX_LOG(DEBUG,
1160                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
1161                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
1162                 rx_id = (uint16_t)((rx_id == 0) ?
1163                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1164                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1165                 nb_hold = 0;
1166         }
1167         rxq->nb_rx_hold = nb_hold;
1168 }
1169
1170 /* implement recv_pkts */
1171 uint16_t
1172 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1173 {
1174         volatile union iavf_rx_desc *rx_ring;
1175         volatile union iavf_rx_desc *rxdp;
1176         struct iavf_rx_queue *rxq;
1177         union iavf_rx_desc rxd;
1178         struct rte_mbuf *rxe;
1179         struct rte_eth_dev *dev;
1180         struct rte_mbuf *rxm;
1181         struct rte_mbuf *nmb;
1182         uint16_t nb_rx;
1183         uint32_t rx_status;
1184         uint64_t qword1;
1185         uint16_t rx_packet_len;
1186         uint16_t rx_id, nb_hold;
1187         uint64_t dma_addr;
1188         uint64_t pkt_flags;
1189         const uint32_t *ptype_tbl;
1190
1191         nb_rx = 0;
1192         nb_hold = 0;
1193         rxq = rx_queue;
1194         rx_id = rxq->rx_tail;
1195         rx_ring = rxq->rx_ring;
1196         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1197
1198         while (nb_rx < nb_pkts) {
1199                 rxdp = &rx_ring[rx_id];
1200                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1201                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1202                             IAVF_RXD_QW1_STATUS_SHIFT;
1203
1204                 /* Check the DD bit first */
1205                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1206                         break;
1207                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1208
1209                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1210                 if (unlikely(!nmb)) {
1211                         dev = &rte_eth_devices[rxq->port_id];
1212                         dev->data->rx_mbuf_alloc_failed++;
1213                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1214                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1215                         break;
1216                 }
1217
1218                 rxd = *rxdp;
1219                 nb_hold++;
1220                 rxe = rxq->sw_ring[rx_id];
1221                 rx_id++;
1222                 if (unlikely(rx_id == rxq->nb_rx_desc))
1223                         rx_id = 0;
1224
1225                 /* Prefetch next mbuf */
1226                 rte_prefetch0(rxq->sw_ring[rx_id]);
1227
1228                 /* When next RX descriptor is on a cache line boundary,
1229                  * prefetch the next 4 RX descriptors and next 8 pointers
1230                  * to mbufs.
1231                  */
1232                 if ((rx_id & 0x3) == 0) {
1233                         rte_prefetch0(&rx_ring[rx_id]);
1234                         rte_prefetch0(rxq->sw_ring[rx_id]);
1235                 }
1236                 rxm = rxe;
1237                 dma_addr =
1238                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1239                 rxdp->read.hdr_addr = 0;
1240                 rxdp->read.pkt_addr = dma_addr;
1241
1242                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1243                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1244
1245                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1246                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1247                 rxm->nb_segs = 1;
1248                 rxm->next = NULL;
1249                 rxm->pkt_len = rx_packet_len;
1250                 rxm->data_len = rx_packet_len;
1251                 rxm->port = rxq->port_id;
1252                 rxm->ol_flags = 0;
1253                 iavf_rxd_to_vlan_tci(rxm, &rxd);
1254                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1255                 rxm->packet_type =
1256                         ptype_tbl[(uint8_t)((qword1 &
1257                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1258
1259                 if (pkt_flags & PKT_RX_RSS_HASH)
1260                         rxm->hash.rss =
1261                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1262
1263                 if (pkt_flags & PKT_RX_FDIR)
1264                         pkt_flags |= iavf_rxd_build_fdir(&rxd, rxm);
1265
1266                 rxm->ol_flags |= pkt_flags;
1267
1268                 rx_pkts[nb_rx++] = rxm;
1269         }
1270         rxq->rx_tail = rx_id;
1271
1272         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1273
1274         return nb_rx;
1275 }
1276
1277 /* implement recv_pkts for flexible Rx descriptor */
1278 uint16_t
1279 iavf_recv_pkts_flex_rxd(void *rx_queue,
1280                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1281 {
1282         volatile union iavf_rx_desc *rx_ring;
1283         volatile union iavf_rx_flex_desc *rxdp;
1284         struct iavf_rx_queue *rxq;
1285         union iavf_rx_flex_desc rxd;
1286         struct rte_mbuf *rxe;
1287         struct rte_eth_dev *dev;
1288         struct rte_mbuf *rxm;
1289         struct rte_mbuf *nmb;
1290         uint16_t nb_rx;
1291         uint16_t rx_stat_err0;
1292         uint16_t rx_packet_len;
1293         uint16_t rx_id, nb_hold;
1294         uint64_t dma_addr;
1295         uint64_t pkt_flags;
1296         const uint32_t *ptype_tbl;
1297
1298         nb_rx = 0;
1299         nb_hold = 0;
1300         rxq = rx_queue;
1301         rx_id = rxq->rx_tail;
1302         rx_ring = rxq->rx_ring;
1303         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1304
1305         while (nb_rx < nb_pkts) {
1306                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1307                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1308
1309                 /* Check the DD bit first */
1310                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1311                         break;
1312                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1313
1314                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1315                 if (unlikely(!nmb)) {
1316                         dev = &rte_eth_devices[rxq->port_id];
1317                         dev->data->rx_mbuf_alloc_failed++;
1318                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1319                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1320                         break;
1321                 }
1322
1323                 rxd = *rxdp;
1324                 nb_hold++;
1325                 rxe = rxq->sw_ring[rx_id];
1326                 rx_id++;
1327                 if (unlikely(rx_id == rxq->nb_rx_desc))
1328                         rx_id = 0;
1329
1330                 /* Prefetch next mbuf */
1331                 rte_prefetch0(rxq->sw_ring[rx_id]);
1332
1333                 /* When next RX descriptor is on a cache line boundary,
1334                  * prefetch the next 4 RX descriptors and next 8 pointers
1335                  * to mbufs.
1336                  */
1337                 if ((rx_id & 0x3) == 0) {
1338                         rte_prefetch0(&rx_ring[rx_id]);
1339                         rte_prefetch0(rxq->sw_ring[rx_id]);
1340                 }
1341                 rxm = rxe;
1342                 dma_addr =
1343                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1344                 rxdp->read.hdr_addr = 0;
1345                 rxdp->read.pkt_addr = dma_addr;
1346
1347                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1348                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1349
1350                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1351                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1352                 rxm->nb_segs = 1;
1353                 rxm->next = NULL;
1354                 rxm->pkt_len = rx_packet_len;
1355                 rxm->data_len = rx_packet_len;
1356                 rxm->port = rxq->port_id;
1357                 rxm->ol_flags = 0;
1358                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1359                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1360                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd, rxq->rx_flags);
1361                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
1362                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1363                 rxm->ol_flags |= pkt_flags;
1364
1365                 rx_pkts[nb_rx++] = rxm;
1366         }
1367         rxq->rx_tail = rx_id;
1368
1369         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1370
1371         return nb_rx;
1372 }
1373
1374 /* implement recv_scattered_pkts for flexible Rx descriptor */
1375 uint16_t
1376 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1377                                   uint16_t nb_pkts)
1378 {
1379         struct iavf_rx_queue *rxq = rx_queue;
1380         union iavf_rx_flex_desc rxd;
1381         struct rte_mbuf *rxe;
1382         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1383         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1384         struct rte_mbuf *nmb, *rxm;
1385         uint16_t rx_id = rxq->rx_tail;
1386         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1387         struct rte_eth_dev *dev;
1388         uint16_t rx_stat_err0;
1389         uint64_t dma_addr;
1390         uint64_t pkt_flags;
1391
1392         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1393         volatile union iavf_rx_flex_desc *rxdp;
1394         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1395
1396         while (nb_rx < nb_pkts) {
1397                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1398                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1399
1400                 /* Check the DD bit */
1401                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1402                         break;
1403                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1404
1405                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1406                 if (unlikely(!nmb)) {
1407                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1408                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1409                         dev = &rte_eth_devices[rxq->port_id];
1410                         dev->data->rx_mbuf_alloc_failed++;
1411                         break;
1412                 }
1413
1414                 rxd = *rxdp;
1415                 nb_hold++;
1416                 rxe = rxq->sw_ring[rx_id];
1417                 rx_id++;
1418                 if (rx_id == rxq->nb_rx_desc)
1419                         rx_id = 0;
1420
1421                 /* Prefetch next mbuf */
1422                 rte_prefetch0(rxq->sw_ring[rx_id]);
1423
1424                 /* When next RX descriptor is on a cache line boundary,
1425                  * prefetch the next 4 RX descriptors and next 8 pointers
1426                  * to mbufs.
1427                  */
1428                 if ((rx_id & 0x3) == 0) {
1429                         rte_prefetch0(&rx_ring[rx_id]);
1430                         rte_prefetch0(rxq->sw_ring[rx_id]);
1431                 }
1432
1433                 rxm = rxe;
1434                 dma_addr =
1435                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1436
1437                 /* Set data buffer address and data length of the mbuf */
1438                 rxdp->read.hdr_addr = 0;
1439                 rxdp->read.pkt_addr = dma_addr;
1440                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1441                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1442                 rxm->data_len = rx_packet_len;
1443                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1444
1445                 /* If this is the first buffer of the received packet, set the
1446                  * pointer to the first mbuf of the packet and initialize its
1447                  * context. Otherwise, update the total length and the number
1448                  * of segments of the current scattered packet, and update the
1449                  * pointer to the last mbuf of the current packet.
1450                  */
1451                 if (!first_seg) {
1452                         first_seg = rxm;
1453                         first_seg->nb_segs = 1;
1454                         first_seg->pkt_len = rx_packet_len;
1455                 } else {
1456                         first_seg->pkt_len =
1457                                 (uint16_t)(first_seg->pkt_len +
1458                                                 rx_packet_len);
1459                         first_seg->nb_segs++;
1460                         last_seg->next = rxm;
1461                 }
1462
1463                 /* If this is not the last buffer of the received packet,
1464                  * update the pointer to the last mbuf of the current scattered
1465                  * packet and continue to parse the RX ring.
1466                  */
1467                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1468                         last_seg = rxm;
1469                         continue;
1470                 }
1471
1472                 /* This is the last buffer of the received packet. If the CRC
1473                  * is not stripped by the hardware:
1474                  *  - Subtract the CRC length from the total packet length.
1475                  *  - If the last buffer only contains the whole CRC or a part
1476                  *  of it, free the mbuf associated to the last buffer. If part
1477                  *  of the CRC is also contained in the previous mbuf, subtract
1478                  *  the length of that CRC part from the data length of the
1479                  *  previous mbuf.
1480                  */
1481                 rxm->next = NULL;
1482                 if (unlikely(rxq->crc_len > 0)) {
1483                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1484                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1485                                 rte_pktmbuf_free_seg(rxm);
1486                                 first_seg->nb_segs--;
1487                                 last_seg->data_len =
1488                                         (uint16_t)(last_seg->data_len -
1489                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1490                                 last_seg->next = NULL;
1491                         } else {
1492                                 rxm->data_len = (uint16_t)(rx_packet_len -
1493                                                         RTE_ETHER_CRC_LEN);
1494                         }
1495                 }
1496
1497                 first_seg->port = rxq->port_id;
1498                 first_seg->ol_flags = 0;
1499                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1500                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1501                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd, rxq->rx_flags);
1502                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1503                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1504
1505                 first_seg->ol_flags |= pkt_flags;
1506
1507                 /* Prefetch data of first segment, if configured to do so. */
1508                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1509                                           first_seg->data_off));
1510                 rx_pkts[nb_rx++] = first_seg;
1511                 first_seg = NULL;
1512         }
1513
1514         /* Record index of the next RX descriptor to probe. */
1515         rxq->rx_tail = rx_id;
1516         rxq->pkt_first_seg = first_seg;
1517         rxq->pkt_last_seg = last_seg;
1518
1519         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1520
1521         return nb_rx;
1522 }
1523
1524 /* implement recv_scattered_pkts  */
1525 uint16_t
1526 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1527                         uint16_t nb_pkts)
1528 {
1529         struct iavf_rx_queue *rxq = rx_queue;
1530         union iavf_rx_desc rxd;
1531         struct rte_mbuf *rxe;
1532         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1533         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1534         struct rte_mbuf *nmb, *rxm;
1535         uint16_t rx_id = rxq->rx_tail;
1536         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1537         struct rte_eth_dev *dev;
1538         uint32_t rx_status;
1539         uint64_t qword1;
1540         uint64_t dma_addr;
1541         uint64_t pkt_flags;
1542
1543         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1544         volatile union iavf_rx_desc *rxdp;
1545         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1546
1547         while (nb_rx < nb_pkts) {
1548                 rxdp = &rx_ring[rx_id];
1549                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1550                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1551                             IAVF_RXD_QW1_STATUS_SHIFT;
1552
1553                 /* Check the DD bit */
1554                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1555                         break;
1556                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1557
1558                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1559                 if (unlikely(!nmb)) {
1560                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1561                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1562                         dev = &rte_eth_devices[rxq->port_id];
1563                         dev->data->rx_mbuf_alloc_failed++;
1564                         break;
1565                 }
1566
1567                 rxd = *rxdp;
1568                 nb_hold++;
1569                 rxe = rxq->sw_ring[rx_id];
1570                 rx_id++;
1571                 if (rx_id == rxq->nb_rx_desc)
1572                         rx_id = 0;
1573
1574                 /* Prefetch next mbuf */
1575                 rte_prefetch0(rxq->sw_ring[rx_id]);
1576
1577                 /* When next RX descriptor is on a cache line boundary,
1578                  * prefetch the next 4 RX descriptors and next 8 pointers
1579                  * to mbufs.
1580                  */
1581                 if ((rx_id & 0x3) == 0) {
1582                         rte_prefetch0(&rx_ring[rx_id]);
1583                         rte_prefetch0(rxq->sw_ring[rx_id]);
1584                 }
1585
1586                 rxm = rxe;
1587                 dma_addr =
1588                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1589
1590                 /* Set data buffer address and data length of the mbuf */
1591                 rxdp->read.hdr_addr = 0;
1592                 rxdp->read.pkt_addr = dma_addr;
1593                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1594                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1595                 rxm->data_len = rx_packet_len;
1596                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1597
1598                 /* If this is the first buffer of the received packet, set the
1599                  * pointer to the first mbuf of the packet and initialize its
1600                  * context. Otherwise, update the total length and the number
1601                  * of segments of the current scattered packet, and update the
1602                  * pointer to the last mbuf of the current packet.
1603                  */
1604                 if (!first_seg) {
1605                         first_seg = rxm;
1606                         first_seg->nb_segs = 1;
1607                         first_seg->pkt_len = rx_packet_len;
1608                 } else {
1609                         first_seg->pkt_len =
1610                                 (uint16_t)(first_seg->pkt_len +
1611                                                 rx_packet_len);
1612                         first_seg->nb_segs++;
1613                         last_seg->next = rxm;
1614                 }
1615
1616                 /* If this is not the last buffer of the received packet,
1617                  * update the pointer to the last mbuf of the current scattered
1618                  * packet and continue to parse the RX ring.
1619                  */
1620                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1621                         last_seg = rxm;
1622                         continue;
1623                 }
1624
1625                 /* This is the last buffer of the received packet. If the CRC
1626                  * is not stripped by the hardware:
1627                  *  - Subtract the CRC length from the total packet length.
1628                  *  - If the last buffer only contains the whole CRC or a part
1629                  *  of it, free the mbuf associated to the last buffer. If part
1630                  *  of the CRC is also contained in the previous mbuf, subtract
1631                  *  the length of that CRC part from the data length of the
1632                  *  previous mbuf.
1633                  */
1634                 rxm->next = NULL;
1635                 if (unlikely(rxq->crc_len > 0)) {
1636                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1637                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1638                                 rte_pktmbuf_free_seg(rxm);
1639                                 first_seg->nb_segs--;
1640                                 last_seg->data_len =
1641                                         (uint16_t)(last_seg->data_len -
1642                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1643                                 last_seg->next = NULL;
1644                         } else
1645                                 rxm->data_len = (uint16_t)(rx_packet_len -
1646                                                         RTE_ETHER_CRC_LEN);
1647                 }
1648
1649                 first_seg->port = rxq->port_id;
1650                 first_seg->ol_flags = 0;
1651                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1652                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1653                 first_seg->packet_type =
1654                         ptype_tbl[(uint8_t)((qword1 &
1655                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1656
1657                 if (pkt_flags & PKT_RX_RSS_HASH)
1658                         first_seg->hash.rss =
1659                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1660
1661                 if (pkt_flags & PKT_RX_FDIR)
1662                         pkt_flags |= iavf_rxd_build_fdir(&rxd, first_seg);
1663
1664                 first_seg->ol_flags |= pkt_flags;
1665
1666                 /* Prefetch data of first segment, if configured to do so. */
1667                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1668                                           first_seg->data_off));
1669                 rx_pkts[nb_rx++] = first_seg;
1670                 first_seg = NULL;
1671         }
1672
1673         /* Record index of the next RX descriptor to probe. */
1674         rxq->rx_tail = rx_id;
1675         rxq->pkt_first_seg = first_seg;
1676         rxq->pkt_last_seg = last_seg;
1677
1678         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1679
1680         return nb_rx;
1681 }
1682
1683 #define IAVF_LOOK_AHEAD 8
1684 static inline int
1685 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1686 {
1687         volatile union iavf_rx_flex_desc *rxdp;
1688         struct rte_mbuf **rxep;
1689         struct rte_mbuf *mb;
1690         uint16_t stat_err0;
1691         uint16_t pkt_len;
1692         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1693         int32_t i, j, nb_rx = 0;
1694         uint64_t pkt_flags;
1695         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1696
1697         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1698         rxep = &rxq->sw_ring[rxq->rx_tail];
1699
1700         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1701
1702         /* Make sure there is at least 1 packet to receive */
1703         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1704                 return 0;
1705
1706         /* Scan LOOK_AHEAD descriptors at a time to determine which
1707          * descriptors reference packets that are ready to be received.
1708          */
1709         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1710              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1711                 /* Read desc statuses backwards to avoid race condition */
1712                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1713                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1714
1715                 rte_smp_rmb();
1716
1717                 /* Compute how many status bits were set */
1718                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1719                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1720
1721                 nb_rx += nb_dd;
1722
1723                 /* Translate descriptor info to mbuf parameters */
1724                 for (j = 0; j < nb_dd; j++) {
1725                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1726                                           rxq->rx_tail +
1727                                           i * IAVF_LOOK_AHEAD + j);
1728
1729                         mb = rxep[j];
1730                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1731                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1732                         mb->data_len = pkt_len;
1733                         mb->pkt_len = pkt_len;
1734                         mb->ol_flags = 0;
1735
1736                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1737                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1738                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j], rxq->rx_flags);
1739                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1740                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1741                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1742
1743                         mb->ol_flags |= pkt_flags;
1744                 }
1745
1746                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1747                         rxq->rx_stage[i + j] = rxep[j];
1748
1749                 if (nb_dd != IAVF_LOOK_AHEAD)
1750                         break;
1751         }
1752
1753         /* Clear software ring entries */
1754         for (i = 0; i < nb_rx; i++)
1755                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1756
1757         return nb_rx;
1758 }
1759
1760 static inline int
1761 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1762 {
1763         volatile union iavf_rx_desc *rxdp;
1764         struct rte_mbuf **rxep;
1765         struct rte_mbuf *mb;
1766         uint16_t pkt_len;
1767         uint64_t qword1;
1768         uint32_t rx_status;
1769         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1770         int32_t i, j, nb_rx = 0;
1771         uint64_t pkt_flags;
1772         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1773
1774         rxdp = &rxq->rx_ring[rxq->rx_tail];
1775         rxep = &rxq->sw_ring[rxq->rx_tail];
1776
1777         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1778         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1779                     IAVF_RXD_QW1_STATUS_SHIFT;
1780
1781         /* Make sure there is at least 1 packet to receive */
1782         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1783                 return 0;
1784
1785         /* Scan LOOK_AHEAD descriptors at a time to determine which
1786          * descriptors reference packets that are ready to be received.
1787          */
1788         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1789              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1790                 /* Read desc statuses backwards to avoid race condition */
1791                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1792                         qword1 = rte_le_to_cpu_64(
1793                                 rxdp[j].wb.qword1.status_error_len);
1794                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1795                                IAVF_RXD_QW1_STATUS_SHIFT;
1796                 }
1797
1798                 rte_smp_rmb();
1799
1800                 /* Compute how many status bits were set */
1801                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1802                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1803
1804                 nb_rx += nb_dd;
1805
1806                 /* Translate descriptor info to mbuf parameters */
1807                 for (j = 0; j < nb_dd; j++) {
1808                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1809                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1810
1811                         mb = rxep[j];
1812                         qword1 = rte_le_to_cpu_64
1813                                         (rxdp[j].wb.qword1.status_error_len);
1814                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1815                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1816                         mb->data_len = pkt_len;
1817                         mb->pkt_len = pkt_len;
1818                         mb->ol_flags = 0;
1819                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1820                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1821                         mb->packet_type =
1822                                 ptype_tbl[(uint8_t)((qword1 &
1823                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1824                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1825
1826                         if (pkt_flags & PKT_RX_RSS_HASH)
1827                                 mb->hash.rss = rte_le_to_cpu_32(
1828                                         rxdp[j].wb.qword0.hi_dword.rss);
1829
1830                         if (pkt_flags & PKT_RX_FDIR)
1831                                 pkt_flags |= iavf_rxd_build_fdir(&rxdp[j], mb);
1832
1833                         mb->ol_flags |= pkt_flags;
1834                 }
1835
1836                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1837                         rxq->rx_stage[i + j] = rxep[j];
1838
1839                 if (nb_dd != IAVF_LOOK_AHEAD)
1840                         break;
1841         }
1842
1843         /* Clear software ring entries */
1844         for (i = 0; i < nb_rx; i++)
1845                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1846
1847         return nb_rx;
1848 }
1849
1850 static inline uint16_t
1851 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1852                        struct rte_mbuf **rx_pkts,
1853                        uint16_t nb_pkts)
1854 {
1855         uint16_t i;
1856         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1857
1858         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1859
1860         for (i = 0; i < nb_pkts; i++)
1861                 rx_pkts[i] = stage[i];
1862
1863         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1864         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1865
1866         return nb_pkts;
1867 }
1868
1869 static inline int
1870 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1871 {
1872         volatile union iavf_rx_desc *rxdp;
1873         struct rte_mbuf **rxep;
1874         struct rte_mbuf *mb;
1875         uint16_t alloc_idx, i;
1876         uint64_t dma_addr;
1877         int diag;
1878
1879         /* Allocate buffers in bulk */
1880         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1881                                 (rxq->rx_free_thresh - 1));
1882         rxep = &rxq->sw_ring[alloc_idx];
1883         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1884                                     rxq->rx_free_thresh);
1885         if (unlikely(diag != 0)) {
1886                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1887                 return -ENOMEM;
1888         }
1889
1890         rxdp = &rxq->rx_ring[alloc_idx];
1891         for (i = 0; i < rxq->rx_free_thresh; i++) {
1892                 if (likely(i < (rxq->rx_free_thresh - 1)))
1893                         /* Prefetch next mbuf */
1894                         rte_prefetch0(rxep[i + 1]);
1895
1896                 mb = rxep[i];
1897                 rte_mbuf_refcnt_set(mb, 1);
1898                 mb->next = NULL;
1899                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1900                 mb->nb_segs = 1;
1901                 mb->port = rxq->port_id;
1902                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1903                 rxdp[i].read.hdr_addr = 0;
1904                 rxdp[i].read.pkt_addr = dma_addr;
1905         }
1906
1907         /* Update rx tail register */
1908         rte_wmb();
1909         IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1910
1911         rxq->rx_free_trigger =
1912                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1913         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1914                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1915
1916         return 0;
1917 }
1918
1919 static inline uint16_t
1920 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1921 {
1922         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1923         uint16_t nb_rx = 0;
1924
1925         if (!nb_pkts)
1926                 return 0;
1927
1928         if (rxq->rx_nb_avail)
1929                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1930
1931         if (rxq->rxdid >= IAVF_RXDID_FLEX_NIC && rxq->rxdid <= IAVF_RXDID_LAST)
1932                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1933         else
1934                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1935         rxq->rx_next_avail = 0;
1936         rxq->rx_nb_avail = nb_rx;
1937         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1938
1939         if (rxq->rx_tail > rxq->rx_free_trigger) {
1940                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1941                         uint16_t i, j;
1942
1943                         /* TODO: count rx_mbuf_alloc_failed here */
1944
1945                         rxq->rx_nb_avail = 0;
1946                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1947                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1948                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1949
1950                         return 0;
1951                 }
1952         }
1953
1954         if (rxq->rx_tail >= rxq->nb_rx_desc)
1955                 rxq->rx_tail = 0;
1956
1957         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1958                    rxq->port_id, rxq->queue_id,
1959                    rxq->rx_tail, nb_rx);
1960
1961         if (rxq->rx_nb_avail)
1962                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1963
1964         return 0;
1965 }
1966
1967 static uint16_t
1968 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1969                          struct rte_mbuf **rx_pkts,
1970                          uint16_t nb_pkts)
1971 {
1972         uint16_t nb_rx = 0, n, count;
1973
1974         if (unlikely(nb_pkts == 0))
1975                 return 0;
1976
1977         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1978                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1979
1980         while (nb_pkts) {
1981                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1982                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1983                 nb_rx = (uint16_t)(nb_rx + count);
1984                 nb_pkts = (uint16_t)(nb_pkts - count);
1985                 if (count < n)
1986                         break;
1987         }
1988
1989         return nb_rx;
1990 }
1991
1992 static inline int
1993 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1994 {
1995         struct iavf_tx_entry *sw_ring = txq->sw_ring;
1996         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1997         uint16_t nb_tx_desc = txq->nb_tx_desc;
1998         uint16_t desc_to_clean_to;
1999         uint16_t nb_tx_to_clean;
2000
2001         volatile struct iavf_tx_desc *txd = txq->tx_ring;
2002
2003         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
2004         if (desc_to_clean_to >= nb_tx_desc)
2005                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2006
2007         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2008         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
2009                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
2010                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
2011                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2012                            "(port=%d queue=%d)", desc_to_clean_to,
2013                            txq->port_id, txq->queue_id);
2014                 return -1;
2015         }
2016
2017         if (last_desc_cleaned > desc_to_clean_to)
2018                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2019                                                         desc_to_clean_to);
2020         else
2021                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2022                                         last_desc_cleaned);
2023
2024         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2025
2026         txq->last_desc_cleaned = desc_to_clean_to;
2027         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
2028
2029         return 0;
2030 }
2031
2032 /* Check if the context descriptor is needed for TX offloading */
2033 static inline uint16_t
2034 iavf_calc_context_desc(uint64_t flags, uint8_t vlan_flag)
2035 {
2036         if (flags & PKT_TX_TCP_SEG)
2037                 return 1;
2038         if (flags & PKT_TX_VLAN_PKT &&
2039             vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2)
2040                 return 1;
2041         return 0;
2042 }
2043
2044 static inline void
2045 iavf_txd_enable_checksum(uint64_t ol_flags,
2046                         uint32_t *td_cmd,
2047                         uint32_t *td_offset,
2048                         union iavf_tx_offload tx_offload)
2049 {
2050         /* Set MACLEN */
2051         *td_offset |= (tx_offload.l2_len >> 1) <<
2052                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
2053
2054         /* Enable L3 checksum offloads */
2055         if (ol_flags & PKT_TX_IP_CKSUM) {
2056                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
2057                 *td_offset |= (tx_offload.l3_len >> 2) <<
2058                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2059         } else if (ol_flags & PKT_TX_IPV4) {
2060                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
2061                 *td_offset |= (tx_offload.l3_len >> 2) <<
2062                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2063         } else if (ol_flags & PKT_TX_IPV6) {
2064                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2065                 *td_offset |= (tx_offload.l3_len >> 2) <<
2066                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2067         }
2068
2069         if (ol_flags & PKT_TX_TCP_SEG) {
2070                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2071                 *td_offset |= (tx_offload.l4_len >> 2) <<
2072                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2073                 return;
2074         }
2075
2076         /* Enable L4 checksum offloads */
2077         switch (ol_flags & PKT_TX_L4_MASK) {
2078         case PKT_TX_TCP_CKSUM:
2079                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2080                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2081                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2082                 break;
2083         case PKT_TX_SCTP_CKSUM:
2084                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2085                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2086                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2087                 break;
2088         case PKT_TX_UDP_CKSUM:
2089                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2090                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2091                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2092                 break;
2093         default:
2094                 break;
2095         }
2096 }
2097
2098 /* set TSO context descriptor
2099  * support IP -> L4 and IP -> IP -> L4
2100  */
2101 static inline uint64_t
2102 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
2103 {
2104         uint64_t ctx_desc = 0;
2105         uint32_t cd_cmd, hdr_len, cd_tso_len;
2106
2107         if (!tx_offload.l4_len) {
2108                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2109                 return ctx_desc;
2110         }
2111
2112         hdr_len = tx_offload.l2_len +
2113                   tx_offload.l3_len +
2114                   tx_offload.l4_len;
2115
2116         cd_cmd = IAVF_TX_CTX_DESC_TSO;
2117         cd_tso_len = mbuf->pkt_len - hdr_len;
2118         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
2119                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2120                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
2121
2122         return ctx_desc;
2123 }
2124
2125 /* Construct the tx flags */
2126 static inline uint64_t
2127 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
2128                uint32_t td_tag)
2129 {
2130         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
2131                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
2132                                 ((uint64_t)td_offset <<
2133                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
2134                                 ((uint64_t)size  <<
2135                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
2136                                 ((uint64_t)td_tag  <<
2137                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
2138 }
2139
2140 /* TX function */
2141 uint16_t
2142 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2143 {
2144         volatile struct iavf_tx_desc *txd;
2145         volatile struct iavf_tx_desc *txr;
2146         struct iavf_tx_queue *txq;
2147         struct iavf_tx_entry *sw_ring;
2148         struct iavf_tx_entry *txe, *txn;
2149         struct rte_mbuf *tx_pkt;
2150         struct rte_mbuf *m_seg;
2151         uint16_t tx_id;
2152         uint16_t nb_tx;
2153         uint32_t td_cmd;
2154         uint32_t td_offset;
2155         uint32_t td_tag;
2156         uint64_t ol_flags;
2157         uint16_t nb_used;
2158         uint16_t nb_ctx;
2159         uint16_t tx_last;
2160         uint16_t slen;
2161         uint64_t buf_dma_addr;
2162         uint16_t cd_l2tag2 = 0;
2163         union iavf_tx_offload tx_offload = {0};
2164
2165         txq = tx_queue;
2166         sw_ring = txq->sw_ring;
2167         txr = txq->tx_ring;
2168         tx_id = txq->tx_tail;
2169         txe = &sw_ring[tx_id];
2170
2171         /* Check if the descriptor ring needs to be cleaned. */
2172         if (txq->nb_free < txq->free_thresh)
2173                 (void)iavf_xmit_cleanup(txq);
2174
2175         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2176                 td_cmd = 0;
2177                 td_tag = 0;
2178                 td_offset = 0;
2179
2180                 tx_pkt = *tx_pkts++;
2181                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
2182
2183                 ol_flags = tx_pkt->ol_flags;
2184                 tx_offload.l2_len = tx_pkt->l2_len;
2185                 tx_offload.l3_len = tx_pkt->l3_len;
2186                 tx_offload.l4_len = tx_pkt->l4_len;
2187                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2188                 /* Calculate the number of context descriptors needed. */
2189                 nb_ctx = iavf_calc_context_desc(ol_flags, txq->vlan_flag);
2190
2191                 /* The number of descriptors that must be allocated for
2192                  * a packet equals to the number of the segments of that
2193                  * packet plus 1 context descriptor if needed.
2194                  */
2195                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2196                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2197
2198                 /* Circular ring */
2199                 if (tx_last >= txq->nb_tx_desc)
2200                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2201
2202                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
2203                            " tx_first=%u tx_last=%u",
2204                            txq->port_id, txq->queue_id, tx_id, tx_last);
2205
2206                 if (nb_used > txq->nb_free) {
2207                         if (iavf_xmit_cleanup(txq)) {
2208                                 if (nb_tx == 0)
2209                                         return 0;
2210                                 goto end_of_tx;
2211                         }
2212                         if (unlikely(nb_used > txq->rs_thresh)) {
2213                                 while (nb_used > txq->nb_free) {
2214                                         if (iavf_xmit_cleanup(txq)) {
2215                                                 if (nb_tx == 0)
2216                                                         return 0;
2217                                                 goto end_of_tx;
2218                                         }
2219                                 }
2220                         }
2221                 }
2222
2223                 /* Descriptor based VLAN insertion */
2224                 if (ol_flags & PKT_TX_VLAN_PKT &&
2225                     txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
2226                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2227                         td_tag = tx_pkt->vlan_tci;
2228                 }
2229
2230                 /* According to datasheet, the bit2 is reserved and must be
2231                  * set to 1.
2232                  */
2233                 td_cmd |= 0x04;
2234
2235                 /* Enable checksum offloading */
2236                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
2237                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
2238                                                 &td_offset, tx_offload);
2239
2240                 if (nb_ctx) {
2241                         /* Setup TX context descriptor if required */
2242                         uint64_t cd_type_cmd_tso_mss =
2243                                 IAVF_TX_DESC_DTYPE_CONTEXT;
2244                         volatile struct iavf_tx_context_desc *ctx_txd =
2245                                 (volatile struct iavf_tx_context_desc *)
2246                                                         &txr[tx_id];
2247
2248                         txn = &sw_ring[txe->next_id];
2249                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2250                         if (txe->mbuf) {
2251                                 rte_pktmbuf_free_seg(txe->mbuf);
2252                                 txe->mbuf = NULL;
2253                         }
2254
2255                         /* TSO enabled */
2256                         if (ol_flags & PKT_TX_TCP_SEG)
2257                                 cd_type_cmd_tso_mss |=
2258                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
2259
2260                         if (ol_flags & PKT_TX_VLAN_PKT &&
2261                            txq->vlan_flag & IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2) {
2262                                 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2
2263                                         << IAVF_TXD_CTX_QW1_CMD_SHIFT;
2264                                 cd_l2tag2 = tx_pkt->vlan_tci;
2265                         }
2266
2267                         ctx_txd->type_cmd_tso_mss =
2268                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2269                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2270
2271                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
2272                         txe->last_id = tx_last;
2273                         tx_id = txe->next_id;
2274                         txe = txn;
2275                 }
2276
2277                 m_seg = tx_pkt;
2278                 do {
2279                         txd = &txr[tx_id];
2280                         txn = &sw_ring[txe->next_id];
2281
2282                         if (txe->mbuf)
2283                                 rte_pktmbuf_free_seg(txe->mbuf);
2284                         txe->mbuf = m_seg;
2285
2286                         /* Setup TX Descriptor */
2287                         slen = m_seg->data_len;
2288                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2289                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
2290                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
2291                                                                   td_offset,
2292                                                                   slen,
2293                                                                   td_tag);
2294
2295                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2296                         txe->last_id = tx_last;
2297                         tx_id = txe->next_id;
2298                         txe = txn;
2299                         m_seg = m_seg->next;
2300                 } while (m_seg);
2301
2302                 /* The last packet data descriptor needs End Of Packet (EOP) */
2303                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
2304                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
2305                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
2306
2307                 if (txq->nb_used >= txq->rs_thresh) {
2308                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
2309                                    "%4u (port=%d queue=%d)",
2310                                    tx_last, txq->port_id, txq->queue_id);
2311
2312                         td_cmd |= IAVF_TX_DESC_CMD_RS;
2313
2314                         /* Update txq RS bit counters */
2315                         txq->nb_used = 0;
2316                 }
2317
2318                 txd->cmd_type_offset_bsz |=
2319                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2320                                          IAVF_TXD_QW1_CMD_SHIFT);
2321                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2322         }
2323
2324 end_of_tx:
2325         rte_wmb();
2326
2327         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2328                    txq->port_id, txq->queue_id, tx_id, nb_tx);
2329
2330         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2331         txq->tx_tail = tx_id;
2332
2333         return nb_tx;
2334 }
2335
2336 /* TX prep functions */
2337 uint16_t
2338 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2339               uint16_t nb_pkts)
2340 {
2341         int i, ret;
2342         uint64_t ol_flags;
2343         struct rte_mbuf *m;
2344
2345         for (i = 0; i < nb_pkts; i++) {
2346                 m = tx_pkts[i];
2347                 ol_flags = m->ol_flags;
2348
2349                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2350                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2351                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2352                                 rte_errno = EINVAL;
2353                                 return i;
2354                         }
2355                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2356                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2357                         /* MSS outside the range are considered malicious */
2358                         rte_errno = EINVAL;
2359                         return i;
2360                 }
2361
2362                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2363                         rte_errno = ENOTSUP;
2364                         return i;
2365                 }
2366
2367 #ifdef RTE_ETHDEV_DEBUG_TX
2368                 ret = rte_validate_tx_offload(m);
2369                 if (ret != 0) {
2370                         rte_errno = -ret;
2371                         return i;
2372                 }
2373 #endif
2374                 ret = rte_net_intel_cksum_prepare(m);
2375                 if (ret != 0) {
2376                         rte_errno = -ret;
2377                         return i;
2378                 }
2379         }
2380
2381         return i;
2382 }
2383
2384 /* choose rx function*/
2385 void
2386 iavf_set_rx_function(struct rte_eth_dev *dev)
2387 {
2388         struct iavf_adapter *adapter =
2389                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2390         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2391
2392 #ifdef RTE_ARCH_X86
2393         struct iavf_rx_queue *rxq;
2394         int i;
2395         int check_ret;
2396         bool use_sse = false;
2397         bool use_avx2 = false;
2398         bool use_avx512 = false;
2399         bool use_flex = false;
2400
2401         check_ret = iavf_rx_vec_dev_check(dev);
2402         if (check_ret >= 0 &&
2403             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2404                 if (check_ret == IAVF_VECTOR_PATH) {
2405                         use_sse = true;
2406                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2407                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2408                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2409                                 use_avx2 = true;
2410                 }
2411
2412 #ifdef CC_AVX512_SUPPORT
2413                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2414                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2415                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2416                         use_avx512 = true;
2417 #endif
2418
2419                 if (!use_sse && !use_avx2 && !use_avx512)
2420                         goto normal;
2421
2422                 if (vf->vf_res->vf_cap_flags &
2423                         VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC) {
2424                         use_flex = true;
2425                         if (use_avx512 && check_ret == IAVF_VECTOR_OFFLOAD_PATH)
2426                                 use_flex = false;
2427                 }
2428
2429                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2430                         rxq = dev->data->rx_queues[i];
2431                         (void)iavf_rxq_vec_setup(rxq);
2432                 }
2433
2434                 if (dev->data->scattered_rx) {
2435                         if (!use_avx512) {
2436                                 PMD_DRV_LOG(DEBUG,
2437                                             "Using %sVector Scattered Rx (port %d).",
2438                                             use_avx2 ? "avx2 " : "",
2439                                             dev->data->port_id);
2440                         } else {
2441                                 if (check_ret == IAVF_VECTOR_PATH)
2442                                         PMD_DRV_LOG(DEBUG,
2443                                                     "Using AVX512 Vector Scattered Rx (port %d).",
2444                                                     dev->data->port_id);
2445                                 else
2446                                         PMD_DRV_LOG(DEBUG,
2447                                                     "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
2448                                                     dev->data->port_id);
2449                         }
2450                         if (use_flex) {
2451                                 dev->rx_pkt_burst = use_avx2 ?
2452                                         iavf_recv_scattered_pkts_vec_avx2_flex_rxd :
2453                                         iavf_recv_scattered_pkts_vec_flex_rxd;
2454 #ifdef CC_AVX512_SUPPORT
2455                                 if (use_avx512)
2456                                         dev->rx_pkt_burst =
2457                                                 iavf_recv_scattered_pkts_vec_avx512_flex_rxd;
2458 #endif
2459                         } else {
2460                                 dev->rx_pkt_burst = use_avx2 ?
2461                                         iavf_recv_scattered_pkts_vec_avx2 :
2462                                         iavf_recv_scattered_pkts_vec;
2463 #ifdef CC_AVX512_SUPPORT
2464                                 if (use_avx512) {
2465                                         if (check_ret == IAVF_VECTOR_PATH)
2466                                                 dev->rx_pkt_burst =
2467                                                         iavf_recv_scattered_pkts_vec_avx512;
2468                                         else
2469                                                 dev->rx_pkt_burst =
2470                                                         iavf_recv_scattered_pkts_vec_avx512_offload;
2471                                 }
2472 #endif
2473                         }
2474                 } else {
2475                         if (!use_avx512) {
2476                                 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2477                                             use_avx2 ? "avx2 " : "",
2478                                             dev->data->port_id);
2479                         } else {
2480                                 if (check_ret == IAVF_VECTOR_PATH)
2481                                         PMD_DRV_LOG(DEBUG,
2482                                                     "Using AVX512 Vector Rx (port %d).",
2483                                                     dev->data->port_id);
2484                                 else
2485                                         PMD_DRV_LOG(DEBUG,
2486                                                     "Using AVX512 OFFLOAD Vector Rx (port %d).",
2487                                                     dev->data->port_id);
2488                         }
2489                         if (use_flex) {
2490                                 dev->rx_pkt_burst = use_avx2 ?
2491                                         iavf_recv_pkts_vec_avx2_flex_rxd :
2492                                         iavf_recv_pkts_vec_flex_rxd;
2493 #ifdef CC_AVX512_SUPPORT
2494                                 if (use_avx512)
2495                                         dev->rx_pkt_burst =
2496                                                 iavf_recv_pkts_vec_avx512_flex_rxd;
2497 #endif
2498                         } else {
2499                                 dev->rx_pkt_burst = use_avx2 ?
2500                                         iavf_recv_pkts_vec_avx2 :
2501                                         iavf_recv_pkts_vec;
2502 #ifdef CC_AVX512_SUPPORT
2503                                 if (use_avx512) {
2504                                         if (check_ret == IAVF_VECTOR_PATH)
2505                                                 dev->rx_pkt_burst =
2506                                                         iavf_recv_pkts_vec_avx512;
2507                                         else
2508                                                 dev->rx_pkt_burst =
2509                                                         iavf_recv_pkts_vec_avx512_offload;
2510                                 }
2511 #endif
2512                         }
2513                 }
2514
2515                 return;
2516         }
2517
2518 normal:
2519 #endif
2520         if (dev->data->scattered_rx) {
2521                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2522                             dev->data->port_id);
2523                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2524                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2525                 else
2526                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2527         } else if (adapter->rx_bulk_alloc_allowed) {
2528                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2529                             dev->data->port_id);
2530                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2531         } else {
2532                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2533                             dev->data->port_id);
2534                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2535                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2536                 else
2537                         dev->rx_pkt_burst = iavf_recv_pkts;
2538         }
2539 }
2540
2541 /* choose tx function*/
2542 void
2543 iavf_set_tx_function(struct rte_eth_dev *dev)
2544 {
2545 #ifdef RTE_ARCH_X86
2546         struct iavf_tx_queue *txq;
2547         int i;
2548         int check_ret;
2549         bool use_sse = false;
2550         bool use_avx2 = false;
2551         bool use_avx512 = false;
2552
2553         check_ret = iavf_tx_vec_dev_check(dev);
2554
2555         if (check_ret >= 0 &&
2556             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
2557                 /* SSE and AVX2 not support offload path yet. */
2558                 if (check_ret == IAVF_VECTOR_PATH) {
2559                         use_sse = true;
2560                         if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2561                              rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
2562                             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2563                                 use_avx2 = true;
2564                 }
2565 #ifdef CC_AVX512_SUPPORT
2566                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
2567                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
2568                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
2569                         use_avx512 = true;
2570 #endif
2571
2572                 if (!use_sse && !use_avx2 && !use_avx512)
2573                         goto normal;
2574
2575                 if (!use_avx512) {
2576                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2577                                     use_avx2 ? "avx2 " : "",
2578                                     dev->data->port_id);
2579                         dev->tx_pkt_burst = use_avx2 ?
2580                                             iavf_xmit_pkts_vec_avx2 :
2581                                             iavf_xmit_pkts_vec;
2582                 }
2583 #ifdef CC_AVX512_SUPPORT
2584                 if (use_avx512) {
2585                         if (check_ret == IAVF_VECTOR_PATH) {
2586                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;
2587                                 PMD_DRV_LOG(DEBUG, "Using AVX512 Vector Tx (port %d).",
2588                                             dev->data->port_id);
2589                         } else {
2590                                 dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;
2591                                 PMD_DRV_LOG(DEBUG, "Using AVX512 OFFLOAD Vector Tx (port %d).",
2592                                             dev->data->port_id);
2593                         }
2594                 }
2595 #endif
2596                 dev->tx_pkt_prepare = NULL;
2597
2598                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2599                         txq = dev->data->tx_queues[i];
2600                         if (!txq)
2601                                 continue;
2602 #ifdef CC_AVX512_SUPPORT
2603                         if (use_avx512)
2604                                 iavf_txq_vec_setup_avx512(txq);
2605                         else
2606                                 iavf_txq_vec_setup(txq);
2607 #else
2608                         iavf_txq_vec_setup(txq);
2609 #endif
2610                 }
2611
2612                 return;
2613         }
2614
2615 normal:
2616 #endif
2617         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2618                     dev->data->port_id);
2619         dev->tx_pkt_burst = iavf_xmit_pkts;
2620         dev->tx_pkt_prepare = iavf_prep_pkts;
2621 }
2622
2623 static int
2624 iavf_tx_done_cleanup_full(struct iavf_tx_queue *txq,
2625                         uint32_t free_cnt)
2626 {
2627         struct iavf_tx_entry *swr_ring = txq->sw_ring;
2628         uint16_t i, tx_last, tx_id;
2629         uint16_t nb_tx_free_last;
2630         uint16_t nb_tx_to_clean;
2631         uint32_t pkt_cnt;
2632
2633         /* Start free mbuf from the next of tx_tail */
2634         tx_last = txq->tx_tail;
2635         tx_id  = swr_ring[tx_last].next_id;
2636
2637         if (txq->nb_free == 0 && iavf_xmit_cleanup(txq))
2638                 return 0;
2639
2640         nb_tx_to_clean = txq->nb_free;
2641         nb_tx_free_last = txq->nb_free;
2642         if (!free_cnt)
2643                 free_cnt = txq->nb_tx_desc;
2644
2645         /* Loop through swr_ring to count the amount of
2646          * freeable mubfs and packets.
2647          */
2648         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2649                 for (i = 0; i < nb_tx_to_clean &&
2650                         pkt_cnt < free_cnt &&
2651                         tx_id != tx_last; i++) {
2652                         if (swr_ring[tx_id].mbuf != NULL) {
2653                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2654                                 swr_ring[tx_id].mbuf = NULL;
2655
2656                                 /*
2657                                  * last segment in the packet,
2658                                  * increment packet count
2659                                  */
2660                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2661                         }
2662
2663                         tx_id = swr_ring[tx_id].next_id;
2664                 }
2665
2666                 if (txq->rs_thresh > txq->nb_tx_desc -
2667                         txq->nb_free || tx_id == tx_last)
2668                         break;
2669
2670                 if (pkt_cnt < free_cnt) {
2671                         if (iavf_xmit_cleanup(txq))
2672                                 break;
2673
2674                         nb_tx_to_clean = txq->nb_free - nb_tx_free_last;
2675                         nb_tx_free_last = txq->nb_free;
2676                 }
2677         }
2678
2679         return (int)pkt_cnt;
2680 }
2681
2682 int
2683 iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt)
2684 {
2685         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
2686
2687         return iavf_tx_done_cleanup_full(q, free_cnt);
2688 }
2689
2690 void
2691 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2692                      struct rte_eth_rxq_info *qinfo)
2693 {
2694         struct iavf_rx_queue *rxq;
2695
2696         rxq = dev->data->rx_queues[queue_id];
2697
2698         qinfo->mp = rxq->mp;
2699         qinfo->scattered_rx = dev->data->scattered_rx;
2700         qinfo->nb_desc = rxq->nb_rx_desc;
2701
2702         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2703         qinfo->conf.rx_drop_en = true;
2704         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2705 }
2706
2707 void
2708 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2709                      struct rte_eth_txq_info *qinfo)
2710 {
2711         struct iavf_tx_queue *txq;
2712
2713         txq = dev->data->tx_queues[queue_id];
2714
2715         qinfo->nb_desc = txq->nb_tx_desc;
2716
2717         qinfo->conf.tx_free_thresh = txq->free_thresh;
2718         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2719         qinfo->conf.offloads = txq->offloads;
2720         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2721 }
2722
2723 /* Get the number of used descriptors of a rx queue */
2724 uint32_t
2725 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2726 {
2727 #define IAVF_RXQ_SCAN_INTERVAL 4
2728         volatile union iavf_rx_desc *rxdp;
2729         struct iavf_rx_queue *rxq;
2730         uint16_t desc = 0;
2731
2732         rxq = dev->data->rx_queues[queue_id];
2733         rxdp = &rxq->rx_ring[rxq->rx_tail];
2734
2735         while ((desc < rxq->nb_rx_desc) &&
2736                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2737                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2738                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2739                 /* Check the DD bit of a rx descriptor of each 4 in a group,
2740                  * to avoid checking too frequently and downgrading performance
2741                  * too much.
2742                  */
2743                 desc += IAVF_RXQ_SCAN_INTERVAL;
2744                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2745                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2746                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2747                                         desc - rxq->nb_rx_desc]);
2748         }
2749
2750         return desc;
2751 }
2752
2753 int
2754 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2755 {
2756         struct iavf_rx_queue *rxq = rx_queue;
2757         volatile uint64_t *status;
2758         uint64_t mask;
2759         uint32_t desc;
2760
2761         if (unlikely(offset >= rxq->nb_rx_desc))
2762                 return -EINVAL;
2763
2764         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2765                 return RTE_ETH_RX_DESC_UNAVAIL;
2766
2767         desc = rxq->rx_tail + offset;
2768         if (desc >= rxq->nb_rx_desc)
2769                 desc -= rxq->nb_rx_desc;
2770
2771         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2772         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2773                 << IAVF_RXD_QW1_STATUS_SHIFT);
2774         if (*status & mask)
2775                 return RTE_ETH_RX_DESC_DONE;
2776
2777         return RTE_ETH_RX_DESC_AVAIL;
2778 }
2779
2780 int
2781 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2782 {
2783         struct iavf_tx_queue *txq = tx_queue;
2784         volatile uint64_t *status;
2785         uint64_t mask, expect;
2786         uint32_t desc;
2787
2788         if (unlikely(offset >= txq->nb_tx_desc))
2789                 return -EINVAL;
2790
2791         desc = txq->tx_tail + offset;
2792         /* go to next desc that has the RS bit */
2793         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2794                 txq->rs_thresh;
2795         if (desc >= txq->nb_tx_desc) {
2796                 desc -= txq->nb_tx_desc;
2797                 if (desc >= txq->nb_tx_desc)
2798                         desc -= txq->nb_tx_desc;
2799         }
2800
2801         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2802         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2803         expect = rte_cpu_to_le_64(
2804                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2805         if ((*status & mask) == expect)
2806                 return RTE_ETH_TX_DESC_DONE;
2807
2808         return RTE_ETH_TX_DESC_FULL;
2809 }
2810
2811 const uint32_t *
2812 iavf_get_default_ptype_table(void)
2813 {
2814         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2815                 __rte_cache_aligned = {
2816                 /* L2 types */
2817                 /* [0] reserved */
2818                 [1] = RTE_PTYPE_L2_ETHER,
2819                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2820                 /* [3] - [5] reserved */
2821                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2822                 /* [7] - [10] reserved */
2823                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2824                 /* [12] - [21] reserved */
2825
2826                 /* Non tunneled IPv4 */
2827                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2828                        RTE_PTYPE_L4_FRAG,
2829                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2830                        RTE_PTYPE_L4_NONFRAG,
2831                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2832                        RTE_PTYPE_L4_UDP,
2833                 /* [25] reserved */
2834                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2835                        RTE_PTYPE_L4_TCP,
2836                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2837                        RTE_PTYPE_L4_SCTP,
2838                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2839                        RTE_PTYPE_L4_ICMP,
2840
2841                 /* IPv4 --> IPv4 */
2842                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2843                        RTE_PTYPE_TUNNEL_IP |
2844                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2845                        RTE_PTYPE_INNER_L4_FRAG,
2846                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2847                        RTE_PTYPE_TUNNEL_IP |
2848                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2849                        RTE_PTYPE_INNER_L4_NONFRAG,
2850                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2851                        RTE_PTYPE_TUNNEL_IP |
2852                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2853                        RTE_PTYPE_INNER_L4_UDP,
2854                 /* [32] reserved */
2855                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2856                        RTE_PTYPE_TUNNEL_IP |
2857                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2858                        RTE_PTYPE_INNER_L4_TCP,
2859                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2860                        RTE_PTYPE_TUNNEL_IP |
2861                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2862                        RTE_PTYPE_INNER_L4_SCTP,
2863                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2864                        RTE_PTYPE_TUNNEL_IP |
2865                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2866                        RTE_PTYPE_INNER_L4_ICMP,
2867
2868                 /* IPv4 --> IPv6 */
2869                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2870                        RTE_PTYPE_TUNNEL_IP |
2871                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2872                        RTE_PTYPE_INNER_L4_FRAG,
2873                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2874                        RTE_PTYPE_TUNNEL_IP |
2875                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2876                        RTE_PTYPE_INNER_L4_NONFRAG,
2877                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2878                        RTE_PTYPE_TUNNEL_IP |
2879                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2880                        RTE_PTYPE_INNER_L4_UDP,
2881                 /* [39] reserved */
2882                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2883                        RTE_PTYPE_TUNNEL_IP |
2884                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2885                        RTE_PTYPE_INNER_L4_TCP,
2886                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2887                        RTE_PTYPE_TUNNEL_IP |
2888                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2889                        RTE_PTYPE_INNER_L4_SCTP,
2890                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2891                        RTE_PTYPE_TUNNEL_IP |
2892                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2893                        RTE_PTYPE_INNER_L4_ICMP,
2894
2895                 /* IPv4 --> GRE/Teredo/VXLAN */
2896                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2897                        RTE_PTYPE_TUNNEL_GRENAT,
2898
2899                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2900                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2901                        RTE_PTYPE_TUNNEL_GRENAT |
2902                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2903                        RTE_PTYPE_INNER_L4_FRAG,
2904                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2905                        RTE_PTYPE_TUNNEL_GRENAT |
2906                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2907                        RTE_PTYPE_INNER_L4_NONFRAG,
2908                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2909                        RTE_PTYPE_TUNNEL_GRENAT |
2910                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2911                        RTE_PTYPE_INNER_L4_UDP,
2912                 /* [47] reserved */
2913                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2914                        RTE_PTYPE_TUNNEL_GRENAT |
2915                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2916                        RTE_PTYPE_INNER_L4_TCP,
2917                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2918                        RTE_PTYPE_TUNNEL_GRENAT |
2919                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2920                        RTE_PTYPE_INNER_L4_SCTP,
2921                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2922                        RTE_PTYPE_TUNNEL_GRENAT |
2923                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2924                        RTE_PTYPE_INNER_L4_ICMP,
2925
2926                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2927                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2928                        RTE_PTYPE_TUNNEL_GRENAT |
2929                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2930                        RTE_PTYPE_INNER_L4_FRAG,
2931                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2932                        RTE_PTYPE_TUNNEL_GRENAT |
2933                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2934                        RTE_PTYPE_INNER_L4_NONFRAG,
2935                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2936                        RTE_PTYPE_TUNNEL_GRENAT |
2937                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2938                        RTE_PTYPE_INNER_L4_UDP,
2939                 /* [54] reserved */
2940                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2941                        RTE_PTYPE_TUNNEL_GRENAT |
2942                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2943                        RTE_PTYPE_INNER_L4_TCP,
2944                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2945                        RTE_PTYPE_TUNNEL_GRENAT |
2946                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2947                        RTE_PTYPE_INNER_L4_SCTP,
2948                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2949                        RTE_PTYPE_TUNNEL_GRENAT |
2950                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2951                        RTE_PTYPE_INNER_L4_ICMP,
2952
2953                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2954                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2955                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2956
2957                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2958                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2959                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2960                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2961                        RTE_PTYPE_INNER_L4_FRAG,
2962                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2963                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2964                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2965                        RTE_PTYPE_INNER_L4_NONFRAG,
2966                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2967                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2968                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2969                        RTE_PTYPE_INNER_L4_UDP,
2970                 /* [62] reserved */
2971                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2972                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2973                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2974                        RTE_PTYPE_INNER_L4_TCP,
2975                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2976                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2977                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2978                        RTE_PTYPE_INNER_L4_SCTP,
2979                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2980                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2981                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2982                        RTE_PTYPE_INNER_L4_ICMP,
2983
2984                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2985                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2986                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2987                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2988                        RTE_PTYPE_INNER_L4_FRAG,
2989                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2990                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2991                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2992                        RTE_PTYPE_INNER_L4_NONFRAG,
2993                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2994                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2995                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2996                        RTE_PTYPE_INNER_L4_UDP,
2997                 /* [69] reserved */
2998                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2999                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3000                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3001                        RTE_PTYPE_INNER_L4_TCP,
3002                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3003                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3004                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3005                        RTE_PTYPE_INNER_L4_SCTP,
3006                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3007                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3008                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3009                        RTE_PTYPE_INNER_L4_ICMP,
3010                 /* [73] - [87] reserved */
3011
3012                 /* Non tunneled IPv6 */
3013                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3014                        RTE_PTYPE_L4_FRAG,
3015                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3016                        RTE_PTYPE_L4_NONFRAG,
3017                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3018                        RTE_PTYPE_L4_UDP,
3019                 /* [91] reserved */
3020                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3021                        RTE_PTYPE_L4_TCP,
3022                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3023                        RTE_PTYPE_L4_SCTP,
3024                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3025                        RTE_PTYPE_L4_ICMP,
3026
3027                 /* IPv6 --> IPv4 */
3028                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3029                        RTE_PTYPE_TUNNEL_IP |
3030                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3031                        RTE_PTYPE_INNER_L4_FRAG,
3032                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3033                        RTE_PTYPE_TUNNEL_IP |
3034                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3035                        RTE_PTYPE_INNER_L4_NONFRAG,
3036                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3037                        RTE_PTYPE_TUNNEL_IP |
3038                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3039                        RTE_PTYPE_INNER_L4_UDP,
3040                 /* [98] reserved */
3041                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3042                        RTE_PTYPE_TUNNEL_IP |
3043                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3044                        RTE_PTYPE_INNER_L4_TCP,
3045                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3046                         RTE_PTYPE_TUNNEL_IP |
3047                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3048                         RTE_PTYPE_INNER_L4_SCTP,
3049                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3050                         RTE_PTYPE_TUNNEL_IP |
3051                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3052                         RTE_PTYPE_INNER_L4_ICMP,
3053
3054                 /* IPv6 --> IPv6 */
3055                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3056                         RTE_PTYPE_TUNNEL_IP |
3057                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3058                         RTE_PTYPE_INNER_L4_FRAG,
3059                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3060                         RTE_PTYPE_TUNNEL_IP |
3061                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3062                         RTE_PTYPE_INNER_L4_NONFRAG,
3063                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3064                         RTE_PTYPE_TUNNEL_IP |
3065                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3066                         RTE_PTYPE_INNER_L4_UDP,
3067                 /* [105] reserved */
3068                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3069                         RTE_PTYPE_TUNNEL_IP |
3070                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3071                         RTE_PTYPE_INNER_L4_TCP,
3072                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3073                         RTE_PTYPE_TUNNEL_IP |
3074                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3075                         RTE_PTYPE_INNER_L4_SCTP,
3076                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3077                         RTE_PTYPE_TUNNEL_IP |
3078                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3079                         RTE_PTYPE_INNER_L4_ICMP,
3080
3081                 /* IPv6 --> GRE/Teredo/VXLAN */
3082                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3083                         RTE_PTYPE_TUNNEL_GRENAT,
3084
3085                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3086                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3087                         RTE_PTYPE_TUNNEL_GRENAT |
3088                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3089                         RTE_PTYPE_INNER_L4_FRAG,
3090                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3091                         RTE_PTYPE_TUNNEL_GRENAT |
3092                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3093                         RTE_PTYPE_INNER_L4_NONFRAG,
3094                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3095                         RTE_PTYPE_TUNNEL_GRENAT |
3096                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3097                         RTE_PTYPE_INNER_L4_UDP,
3098                 /* [113] reserved */
3099                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3100                         RTE_PTYPE_TUNNEL_GRENAT |
3101                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3102                         RTE_PTYPE_INNER_L4_TCP,
3103                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3104                         RTE_PTYPE_TUNNEL_GRENAT |
3105                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3106                         RTE_PTYPE_INNER_L4_SCTP,
3107                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3108                         RTE_PTYPE_TUNNEL_GRENAT |
3109                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3110                         RTE_PTYPE_INNER_L4_ICMP,
3111
3112                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3113                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3114                         RTE_PTYPE_TUNNEL_GRENAT |
3115                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3116                         RTE_PTYPE_INNER_L4_FRAG,
3117                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3118                         RTE_PTYPE_TUNNEL_GRENAT |
3119                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3120                         RTE_PTYPE_INNER_L4_NONFRAG,
3121                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3122                         RTE_PTYPE_TUNNEL_GRENAT |
3123                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3124                         RTE_PTYPE_INNER_L4_UDP,
3125                 /* [120] reserved */
3126                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3127                         RTE_PTYPE_TUNNEL_GRENAT |
3128                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3129                         RTE_PTYPE_INNER_L4_TCP,
3130                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3131                         RTE_PTYPE_TUNNEL_GRENAT |
3132                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3133                         RTE_PTYPE_INNER_L4_SCTP,
3134                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3135                         RTE_PTYPE_TUNNEL_GRENAT |
3136                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3137                         RTE_PTYPE_INNER_L4_ICMP,
3138
3139                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3140                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3141                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3142
3143                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3144                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3145                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3146                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3147                         RTE_PTYPE_INNER_L4_FRAG,
3148                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3149                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3150                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3151                         RTE_PTYPE_INNER_L4_NONFRAG,
3152                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3153                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3154                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3155                         RTE_PTYPE_INNER_L4_UDP,
3156                 /* [128] reserved */
3157                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3158                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3159                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3160                         RTE_PTYPE_INNER_L4_TCP,
3161                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3162                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3163                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3164                         RTE_PTYPE_INNER_L4_SCTP,
3165                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3166                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3167                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3168                         RTE_PTYPE_INNER_L4_ICMP,
3169
3170                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3171                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3172                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3173                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3174                         RTE_PTYPE_INNER_L4_FRAG,
3175                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3176                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3177                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3178                         RTE_PTYPE_INNER_L4_NONFRAG,
3179                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3180                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3181                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3182                         RTE_PTYPE_INNER_L4_UDP,
3183                 /* [135] reserved */
3184                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3185                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3186                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3187                         RTE_PTYPE_INNER_L4_TCP,
3188                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3189                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3190                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3191                         RTE_PTYPE_INNER_L4_SCTP,
3192                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3193                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3194                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3195                         RTE_PTYPE_INNER_L4_ICMP,
3196                 /* [139] - [299] reserved */
3197
3198                 /* PPPoE */
3199                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3200                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3201
3202                 /* PPPoE --> IPv4 */
3203                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3204                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3205                         RTE_PTYPE_L4_FRAG,
3206                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3207                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208                         RTE_PTYPE_L4_NONFRAG,
3209                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3210                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3211                         RTE_PTYPE_L4_UDP,
3212                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3213                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3214                         RTE_PTYPE_L4_TCP,
3215                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3216                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3217                         RTE_PTYPE_L4_SCTP,
3218                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3219                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3220                         RTE_PTYPE_L4_ICMP,
3221
3222                 /* PPPoE --> IPv6 */
3223                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3224                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3225                         RTE_PTYPE_L4_FRAG,
3226                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3227                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3228                         RTE_PTYPE_L4_NONFRAG,
3229                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3230                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3231                         RTE_PTYPE_L4_UDP,
3232                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3233                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3234                         RTE_PTYPE_L4_TCP,
3235                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3236                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3237                         RTE_PTYPE_L4_SCTP,
3238                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3239                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3240                         RTE_PTYPE_L4_ICMP,
3241                 /* [314] - [324] reserved */
3242
3243                 /* IPv4/IPv6 --> GTPC/GTPU */
3244                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3245                         RTE_PTYPE_TUNNEL_GTPC,
3246                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3247                         RTE_PTYPE_TUNNEL_GTPC,
3248                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3249                         RTE_PTYPE_TUNNEL_GTPC,
3250                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3251                         RTE_PTYPE_TUNNEL_GTPC,
3252                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3253                         RTE_PTYPE_TUNNEL_GTPU,
3254                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3255                         RTE_PTYPE_TUNNEL_GTPU,
3256
3257                 /* IPv4 --> GTPU --> IPv4 */
3258                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3259                         RTE_PTYPE_TUNNEL_GTPU |
3260                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3261                         RTE_PTYPE_INNER_L4_FRAG,
3262                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3263                         RTE_PTYPE_TUNNEL_GTPU |
3264                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3265                         RTE_PTYPE_INNER_L4_NONFRAG,
3266                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3267                         RTE_PTYPE_TUNNEL_GTPU |
3268                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3269                         RTE_PTYPE_INNER_L4_UDP,
3270                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3271                         RTE_PTYPE_TUNNEL_GTPU |
3272                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3273                         RTE_PTYPE_INNER_L4_TCP,
3274                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3275                         RTE_PTYPE_TUNNEL_GTPU |
3276                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3277                         RTE_PTYPE_INNER_L4_ICMP,
3278
3279                 /* IPv6 --> GTPU --> IPv4 */
3280                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3281                         RTE_PTYPE_TUNNEL_GTPU |
3282                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3283                         RTE_PTYPE_INNER_L4_FRAG,
3284                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3285                         RTE_PTYPE_TUNNEL_GTPU |
3286                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3287                         RTE_PTYPE_INNER_L4_NONFRAG,
3288                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3289                         RTE_PTYPE_TUNNEL_GTPU |
3290                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3291                         RTE_PTYPE_INNER_L4_UDP,
3292                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3293                         RTE_PTYPE_TUNNEL_GTPU |
3294                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3295                         RTE_PTYPE_INNER_L4_TCP,
3296                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3297                         RTE_PTYPE_TUNNEL_GTPU |
3298                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3299                         RTE_PTYPE_INNER_L4_ICMP,
3300
3301                 /* IPv4 --> GTPU --> IPv6 */
3302                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3303                         RTE_PTYPE_TUNNEL_GTPU |
3304                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3305                         RTE_PTYPE_INNER_L4_FRAG,
3306                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3307                         RTE_PTYPE_TUNNEL_GTPU |
3308                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3309                         RTE_PTYPE_INNER_L4_NONFRAG,
3310                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3311                         RTE_PTYPE_TUNNEL_GTPU |
3312                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3313                         RTE_PTYPE_INNER_L4_UDP,
3314                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3315                         RTE_PTYPE_TUNNEL_GTPU |
3316                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3317                         RTE_PTYPE_INNER_L4_TCP,
3318                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3319                         RTE_PTYPE_TUNNEL_GTPU |
3320                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3321                         RTE_PTYPE_INNER_L4_ICMP,
3322
3323                 /* IPv6 --> GTPU --> IPv6 */
3324                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3325                         RTE_PTYPE_TUNNEL_GTPU |
3326                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3327                         RTE_PTYPE_INNER_L4_FRAG,
3328                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3329                         RTE_PTYPE_TUNNEL_GTPU |
3330                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3331                         RTE_PTYPE_INNER_L4_NONFRAG,
3332                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3333                         RTE_PTYPE_TUNNEL_GTPU |
3334                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3335                         RTE_PTYPE_INNER_L4_UDP,
3336                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3337                         RTE_PTYPE_TUNNEL_GTPU |
3338                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3339                         RTE_PTYPE_INNER_L4_TCP,
3340                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3341                         RTE_PTYPE_TUNNEL_GTPU |
3342                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3343                         RTE_PTYPE_INNER_L4_ICMP,
3344
3345                 /* IPv4 --> UDP ECPRI */
3346                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3347                         RTE_PTYPE_L4_UDP,
3348                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3349                         RTE_PTYPE_L4_UDP,
3350                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3351                         RTE_PTYPE_L4_UDP,
3352                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3353                         RTE_PTYPE_L4_UDP,
3354                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3355                         RTE_PTYPE_L4_UDP,
3356                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3357                         RTE_PTYPE_L4_UDP,
3358                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3359                         RTE_PTYPE_L4_UDP,
3360                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3361                         RTE_PTYPE_L4_UDP,
3362                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3363                         RTE_PTYPE_L4_UDP,
3364                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3365                         RTE_PTYPE_L4_UDP,
3366
3367                 /* IPV6 --> UDP ECPRI */
3368                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3369                         RTE_PTYPE_L4_UDP,
3370                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3371                         RTE_PTYPE_L4_UDP,
3372                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3373                         RTE_PTYPE_L4_UDP,
3374                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3375                         RTE_PTYPE_L4_UDP,
3376                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3377                         RTE_PTYPE_L4_UDP,
3378                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3379                         RTE_PTYPE_L4_UDP,
3380                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3381                         RTE_PTYPE_L4_UDP,
3382                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3383                         RTE_PTYPE_L4_UDP,
3384                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3385                         RTE_PTYPE_L4_UDP,
3386                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3387                         RTE_PTYPE_L4_UDP,
3388                 /* All others reserved */
3389         };
3390
3391         return ptype_tbl;
3392 }