drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_NO_VECTOR_FLAGS (                           \
  27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
  28                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
  29                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
  30                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
  31                 DEV_TX_OFFLOAD_TCP_TSO |                 \
  32                 DEV_TX_OFFLOAD_TCP_CKSUM)
  33
  34 #define DEFAULT_TX_RS_THRESH     32
  35 #define DEFAULT_TX_FREE_THRESH   32
  36
  37 #define IAVF_MIN_TSO_MSS          256
  38 #define IAVF_MAX_TSO_MSS          9668
  39 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  40 #define IAVF_TX_MAX_MTU_SEG       8
  41
  42 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  43                 PKT_TX_IP_CKSUM |                \
  44                 PKT_TX_L4_MASK |                 \
  45                 PKT_TX_TCP_SEG)
  46
  47 #define IAVF_TX_OFFLOAD_MASK (  \
  48                 PKT_TX_OUTER_IPV6 |              \
  49                 PKT_TX_OUTER_IPV4 |              \
  50                 PKT_TX_IPV6 |                    \
  51                 PKT_TX_IPV4 |                    \
  52                 PKT_TX_VLAN_PKT |                \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG)
  56
  57 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  58                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  59
  60 /* HW desc structure, both 16-byte and 32-byte types are supported */
  61 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  62 #define iavf_rx_desc iavf_16byte_rx_desc
  63 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
  64 #else
  65 #define iavf_rx_desc iavf_32byte_rx_desc
  66 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
  67 #endif
  68
  69 struct iavf_rxq_ops {
  70         void (*release_mbufs)(struct iavf_rx_queue *rxq);
  71 };
  72
  73 struct iavf_txq_ops {
  74         void (*release_mbufs)(struct iavf_tx_queue *txq);
  75 };
  76
  77 /* Structure associated with each Rx queue. */
  78 struct iavf_rx_queue {
  79         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
  80         const struct rte_memzone *mz; /* memzone for Rx ring */
  81         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
  82         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
  83         struct rte_mbuf **sw_ring;     /* address of SW ring */
  84         uint16_t nb_rx_desc;          /* ring length */
  85         uint16_t rx_tail;             /* current value of tail */
  86         volatile uint8_t *qrx_tail;   /* register address of tail */
  87         uint16_t rx_free_thresh;      /* max free RX desc to hold */
  88         uint16_t nb_rx_hold;          /* number of held free RX desc */
  89         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
  90         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
  91         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
  92         uint8_t rxdid;
  93
  94         /* used for VPMD */
  95         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
  96         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
  97         uint64_t mbuf_initializer; /* value to init mbufs */
  98
  99         /* for rx bulk */
 100         uint16_t rx_nb_avail;      /* number of staged packets ready */
 101         uint16_t rx_next_avail;    /* index of next staged packets */
 102         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 103         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 104
 105         uint16_t port_id;        /* device port ID */
 106         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 107         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 108         uint16_t queue_id;      /* Rx queue index */
 109         uint16_t rx_buf_len;    /* The packet buffer size */
 110         uint16_t rx_hdr_len;    /* The header buffer size */
 111         uint16_t max_pkt_len;   /* Maximum packet length */
 112         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 113
 114         bool q_set;             /* if rx queue has been configured */
 115         bool rx_deferred_start; /* don't start this queue in dev start */
 116         const struct iavf_rxq_ops *ops;
 117 };
 118
 119 struct iavf_tx_entry {
 120         struct rte_mbuf *mbuf;
 121         uint16_t next_id;
 122         uint16_t last_id;
 123 };
 124
 125 struct iavf_tx_vec_entry {
 126         struct rte_mbuf *mbuf;
 127 };
 128
 129 /* Structure associated with each TX queue. */
 130 struct iavf_tx_queue {
 131         const struct rte_memzone *mz;  /* memzone for Tx ring */
 132         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 133         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 134         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 135         uint16_t nb_tx_desc;           /* ring length */
 136         uint16_t tx_tail;              /* current value of tail */
 137         volatile uint8_t *qtx_tail;    /* register address of tail */
 138         /* number of used desc since RS bit set */
 139         uint16_t nb_used;
 140         uint16_t nb_free;
 141         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 142         uint16_t free_thresh;
 143         uint16_t rs_thresh;
 144
 145         uint16_t port_id;
 146         uint16_t queue_id;
 147         uint64_t offloads;
 148         uint16_t next_dd;              /* next to set RS, for VPMD */
 149         uint16_t next_rs;              /* next to check DD,  for VPMD */
 150
 151         bool q_set;                    /* if rx queue has been configured */
 152         bool tx_deferred_start;        /* don't start this queue in dev start */
 153         const struct iavf_txq_ops *ops;
 154 };
 155
 156 /* Offload features */
 157 union iavf_tx_offload {
 158         uint64_t data;
 159         struct {
 160                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 161                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 162                 uint64_t l4_len:8; /* L4 Header Length. */
 163                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 164                 /* uint64_t unused : 24; */
 165         };
 166 };
 167
 168 /* Rx Flex Descriptors
 169  * These descriptors are used instead of the legacy version descriptors
 170  */
 171 union iavf_16b_rx_flex_desc {
 172         struct {
 173                 __le64 pkt_addr; /* Packet buffer address */
 174                 __le64 hdr_addr; /* Header buffer address */
 175                                  /* bit 0 of hdr_addr is DD bit */
 176         } read;
 177         struct {
 178                 /* Qword 0 */
 179                 u8 rxdid; /* descriptor builder profile ID */
 180                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 181                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 182                 __le16 pkt_len; /* [15:14] are reserved */
 183                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 184                                                 /* sph=[11:11] */
 185                                                 /* ff1/ext=[15:12] */
 186
 187                 /* Qword 1 */
 188                 __le16 status_error0;
 189                 __le16 l2tag1;
 190                 __le16 flex_meta0;
 191                 __le16 flex_meta1;
 192         } wb; /* writeback */
 193 };
 194
 195 union iavf_32b_rx_flex_desc {
 196         struct {
 197                 __le64 pkt_addr; /* Packet buffer address */
 198                 __le64 hdr_addr; /* Header buffer address */
 199                                  /* bit 0 of hdr_addr is DD bit */
 200                 __le64 rsvd1;
 201                 __le64 rsvd2;
 202         } read;
 203         struct {
 204                 /* Qword 0 */
 205                 u8 rxdid; /* descriptor builder profile ID */
 206                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 207                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 208                 __le16 pkt_len; /* [15:14] are reserved */
 209                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 210                                                 /* sph=[11:11] */
 211                                                 /* ff1/ext=[15:12] */
 212
 213                 /* Qword 1 */
 214                 __le16 status_error0;
 215                 __le16 l2tag1;
 216                 __le16 flex_meta0;
 217                 __le16 flex_meta1;
 218
 219                 /* Qword 2 */
 220                 __le16 status_error1;
 221                 u8 flex_flags2;
 222                 u8 time_stamp_low;
 223                 __le16 l2tag2_1st;
 224                 __le16 l2tag2_2nd;
 225
 226                 /* Qword 3 */
 227                 __le16 flex_meta2;
 228                 __le16 flex_meta3;
 229                 union {
 230                         struct {
 231                                 __le16 flex_meta4;
 232                                 __le16 flex_meta5;
 233                         } flex;
 234                         __le32 ts_high;
 235                 } flex_ts;
 236         } wb; /* writeback */
 237 };
 238
 239 /* Rx Flex Descriptor
 240  * RxDID Profile ID 16-21
 241  * Flex-field 0: RSS hash lower 16-bits
 242  * Flex-field 1: RSS hash upper 16-bits
 243  * Flex-field 2: Flow ID lower 16-bits
 244  * Flex-field 3: Flow ID upper 16-bits
 245  * Flex-field 4: AUX0
 246  * Flex-field 5: AUX1
 247  */
 248 struct iavf_32b_rx_flex_desc_comms {
 249         /* Qword 0 */
 250         u8 rxdid;
 251         u8 mir_id_umb_cast;
 252         __le16 ptype_flexi_flags0;
 253         __le16 pkt_len;
 254         __le16 hdr_len_sph_flex_flags1;
 255
 256         /* Qword 1 */
 257         __le16 status_error0;
 258         __le16 l2tag1;
 259         __le32 rss_hash;
 260
 261         /* Qword 2 */
 262         __le16 status_error1;
 263         u8 flexi_flags2;
 264         u8 ts_low;
 265         __le16 l2tag2_1st;
 266         __le16 l2tag2_2nd;
 267
 268         /* Qword 3 */
 269         __le32 flow_id;
 270         union {
 271                 struct {
 272                         __le16 aux0;
 273                         __le16 aux1;
 274                 } flex;
 275                 __le32 ts_high;
 276         } flex_ts;
 277 };
 278
 279 /* Rx Flex Descriptor
 280  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 281  * Flex-field 0: Flow ID lower 16-bits
 282  * Flex-field 1: Flow ID upper 16-bits
 283  * Flex-field 2: RSS hash lower 16-bits
 284  * Flex-field 3: RSS hash upper 16-bits
 285  * Flex-field 4: AUX0
 286  * Flex-field 5: AUX1
 287  */
 288 struct iavf_32b_rx_flex_desc_comms_ovs {
 289         /* Qword 0 */
 290         u8 rxdid;
 291         u8 mir_id_umb_cast;
 292         __le16 ptype_flexi_flags0;
 293         __le16 pkt_len;
 294         __le16 hdr_len_sph_flex_flags1;
 295
 296         /* Qword 1 */
 297         __le16 status_error0;
 298         __le16 l2tag1;
 299         __le32 flow_id;
 300
 301         /* Qword 2 */
 302         __le16 status_error1;
 303         u8 flexi_flags2;
 304         u8 ts_low;
 305         __le16 l2tag2_1st;
 306         __le16 l2tag2_2nd;
 307
 308         /* Qword 3 */
 309         __le32 rss_hash;
 310         union {
 311                 struct {
 312                         __le16 aux0;
 313                         __le16 aux1;
 314                 } flex;
 315                 __le32 ts_high;
 316         } flex_ts;
 317 };
 318
 319 /* Receive Flex Descriptor profile IDs: There are a total
 320  * of 64 profiles where profile IDs 0/1 are for legacy; and
 321  * profiles 2-63 are flex profiles that can be programmed
 322  * with a specific metadata (profile 7 reserved for HW)
 323  */
 324 enum iavf_rxdid {
 325         IAVF_RXDID_LEGACY_0             = 0,
 326         IAVF_RXDID_LEGACY_1             = 1,
 327         IAVF_RXDID_FLEX_NIC             = 2,
 328         IAVF_RXDID_FLEX_NIC_2           = 6,
 329         IAVF_RXDID_HW                   = 7,
 330         IAVF_RXDID_COMMS_GENERIC        = 16,
 331         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 332         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 333         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 334         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 335         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 336         IAVF_RXDID_COMMS_OVS_1          = 22,
 337         IAVF_RXDID_COMMS_OVS_2          = 23,
 338         IAVF_RXDID_LAST                 = 63,
 339 };
 340
 341 enum iavf_rx_flex_desc_status_error_0_bits {
 342         /* Note: These are predefined bit offsets */
 343         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 344         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 345         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 346         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 347         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 348         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 349         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 350         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 351         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 352         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 353         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 354         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 355         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 356         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 357         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 358         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 359         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 360 };
 361
 362 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 363 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 364
 365 /* for iavf_32b_rx_flex_desc.pkt_len member */
 366 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 367
 368 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 369                            uint16_t queue_idx,
 370                            uint16_t nb_desc,
 371                            unsigned int socket_id,
 372                            const struct rte_eth_rxconf *rx_conf,
 373                            struct rte_mempool *mp);
 374
 375 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 376 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 377 void iavf_dev_rx_queue_release(void *rxq);
 378
 379 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 380                            uint16_t queue_idx,
 381                            uint16_t nb_desc,
 382                            unsigned int socket_id,
 383                            const struct rte_eth_txconf *tx_conf);
 384 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 385 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 386 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 387 void iavf_dev_tx_queue_release(void *txq);
 388 void iavf_stop_queues(struct rte_eth_dev *dev);
 389 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 390                        uint16_t nb_pkts);
 391 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 392                                  struct rte_mbuf **rx_pkts,
 393                                  uint16_t nb_pkts);
 394 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 395                                  struct rte_mbuf **rx_pkts,
 396                                  uint16_t nb_pkts);
 397 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 398                                            struct rte_mbuf **rx_pkts,
 399                                            uint16_t nb_pkts);
 400 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 401                        uint16_t nb_pkts);
 402 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 403                        uint16_t nb_pkts);
 404 void iavf_set_rx_function(struct rte_eth_dev *dev);
 405 void iavf_set_tx_function(struct rte_eth_dev *dev);
 406 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 407                           struct rte_eth_rxq_info *qinfo);
 408 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 409                           struct rte_eth_txq_info *qinfo);
 410 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
 411 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 412 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 413
 414 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 415                            uint16_t nb_pkts);
 416 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 417                                      uint16_t nb_pkts);
 418 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 419                                      struct rte_mbuf **rx_pkts,
 420                                      uint16_t nb_pkts);
 421 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 422                                                struct rte_mbuf **rx_pkts,
 423                                                uint16_t nb_pkts);
 424 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 425                                   uint16_t nb_pkts);
 426 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 427                                  uint16_t nb_pkts);
 428 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 429                                           struct rte_mbuf **rx_pkts,
 430                                           uint16_t nb_pkts);
 431 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 432                                            struct rte_mbuf **rx_pkts,
 433                                            uint16_t nb_pkts);
 434 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 435                                                     struct rte_mbuf **rx_pkts,
 436                                                     uint16_t nb_pkts);
 437 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 438                             uint16_t nb_pkts);
 439 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 440                                  uint16_t nb_pkts);
 441 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 442 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 443 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 444 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 445 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 446                                    uint16_t nb_pkts);
 447 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 448                                             struct rte_mbuf **rx_pkts,
 449                                             uint16_t nb_pkts);
 450 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 451                                              struct rte_mbuf **rx_pkts,
 452                                              uint16_t nb_pkts);
 453 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 454                                                       struct rte_mbuf **rx_pkts,
 455                                                       uint16_t nb_pkts);
 456 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 457                                    uint16_t nb_pkts);
 458 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 459
 460 const uint32_t *iavf_get_default_ptype_table(void);
 461
 462 static inline
 463 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 464                             const volatile void *desc,
 465                             uint16_t rx_id)
 466 {
 467 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 468         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 469
 470         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 471                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 472                rx_desc->read.hdr_addr);
 473 #else
 474         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 475
 476         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 477                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 478                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 479                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 480 #endif
 481 }
 482
 483 /* All the descriptors are 16 bytes, so just use one of them
 484  * to print the qwords
 485  */
 486 static inline
 487 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 488                             const volatile void *desc, uint16_t tx_id)
 489 {
 490         const char *name;
 491         const volatile struct iavf_tx_desc *tx_desc = desc;
 492         enum iavf_tx_desc_dtype_value type;
 493
 494         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
 495                 tx_desc->cmd_type_offset_bsz &
 496                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
 497         switch (type) {
 498         case IAVF_TX_DESC_DTYPE_DATA:
 499                 name = "Tx_data_desc";
 500                 break;
 501         case IAVF_TX_DESC_DTYPE_CONTEXT:
 502                 name = "Tx_context_desc";
 503                 break;
 504         default:
 505                 name = "unknown_desc";
 506                 break;
 507         }
 508
 509         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 510                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 511                tx_desc->cmd_type_offset_bsz);
 512 }
 513
 514 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 515         int i; \
 516         for (i = 0; i < (ad)->eth_dev->data->nb_rx_queues; i++) { \
 517                 struct iavf_rx_queue *rxq = (ad)->eth_dev->data->rx_queues[i]; \
 518                 if (!rxq) \
 519                         continue; \
 520                 rxq->fdir_enabled = on; \
 521         } \
 522         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 523 } while (0)
 524
 525 /* Enable/disable flow director Rx processing in data path. */
 526 static inline
 527 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 528 {
 529         if (on) {
 530                 /* enable flow director processing */
 531                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 532                 ad->fdir_ref_cnt++;
 533         } else {
 534                 if (ad->fdir_ref_cnt >= 1) {
 535                         ad->fdir_ref_cnt--;
 536
 537                         if (ad->fdir_ref_cnt == 0)
 538                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 539                 }
 540         }
 541 }
 542
 543 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 544 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 545         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 546 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 547         iavf_dump_tx_descriptor(txq, desc, tx_id)
 548 #else
 549 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 550 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 551 #endif
 552
 553 #endif /* _IAVF_RXTX_H_ */