drivers/net/iavf/iavf_rxtx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #ifndef _IAVF_RXTX_H_
   6 #define _IAVF_RXTX_H_
   7
   8 /* In QLEN must be whole number of 32 descriptors. */
   9 #define IAVF_ALIGN_RING_DESC      32
  10 #define IAVF_MIN_RING_DESC        64
  11 #define IAVF_MAX_RING_DESC        4096
  12 #define IAVF_DMA_MEM_ALIGN        4096
  13 /* Base address of the HW descriptor ring should be 128B aligned. */
  14 #define IAVF_RING_BASE_ALIGN      128
  15
  16 /* used for Rx Bulk Allocate */
  17 #define IAVF_RX_MAX_BURST         32
  18
  19 /* used for Vector PMD */
  20 #define IAVF_VPMD_RX_MAX_BURST    32
  21 #define IAVF_VPMD_TX_MAX_BURST    32
  22 #define IAVF_RXQ_REARM_THRESH     32
  23 #define IAVF_VPMD_DESCS_PER_LOOP  4
  24 #define IAVF_VPMD_TX_MAX_FREE_BUF 64
  25
  26 #define IAVF_NO_VECTOR_FLAGS (                           \
  27                 DEV_TX_OFFLOAD_MULTI_SEGS |              \
  28                 DEV_TX_OFFLOAD_VLAN_INSERT |             \
  29                 DEV_TX_OFFLOAD_SCTP_CKSUM |              \
  30                 DEV_TX_OFFLOAD_UDP_CKSUM |               \
  31                 DEV_TX_OFFLOAD_TCP_TSO |                 \
  32                 DEV_TX_OFFLOAD_TCP_CKSUM)
  33
  34 #define DEFAULT_TX_RS_THRESH     32
  35 #define DEFAULT_TX_FREE_THRESH   32
  36
  37 #define IAVF_MIN_TSO_MSS          88
  38 #define IAVF_MAX_TSO_MSS          9668
  39 #define IAVF_TSO_MAX_SEG          UINT8_MAX
  40 #define IAVF_TX_MAX_MTU_SEG       8
  41
  42 #define IAVF_TX_CKSUM_OFFLOAD_MASK (             \
  43                 PKT_TX_IP_CKSUM |                \
  44                 PKT_TX_L4_MASK |                 \
  45                 PKT_TX_TCP_SEG)
  46
  47 #define IAVF_TX_OFFLOAD_MASK (  \
  48                 PKT_TX_OUTER_IPV6 |              \
  49                 PKT_TX_OUTER_IPV4 |              \
  50                 PKT_TX_IPV6 |                    \
  51                 PKT_TX_IPV4 |                    \
  52                 PKT_TX_VLAN_PKT |                \
  53                 PKT_TX_IP_CKSUM |                \
  54                 PKT_TX_L4_MASK |                 \
  55                 PKT_TX_TCP_SEG)
  56
  57 #define IAVF_TX_OFFLOAD_NOTSUP_MASK \
  58                 (PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
  59
  60 /**
  61  * Rx Flex Descriptors
  62  * These descriptors are used instead of the legacy version descriptors
  63  */
  64 union iavf_16b_rx_flex_desc {
  65         struct {
  66                 __le64 pkt_addr; /* Packet buffer address */
  67                 __le64 hdr_addr; /* Header buffer address */
  68                                  /* bit 0 of hdr_addr is DD bit */
  69         } read;
  70         struct {
  71                 /* Qword 0 */
  72                 u8 rxdid; /* descriptor builder profile ID */
  73                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
  74                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
  75                 __le16 pkt_len; /* [15:14] are reserved */
  76                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
  77                                                 /* sph=[11:11] */
  78                                                 /* ff1/ext=[15:12] */
  79
  80                 /* Qword 1 */
  81                 __le16 status_error0;
  82                 __le16 l2tag1;
  83                 __le16 flex_meta0;
  84                 __le16 flex_meta1;
  85         } wb; /* writeback */
  86 };
  87
  88 union iavf_32b_rx_flex_desc {
  89         struct {
  90                 __le64 pkt_addr; /* Packet buffer address */
  91                 __le64 hdr_addr; /* Header buffer address */
  92                                  /* bit 0 of hdr_addr is DD bit */
  93                 __le64 rsvd1;
  94                 __le64 rsvd2;
  95         } read;
  96         struct {
  97                 /* Qword 0 */
  98                 u8 rxdid; /* descriptor builder profile ID */
  99                 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
 100                 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
 101                 __le16 pkt_len; /* [15:14] are reserved */
 102                 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
 103                                                 /* sph=[11:11] */
 104                                                 /* ff1/ext=[15:12] */
 105
 106                 /* Qword 1 */
 107                 __le16 status_error0;
 108                 __le16 l2tag1;
 109                 __le16 flex_meta0;
 110                 __le16 flex_meta1;
 111
 112                 /* Qword 2 */
 113                 __le16 status_error1;
 114                 u8 flex_flags2;
 115                 u8 time_stamp_low;
 116                 __le16 l2tag2_1st;
 117                 __le16 l2tag2_2nd;
 118
 119                 /* Qword 3 */
 120                 __le16 flex_meta2;
 121                 __le16 flex_meta3;
 122                 union {
 123                         struct {
 124                                 __le16 flex_meta4;
 125                                 __le16 flex_meta5;
 126                         } flex;
 127                         __le32 ts_high;
 128                 } flex_ts;
 129         } wb; /* writeback */
 130 };
 131
 132 /* HW desc structure, both 16-byte and 32-byte types are supported */
 133 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 134 #define iavf_rx_desc iavf_16byte_rx_desc
 135 #define iavf_rx_flex_desc iavf_16b_rx_flex_desc
 136 #else
 137 #define iavf_rx_desc iavf_32byte_rx_desc
 138 #define iavf_rx_flex_desc iavf_32b_rx_flex_desc
 139 #endif
 140
 141 typedef void (*iavf_rxd_to_pkt_fields_t)(struct iavf_rx_queue *rxq,
 142                                 struct rte_mbuf *mb,
 143                                 volatile union iavf_rx_flex_desc *rxdp);
 144
 145 struct iavf_rxq_ops {
 146         void (*release_mbufs)(struct iavf_rx_queue *rxq);
 147 };
 148
 149 struct iavf_txq_ops {
 150         void (*release_mbufs)(struct iavf_tx_queue *txq);
 151 };
 152
 153 /* Structure associated with each Rx queue. */
 154 struct iavf_rx_queue {
 155         struct rte_mempool *mp;       /* mbuf pool to populate Rx ring */
 156         const struct rte_memzone *mz; /* memzone for Rx ring */
 157         volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
 158         uint64_t rx_ring_phys_addr;   /* Rx ring DMA address */
 159         struct rte_mbuf **sw_ring;     /* address of SW ring */
 160         uint16_t nb_rx_desc;          /* ring length */
 161         uint16_t rx_tail;             /* current value of tail */
 162         volatile uint8_t *qrx_tail;   /* register address of tail */
 163         uint16_t rx_free_thresh;      /* max free RX desc to hold */
 164         uint16_t nb_rx_hold;          /* number of held free RX desc */
 165         struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
 166         struct rte_mbuf *pkt_last_seg;  /* last segment of current packet */
 167         struct rte_mbuf fake_mbuf;      /* dummy mbuf */
 168         uint8_t rxdid;
 169
 170         /* used for VPMD */
 171         uint16_t rxrearm_nb;       /* number of remaining to be re-armed */
 172         uint16_t rxrearm_start;    /* the idx we start the re-arming from */
 173         uint64_t mbuf_initializer; /* value to init mbufs */
 174
 175         /* for rx bulk */
 176         uint16_t rx_nb_avail;      /* number of staged packets ready */
 177         uint16_t rx_next_avail;    /* index of next staged packets */
 178         uint16_t rx_free_trigger;  /* triggers rx buffer allocation */
 179         struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
 180
 181         uint16_t port_id;        /* device port ID */
 182         uint8_t crc_len;        /* 0 if CRC stripped, 4 otherwise */
 183         uint8_t fdir_enabled;   /* 0 if FDIR disabled, 1 when enabled */
 184         uint16_t queue_id;      /* Rx queue index */
 185         uint16_t rx_buf_len;    /* The packet buffer size */
 186         uint16_t rx_hdr_len;    /* The header buffer size */
 187         uint16_t max_pkt_len;   /* Maximum packet length */
 188         struct iavf_vsi *vsi; /**< the VSI this queue belongs to */
 189
 190         bool q_set;             /* if rx queue has been configured */
 191         bool rx_deferred_start; /* don't start this queue in dev start */
 192         const struct iavf_rxq_ops *ops;
 193         uint8_t rx_flags;
 194 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1     BIT(0)
 195 #define IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2   BIT(1)
 196         uint8_t proto_xtr; /* protocol extraction type */
 197         uint64_t xtr_ol_flag;
 198                 /* flexible descriptor metadata extraction offload flag */
 199         iavf_rxd_to_pkt_fields_t rxd_to_pkt_fields;
 200                                 /* handle flexible descriptor by RXDID */
 201         uint64_t offloads;
 202 };
 203
 204 struct iavf_tx_entry {
 205         struct rte_mbuf *mbuf;
 206         uint16_t next_id;
 207         uint16_t last_id;
 208 };
 209
 210 struct iavf_tx_vec_entry {
 211         struct rte_mbuf *mbuf;
 212 };
 213
 214 /* Structure associated with each TX queue. */
 215 struct iavf_tx_queue {
 216         const struct rte_memzone *mz;  /* memzone for Tx ring */
 217         volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
 218         uint64_t tx_ring_phys_addr;    /* Tx ring DMA address */
 219         struct iavf_tx_entry *sw_ring;  /* address array of SW ring */
 220         uint16_t nb_tx_desc;           /* ring length */
 221         uint16_t tx_tail;              /* current value of tail */
 222         volatile uint8_t *qtx_tail;    /* register address of tail */
 223         /* number of used desc since RS bit set */
 224         uint16_t nb_used;
 225         uint16_t nb_free;
 226         uint16_t last_desc_cleaned;    /* last desc have been cleaned*/
 227         uint16_t free_thresh;
 228         uint16_t rs_thresh;
 229
 230         uint16_t port_id;
 231         uint16_t queue_id;
 232         uint64_t offloads;
 233         uint16_t next_dd;              /* next to set RS, for VPMD */
 234         uint16_t next_rs;              /* next to check DD,  for VPMD */
 235
 236         bool q_set;                    /* if rx queue has been configured */
 237         bool tx_deferred_start;        /* don't start this queue in dev start */
 238         const struct iavf_txq_ops *ops;
 239 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG1       BIT(0)
 240 #define IAVF_TX_FLAGS_VLAN_TAG_LOC_L2TAG2       BIT(1)
 241         uint8_t vlan_flag;
 242 };
 243
 244 /* Offload features */
 245 union iavf_tx_offload {
 246         uint64_t data;
 247         struct {
 248                 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
 249                 uint64_t l3_len:9; /* L3 (IP) Header Length. */
 250                 uint64_t l4_len:8; /* L4 Header Length. */
 251                 uint64_t tso_segsz:16; /* TCP TSO segment size */
 252                 /* uint64_t unused : 24; */
 253         };
 254 };
 255
 256 /* Rx Flex Descriptor
 257  * RxDID Profile ID 16-21
 258  * Flex-field 0: RSS hash lower 16-bits
 259  * Flex-field 1: RSS hash upper 16-bits
 260  * Flex-field 2: Flow ID lower 16-bits
 261  * Flex-field 3: Flow ID upper 16-bits
 262  * Flex-field 4: AUX0
 263  * Flex-field 5: AUX1
 264  */
 265 struct iavf_32b_rx_flex_desc_comms {
 266         /* Qword 0 */
 267         u8 rxdid;
 268         u8 mir_id_umb_cast;
 269         __le16 ptype_flexi_flags0;
 270         __le16 pkt_len;
 271         __le16 hdr_len_sph_flex_flags1;
 272
 273         /* Qword 1 */
 274         __le16 status_error0;
 275         __le16 l2tag1;
 276         __le32 rss_hash;
 277
 278         /* Qword 2 */
 279         __le16 status_error1;
 280         u8 flexi_flags2;
 281         u8 ts_low;
 282         __le16 l2tag2_1st;
 283         __le16 l2tag2_2nd;
 284
 285         /* Qword 3 */
 286         __le32 flow_id;
 287         union {
 288                 struct {
 289                         __le16 aux0;
 290                         __le16 aux1;
 291                 } flex;
 292                 __le32 ts_high;
 293         } flex_ts;
 294 };
 295
 296 /* Rx Flex Descriptor
 297  * RxDID Profile ID 22-23 (swap Hash and FlowID)
 298  * Flex-field 0: Flow ID lower 16-bits
 299  * Flex-field 1: Flow ID upper 16-bits
 300  * Flex-field 2: RSS hash lower 16-bits
 301  * Flex-field 3: RSS hash upper 16-bits
 302  * Flex-field 4: AUX0
 303  * Flex-field 5: AUX1
 304  */
 305 struct iavf_32b_rx_flex_desc_comms_ovs {
 306         /* Qword 0 */
 307         u8 rxdid;
 308         u8 mir_id_umb_cast;
 309         __le16 ptype_flexi_flags0;
 310         __le16 pkt_len;
 311         __le16 hdr_len_sph_flex_flags1;
 312
 313         /* Qword 1 */
 314         __le16 status_error0;
 315         __le16 l2tag1;
 316         __le32 flow_id;
 317
 318         /* Qword 2 */
 319         __le16 status_error1;
 320         u8 flexi_flags2;
 321         u8 ts_low;
 322         __le16 l2tag2_1st;
 323         __le16 l2tag2_2nd;
 324
 325         /* Qword 3 */
 326         __le32 rss_hash;
 327         union {
 328                 struct {
 329                         __le16 aux0;
 330                         __le16 aux1;
 331                 } flex;
 332                 __le32 ts_high;
 333         } flex_ts;
 334 };
 335
 336 /* Receive Flex Descriptor profile IDs: There are a total
 337  * of 64 profiles where profile IDs 0/1 are for legacy; and
 338  * profiles 2-63 are flex profiles that can be programmed
 339  * with a specific metadata (profile 7 reserved for HW)
 340  */
 341 enum iavf_rxdid {
 342         IAVF_RXDID_LEGACY_0             = 0,
 343         IAVF_RXDID_LEGACY_1             = 1,
 344         IAVF_RXDID_FLEX_NIC             = 2,
 345         IAVF_RXDID_FLEX_NIC_2           = 6,
 346         IAVF_RXDID_HW                   = 7,
 347         IAVF_RXDID_COMMS_GENERIC        = 16,
 348         IAVF_RXDID_COMMS_AUX_VLAN       = 17,
 349         IAVF_RXDID_COMMS_AUX_IPV4       = 18,
 350         IAVF_RXDID_COMMS_AUX_IPV6       = 19,
 351         IAVF_RXDID_COMMS_AUX_IPV6_FLOW  = 20,
 352         IAVF_RXDID_COMMS_AUX_TCP        = 21,
 353         IAVF_RXDID_COMMS_OVS_1          = 22,
 354         IAVF_RXDID_COMMS_OVS_2          = 23,
 355         IAVF_RXDID_COMMS_AUX_IP_OFFSET  = 25,
 356         IAVF_RXDID_LAST                 = 63,
 357 };
 358
 359 enum iavf_rx_flex_desc_status_error_0_bits {
 360         /* Note: These are predefined bit offsets */
 361         IAVF_RX_FLEX_DESC_STATUS0_DD_S = 0,
 362         IAVF_RX_FLEX_DESC_STATUS0_EOF_S,
 363         IAVF_RX_FLEX_DESC_STATUS0_HBO_S,
 364         IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S,
 365         IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
 366         IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
 367         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
 368         IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
 369         IAVF_RX_FLEX_DESC_STATUS0_LPBK_S,
 370         IAVF_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
 371         IAVF_RX_FLEX_DESC_STATUS0_RXE_S,
 372         IAVF_RX_FLEX_DESC_STATUS0_CRCP_S,
 373         IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
 374         IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
 375         IAVF_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
 376         IAVF_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
 377         IAVF_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
 378 };
 379
 380 enum iavf_rx_flex_desc_status_error_1_bits {
 381         /* Note: These are predefined bit offsets */
 382         IAVF_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */
 383         IAVF_RX_FLEX_DESC_STATUS1_NAT_S = 4,
 384         IAVF_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5,
 385         /* [10:6] reserved */
 386         IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
 387         IAVF_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,
 388         IAVF_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,
 389         IAVF_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,
 390         IAVF_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,
 391         IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 392 };
 393
 394 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 395 #define IAVF_RX_FLEX_DESC_PTYPE_M       (0x3FF) /* 10-bits */
 396
 397 /* for iavf_32b_rx_flex_desc.pkt_len member */
 398 #define IAVF_RX_FLX_DESC_PKT_LEN_M      (0x3FFF) /* 14-bits */
 399
 400 int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
 401                            uint16_t queue_idx,
 402                            uint16_t nb_desc,
 403                            unsigned int socket_id,
 404                            const struct rte_eth_rxconf *rx_conf,
 405                            struct rte_mempool *mp);
 406
 407 int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 408 int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 409 void iavf_dev_rx_queue_release(void *rxq);
 410
 411 int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 412                            uint16_t queue_idx,
 413                            uint16_t nb_desc,
 414                            unsigned int socket_id,
 415                            const struct rte_eth_txconf *tx_conf);
 416 int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 417 int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 418 int iavf_dev_tx_done_cleanup(void *txq, uint32_t free_cnt);
 419 void iavf_dev_tx_queue_release(void *txq);
 420 void iavf_stop_queues(struct rte_eth_dev *dev);
 421 uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 422                        uint16_t nb_pkts);
 423 uint16_t iavf_recv_pkts_flex_rxd(void *rx_queue,
 424                                  struct rte_mbuf **rx_pkts,
 425                                  uint16_t nb_pkts);
 426 uint16_t iavf_recv_scattered_pkts(void *rx_queue,
 427                                  struct rte_mbuf **rx_pkts,
 428                                  uint16_t nb_pkts);
 429 uint16_t iavf_recv_scattered_pkts_flex_rxd(void *rx_queue,
 430                                            struct rte_mbuf **rx_pkts,
 431                                            uint16_t nb_pkts);
 432 uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 433                        uint16_t nb_pkts);
 434 uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 435                        uint16_t nb_pkts);
 436 void iavf_set_rx_function(struct rte_eth_dev *dev);
 437 void iavf_set_tx_function(struct rte_eth_dev *dev);
 438 void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 439                           struct rte_eth_rxq_info *qinfo);
 440 void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 441                           struct rte_eth_txq_info *qinfo);
 442 uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
 443 int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
 444 int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
 445
 446 uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 447                            uint16_t nb_pkts);
 448 uint16_t iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
 449                                      uint16_t nb_pkts);
 450 uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
 451                                      struct rte_mbuf **rx_pkts,
 452                                      uint16_t nb_pkts);
 453 uint16_t iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
 454                                                struct rte_mbuf **rx_pkts,
 455                                                uint16_t nb_pkts);
 456 uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 457                                   uint16_t nb_pkts);
 458 uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 459                                  uint16_t nb_pkts);
 460 uint16_t iavf_recv_pkts_vec_avx2_flex_rxd(void *rx_queue,
 461                                           struct rte_mbuf **rx_pkts,
 462                                           uint16_t nb_pkts);
 463 uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
 464                                            struct rte_mbuf **rx_pkts,
 465                                            uint16_t nb_pkts);
 466 uint16_t iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue,
 467                                                     struct rte_mbuf **rx_pkts,
 468                                                     uint16_t nb_pkts);
 469 uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 470                             uint16_t nb_pkts);
 471 uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 472                                  uint16_t nb_pkts);
 473 int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
 474 int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
 475 int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
 476 int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
 477 int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
 478 uint16_t iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 479                                    uint16_t nb_pkts);
 480 uint16_t iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue,
 481                                             struct rte_mbuf **rx_pkts,
 482                                             uint16_t nb_pkts);
 483 uint16_t iavf_recv_scattered_pkts_vec_avx512(void *rx_queue,
 484                                              struct rte_mbuf **rx_pkts,
 485                                              uint16_t nb_pkts);
 486 uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
 487                                                       struct rte_mbuf **rx_pkts,
 488                                                       uint16_t nb_pkts);
 489 uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 490                                    uint16_t nb_pkts);
 491 int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);
 492
 493 uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);
 494
 495 const uint32_t *iavf_get_default_ptype_table(void);
 496
 497 static inline
 498 void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
 499                             const volatile void *desc,
 500                             uint16_t rx_id)
 501 {
 502 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 503         const volatile union iavf_16byte_rx_desc *rx_desc = desc;
 504
 505         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 506                rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
 507                rx_desc->read.hdr_addr);
 508 #else
 509         const volatile union iavf_32byte_rx_desc *rx_desc = desc;
 510
 511         printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
 512                " QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
 513                rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
 514                rx_desc->read.rsvd1, rx_desc->read.rsvd2);
 515 #endif
 516 }
 517
 518 /* All the descriptors are 16 bytes, so just use one of them
 519  * to print the qwords
 520  */
 521 static inline
 522 void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
 523                             const volatile void *desc, uint16_t tx_id)
 524 {
 525         const char *name;
 526         const volatile struct iavf_tx_desc *tx_desc = desc;
 527         enum iavf_tx_desc_dtype_value type;
 528
 529         type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
 530                 tx_desc->cmd_type_offset_bsz &
 531                 rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
 532         switch (type) {
 533         case IAVF_TX_DESC_DTYPE_DATA:
 534                 name = "Tx_data_desc";
 535                 break;
 536         case IAVF_TX_DESC_DTYPE_CONTEXT:
 537                 name = "Tx_context_desc";
 538                 break;
 539         default:
 540                 name = "unknown_desc";
 541                 break;
 542         }
 543
 544         printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
 545                txq->queue_id, name, tx_id, tx_desc->buffer_addr,
 546                tx_desc->cmd_type_offset_bsz);
 547 }
 548
 549 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \
 550         int i; \
 551         for (i = 0; i < (ad)->eth_dev->data->nb_rx_queues; i++) { \
 552                 struct iavf_rx_queue *rxq = (ad)->eth_dev->data->rx_queues[i]; \
 553                 if (!rxq) \
 554                         continue; \
 555                 rxq->fdir_enabled = on; \
 556         } \
 557         PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
 558 } while (0)
 559
 560 /* Enable/disable flow director Rx processing in data path. */
 561 static inline
 562 void iavf_fdir_rx_proc_enable(struct iavf_adapter *ad, bool on)
 563 {
 564         if (on) {
 565                 /* enable flow director processing */
 566                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 567                 ad->fdir_ref_cnt++;
 568         } else {
 569                 if (ad->fdir_ref_cnt >= 1) {
 570                         ad->fdir_ref_cnt--;
 571
 572                         if (ad->fdir_ref_cnt == 0)
 573                                 FDIR_PROC_ENABLE_PER_QUEUE(ad, on);
 574                 }
 575         }
 576 }
 577
 578 #ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
 579 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
 580         iavf_dump_rx_descriptor(rxq, desc, rx_id)
 581 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
 582         iavf_dump_tx_descriptor(txq, desc, tx_id)
 583 #else
 584 #define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
 585 #define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
 586 #endif
 587
 588 #endif /* _IAVF_RXTX_H_ */