drivers/net/iavf/iavf_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include "iavf_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define IAVF_DESCS_PER_LOOP_AVX 8
  14 #define PKTLEN_SHIFT 10
  15
  16 static inline void
  17 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  18 {
  19         int i;
  20         uint16_t rx_id;
  21         volatile union iavf_rx_desc *rxdp;
  22         struct rte_mempool_cache *cache =
  23                 rte_mempool_default_cache(rxq->mp, rte_lcore_id());
  24         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  25
  26         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  27
  28         /* We need to pull 'n' more MBUFs into the software ring from mempool
  29          * We inline the mempool function here, so we can vectorize the copy
  30          * from the cache into the shadow ring.
  31          */
  32
  33         /* Can this be satisfied from the cache? */
  34         if (cache->len < IAVF_RXQ_REARM_THRESH) {
  35                 /* No. Backfill the cache first, and then fill from it */
  36                 uint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -
  37                                                         cache->len);
  38
  39                 /* How many do we require i.e. number to fill the cache + the request */
  40                 int ret = rte_mempool_ops_dequeue_bulk
  41                                 (rxq->mp, &cache->objs[cache->len], req);
  42                 if (ret == 0) {
  43                         cache->len += req;
  44                 } else {
  45                         if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  46                             rxq->nb_rx_desc) {
  47                                 __m128i dma_addr0;
  48
  49                                 dma_addr0 = _mm_setzero_si128();
  50                                 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  51                                         rxp[i] = &rxq->fake_mbuf;
  52                                         _mm_storeu_si128((__m128i *)&rxdp[i].read,
  53                                                          dma_addr0);
  54                                 }
  55                         }
  56                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  57                                         IAVF_RXQ_REARM_THRESH;
  58                         return;
  59                 }
  60         }
  61
  62         const __m512i iova_offsets =  _mm512_set1_epi64(offsetof
  63                                                         (struct rte_mbuf, buf_iova));
  64         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  65
  66 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  67         /* to shuffle the addresses to correct slots. Values 4-7 will contain
  68          * zeros, so use 7 for a zero-value.
  69          */
  70         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  71 #else
  72         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  73 #endif
  74
  75         /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
  76          * from mempool cache and populating both shadow and HW rings
  77          */
  78         for (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {
  79                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  80                         (&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);
  81                 _mm512_storeu_si512(rxp, mbuf_ptrs);
  82
  83                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
  84                                 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
  85                                  0, /* base */
  86                                  1  /* scale */);
  87                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
  88                                 headroom);
  89 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  90                 const __m512i iovas0 = _mm512_castsi256_si512
  91                                 (_mm512_extracti64x4_epi64(iova_addrs, 0));
  92                 const __m512i iovas1 = _mm512_castsi256_si512
  93                                 (_mm512_extracti64x4_epi64(iova_addrs, 1));
  94
  95                 /* permute leaves desc 2-3 addresses in header address slots 0-1
  96                  * but these are ignored by driver since header split not
  97                  * enabled. Similarly for desc 6 & 7.
  98                  */
  99                 const __m512i desc0_1 = _mm512_permutexvar_epi64
 100                                 (permute_idx,
 101                                  iovas0);
 102                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
 103
 104                 const __m512i desc4_5 = _mm512_permutexvar_epi64
 105                                 (permute_idx,
 106                                  iovas1);
 107                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
 108
 109                 _mm512_storeu_si512((void *)rxdp, desc0_1);
 110                 _mm512_storeu_si512((void *)(rxdp + 2), desc2_3);
 111                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_5);
 112                 _mm512_storeu_si512((void *)(rxdp + 6), desc6_7);
 113 #else
 114                 /* permute leaves desc 4-7 addresses in header address slots 0-3
 115                  * but these are ignored by driver since header split not
 116                  * enabled.
 117                  */
 118                 const __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx,
 119                                                                  iova_addrs);
 120                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 121
 122                 _mm512_storeu_si512((void *)rxdp, desc0_3);
 123                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_7);
 124 #endif
 125                 rxp += IAVF_DESCS_PER_LOOP_AVX;
 126                 rxdp += IAVF_DESCS_PER_LOOP_AVX;
 127                 cache->len -= IAVF_DESCS_PER_LOOP_AVX;
 128         }
 129
 130         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 131         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 132                 rxq->rxrearm_start = 0;
 133
 134         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 135
 136         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 137                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 138
 139         /* Update the tail pointer on the NIC */
 140         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 141 }
 142
 143 #define IAVF_RX_LEN_MASK 0x80808080
 144 static inline uint16_t
 145 _iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,
 146                                struct rte_mbuf **rx_pkts,
 147                                uint16_t nb_pkts, uint8_t *split_packet)
 148 {
 149         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 150
 151         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 152                                                     rxq->mbuf_initializer);
 153         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 154         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 155
 156         rte_prefetch0(rxdp);
 157
 158         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 159         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 160
 161         /* See if we need to rearm the RX queue - gives the prefetch a bit
 162          * of time to act
 163          */
 164         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 165                 iavf_rxq_rearm(rxq);
 166
 167         /* Before we start moving massive data around, check to see if
 168          * there is actually a packet available
 169          */
 170         if (!(rxdp->wb.qword1.status_error_len &
 171               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 172                 return 0;
 173
 174         /* constants used in processing loop */
 175         const __m512i crc_adjust =
 176                 _mm512_set_epi32
 177                         (/* 1st descriptor */
 178                          0,             /* ignore non-length fields */
 179                          -rxq->crc_len, /* sub crc on data_len */
 180                          -rxq->crc_len, /* sub crc on pkt_len */
 181                          0,             /* ignore pkt_type field */
 182                          /* 2nd descriptor */
 183                          0,             /* ignore non-length fields */
 184                          -rxq->crc_len, /* sub crc on data_len */
 185                          -rxq->crc_len, /* sub crc on pkt_len */
 186                          0,             /* ignore pkt_type field */
 187                          /* 3rd descriptor */
 188                          0,             /* ignore non-length fields */
 189                          -rxq->crc_len, /* sub crc on data_len */
 190                          -rxq->crc_len, /* sub crc on pkt_len */
 191                          0,             /* ignore pkt_type field */
 192                          /* 4th descriptor */
 193                          0,             /* ignore non-length fields */
 194                          -rxq->crc_len, /* sub crc on data_len */
 195                          -rxq->crc_len, /* sub crc on pkt_len */
 196                          0              /* ignore pkt_type field */
 197                         );
 198
 199         /* 8 packets DD mask, LSB in each 32-bit value */
 200         const __m256i dd_check = _mm256_set1_epi32(1);
 201
 202         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 203         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 204                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 205
 206         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 207         const __m512i shuf_msk =
 208                 _mm512_set_epi32
 209                         (/* 1st descriptor */
 210                          0x07060504,    /* octet 4~7, 32bits rss */
 211                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 212                                         /* octet 15~14, 16 bits data_len */
 213                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 214                                         /* octet 15~14, low 16 bits pkt_len */
 215                          0xFFFFFFFF,    /* pkt_type set as unknown */
 216                          /* 2nd descriptor */
 217                          0x07060504,    /* octet 4~7, 32bits rss */
 218                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 219                                         /* octet 15~14, 16 bits data_len */
 220                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 221                                         /* octet 15~14, low 16 bits pkt_len */
 222                          0xFFFFFFFF,    /* pkt_type set as unknown */
 223                          /* 3rd descriptor */
 224                          0x07060504,    /* octet 4~7, 32bits rss */
 225                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 226                                         /* octet 15~14, 16 bits data_len */
 227                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 228                                         /* octet 15~14, low 16 bits pkt_len */
 229                          0xFFFFFFFF,    /* pkt_type set as unknown */
 230                          /* 4th descriptor */
 231                          0x07060504,    /* octet 4~7, 32bits rss */
 232                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 233                                         /* octet 15~14, 16 bits data_len */
 234                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 235                                         /* octet 15~14, low 16 bits pkt_len */
 236                          0xFFFFFFFF     /* pkt_type set as unknown */
 237                         );
 238         /**
 239          * compile-time check the above crc and shuffle layout is correct.
 240          * NOTE: the first field (lowest address) is given last in set_epi
 241          * calls above.
 242          */
 243         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 244                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 245         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 246                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 247         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 248                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 249         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 250                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 251
 252         /* Status/Error flag masks */
 253         /**
 254          * mask everything except RSS, flow director and VLAN flags
 255          * bit2 is for VLAN tag, bit11 for flow director indication
 256          * bit13:12 for RSS indication. Bits 3-5 of error
 257          * field (bits 22-24) are for IP/L4 checksum errors
 258          */
 259         const __m256i flags_mask =
 260                 _mm256_set1_epi32((1 << 2) | (1 << 11) |
 261                                   (3 << 12) | (7 << 22));
 262         /**
 263          * data to be shuffled by result of flag mask. If VLAN bit is set,
 264          * (bit 2), then position 4 in this array will be used in the
 265          * destination
 266          */
 267         const __m256i vlan_flags_shuf =
 268                 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
 269                                  0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
 270         /**
 271          * data to be shuffled by result of flag mask, shifted down 11.
 272          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 273          * place.
 274          */
 275         const __m256i rss_flags_shuf =
 276                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 277                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 278                                 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
 279                                 0, 0, 0, 0, 0, 0, 0, 0,
 280                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 281                                 0, 0, 0, 0, PKT_RX_FDIR, 0);
 282
 283         /**
 284          * data to be shuffled by the result of the flags mask shifted by 22
 285          * bits.  This gives use the l3_l4 flags.
 286          */
 287         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 288                         /* shift right 1 bit to make sure it not exceed 255 */
 289                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 290                          PKT_RX_IP_CKSUM_BAD) >> 1,
 291                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 292                          PKT_RX_L4_CKSUM_BAD) >> 1,
 293                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 294                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 295                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 296                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 297                         PKT_RX_IP_CKSUM_BAD >> 1,
 298                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
 299                         /* second 128-bits */
 300                         0, 0, 0, 0, 0, 0, 0, 0,
 301                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 302                          PKT_RX_IP_CKSUM_BAD) >> 1,
 303                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 304                          PKT_RX_L4_CKSUM_BAD) >> 1,
 305                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 306                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 307                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 308                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 309                         PKT_RX_IP_CKSUM_BAD >> 1,
 310                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 311
 312         const __m256i cksum_mask =
 313                 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 314                                   PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 315                                   PKT_RX_EIP_CKSUM_BAD);
 316
 317         uint16_t i, received;
 318
 319         for (i = 0, received = 0; i < nb_pkts;
 320              i += IAVF_DESCS_PER_LOOP_AVX,
 321              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 322                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 323                 _mm256_storeu_si256((void *)&rx_pkts[i],
 324                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 325 #ifdef RTE_ARCH_X86_64
 326                 _mm256_storeu_si256
 327                         ((void *)&rx_pkts[i + 4],
 328                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 329 #endif
 330
 331                 __m512i raw_desc0_3, raw_desc4_7;
 332                 const __m128i raw_desc7 =
 333                         _mm_load_si128((void *)(rxdp + 7));
 334                 rte_compiler_barrier();
 335                 const __m128i raw_desc6 =
 336                         _mm_load_si128((void *)(rxdp + 6));
 337                 rte_compiler_barrier();
 338                 const __m128i raw_desc5 =
 339                         _mm_load_si128((void *)(rxdp + 5));
 340                 rte_compiler_barrier();
 341                 const __m128i raw_desc4 =
 342                         _mm_load_si128((void *)(rxdp + 4));
 343                 rte_compiler_barrier();
 344                 const __m128i raw_desc3 =
 345                         _mm_load_si128((void *)(rxdp + 3));
 346                 rte_compiler_barrier();
 347                 const __m128i raw_desc2 =
 348                         _mm_load_si128((void *)(rxdp + 2));
 349                 rte_compiler_barrier();
 350                 const __m128i raw_desc1 =
 351                         _mm_load_si128((void *)(rxdp + 1));
 352                 rte_compiler_barrier();
 353                 const __m128i raw_desc0 =
 354                         _mm_load_si128((void *)(rxdp + 0));
 355
 356                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 357                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 358                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 359                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 360                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 361                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 362                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 363                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 364
 365                 if (split_packet) {
 366                         int j;
 367
 368                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 369                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 370                 }
 371
 372                 /**
 373                  * convert descriptors 4-7 into mbufs, adjusting length and
 374                  * re-arranging fields. Then write into the mbuf
 375                  */
 376                 const __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,
 377                                                          PKTLEN_SHIFT);
 378                 const __m512i desc4_7 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 379                                                                 raw_desc4_7,
 380                                                                 len4_7);
 381                 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
 382
 383                 mb4_7 = _mm512_add_epi16(mb4_7, crc_adjust);
 384                 /**
 385                  * to get packet types, shift 64-bit values down 30 bits
 386                  * and so ptype is in lower 8-bits in each
 387                  */
 388                 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
 389                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 390                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 391                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 392                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 393                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 394                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 395
 396                 const __m512i ptype4_7 = _mm512_set_epi32
 397                         (0, 0, 0, type_table[ptype7],
 398                          0, 0, 0, type_table[ptype6],
 399                          0, 0, 0, type_table[ptype5],
 400                          0, 0, 0, type_table[ptype4]);
 401                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 402
 403                 /**
 404                  * convert descriptors 0-3 into mbufs, adjusting length and
 405                  * re-arranging fields. Then write into the mbuf
 406                  */
 407                 const __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,
 408                                                          PKTLEN_SHIFT);
 409                 const __m512i desc0_3 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 410                                                                 raw_desc0_3,
 411                                                                 len0_3);
 412                 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
 413
 414                 mb0_3 = _mm512_add_epi16(mb0_3, crc_adjust);
 415                 /* get the packet types */
 416                 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
 417                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 418                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 419                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 420                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 421                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 422                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 423
 424                 const __m512i ptype0_3 = _mm512_set_epi32
 425                         (0, 0, 0, type_table[ptype3],
 426                          0, 0, 0, type_table[ptype2],
 427                          0, 0, 0, type_table[ptype1],
 428                          0, 0, 0, type_table[ptype0]);
 429                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 430
 431                 /**
 432                  * use permute/extract to get status content
 433                  * After the operations, the packets status flags are in the
 434                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 435                  */
 436                 /* merge the status bits into one register */
 437                 const __m512i status_permute_msk = _mm512_set_epi32
 438                         (0, 0, 0, 0,
 439                          0, 0, 0, 0,
 440                          22, 30, 6, 14,
 441                          18, 26, 2, 10);
 442                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 443                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 444                 __m256i status0_7 = _mm512_extracti64x4_epi64
 445                         (raw_status0_7, 0);
 446
 447                 /* now do flag manipulation */
 448
 449                 /* get only flag/error bits we want */
 450                 const __m256i flag_bits =
 451                         _mm256_and_si256(status0_7, flags_mask);
 452                 /* set vlan and rss flags */
 453                 const __m256i vlan_flags =
 454                         _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 455                 const __m256i rss_flags =
 456                         _mm256_shuffle_epi8(rss_flags_shuf,
 457                                             _mm256_srli_epi32(flag_bits, 11));
 458                 /**
 459                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 460                  * of flags in flags_shuf, and finally mask out extra bits
 461                  */
 462                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 463                                                 _mm256_srli_epi32(flag_bits, 22));
 464                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 465                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 466
 467                 /* merge flags */
 468                 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 469                                 _mm256_or_si256(rss_flags, vlan_flags));
 470                 /**
 471                  * At this point, we have the 8 sets of flags in the low 16-bits
 472                  * of each 32-bit value in vlan0.
 473                  * We want to extract these, and merge them with the mbuf init
 474                  * data so we can do a single write to the mbuf to set the flags
 475                  * and all the other initialization fields. Extracting the
 476                  * appropriate flags means that we have to do a shift and blend
 477                  * for each mbuf before we do the write. However, we can also
 478                  * add in the previously computed rx_descriptor fields to
 479                  * make a single 256-bit write per mbuf
 480                  */
 481                 /* check the structure matches expectations */
 482                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 483                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 484                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 485                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 486                                                     rearm_data),
 487                                            16));
 488                 /* build up data and do writes */
 489                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 490                         rearm6, rearm7;
 491                 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 492                 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 493                 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 494                 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 495
 496                 rearm6 = _mm256_blend_epi32(mbuf_init,
 497                                             _mm256_slli_si256(mbuf_flags, 8),
 498                                             0x04);
 499                 rearm4 = _mm256_blend_epi32(mbuf_init,
 500                                             _mm256_slli_si256(mbuf_flags, 4),
 501                                             0x04);
 502                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 503                 rearm0 = _mm256_blend_epi32(mbuf_init,
 504                                             _mm256_srli_si256(mbuf_flags, 4),
 505                                             0x04);
 506                 /* permute to add in the rx_descriptor e.g. rss fields */
 507                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 508                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 509                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 510                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 511                 /* write to mbuf */
 512                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 513                                     rearm6);
 514                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 515                                     rearm4);
 516                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 517                                     rearm2);
 518                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 519                                     rearm0);
 520
 521                 /* repeat for the odd mbufs */
 522                 const __m256i odd_flags =
 523                         _mm256_castsi128_si256
 524                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 525                 rearm7 = _mm256_blend_epi32(mbuf_init,
 526                                             _mm256_slli_si256(odd_flags, 8),
 527                                             0x04);
 528                 rearm5 = _mm256_blend_epi32(mbuf_init,
 529                                             _mm256_slli_si256(odd_flags, 4),
 530                                             0x04);
 531                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 532                 rearm1 = _mm256_blend_epi32(mbuf_init,
 533                                             _mm256_srli_si256(odd_flags, 4),
 534                                             0x04);
 535                 /* since odd mbufs are already in hi 128-bits use blend */
 536                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 537                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 538                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 539                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 540                 /* again write to mbufs */
 541                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 542                                     rearm7);
 543                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 544                                     rearm5);
 545                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 546                                     rearm3);
 547                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 548                                     rearm1);
 549
 550                 /* extract and record EOP bit */
 551                 if (split_packet) {
 552                         const __m128i eop_mask =
 553                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 554                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 555                                                                      eop_check);
 556                         /* pack status bits into a single 128-bit register */
 557                         const __m128i eop_bits =
 558                                 _mm_packus_epi32
 559                                         (_mm256_castsi256_si128(eop_bits256),
 560                                          _mm256_extractf128_si256(eop_bits256,
 561                                                                   1));
 562                         /**
 563                          * flip bits, and mask out the EOP bit, which is now
 564                          * a split-packet bit i.e. !EOP, rather than EOP one.
 565                          */
 566                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 567                                                               eop_mask);
 568                         /**
 569                          * eop bits are out of order, so we need to shuffle them
 570                          * back into order again. In doing so, only use low 8
 571                          * bits, which acts like another pack instruction
 572                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 573                          * [Since we use epi8, the 16-bit positions are
 574                          * multiplied by 2 in the eop_shuffle value.]
 575                          */
 576                         __m128i eop_shuffle =
 577                                 _mm_set_epi8(/* zero hi 64b */
 578                                              0xFF, 0xFF, 0xFF, 0xFF,
 579                                              0xFF, 0xFF, 0xFF, 0xFF,
 580                                              /* move values to lo 64b */
 581                                              8, 0, 10, 2,
 582                                              12, 4, 14, 6);
 583                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 584                         *(uint64_t *)split_packet =
 585                                 _mm_cvtsi128_si64(split_bits);
 586                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 587                 }
 588
 589                 /* perform dd_check */
 590                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 591                 status0_7 = _mm256_packs_epi32(status0_7,
 592                                                _mm256_setzero_si256());
 593
 594                 uint64_t burst = __builtin_popcountll
 595                                         (_mm_cvtsi128_si64
 596                                                 (_mm256_extracti128_si256
 597                                                         (status0_7, 1)));
 598                 burst += __builtin_popcountll
 599                                 (_mm_cvtsi128_si64
 600                                         (_mm256_castsi256_si128(status0_7)));
 601                 received += burst;
 602                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 603                         break;
 604         }
 605
 606         /* update tail pointers */
 607         rxq->rx_tail += received;
 608         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 609         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
 610                 rxq->rx_tail--;
 611                 received--;
 612         }
 613         rxq->rxrearm_nb += received;
 614         return received;
 615 }
 616
 617 /**
 618  * Notice:
 619  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 620  */
 621 uint16_t
 622 iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 623                           uint16_t nb_pkts)
 624 {
 625         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);
 626 }
 627
 628 /**
 629  * vPMD receive routine that reassembles single burst of 32 scattered packets
 630  * Notice:
 631  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 632  */
 633 static uint16_t
 634 iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 635                                      uint16_t nb_pkts)
 636 {
 637         struct iavf_rx_queue *rxq = rx_queue;
 638         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
 639
 640         /* get some new buffers */
 641         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
 642                                                           split_flags);
 643         if (nb_bufs == 0)
 644                 return 0;
 645
 646         /* happy day case, full burst + no packets to be joined */
 647         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 648
 649         if (!rxq->pkt_first_seg &&
 650             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 651             split_fl64[2] == 0 && split_fl64[3] == 0)
 652                 return nb_bufs;
 653
 654         /* reassemble any packets that need reassembly*/
 655         unsigned int i = 0;
 656
 657         if (!rxq->pkt_first_seg) {
 658                 /* find the first split flag, and only reassemble then*/
 659                 while (i < nb_bufs && !split_flags[i])
 660                         i++;
 661                 if (i == nb_bufs)
 662                         return nb_bufs;
 663                 rxq->pkt_first_seg = rx_pkts[i];
 664         }
 665         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 666                                       &split_flags[i]);
 667 }
 668
 669 /**
 670  * vPMD receive routine that reassembles scattered packets.
 671  * Main receive routine that can handle arbitrary burst sizes
 672  * Notice:
 673  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 674  */
 675 uint16_t
 676 iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 677                                     uint16_t nb_pkts)
 678 {
 679         uint16_t retval = 0;
 680
 681         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
 682                 uint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,
 683                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
 684                 retval += burst;
 685                 nb_pkts -= burst;
 686                 if (burst < IAVF_VPMD_RX_MAX_BURST)
 687                         return retval;
 688         }
 689         return retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,
 690                                 rx_pkts + retval, nb_pkts);
 691 }