drivers/net/iavf/iavf_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include "iavf_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define IAVF_DESCS_PER_LOOP_AVX 8
  14 #define PKTLEN_SHIFT 10
  15
  16 /******************************************************************************
  17  * If user knows a specific offload is not enabled by APP,
  18  * the macro can be commented to save the effort of fast path.
  19  * Currently below 2 features are supported in RX path,
  20  * 1, checksum offload
  21  * 2, VLAN/QINQ stripping
  22  * 3, RSS hash
  23  * 4, packet type analysis
  24  * 5, flow director ID report
  25  ******************************************************************************/
  26 #define IAVF_RX_CSUM_OFFLOAD
  27 #define IAVF_RX_VLAN_OFFLOAD
  28 #define IAVF_RX_RSS_OFFLOAD
  29 #define IAVF_RX_PTYPE_OFFLOAD
  30 #define IAVF_RX_FDIR_OFFLOAD
  31
  32 static __rte_always_inline void
  33 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  34 {
  35         int i;
  36         uint16_t rx_id;
  37         volatile union iavf_rx_desc *rxdp;
  38         struct rte_mempool_cache *cache =
  39                 rte_mempool_default_cache(rxq->mp, rte_lcore_id());
  40         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  41
  42         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  43
  44         if (unlikely(!cache))
  45                 return iavf_rxq_rearm_common(rxq, true);
  46
  47         /* We need to pull 'n' more MBUFs into the software ring from mempool
  48          * We inline the mempool function here, so we can vectorize the copy
  49          * from the cache into the shadow ring.
  50          */
  51
  52         /* Can this be satisfied from the cache? */
  53         if (cache->len < IAVF_RXQ_REARM_THRESH) {
  54                 /* No. Backfill the cache first, and then fill from it */
  55                 uint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -
  56                                                         cache->len);
  57
  58                 /* How many do we require i.e. number to fill the cache + the request */
  59                 int ret = rte_mempool_ops_dequeue_bulk
  60                                 (rxq->mp, &cache->objs[cache->len], req);
  61                 if (ret == 0) {
  62                         cache->len += req;
  63                 } else {
  64                         if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  65                             rxq->nb_rx_desc) {
  66                                 __m128i dma_addr0;
  67
  68                                 dma_addr0 = _mm_setzero_si128();
  69                                 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  70                                         rxp[i] = &rxq->fake_mbuf;
  71                                         _mm_storeu_si128((__m128i *)&rxdp[i].read,
  72                                                          dma_addr0);
  73                                 }
  74                         }
  75                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  76                                         IAVF_RXQ_REARM_THRESH;
  77                         return;
  78                 }
  79         }
  80
  81         const __m512i iova_offsets =  _mm512_set1_epi64(offsetof
  82                                                         (struct rte_mbuf, buf_iova));
  83         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  84
  85 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  86         /* to shuffle the addresses to correct slots. Values 4-7 will contain
  87          * zeros, so use 7 for a zero-value.
  88          */
  89         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  90 #else
  91         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  92 #endif
  93
  94         /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
  95          * from mempool cache and populating both shadow and HW rings
  96          */
  97         for (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {
  98                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  99                         (&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);
 100                 _mm512_storeu_si512(rxp, mbuf_ptrs);
 101
 102                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
 103                                 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
 104                                  0, /* base */
 105                                  1  /* scale */);
 106                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
 107                                 headroom);
 108 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 109                 const __m512i iovas0 = _mm512_castsi256_si512
 110                                 (_mm512_extracti64x4_epi64(iova_addrs, 0));
 111                 const __m512i iovas1 = _mm512_castsi256_si512
 112                                 (_mm512_extracti64x4_epi64(iova_addrs, 1));
 113
 114                 /* permute leaves desc 2-3 addresses in header address slots 0-1
 115                  * but these are ignored by driver since header split not
 116                  * enabled. Similarly for desc 6 & 7.
 117                  */
 118                 const __m512i desc0_1 = _mm512_permutexvar_epi64
 119                                 (permute_idx,
 120                                  iovas0);
 121                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
 122
 123                 const __m512i desc4_5 = _mm512_permutexvar_epi64
 124                                 (permute_idx,
 125                                  iovas1);
 126                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
 127
 128                 _mm512_storeu_si512((void *)rxdp, desc0_1);
 129                 _mm512_storeu_si512((void *)(rxdp + 2), desc2_3);
 130                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_5);
 131                 _mm512_storeu_si512((void *)(rxdp + 6), desc6_7);
 132 #else
 133                 /* permute leaves desc 4-7 addresses in header address slots 0-3
 134                  * but these are ignored by driver since header split not
 135                  * enabled.
 136                  */
 137                 const __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx,
 138                                                                  iova_addrs);
 139                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 140
 141                 _mm512_storeu_si512((void *)rxdp, desc0_3);
 142                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_7);
 143 #endif
 144                 rxp += IAVF_DESCS_PER_LOOP_AVX;
 145                 rxdp += IAVF_DESCS_PER_LOOP_AVX;
 146                 cache->len -= IAVF_DESCS_PER_LOOP_AVX;
 147         }
 148
 149         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 150         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 151                 rxq->rxrearm_start = 0;
 152
 153         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 154
 155         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 156                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 157
 158         /* Update the tail pointer on the NIC */
 159         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 160 }
 161
 162 #define IAVF_RX_LEN_MASK 0x80808080
 163 static __rte_always_inline uint16_t
 164 _iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,
 165                                struct rte_mbuf **rx_pkts,
 166                                uint16_t nb_pkts, uint8_t *split_packet,
 167                                bool offload)
 168 {
 169 #ifdef IAVF_RX_PTYPE_OFFLOAD
 170         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 171 #endif
 172
 173         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 174                                                     rxq->mbuf_initializer);
 175         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 176         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 177
 178         rte_prefetch0(rxdp);
 179
 180         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 181         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 182
 183         /* See if we need to rearm the RX queue - gives the prefetch a bit
 184          * of time to act
 185          */
 186         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 187                 iavf_rxq_rearm(rxq);
 188
 189         /* Before we start moving massive data around, check to see if
 190          * there is actually a packet available
 191          */
 192         if (!(rxdp->wb.qword1.status_error_len &
 193               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 194                 return 0;
 195
 196         /* constants used in processing loop */
 197         const __m512i crc_adjust =
 198                 _mm512_set_epi32
 199                         (/* 1st descriptor */
 200                          0,             /* ignore non-length fields */
 201                          -rxq->crc_len, /* sub crc on data_len */
 202                          -rxq->crc_len, /* sub crc on pkt_len */
 203                          0,             /* ignore pkt_type field */
 204                          /* 2nd descriptor */
 205                          0,             /* ignore non-length fields */
 206                          -rxq->crc_len, /* sub crc on data_len */
 207                          -rxq->crc_len, /* sub crc on pkt_len */
 208                          0,             /* ignore pkt_type field */
 209                          /* 3rd descriptor */
 210                          0,             /* ignore non-length fields */
 211                          -rxq->crc_len, /* sub crc on data_len */
 212                          -rxq->crc_len, /* sub crc on pkt_len */
 213                          0,             /* ignore pkt_type field */
 214                          /* 4th descriptor */
 215                          0,             /* ignore non-length fields */
 216                          -rxq->crc_len, /* sub crc on data_len */
 217                          -rxq->crc_len, /* sub crc on pkt_len */
 218                          0              /* ignore pkt_type field */
 219                         );
 220
 221         /* 8 packets DD mask, LSB in each 32-bit value */
 222         const __m256i dd_check = _mm256_set1_epi32(1);
 223
 224         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 225         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 226                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 227
 228         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 229         const __m512i shuf_msk =
 230                 _mm512_set_epi32
 231                         (/* 1st descriptor */
 232                          0x07060504,    /* octet 4~7, 32bits rss */
 233                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 234                                         /* octet 15~14, 16 bits data_len */
 235                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 236                                         /* octet 15~14, low 16 bits pkt_len */
 237                          0xFFFFFFFF,    /* pkt_type set as unknown */
 238                          /* 2nd descriptor */
 239                          0x07060504,    /* octet 4~7, 32bits rss */
 240                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 241                                         /* octet 15~14, 16 bits data_len */
 242                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 243                                         /* octet 15~14, low 16 bits pkt_len */
 244                          0xFFFFFFFF,    /* pkt_type set as unknown */
 245                          /* 3rd descriptor */
 246                          0x07060504,    /* octet 4~7, 32bits rss */
 247                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 248                                         /* octet 15~14, 16 bits data_len */
 249                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 250                                         /* octet 15~14, low 16 bits pkt_len */
 251                          0xFFFFFFFF,    /* pkt_type set as unknown */
 252                          /* 4th descriptor */
 253                          0x07060504,    /* octet 4~7, 32bits rss */
 254                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 255                                         /* octet 15~14, 16 bits data_len */
 256                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 257                                         /* octet 15~14, low 16 bits pkt_len */
 258                          0xFFFFFFFF     /* pkt_type set as unknown */
 259                         );
 260         /**
 261          * compile-time check the above crc and shuffle layout is correct.
 262          * NOTE: the first field (lowest address) is given last in set_epi
 263          * calls above.
 264          */
 265         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 266                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 267         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 268                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 269         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 270                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 271         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 272                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 273
 274         uint16_t i, received;
 275
 276         for (i = 0, received = 0; i < nb_pkts;
 277              i += IAVF_DESCS_PER_LOOP_AVX,
 278              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 279                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 280                 _mm256_storeu_si256((void *)&rx_pkts[i],
 281                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 282 #ifdef RTE_ARCH_X86_64
 283                 _mm256_storeu_si256
 284                         ((void *)&rx_pkts[i + 4],
 285                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 286 #endif
 287
 288                 __m512i raw_desc0_3, raw_desc4_7;
 289                 const __m128i raw_desc7 =
 290                         _mm_load_si128((void *)(rxdp + 7));
 291                 rte_compiler_barrier();
 292                 const __m128i raw_desc6 =
 293                         _mm_load_si128((void *)(rxdp + 6));
 294                 rte_compiler_barrier();
 295                 const __m128i raw_desc5 =
 296                         _mm_load_si128((void *)(rxdp + 5));
 297                 rte_compiler_barrier();
 298                 const __m128i raw_desc4 =
 299                         _mm_load_si128((void *)(rxdp + 4));
 300                 rte_compiler_barrier();
 301                 const __m128i raw_desc3 =
 302                         _mm_load_si128((void *)(rxdp + 3));
 303                 rte_compiler_barrier();
 304                 const __m128i raw_desc2 =
 305                         _mm_load_si128((void *)(rxdp + 2));
 306                 rte_compiler_barrier();
 307                 const __m128i raw_desc1 =
 308                         _mm_load_si128((void *)(rxdp + 1));
 309                 rte_compiler_barrier();
 310                 const __m128i raw_desc0 =
 311                         _mm_load_si128((void *)(rxdp + 0));
 312
 313                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 314                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 315                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 316                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 317                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 318                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 319                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 320                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 321
 322                 if (split_packet) {
 323                         int j;
 324
 325                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 326                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 327                 }
 328
 329                 /**
 330                  * convert descriptors 4-7 into mbufs, adjusting length and
 331                  * re-arranging fields. Then write into the mbuf
 332                  */
 333                 const __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,
 334                                                          PKTLEN_SHIFT);
 335                 const __m512i desc4_7 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 336                                                                 raw_desc4_7,
 337                                                                 len4_7);
 338                 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
 339
 340                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 341 #ifdef IAVF_RX_PTYPE_OFFLOAD
 342                 /**
 343                  * to get packet types, shift 64-bit values down 30 bits
 344                  * and so ptype is in lower 8-bits in each
 345                  */
 346                 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
 347                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 348                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 349                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 350                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 351                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 352                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 353
 354                 const __m512i ptype4_7 = _mm512_set_epi32
 355                         (0, 0, 0, type_table[ptype7],
 356                          0, 0, 0, type_table[ptype6],
 357                          0, 0, 0, type_table[ptype5],
 358                          0, 0, 0, type_table[ptype4]);
 359                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 360 #endif
 361
 362                 /**
 363                  * convert descriptors 0-3 into mbufs, adjusting length and
 364                  * re-arranging fields. Then write into the mbuf
 365                  */
 366                 const __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,
 367                                                          PKTLEN_SHIFT);
 368                 const __m512i desc0_3 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 369                                                                 raw_desc0_3,
 370                                                                 len0_3);
 371                 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
 372
 373                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 374 #ifdef IAVF_RX_PTYPE_OFFLOAD
 375                 /* get the packet types */
 376                 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
 377                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 378                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 379                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 380                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 381                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 382                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 383
 384                 const __m512i ptype0_3 = _mm512_set_epi32
 385                         (0, 0, 0, type_table[ptype3],
 386                          0, 0, 0, type_table[ptype2],
 387                          0, 0, 0, type_table[ptype1],
 388                          0, 0, 0, type_table[ptype0]);
 389                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 390 #endif
 391
 392                 /**
 393                  * use permute/extract to get status content
 394                  * After the operations, the packets status flags are in the
 395                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 396                  */
 397                 /* merge the status bits into one register */
 398                 const __m512i status_permute_msk = _mm512_set_epi32
 399                         (0, 0, 0, 0,
 400                          0, 0, 0, 0,
 401                          22, 30, 6, 14,
 402                          18, 26, 2, 10);
 403                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 404                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 405                 __m256i status0_7 = _mm512_extracti64x4_epi64
 406                         (raw_status0_7, 0);
 407
 408                 /* now do flag manipulation */
 409
 410                 /* merge flags */
 411                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 412
 413                 if (offload) {
 414 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 415                         /* Status/Error flag masks */
 416                         /**
 417                          * mask everything except RSS, flow director and VLAN flags
 418                          * bit2 is for VLAN tag, bit11 for flow director indication
 419                          * bit13:12 for RSS indication. Bits 3-5 of error
 420                          * field (bits 22-24) are for IP/L4 checksum errors
 421                          */
 422                         const __m256i flags_mask =
 423                                 _mm256_set1_epi32((1 << 2) | (1 << 11) |
 424                                                   (3 << 12) | (7 << 22));
 425 #endif
 426
 427 #ifdef IAVF_RX_VLAN_OFFLOAD
 428                         /**
 429                          * data to be shuffled by result of flag mask. If VLAN bit is set,
 430                          * (bit 2), then position 4 in this array will be used in the
 431                          * destination
 432                          */
 433                         const __m256i vlan_flags_shuf =
 434                                 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
 435                                                  0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
 436 #endif
 437
 438 #ifdef IAVF_RX_RSS_OFFLOAD
 439                         /**
 440                          * data to be shuffled by result of flag mask, shifted down 11.
 441                          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 442                          * place.
 443                          */
 444                         const __m256i rss_flags_shuf =
 445                                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 446                                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 447                                                 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
 448                                                 0, 0, 0, 0, 0, 0, 0, 0,
 449                                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 450                                                 0, 0, 0, 0, PKT_RX_FDIR, 0);
 451 #endif
 452
 453 #ifdef IAVF_RX_CSUM_OFFLOAD
 454                         /**
 455                          * data to be shuffled by the result of the flags mask shifted by 22
 456                          * bits.  This gives use the l3_l4 flags.
 457                          */
 458                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 459                                         /* shift right 1 bit to make sure it not exceed 255 */
 460                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 461                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 462                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
 463                                          PKT_RX_L4_CKSUM_BAD) >> 1,
 464                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 465                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
 466                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 467                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 468                                         PKT_RX_IP_CKSUM_BAD >> 1,
 469                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
 470                                         /* second 128-bits */
 471                                         0, 0, 0, 0, 0, 0, 0, 0,
 472                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 473                                          PKT_RX_IP_CKSUM_BAD) >> 1,
 474                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD |
 475                                          PKT_RX_L4_CKSUM_BAD) >> 1,
 476                                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 477                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_OUTER_IP_CKSUM_BAD) >> 1,
 478                                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 479                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 480                                         PKT_RX_IP_CKSUM_BAD >> 1,
 481                                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 482
 483                         const __m256i cksum_mask =
 484                                 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 485                                                   PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 486                                                   PKT_RX_OUTER_IP_CKSUM_BAD);
 487 #endif
 488
 489 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 490                         /* get only flag/error bits we want */
 491                         const __m256i flag_bits =
 492                                 _mm256_and_si256(status0_7, flags_mask);
 493 #endif
 494                         /* set vlan and rss flags */
 495 #ifdef IAVF_RX_VLAN_OFFLOAD
 496                         const __m256i vlan_flags =
 497                                 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 498 #endif
 499 #ifdef IAVF_RX_RSS_OFFLOAD
 500                         const __m256i rss_flags =
 501                                 _mm256_shuffle_epi8(rss_flags_shuf,
 502                                                     _mm256_srli_epi32(flag_bits, 11));
 503 #endif
 504 #ifdef IAVF_RX_CSUM_OFFLOAD
 505                         /**
 506                          * l3_l4_error flags, shuffle, then shift to correct adjustment
 507                          * of flags in flags_shuf, and finally mask out extra bits
 508                          */
 509                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 510                                                         _mm256_srli_epi32(flag_bits, 22));
 511                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 512                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 513 #endif
 514
 515 #ifdef IAVF_RX_CSUM_OFFLOAD
 516                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
 517 #endif
 518 #ifdef IAVF_RX_RSS_OFFLOAD
 519                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_flags);
 520 #endif
 521 #ifdef IAVF_RX_VLAN_OFFLOAD
 522                         mbuf_flags = _mm256_or_si256(mbuf_flags, vlan_flags);
 523 #endif
 524                 }
 525
 526                 /**
 527                  * At this point, we have the 8 sets of flags in the low 16-bits
 528                  * of each 32-bit value in vlan0.
 529                  * We want to extract these, and merge them with the mbuf init
 530                  * data so we can do a single write to the mbuf to set the flags
 531                  * and all the other initialization fields. Extracting the
 532                  * appropriate flags means that we have to do a shift and blend
 533                  * for each mbuf before we do the write. However, we can also
 534                  * add in the previously computed rx_descriptor fields to
 535                  * make a single 256-bit write per mbuf
 536                  */
 537                 /* check the structure matches expectations */
 538                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 539                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 540                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 541                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 542                                                     rearm_data),
 543                                                     16));
 544                 /* build up data and do writes */
 545                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 546                         rearm6, rearm7;
 547                 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 548                 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 549                 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 550                 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 551
 552                 if (offload) {
 553                         rearm6 = _mm256_blend_epi32(mbuf_init,
 554                                                     _mm256_slli_si256(mbuf_flags, 8),
 555                                                     0x04);
 556                         rearm4 = _mm256_blend_epi32(mbuf_init,
 557                                                     _mm256_slli_si256(mbuf_flags, 4),
 558                                                     0x04);
 559                         rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 560                         rearm0 = _mm256_blend_epi32(mbuf_init,
 561                                                     _mm256_srli_si256(mbuf_flags, 4),
 562                                                     0x04);
 563                         /* permute to add in the rx_descriptor e.g. rss fields */
 564                         rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 565                         rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 566                         rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 567                         rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 568                 } else {
 569                         rearm6 = _mm256_permute2f128_si256(mbuf_init, mb6_7, 0x20);
 570                         rearm4 = _mm256_permute2f128_si256(mbuf_init, mb4_5, 0x20);
 571                         rearm2 = _mm256_permute2f128_si256(mbuf_init, mb2_3, 0x20);
 572                         rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
 573                 }
 574                 /* write to mbuf */
 575                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 576                                     rearm6);
 577                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 578                                     rearm4);
 579                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 580                                     rearm2);
 581                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 582                                     rearm0);
 583
 584                 /* repeat for the odd mbufs */
 585                 if (offload) {
 586                         const __m256i odd_flags =
 587                                 _mm256_castsi128_si256
 588                                         (_mm256_extracti128_si256(mbuf_flags, 1));
 589                         rearm7 = _mm256_blend_epi32(mbuf_init,
 590                                                     _mm256_slli_si256(odd_flags, 8),
 591                                                     0x04);
 592                         rearm5 = _mm256_blend_epi32(mbuf_init,
 593                                                     _mm256_slli_si256(odd_flags, 4),
 594                                                     0x04);
 595                         rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 596                         rearm1 = _mm256_blend_epi32(mbuf_init,
 597                                                     _mm256_srli_si256(odd_flags, 4),
 598                                                     0x04);
 599                         /* since odd mbufs are already in hi 128-bits use blend */
 600                         rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 601                         rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 602                         rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 603                         rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 604                 } else {
 605                         rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
 606                         rearm5 = _mm256_blend_epi32(mbuf_init, mb4_5, 0xF0);
 607                         rearm3 = _mm256_blend_epi32(mbuf_init, mb2_3, 0xF0);
 608                         rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
 609                 }
 610                 /* again write to mbufs */
 611                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 612                                     rearm7);
 613                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 614                                     rearm5);
 615                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 616                                     rearm3);
 617                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 618                                     rearm1);
 619
 620                 /* extract and record EOP bit */
 621                 if (split_packet) {
 622                         const __m128i eop_mask =
 623                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 624                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 625                                                                      eop_check);
 626                         /* pack status bits into a single 128-bit register */
 627                         const __m128i eop_bits =
 628                                 _mm_packus_epi32
 629                                         (_mm256_castsi256_si128(eop_bits256),
 630                                          _mm256_extractf128_si256(eop_bits256,
 631                                                                   1));
 632                         /**
 633                          * flip bits, and mask out the EOP bit, which is now
 634                          * a split-packet bit i.e. !EOP, rather than EOP one.
 635                          */
 636                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 637                                                               eop_mask);
 638                         /**
 639                          * eop bits are out of order, so we need to shuffle them
 640                          * back into order again. In doing so, only use low 8
 641                          * bits, which acts like another pack instruction
 642                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 643                          * [Since we use epi8, the 16-bit positions are
 644                          * multiplied by 2 in the eop_shuffle value.]
 645                          */
 646                         __m128i eop_shuffle =
 647                                 _mm_set_epi8(/* zero hi 64b */
 648                                              0xFF, 0xFF, 0xFF, 0xFF,
 649                                              0xFF, 0xFF, 0xFF, 0xFF,
 650                                              /* move values to lo 64b */
 651                                              8, 0, 10, 2,
 652                                              12, 4, 14, 6);
 653                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 654                         *(uint64_t *)split_packet =
 655                                 _mm_cvtsi128_si64(split_bits);
 656                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 657                 }
 658
 659                 /* perform dd_check */
 660                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 661                 status0_7 = _mm256_packs_epi32(status0_7,
 662                                                _mm256_setzero_si256());
 663
 664                 uint64_t burst = __builtin_popcountll
 665                                         (_mm_cvtsi128_si64
 666                                                 (_mm256_extracti128_si256
 667                                                         (status0_7, 1)));
 668                 burst += __builtin_popcountll
 669                                 (_mm_cvtsi128_si64
 670                                         (_mm256_castsi256_si128(status0_7)));
 671                 received += burst;
 672                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 673                         break;
 674         }
 675
 676         /* update tail pointers */
 677         rxq->rx_tail += received;
 678         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 679         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
 680                 rxq->rx_tail--;
 681                 received--;
 682         }
 683         rxq->rxrearm_nb += received;
 684         return received;
 685 }
 686
 687 static inline __m256i
 688 flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
 689 {
 690 #define FDID_MIS_MAGIC 0xFFFFFFFF
 691         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
 692         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
 693         const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
 694                                                        PKT_RX_FDIR_ID);
 695         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 696         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 697         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 698                                                fdir_mis_mask);
 699         /* this XOR op results to bit-reverse the fdir_mask */
 700         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 701         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 702
 703         return fdir_flags;
 704 }
 705
 706 static inline uint16_t
 707 _iavf_recv_raw_pkts_vec_avx512_flex_rxd(struct iavf_rx_queue *rxq,
 708                                         struct rte_mbuf **rx_pkts,
 709                                         uint16_t nb_pkts, uint8_t *split_packet)
 710 {
 711         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 712
 713         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 714                                                     rxq->mbuf_initializer);
 715         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 716         volatile union iavf_rx_flex_desc *rxdp =
 717                 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 718
 719         rte_prefetch0(rxdp);
 720
 721         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 722         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 723
 724         /* See if we need to rearm the RX queue - gives the prefetch a bit
 725          * of time to act
 726          */
 727         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 728                 iavf_rxq_rearm(rxq);
 729
 730         /* Before we start moving massive data around, check to see if
 731          * there is actually a packet available
 732          */
 733         if (!(rxdp->wb.status_error0 &
 734               rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 735                 return 0;
 736
 737         /* constants used in processing loop */
 738         const __m512i crc_adjust =
 739                 _mm512_set_epi32
 740                         (/* 1st descriptor */
 741                          0,             /* ignore non-length fields */
 742                          -rxq->crc_len, /* sub crc on data_len */
 743                          -rxq->crc_len, /* sub crc on pkt_len */
 744                          0,             /* ignore pkt_type field */
 745                          /* 2nd descriptor */
 746                          0,             /* ignore non-length fields */
 747                          -rxq->crc_len, /* sub crc on data_len */
 748                          -rxq->crc_len, /* sub crc on pkt_len */
 749                          0,             /* ignore pkt_type field */
 750                          /* 3rd descriptor */
 751                          0,             /* ignore non-length fields */
 752                          -rxq->crc_len, /* sub crc on data_len */
 753                          -rxq->crc_len, /* sub crc on pkt_len */
 754                          0,             /* ignore pkt_type field */
 755                          /* 4th descriptor */
 756                          0,             /* ignore non-length fields */
 757                          -rxq->crc_len, /* sub crc on data_len */
 758                          -rxq->crc_len, /* sub crc on pkt_len */
 759                          0              /* ignore pkt_type field */
 760                         );
 761
 762         /* 8 packets DD mask, LSB in each 32-bit value */
 763         const __m256i dd_check = _mm256_set1_epi32(1);
 764
 765         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 766         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 767                         IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
 768
 769         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 770         const __m512i shuf_msk =
 771                 _mm512_set_epi32
 772                         (/* 1st descriptor */
 773                          0xFFFFFFFF,    /* rss hash parsed separately */
 774                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 775                                         /* octet 4~5, 16 bits data_len */
 776                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 777                                         /* octet 4~5, 16 bits pkt_len */
 778                          0xFFFFFFFF,    /* pkt_type set as unknown */
 779                          /* 2nd descriptor */
 780                          0xFFFFFFFF,    /* rss hash parsed separately */
 781                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 782                                         /* octet 4~5, 16 bits data_len */
 783                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 784                                         /* octet 4~5, 16 bits pkt_len */
 785                          0xFFFFFFFF,    /* pkt_type set as unknown */
 786                          /* 3rd descriptor */
 787                          0xFFFFFFFF,    /* rss hash parsed separately */
 788                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 789                                         /* octet 4~5, 16 bits data_len */
 790                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 791                                         /* octet 4~5, 16 bits pkt_len */
 792                          0xFFFFFFFF,    /* pkt_type set as unknown */
 793                          /* 4th descriptor */
 794                          0xFFFFFFFF,    /* rss hash parsed separately */
 795                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 796                                         /* octet 4~5, 16 bits data_len */
 797                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 798                                         /* octet 4~5, 16 bits pkt_len */
 799                          0xFFFFFFFF     /* pkt_type set as unknown */
 800                         );
 801         /**
 802          * compile-time check the above crc and shuffle layout is correct.
 803          * NOTE: the first field (lowest address) is given last in set_epi
 804          * calls above.
 805          */
 806         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 807                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 808         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 809                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 810         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 811                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 812         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 813                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 814
 815         /* Status/Error flag masks */
 816         /**
 817          * mask everything except Checksum Reports, RSS indication
 818          * and VLAN indication.
 819          * bit6:4 for IP/L4 checksum errors.
 820          * bit12 is for RSS indication.
 821          * bit13 is for VLAN indication.
 822          */
 823         const __m256i flags_mask =
 824                 _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 825         /**
 826          * data to be shuffled by the result of the flags mask shifted by 4
 827          * bits.  This gives use the l3_l4 flags.
 828          */
 829         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 830                         /* shift right 1 bit to make sure it not exceed 255 */
 831                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 832                          PKT_RX_IP_CKSUM_BAD) >> 1,
 833                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 834                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 835                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 836                          PKT_RX_IP_CKSUM_BAD) >> 1,
 837                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 838                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 839                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 840                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 841                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 842                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 843                         /* second 128-bits */
 844                         0, 0, 0, 0, 0, 0, 0, 0,
 845                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 846                          PKT_RX_IP_CKSUM_BAD) >> 1,
 847                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 848                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 849                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 850                          PKT_RX_IP_CKSUM_BAD) >> 1,
 851                         (PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 852                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 853                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 854                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 855                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 856                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 857         const __m256i cksum_mask =
 858                 _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 859                                   PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 860                                   PKT_RX_OUTER_IP_CKSUM_BAD);
 861         /**
 862          * data to be shuffled by result of flag mask, shifted down 12.
 863          * If RSS(bit12)/VLAN(bit13) are set,
 864          * shuffle moves appropriate flags in place.
 865          */
 866         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 867                         0, 0, 0, 0,
 868                         0, 0, 0, 0,
 869                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 870                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 871                         PKT_RX_RSS_HASH, 0,
 872                         /* end up 128-bits */
 873                         0, 0, 0, 0,
 874                         0, 0, 0, 0,
 875                         0, 0, 0, 0,
 876                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 877                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 878                         PKT_RX_RSS_HASH, 0);
 879
 880         uint16_t i, received;
 881
 882         for (i = 0, received = 0; i < nb_pkts;
 883              i += IAVF_DESCS_PER_LOOP_AVX,
 884              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 885                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 886                 _mm256_storeu_si256((void *)&rx_pkts[i],
 887                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 888 #ifdef RTE_ARCH_X86_64
 889                 _mm256_storeu_si256
 890                         ((void *)&rx_pkts[i + 4],
 891                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 892 #endif
 893
 894                 __m512i raw_desc0_3, raw_desc4_7;
 895
 896                 const __m128i raw_desc7 =
 897                         _mm_load_si128((void *)(rxdp + 7));
 898                 rte_compiler_barrier();
 899                 const __m128i raw_desc6 =
 900                         _mm_load_si128((void *)(rxdp + 6));
 901                 rte_compiler_barrier();
 902                 const __m128i raw_desc5 =
 903                         _mm_load_si128((void *)(rxdp + 5));
 904                 rte_compiler_barrier();
 905                 const __m128i raw_desc4 =
 906                         _mm_load_si128((void *)(rxdp + 4));
 907                 rte_compiler_barrier();
 908                 const __m128i raw_desc3 =
 909                         _mm_load_si128((void *)(rxdp + 3));
 910                 rte_compiler_barrier();
 911                 const __m128i raw_desc2 =
 912                         _mm_load_si128((void *)(rxdp + 2));
 913                 rte_compiler_barrier();
 914                 const __m128i raw_desc1 =
 915                         _mm_load_si128((void *)(rxdp + 1));
 916                 rte_compiler_barrier();
 917                 const __m128i raw_desc0 =
 918                         _mm_load_si128((void *)(rxdp + 0));
 919
 920                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 921                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 922                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 923                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 924                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 925                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 926                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 927                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 928
 929                 if (split_packet) {
 930                         int j;
 931
 932                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 933                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 934                 }
 935
 936                 /**
 937                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 938                  * Then write into the mbuf.
 939                  */
 940                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 941
 942                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 943                 /**
 944                  * to get packet types, ptype is located in bit16-25
 945                  * of each 128bits
 946                  */
 947                 const __m512i ptype_mask =
 948                         _mm512_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
 949                 const __m512i ptypes4_7 =
 950                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 951                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 952                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 953                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 954                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 955                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 956                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 957
 958                 const __m512i ptype4_7 = _mm512_set_epi32
 959                         (0, 0, 0, type_table[ptype7],
 960                          0, 0, 0, type_table[ptype6],
 961                          0, 0, 0, type_table[ptype5],
 962                          0, 0, 0, type_table[ptype4]);
 963                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 964
 965                 /**
 966                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 967                  * Then write into the mbuf.
 968                  */
 969                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 970
 971                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 972                 /**
 973                  * to get packet types, ptype is located in bit16-25
 974                  * of each 128bits
 975                  */
 976                 const __m512i ptypes0_3 =
 977                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 978                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 979                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 980                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 981                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 982                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 983                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 984
 985                 const __m512i ptype0_3 = _mm512_set_epi32
 986                         (0, 0, 0, type_table[ptype3],
 987                          0, 0, 0, type_table[ptype2],
 988                          0, 0, 0, type_table[ptype1],
 989                          0, 0, 0, type_table[ptype0]);
 990                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 991
 992                 /**
 993                  * use permute/extract to get status content
 994                  * After the operations, the packets status flags are in the
 995                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 996                  */
 997                 /* merge the status bits into one register */
 998                 const __m512i status_permute_msk = _mm512_set_epi32
 999                         (0, 0, 0, 0,
1000                          0, 0, 0, 0,
1001                          22, 30, 6, 14,
1002                          18, 26, 2, 10);
1003                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
1004                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
1005                 __m256i status0_7 = _mm512_extracti64x4_epi64
1006                         (raw_status0_7, 0);
1007
1008                 /* now do flag manipulation */
1009
1010                 /* get only flag/error bits we want */
1011                 const __m256i flag_bits =
1012                         _mm256_and_si256(status0_7, flags_mask);
1013                 /**
1014                  * l3_l4_error flags, shuffle, then shift to correct adjustment
1015                  * of flags in flags_shuf, and finally mask out extra bits
1016                  */
1017                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
1018                                 _mm256_srli_epi32(flag_bits, 4));
1019                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
1020                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
1021                 /* set rss and vlan flags */
1022                 const __m256i rss_vlan_flag_bits =
1023                         _mm256_srli_epi32(flag_bits, 12);
1024                 const __m256i rss_vlan_flags =
1025                         _mm256_shuffle_epi8(rss_vlan_flags_shuf,
1026                                             rss_vlan_flag_bits);
1027
1028                 /* merge flags */
1029                 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
1030                                                      rss_vlan_flags);
1031
1032                 if (rxq->fdir_enabled) {
1033                         const __m512i fdir_permute_mask = _mm512_set_epi32
1034                                 (0, 0, 0, 0,
1035                                  0, 0, 0, 0,
1036                                  7, 15, 23, 31,
1037                                  3, 11, 19, 27);
1038                         __m512i fdir_tmp = _mm512_permutex2var_epi32
1039                                 (raw_desc0_3, fdir_permute_mask, raw_desc4_7);
1040                         const __m256i fdir_id0_7 = _mm512_extracti64x4_epi64
1041                                 (fdir_tmp, 0);
1042                         const __m256i fdir_flags =
1043                                 flex_rxd_to_fdir_flags_vec_avx512(fdir_id0_7);
1044
1045                         /* merge with fdir_flags */
1046                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
1047
1048                         /* write to mbuf: have to use scalar store here */
1049                         rx_pkts[i + 0]->hash.fdir.hi =
1050                                 _mm256_extract_epi32(fdir_id0_7, 3);
1051
1052                         rx_pkts[i + 1]->hash.fdir.hi =
1053                                 _mm256_extract_epi32(fdir_id0_7, 7);
1054
1055                         rx_pkts[i + 2]->hash.fdir.hi =
1056                                 _mm256_extract_epi32(fdir_id0_7, 2);
1057
1058                         rx_pkts[i + 3]->hash.fdir.hi =
1059                                 _mm256_extract_epi32(fdir_id0_7, 6);
1060
1061                         rx_pkts[i + 4]->hash.fdir.hi =
1062                                 _mm256_extract_epi32(fdir_id0_7, 1);
1063
1064                         rx_pkts[i + 5]->hash.fdir.hi =
1065                                 _mm256_extract_epi32(fdir_id0_7, 5);
1066
1067                         rx_pkts[i + 6]->hash.fdir.hi =
1068                                 _mm256_extract_epi32(fdir_id0_7, 0);
1069
1070                         rx_pkts[i + 7]->hash.fdir.hi =
1071                                 _mm256_extract_epi32(fdir_id0_7, 4);
1072                 } /* if() on fdir_enabled */
1073
1074                 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
1075                 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
1076                 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
1077                 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
1078
1079 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1080                 /**
1081                  * needs to load 2nd 16B of each desc for RSS hash parsing,
1082                  * will cause performance drop to get into this context.
1083                  */
1084                 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1085                     DEV_RX_OFFLOAD_RSS_HASH) {
1086                         /* load bottom half of every 32B desc */
1087                         const __m128i raw_desc_bh7 =
1088                                 _mm_load_si128
1089                                         ((void *)(&rxdp[7].wb.status_error1));
1090                         rte_compiler_barrier();
1091                         const __m128i raw_desc_bh6 =
1092                                 _mm_load_si128
1093                                         ((void *)(&rxdp[6].wb.status_error1));
1094                         rte_compiler_barrier();
1095                         const __m128i raw_desc_bh5 =
1096                                 _mm_load_si128
1097                                         ((void *)(&rxdp[5].wb.status_error1));
1098                         rte_compiler_barrier();
1099                         const __m128i raw_desc_bh4 =
1100                                 _mm_load_si128
1101                                         ((void *)(&rxdp[4].wb.status_error1));
1102                         rte_compiler_barrier();
1103                         const __m128i raw_desc_bh3 =
1104                                 _mm_load_si128
1105                                         ((void *)(&rxdp[3].wb.status_error1));
1106                         rte_compiler_barrier();
1107                         const __m128i raw_desc_bh2 =
1108                                 _mm_load_si128
1109                                         ((void *)(&rxdp[2].wb.status_error1));
1110                         rte_compiler_barrier();
1111                         const __m128i raw_desc_bh1 =
1112                                 _mm_load_si128
1113                                         ((void *)(&rxdp[1].wb.status_error1));
1114                         rte_compiler_barrier();
1115                         const __m128i raw_desc_bh0 =
1116                                 _mm_load_si128
1117                                         ((void *)(&rxdp[0].wb.status_error1));
1118
1119                         __m256i raw_desc_bh6_7 =
1120                                 _mm256_inserti128_si256
1121                                         (_mm256_castsi128_si256(raw_desc_bh6),
1122                                          raw_desc_bh7, 1);
1123                         __m256i raw_desc_bh4_5 =
1124                                 _mm256_inserti128_si256
1125                                         (_mm256_castsi128_si256(raw_desc_bh4),
1126                                          raw_desc_bh5, 1);
1127                         __m256i raw_desc_bh2_3 =
1128                                 _mm256_inserti128_si256
1129                                         (_mm256_castsi128_si256(raw_desc_bh2),
1130                                          raw_desc_bh3, 1);
1131                         __m256i raw_desc_bh0_1 =
1132                                 _mm256_inserti128_si256
1133                                         (_mm256_castsi128_si256(raw_desc_bh0),
1134                                          raw_desc_bh1, 1);
1135
1136                         /**
1137                          * to shift the 32b RSS hash value to the
1138                          * highest 32b of each 128b before mask
1139                          */
1140                         __m256i rss_hash6_7 =
1141                                 _mm256_slli_epi64(raw_desc_bh6_7, 32);
1142                         __m256i rss_hash4_5 =
1143                                 _mm256_slli_epi64(raw_desc_bh4_5, 32);
1144                         __m256i rss_hash2_3 =
1145                                 _mm256_slli_epi64(raw_desc_bh2_3, 32);
1146                         __m256i rss_hash0_1 =
1147                                 _mm256_slli_epi64(raw_desc_bh0_1, 32);
1148
1149                         __m256i rss_hash_msk =
1150                                 _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
1151                                                  0xFFFFFFFF, 0, 0, 0);
1152
1153                         rss_hash6_7 = _mm256_and_si256
1154                                         (rss_hash6_7, rss_hash_msk);
1155                         rss_hash4_5 = _mm256_and_si256
1156                                         (rss_hash4_5, rss_hash_msk);
1157                         rss_hash2_3 = _mm256_and_si256
1158                                         (rss_hash2_3, rss_hash_msk);
1159                         rss_hash0_1 = _mm256_and_si256
1160                                         (rss_hash0_1, rss_hash_msk);
1161
1162                         mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
1163                         mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
1164                         mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
1165                         mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
1166                 } /* if() on RSS hash parsing */
1167 #endif
1168
1169                 /**
1170                  * At this point, we have the 8 sets of flags in the low 16-bits
1171                  * of each 32-bit value in vlan0.
1172                  * We want to extract these, and merge them with the mbuf init
1173                  * data so we can do a single write to the mbuf to set the flags
1174                  * and all the other initialization fields. Extracting the
1175                  * appropriate flags means that we have to do a shift and blend
1176                  * for each mbuf before we do the write. However, we can also
1177                  * add in the previously computed rx_descriptor fields to
1178                  * make a single 256-bit write per mbuf
1179                  */
1180                 /* check the structure matches expectations */
1181                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1182                                  offsetof(struct rte_mbuf, rearm_data) + 8);
1183                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1184                                  RTE_ALIGN(offsetof(struct rte_mbuf,
1185                                                     rearm_data),
1186                                                     16));
1187                 /* build up data and do writes */
1188                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1189                         rearm6, rearm7;
1190                 rearm6 = _mm256_blend_epi32(mbuf_init,
1191                                             _mm256_slli_si256(mbuf_flags, 8),
1192                                             0x04);
1193                 rearm4 = _mm256_blend_epi32(mbuf_init,
1194                                             _mm256_slli_si256(mbuf_flags, 4),
1195                                             0x04);
1196                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1197                 rearm0 = _mm256_blend_epi32(mbuf_init,
1198                                             _mm256_srli_si256(mbuf_flags, 4),
1199                                             0x04);
1200                 /* permute to add in the rx_descriptor e.g. rss fields */
1201                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1202                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1203                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1204                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1205                 /* write to mbuf */
1206                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1207                                     rearm6);
1208                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1209                                     rearm4);
1210                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1211                                     rearm2);
1212                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1213                                     rearm0);
1214
1215                 /* repeat for the odd mbufs */
1216                 const __m256i odd_flags =
1217                         _mm256_castsi128_si256
1218                                 (_mm256_extracti128_si256(mbuf_flags, 1));
1219                 rearm7 = _mm256_blend_epi32(mbuf_init,
1220                                             _mm256_slli_si256(odd_flags, 8),
1221                                             0x04);
1222                 rearm5 = _mm256_blend_epi32(mbuf_init,
1223                                             _mm256_slli_si256(odd_flags, 4),
1224                                             0x04);
1225                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1226                 rearm1 = _mm256_blend_epi32(mbuf_init,
1227                                             _mm256_srli_si256(odd_flags, 4),
1228                                             0x04);
1229                 /* since odd mbufs are already in hi 128-bits use blend */
1230                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1231                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1232                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1233                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1234                 /* again write to mbufs */
1235                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1236                                     rearm7);
1237                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1238                                     rearm5);
1239                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1240                                     rearm3);
1241                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1242                                     rearm1);
1243
1244                 /* extract and record EOP bit */
1245                 if (split_packet) {
1246                         const __m128i eop_mask =
1247                                 _mm_set1_epi16(1 <<
1248                                                IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1249                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1250                                                                      eop_check);
1251                         /* pack status bits into a single 128-bit register */
1252                         const __m128i eop_bits =
1253                                 _mm_packus_epi32
1254                                         (_mm256_castsi256_si128(eop_bits256),
1255                                          _mm256_extractf128_si256(eop_bits256,
1256                                                                   1));
1257                         /**
1258                          * flip bits, and mask out the EOP bit, which is now
1259                          * a split-packet bit i.e. !EOP, rather than EOP one.
1260                          */
1261                         __m128i split_bits = _mm_andnot_si128(eop_bits,
1262                                                               eop_mask);
1263                         /**
1264                          * eop bits are out of order, so we need to shuffle them
1265                          * back into order again. In doing so, only use low 8
1266                          * bits, which acts like another pack instruction
1267                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1268                          * [Since we use epi8, the 16-bit positions are
1269                          * multiplied by 2 in the eop_shuffle value.]
1270                          */
1271                         __m128i eop_shuffle =
1272                                 _mm_set_epi8(/* zero hi 64b */
1273                                              0xFF, 0xFF, 0xFF, 0xFF,
1274                                              0xFF, 0xFF, 0xFF, 0xFF,
1275                                              /* move values to lo 64b */
1276                                              8, 0, 10, 2,
1277                                              12, 4, 14, 6);
1278                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1279                         *(uint64_t *)split_packet =
1280                                 _mm_cvtsi128_si64(split_bits);
1281                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
1282                 }
1283
1284                 /* perform dd_check */
1285                 status0_7 = _mm256_and_si256(status0_7, dd_check);
1286                 status0_7 = _mm256_packs_epi32(status0_7,
1287                                                _mm256_setzero_si256());
1288
1289                 uint64_t burst = __builtin_popcountll
1290                                         (_mm_cvtsi128_si64
1291                                                 (_mm256_extracti128_si256
1292                                                         (status0_7, 1)));
1293                 burst += __builtin_popcountll
1294                                 (_mm_cvtsi128_si64
1295                                         (_mm256_castsi256_si128(status0_7)));
1296                 received += burst;
1297                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1298                         break;
1299         }
1300
1301         /* update tail pointers */
1302         rxq->rx_tail += received;
1303         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1304         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
1305                 rxq->rx_tail--;
1306                 received--;
1307         }
1308         rxq->rxrearm_nb += received;
1309         return received;
1310 }
1311
1312 /**
1313  * Notice:
1314  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1315  */
1316 uint16_t
1317 iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1318                           uint16_t nb_pkts)
1319 {
1320         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts,
1321                                               NULL, false);
1322 }
1323
1324 /**
1325  * Notice:
1326  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1327  */
1328 uint16_t
1329 iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1330                                    uint16_t nb_pkts)
1331 {
1332         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue, rx_pkts,
1333                                                        nb_pkts, NULL);
1334 }
1335
1336 /**
1337  * vPMD receive routine that reassembles single burst of 32 scattered packets
1338  * Notice:
1339  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1340  */
1341 static __rte_always_inline uint16_t
1342 iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1343                                      uint16_t nb_pkts, bool offload)
1344 {
1345         struct iavf_rx_queue *rxq = rx_queue;
1346         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1347
1348         /* get some new buffers */
1349         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
1350                                                           split_flags, offload);
1351         if (nb_bufs == 0)
1352                 return 0;
1353
1354         /* happy day case, full burst + no packets to be joined */
1355         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1356
1357         if (!rxq->pkt_first_seg &&
1358             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1359             split_fl64[2] == 0 && split_fl64[3] == 0)
1360                 return nb_bufs;
1361
1362         /* reassemble any packets that need reassembly*/
1363         unsigned int i = 0;
1364
1365         if (!rxq->pkt_first_seg) {
1366                 /* find the first split flag, and only reassemble then*/
1367                 while (i < nb_bufs && !split_flags[i])
1368                         i++;
1369                 if (i == nb_bufs)
1370                         return nb_bufs;
1371                 rxq->pkt_first_seg = rx_pkts[i];
1372         }
1373         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1374                                       &split_flags[i]);
1375 }
1376
1377 /**
1378  * vPMD receive routine that reassembles scattered packets.
1379  * Main receive routine that can handle arbitrary burst sizes
1380  * Notice:
1381  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1382  */
1383 static __rte_always_inline uint16_t
1384 iavf_recv_scattered_pkts_vec_avx512_cmn(void *rx_queue, struct rte_mbuf **rx_pkts,
1385                                         uint16_t nb_pkts, bool offload)
1386 {
1387         uint16_t retval = 0;
1388
1389         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1390                 uint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,
1391                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST, offload);
1392                 retval += burst;
1393                 nb_pkts -= burst;
1394                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1395                         return retval;
1396         }
1397         return retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,
1398                                 rx_pkts + retval, nb_pkts, offload);
1399 }
1400
1401 uint16_t
1402 iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1403                                     uint16_t nb_pkts)
1404 {
1405         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1406                                                        nb_pkts, false);
1407 }
1408
1409 /**
1410  * vPMD receive routine that reassembles single burst of
1411  * 32 scattered packets for flex RxD
1412  * Notice:
1413  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1414  */
1415 static uint16_t
1416 iavf_recv_scattered_burst_vec_avx512_flex_rxd(void *rx_queue,
1417                                               struct rte_mbuf **rx_pkts,
1418                                               uint16_t nb_pkts)
1419 {
1420         struct iavf_rx_queue *rxq = rx_queue;
1421         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1422
1423         /* get some new buffers */
1424         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rxq,
1425                                         rx_pkts, nb_pkts, split_flags);
1426         if (nb_bufs == 0)
1427                 return 0;
1428
1429         /* happy day case, full burst + no packets to be joined */
1430         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1431
1432         if (!rxq->pkt_first_seg &&
1433             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1434             split_fl64[2] == 0 && split_fl64[3] == 0)
1435                 return nb_bufs;
1436
1437         /* reassemble any packets that need reassembly*/
1438         unsigned int i = 0;
1439
1440         if (!rxq->pkt_first_seg) {
1441                 /* find the first split flag, and only reassemble then*/
1442                 while (i < nb_bufs && !split_flags[i])
1443                         i++;
1444                 if (i == nb_bufs)
1445                         return nb_bufs;
1446                 rxq->pkt_first_seg = rx_pkts[i];
1447         }
1448         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1449                                       &split_flags[i]);
1450 }
1451
1452 /**
1453  * vPMD receive routine that reassembles scattered packets for flex RxD.
1454  * Main receive routine that can handle arbitrary burst sizes
1455  * Notice:
1456  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1457  */
1458 uint16_t
1459 iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
1460                                              struct rte_mbuf **rx_pkts,
1461                                              uint16_t nb_pkts)
1462 {
1463         uint16_t retval = 0;
1464
1465         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1466                 uint16_t burst =
1467                         iavf_recv_scattered_burst_vec_avx512_flex_rxd
1468                                 (rx_queue, rx_pkts + retval,
1469                                  IAVF_VPMD_RX_MAX_BURST);
1470                 retval += burst;
1471                 nb_pkts -= burst;
1472                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1473                         return retval;
1474         }
1475         return retval + iavf_recv_scattered_burst_vec_avx512_flex_rxd(rx_queue,
1476                                 rx_pkts + retval, nb_pkts);
1477 }
1478
1479 uint16_t
1480 iavf_recv_pkts_vec_avx512_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
1481                                   uint16_t nb_pkts)
1482 {
1483         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts,
1484                                               nb_pkts, NULL, true);
1485 }
1486
1487 uint16_t
1488 iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
1489                                             struct rte_mbuf **rx_pkts,
1490                                             uint16_t nb_pkts)
1491 {
1492         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1493                                                        nb_pkts, true);
1494 }
1495
1496 static __rte_always_inline int
1497 iavf_tx_free_bufs_avx512(struct iavf_tx_queue *txq)
1498 {
1499         struct iavf_tx_vec_entry *txep;
1500         uint32_t n;
1501         uint32_t i;
1502         int nb_free = 0;
1503         struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
1504
1505         /* check DD bits on threshold descriptor */
1506         if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
1507              rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1508             rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
1509                 return 0;
1510
1511         n = txq->rs_thresh;
1512
1513          /* first buffer to free from S/W ring is at index
1514           * tx_next_dd - (tx_rs_thresh-1)
1515           */
1516         txep = (void *)txq->sw_ring;
1517         txep += txq->next_dd - (n - 1);
1518
1519         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
1520                 struct rte_mempool *mp = txep[0].mbuf->pool;
1521                 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
1522                                                                 rte_lcore_id());
1523                 void **cache_objs;
1524
1525                 if (!cache || cache->len == 0)
1526                         goto normal;
1527
1528                 cache_objs = &cache->objs[cache->len];
1529
1530                 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
1531                         rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
1532                         goto done;
1533                 }
1534
1535                 /* The cache follows the following algorithm
1536                  *   1. Add the objects to the cache
1537                  *   2. Anything greater than the cache min value (if it crosses the
1538                  *   cache flush threshold) is flushed to the ring.
1539                  */
1540                 /* Add elements back into the cache */
1541                 uint32_t copied = 0;
1542                 /* n is multiple of 32 */
1543                 while (copied < n) {
1544                         const __m512i a = _mm512_loadu_si512(&txep[copied]);
1545                         const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
1546                         const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
1547                         const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
1548
1549                         _mm512_storeu_si512(&cache_objs[copied], a);
1550                         _mm512_storeu_si512(&cache_objs[copied + 8], b);
1551                         _mm512_storeu_si512(&cache_objs[copied + 16], c);
1552                         _mm512_storeu_si512(&cache_objs[copied + 24], d);
1553                         copied += 32;
1554                 }
1555                 cache->len += n;
1556
1557                 if (cache->len >= cache->flushthresh) {
1558                         rte_mempool_ops_enqueue_bulk(mp,
1559                                                      &cache->objs[cache->size],
1560                                                      cache->len - cache->size);
1561                         cache->len = cache->size;
1562                 }
1563                 goto done;
1564         }
1565
1566 normal:
1567         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
1568         if (likely(m)) {
1569                 free[0] = m;
1570                 nb_free = 1;
1571                 for (i = 1; i < n; i++) {
1572                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1573                         if (likely(m)) {
1574                                 if (likely(m->pool == free[0]->pool)) {
1575                                         free[nb_free++] = m;
1576                                 } else {
1577                                         rte_mempool_put_bulk(free[0]->pool,
1578                                                              (void *)free,
1579                                                              nb_free);
1580                                         free[0] = m;
1581                                         nb_free = 1;
1582                                 }
1583                         }
1584                 }
1585                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
1586         } else {
1587                 for (i = 1; i < n; i++) {
1588                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1589                         if (m)
1590                                 rte_mempool_put(m->pool, m);
1591                 }
1592         }
1593
1594 done:
1595         /* buffers were freed, update counters */
1596         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
1597         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
1598         if (txq->next_dd >= txq->nb_tx_desc)
1599                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
1600
1601         return txq->rs_thresh;
1602 }
1603
1604 static __rte_always_inline void
1605 tx_backlog_entry_avx512(struct iavf_tx_vec_entry *txep,
1606                         struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1607 {
1608         int i;
1609
1610         for (i = 0; i < (int)nb_pkts; ++i)
1611                 txep[i].mbuf = tx_pkts[i];
1612 }
1613
1614 static __rte_always_inline void
1615 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1616           struct rte_mbuf *pkt, uint64_t flags, bool offload)
1617 {
1618         uint64_t high_qw =
1619                 (IAVF_TX_DESC_DTYPE_DATA |
1620                  ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
1621                  ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1622         if (offload)
1623                 iavf_txd_enable_offload(pkt, &high_qw);
1624
1625         __m128i descriptor = _mm_set_epi64x(high_qw,
1626                                             pkt->buf_iova + pkt->data_off);
1627         _mm_storeu_si128((__m128i *)txdp, descriptor);
1628 }
1629
1630 #define IAVF_TX_LEN_MASK 0xAA
1631 #define IAVF_TX_OFF_MASK 0x55
1632 static __rte_always_inline void
1633 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1634          struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags,
1635          bool offload)
1636 {
1637         const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1638                         ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT));
1639
1640         /* if unaligned on 32-bit boundary, do one to align */
1641         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1642                 iavf_vtx1(txdp, *pkt, flags, offload);
1643                 nb_pkts--, txdp++, pkt++;
1644         }
1645
1646         /* do 4 at a time while possible, in bursts */
1647         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1648                 uint64_t hi_qw3 =
1649                         hi_qw_tmpl |
1650                         ((uint64_t)pkt[3]->data_len <<
1651                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1652                 if (offload)
1653                         iavf_txd_enable_offload(pkt[3], &hi_qw3);
1654                 uint64_t hi_qw2 =
1655                         hi_qw_tmpl |
1656                         ((uint64_t)pkt[2]->data_len <<
1657                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1658                 if (offload)
1659                         iavf_txd_enable_offload(pkt[2], &hi_qw2);
1660                 uint64_t hi_qw1 =
1661                         hi_qw_tmpl |
1662                         ((uint64_t)pkt[1]->data_len <<
1663                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1664                 if (offload)
1665                         iavf_txd_enable_offload(pkt[1], &hi_qw1);
1666                 uint64_t hi_qw0 =
1667                         hi_qw_tmpl |
1668                         ((uint64_t)pkt[0]->data_len <<
1669                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1670                 if (offload)
1671                         iavf_txd_enable_offload(pkt[0], &hi_qw0);
1672
1673                 __m512i desc0_3 =
1674                         _mm512_set_epi64
1675                                 (hi_qw3,
1676                                  pkt[3]->buf_iova + pkt[3]->data_off,
1677                                  hi_qw2,
1678                                  pkt[2]->buf_iova + pkt[2]->data_off,
1679                                  hi_qw1,
1680                                  pkt[1]->buf_iova + pkt[1]->data_off,
1681                                  hi_qw0,
1682                                  pkt[0]->buf_iova + pkt[0]->data_off);
1683                 _mm512_storeu_si512((void *)txdp, desc0_3);
1684         }
1685
1686         /* do any last ones */
1687         while (nb_pkts) {
1688                 iavf_vtx1(txdp, *pkt, flags, offload);
1689                 txdp++, pkt++, nb_pkts--;
1690         }
1691 }
1692
1693 static __rte_always_inline uint16_t
1694 iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1695                                  uint16_t nb_pkts, bool offload)
1696 {
1697         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1698         volatile struct iavf_tx_desc *txdp;
1699         struct iavf_tx_vec_entry *txep;
1700         uint16_t n, nb_commit, tx_id;
1701         /* bit2 is reserved and must be set to 1 according to Spec */
1702         uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1703         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1704
1705         /* cross rx_thresh boundary is not allowed */
1706         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1707
1708         if (txq->nb_free < txq->free_thresh)
1709                 iavf_tx_free_bufs_avx512(txq);
1710
1711         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1712         if (unlikely(nb_pkts == 0))
1713                 return 0;
1714
1715         tx_id = txq->tx_tail;
1716         txdp = &txq->tx_ring[tx_id];
1717         txep = (void *)txq->sw_ring;
1718         txep += tx_id;
1719
1720         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1721
1722         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1723         if (nb_commit >= n) {
1724                 tx_backlog_entry_avx512(txep, tx_pkts, n);
1725
1726                 iavf_vtx(txdp, tx_pkts, n - 1, flags, offload);
1727                 tx_pkts += (n - 1);
1728                 txdp += (n - 1);
1729
1730                 iavf_vtx1(txdp, *tx_pkts++, rs, offload);
1731
1732                 nb_commit = (uint16_t)(nb_commit - n);
1733
1734                 tx_id = 0;
1735                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1736
1737                 /* avoid reach the end of ring */
1738                 txdp = &txq->tx_ring[tx_id];
1739                 txep = (void *)txq->sw_ring;
1740                 txep += tx_id;
1741         }
1742
1743         tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1744
1745         iavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);
1746
1747         tx_id = (uint16_t)(tx_id + nb_commit);
1748         if (tx_id > txq->next_rs) {
1749                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1750                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1751                                          IAVF_TXD_QW1_CMD_SHIFT);
1752                 txq->next_rs =
1753                         (uint16_t)(txq->next_rs + txq->rs_thresh);
1754         }
1755
1756         txq->tx_tail = tx_id;
1757
1758         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1759
1760         return nb_pkts;
1761 }
1762
1763 static __rte_always_inline uint16_t
1764 iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,
1765                               uint16_t nb_pkts, bool offload)
1766 {
1767         uint16_t nb_tx = 0;
1768         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1769
1770         while (nb_pkts) {
1771                 uint16_t ret, num;
1772
1773                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1774                 ret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],
1775                                                        num, offload);
1776                 nb_tx += ret;
1777                 nb_pkts -= ret;
1778                 if (ret < num)
1779                         break;
1780         }
1781
1782         return nb_tx;
1783 }
1784
1785 uint16_t
1786 iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1787                           uint16_t nb_pkts)
1788 {
1789         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);
1790 }
1791
1792 static inline void
1793 iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)
1794 {
1795         unsigned int i;
1796         const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
1797         struct iavf_tx_vec_entry *swr = (void *)txq->sw_ring;
1798
1799         if (!txq->sw_ring || txq->nb_free == max_desc)
1800                 return;
1801
1802         i = txq->next_dd - txq->rs_thresh + 1;
1803         if (txq->tx_tail < i) {
1804                 for (; i < txq->nb_tx_desc; i++) {
1805                         rte_pktmbuf_free_seg(swr[i].mbuf);
1806                         swr[i].mbuf = NULL;
1807                 }
1808                 i = 0;
1809         }
1810 }
1811
1812 static const struct iavf_txq_ops avx512_vec_txq_ops = {
1813         .release_mbufs = iavf_tx_queue_release_mbufs_avx512,
1814 };
1815
1816 int __rte_cold
1817 iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq)
1818 {
1819         txq->ops = &avx512_vec_txq_ops;
1820         return 0;
1821 }
1822
1823 uint16_t
1824 iavf_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
1825                                   uint16_t nb_pkts)
1826 {
1827         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, true);
1828 }