drivers/net/ice/base/ice_controlq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2019
   3  */
   4
   5 #include "ice_common.h"
   6
   7
   8 #define ICE_CQ_INIT_REGS(qinfo, prefix)                         \
   9 do {                                                            \
  10         (qinfo)->sq.head = prefix##_ATQH;                       \
  11         (qinfo)->sq.tail = prefix##_ATQT;                       \
  12         (qinfo)->sq.len = prefix##_ATQLEN;                      \
  13         (qinfo)->sq.bah = prefix##_ATQBAH;                      \
  14         (qinfo)->sq.bal = prefix##_ATQBAL;                      \
  15         (qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M;        \
  16         (qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M; \
  17         (qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M;           \
  18         (qinfo)->rq.head = prefix##_ARQH;                       \
  19         (qinfo)->rq.tail = prefix##_ARQT;                       \
  20         (qinfo)->rq.len = prefix##_ARQLEN;                      \
  21         (qinfo)->rq.bah = prefix##_ARQBAH;                      \
  22         (qinfo)->rq.bal = prefix##_ARQBAL;                      \
  23         (qinfo)->rq.len_mask = prefix##_ARQLEN_ARQLEN_M;        \
  24         (qinfo)->rq.len_ena_mask = prefix##_ARQLEN_ARQENABLE_M; \
  25         (qinfo)->rq.head_mask = prefix##_ARQH_ARQH_M;           \
  26 } while (0)
  27
  28 /**
  29  * ice_adminq_init_regs - Initialize AdminQ registers
  30  * @hw: pointer to the hardware structure
  31  *
  32  * This assumes the alloc_sq and alloc_rq functions have already been called
  33  */
  34 static void ice_adminq_init_regs(struct ice_hw *hw)
  35 {
  36         struct ice_ctl_q_info *cq = &hw->adminq;
  37
  38         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
  39
  40         ICE_CQ_INIT_REGS(cq, PF_FW);
  41 }
  42
  43 /**
  44  * ice_mailbox_init_regs - Initialize Mailbox registers
  45  * @hw: pointer to the hardware structure
  46  *
  47  * This assumes the alloc_sq and alloc_rq functions have already been called
  48  */
  49 static void ice_mailbox_init_regs(struct ice_hw *hw)
  50 {
  51         struct ice_ctl_q_info *cq = &hw->mailboxq;
  52
  53         ICE_CQ_INIT_REGS(cq, PF_MBX);
  54 }
  55
  56
  57 /**
  58  * ice_check_sq_alive
  59  * @hw: pointer to the HW struct
  60  * @cq: pointer to the specific Control queue
  61  *
  62  * Returns true if Queue is enabled else false.
  63  */
  64 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq)
  65 {
  66         /* check both queue-length and queue-enable fields */
  67         if (cq->sq.len && cq->sq.len_mask && cq->sq.len_ena_mask)
  68                 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask |
  69                                                 cq->sq.len_ena_mask)) ==
  70                         (cq->num_sq_entries | cq->sq.len_ena_mask);
  71
  72         return false;
  73 }
  74
  75 /**
  76  * ice_alloc_ctrlq_sq_ring - Allocate Control Transmit Queue (ATQ) rings
  77  * @hw: pointer to the hardware structure
  78  * @cq: pointer to the specific Control queue
  79  */
  80 static enum ice_status
  81 ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
  82 {
  83         size_t size = cq->num_sq_entries * sizeof(struct ice_aq_desc);
  84
  85         cq->sq.desc_buf.va = ice_alloc_dma_mem(hw, &cq->sq.desc_buf, size);
  86         if (!cq->sq.desc_buf.va)
  87                 return ICE_ERR_NO_MEMORY;
  88
  89         cq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries,
  90                                     sizeof(struct ice_sq_cd));
  91         if (!cq->sq.cmd_buf) {
  92                 ice_free_dma_mem(hw, &cq->sq.desc_buf);
  93                 return ICE_ERR_NO_MEMORY;
  94         }
  95
  96         return ICE_SUCCESS;
  97 }
  98
  99 /**
 100  * ice_alloc_ctrlq_rq_ring - Allocate Control Receive Queue (ARQ) rings
 101  * @hw: pointer to the hardware structure
 102  * @cq: pointer to the specific Control queue
 103  */
 104 static enum ice_status
 105 ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 106 {
 107         size_t size = cq->num_rq_entries * sizeof(struct ice_aq_desc);
 108
 109         cq->rq.desc_buf.va = ice_alloc_dma_mem(hw, &cq->rq.desc_buf, size);
 110         if (!cq->rq.desc_buf.va)
 111                 return ICE_ERR_NO_MEMORY;
 112         return ICE_SUCCESS;
 113 }
 114
 115 /**
 116  * ice_free_cq_ring - Free control queue ring
 117  * @hw: pointer to the hardware structure
 118  * @ring: pointer to the specific control queue ring
 119  *
 120  * This assumes the posted buffers have already been cleaned
 121  * and de-allocated
 122  */
 123 static void ice_free_cq_ring(struct ice_hw *hw, struct ice_ctl_q_ring *ring)
 124 {
 125         ice_free_dma_mem(hw, &ring->desc_buf);
 126 }
 127
 128 /**
 129  * ice_alloc_rq_bufs - Allocate pre-posted buffers for the ARQ
 130  * @hw: pointer to the hardware structure
 131  * @cq: pointer to the specific Control queue
 132  */
 133 static enum ice_status
 134 ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 135 {
 136         int i;
 137
 138         /* We'll be allocating the buffer info memory first, then we can
 139          * allocate the mapped buffers for the event processing
 140          */
 141         cq->rq.dma_head = ice_calloc(hw, cq->num_rq_entries,
 142                                      sizeof(cq->rq.desc_buf));
 143         if (!cq->rq.dma_head)
 144                 return ICE_ERR_NO_MEMORY;
 145         cq->rq.r.rq_bi = (struct ice_dma_mem *)cq->rq.dma_head;
 146
 147         /* allocate the mapped buffers */
 148         for (i = 0; i < cq->num_rq_entries; i++) {
 149                 struct ice_aq_desc *desc;
 150                 struct ice_dma_mem *bi;
 151
 152                 bi = &cq->rq.r.rq_bi[i];
 153                 bi->va = ice_alloc_dma_mem(hw, bi, cq->rq_buf_size);
 154                 if (!bi->va)
 155                         goto unwind_alloc_rq_bufs;
 156
 157                 /* now configure the descriptors for use */
 158                 desc = ICE_CTL_Q_DESC(cq->rq, i);
 159
 160                 desc->flags = CPU_TO_LE16(ICE_AQ_FLAG_BUF);
 161                 if (cq->rq_buf_size > ICE_AQ_LG_BUF)
 162                         desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
 163                 desc->opcode = 0;
 164                 /* This is in accordance with Admin queue design, there is no
 165                  * register for buffer size configuration
 166                  */
 167                 desc->datalen = CPU_TO_LE16(bi->size);
 168                 desc->retval = 0;
 169                 desc->cookie_high = 0;
 170                 desc->cookie_low = 0;
 171                 desc->params.generic.addr_high =
 172                         CPU_TO_LE32(ICE_HI_DWORD(bi->pa));
 173                 desc->params.generic.addr_low =
 174                         CPU_TO_LE32(ICE_LO_DWORD(bi->pa));
 175                 desc->params.generic.param0 = 0;
 176                 desc->params.generic.param1 = 0;
 177         }
 178         return ICE_SUCCESS;
 179
 180 unwind_alloc_rq_bufs:
 181         /* don't try to free the one that failed... */
 182         i--;
 183         for (; i >= 0; i--)
 184                 ice_free_dma_mem(hw, &cq->rq.r.rq_bi[i]);
 185         ice_free(hw, cq->rq.dma_head);
 186
 187         return ICE_ERR_NO_MEMORY;
 188 }
 189
 190 /**
 191  * ice_alloc_sq_bufs - Allocate empty buffer structs for the ATQ
 192  * @hw: pointer to the hardware structure
 193  * @cq: pointer to the specific Control queue
 194  */
 195 static enum ice_status
 196 ice_alloc_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 197 {
 198         int i;
 199
 200         /* No mapped memory needed yet, just the buffer info structures */
 201         cq->sq.dma_head = ice_calloc(hw, cq->num_sq_entries,
 202                                      sizeof(cq->sq.desc_buf));
 203         if (!cq->sq.dma_head)
 204                 return ICE_ERR_NO_MEMORY;
 205         cq->sq.r.sq_bi = (struct ice_dma_mem *)cq->sq.dma_head;
 206
 207         /* allocate the mapped buffers */
 208         for (i = 0; i < cq->num_sq_entries; i++) {
 209                 struct ice_dma_mem *bi;
 210
 211                 bi = &cq->sq.r.sq_bi[i];
 212                 bi->va = ice_alloc_dma_mem(hw, bi, cq->sq_buf_size);
 213                 if (!bi->va)
 214                         goto unwind_alloc_sq_bufs;
 215         }
 216         return ICE_SUCCESS;
 217
 218 unwind_alloc_sq_bufs:
 219         /* don't try to free the one that failed... */
 220         i--;
 221         for (; i >= 0; i--)
 222                 ice_free_dma_mem(hw, &cq->sq.r.sq_bi[i]);
 223         ice_free(hw, cq->sq.dma_head);
 224
 225         return ICE_ERR_NO_MEMORY;
 226 }
 227
 228 static enum ice_status
 229 ice_cfg_cq_regs(struct ice_hw *hw, struct ice_ctl_q_ring *ring, u16 num_entries)
 230 {
 231         /* Clear Head and Tail */
 232         wr32(hw, ring->head, 0);
 233         wr32(hw, ring->tail, 0);
 234
 235         /* set starting point */
 236         wr32(hw, ring->len, (num_entries | ring->len_ena_mask));
 237         wr32(hw, ring->bal, ICE_LO_DWORD(ring->desc_buf.pa));
 238         wr32(hw, ring->bah, ICE_HI_DWORD(ring->desc_buf.pa));
 239
 240         /* Check one register to verify that config was applied */
 241         if (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa))
 242                 return ICE_ERR_AQ_ERROR;
 243
 244         return ICE_SUCCESS;
 245 }
 246
 247 /**
 248  * ice_cfg_sq_regs - configure Control ATQ registers
 249  * @hw: pointer to the hardware structure
 250  * @cq: pointer to the specific Control queue
 251  *
 252  * Configure base address and length registers for the transmit queue
 253  */
 254 static enum ice_status
 255 ice_cfg_sq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 256 {
 257         return ice_cfg_cq_regs(hw, &cq->sq, cq->num_sq_entries);
 258 }
 259
 260 /**
 261  * ice_cfg_rq_regs - configure Control ARQ register
 262  * @hw: pointer to the hardware structure
 263  * @cq: pointer to the specific Control queue
 264  *
 265  * Configure base address and length registers for the receive (event queue)
 266  */
 267 static enum ice_status
 268 ice_cfg_rq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 269 {
 270         enum ice_status status;
 271
 272         status = ice_cfg_cq_regs(hw, &cq->rq, cq->num_rq_entries);
 273         if (status)
 274                 return status;
 275
 276         /* Update tail in the HW to post pre-allocated buffers */
 277         wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1));
 278
 279         return ICE_SUCCESS;
 280 }
 281
 282 /**
 283  * ice_init_sq - main initialization routine for Control ATQ
 284  * @hw: pointer to the hardware structure
 285  * @cq: pointer to the specific Control queue
 286  *
 287  * This is the main initialization routine for the Control Send Queue
 288  * Prior to calling this function, the driver *MUST* set the following fields
 289  * in the cq->structure:
 290  *     - cq->num_sq_entries
 291  *     - cq->sq_buf_size
 292  *
 293  * Do *NOT* hold the lock when calling this as the memory allocation routines
 294  * called are not going to be atomic context safe
 295  */
 296 static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 297 {
 298         enum ice_status ret_code;
 299
 300         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 301
 302         if (cq->sq.count > 0) {
 303                 /* queue already initialized */
 304                 ret_code = ICE_ERR_NOT_READY;
 305                 goto init_ctrlq_exit;
 306         }
 307
 308         /* verify input for valid configuration */
 309         if (!cq->num_sq_entries || !cq->sq_buf_size) {
 310                 ret_code = ICE_ERR_CFG;
 311                 goto init_ctrlq_exit;
 312         }
 313
 314         cq->sq.next_to_use = 0;
 315         cq->sq.next_to_clean = 0;
 316
 317         /* allocate the ring memory */
 318         ret_code = ice_alloc_ctrlq_sq_ring(hw, cq);
 319         if (ret_code)
 320                 goto init_ctrlq_exit;
 321
 322         /* allocate buffers in the rings */
 323         ret_code = ice_alloc_sq_bufs(hw, cq);
 324         if (ret_code)
 325                 goto init_ctrlq_free_rings;
 326
 327         /* initialize base registers */
 328         ret_code = ice_cfg_sq_regs(hw, cq);
 329         if (ret_code)
 330                 goto init_ctrlq_free_rings;
 331
 332         /* success! */
 333         cq->sq.count = cq->num_sq_entries;
 334         goto init_ctrlq_exit;
 335
 336 init_ctrlq_free_rings:
 337         ice_free_cq_ring(hw, &cq->sq);
 338
 339 init_ctrlq_exit:
 340         return ret_code;
 341 }
 342
 343 /**
 344  * ice_init_rq - initialize ARQ
 345  * @hw: pointer to the hardware structure
 346  * @cq: pointer to the specific Control queue
 347  *
 348  * The main initialization routine for the Admin Receive (Event) Queue.
 349  * Prior to calling this function, the driver *MUST* set the following fields
 350  * in the cq->structure:
 351  *     - cq->num_rq_entries
 352  *     - cq->rq_buf_size
 353  *
 354  * Do *NOT* hold the lock when calling this as the memory allocation routines
 355  * called are not going to be atomic context safe
 356  */
 357 static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 358 {
 359         enum ice_status ret_code;
 360
 361         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 362
 363         if (cq->rq.count > 0) {
 364                 /* queue already initialized */
 365                 ret_code = ICE_ERR_NOT_READY;
 366                 goto init_ctrlq_exit;
 367         }
 368
 369         /* verify input for valid configuration */
 370         if (!cq->num_rq_entries || !cq->rq_buf_size) {
 371                 ret_code = ICE_ERR_CFG;
 372                 goto init_ctrlq_exit;
 373         }
 374
 375         cq->rq.next_to_use = 0;
 376         cq->rq.next_to_clean = 0;
 377
 378         /* allocate the ring memory */
 379         ret_code = ice_alloc_ctrlq_rq_ring(hw, cq);
 380         if (ret_code)
 381                 goto init_ctrlq_exit;
 382
 383         /* allocate buffers in the rings */
 384         ret_code = ice_alloc_rq_bufs(hw, cq);
 385         if (ret_code)
 386                 goto init_ctrlq_free_rings;
 387
 388         /* initialize base registers */
 389         ret_code = ice_cfg_rq_regs(hw, cq);
 390         if (ret_code)
 391                 goto init_ctrlq_free_rings;
 392
 393         /* success! */
 394         cq->rq.count = cq->num_rq_entries;
 395         goto init_ctrlq_exit;
 396
 397 init_ctrlq_free_rings:
 398         ice_free_cq_ring(hw, &cq->rq);
 399
 400 init_ctrlq_exit:
 401         return ret_code;
 402 }
 403
 404 #define ICE_FREE_CQ_BUFS(hw, qi, ring)                                  \
 405 do {                                                                    \
 406         int i;                                                          \
 407         /* free descriptors */                                          \
 408         for (i = 0; i < (qi)->num_##ring##_entries; i++)                \
 409                 if ((qi)->ring.r.ring##_bi[i].pa)                       \
 410                         ice_free_dma_mem((hw),                          \
 411                                          &(qi)->ring.r.ring##_bi[i]);   \
 412         /* free the buffer info list */                                 \
 413         if ((qi)->ring.cmd_buf)                                         \
 414                 ice_free(hw, (qi)->ring.cmd_buf);                       \
 415         /* free DMA head */                                             \
 416         ice_free(hw, (qi)->ring.dma_head);                              \
 417 } while (0)
 418
 419 /**
 420  * ice_shutdown_sq - shutdown the Control ATQ
 421  * @hw: pointer to the hardware structure
 422  * @cq: pointer to the specific Control queue
 423  *
 424  * The main shutdown routine for the Control Transmit Queue
 425  */
 426 static enum ice_status
 427 ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 428 {
 429         enum ice_status ret_code = ICE_SUCCESS;
 430
 431         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 432
 433         ice_acquire_lock(&cq->sq_lock);
 434
 435         if (!cq->sq.count) {
 436                 ret_code = ICE_ERR_NOT_READY;
 437                 goto shutdown_sq_out;
 438         }
 439
 440         /* Stop firmware AdminQ processing */
 441         wr32(hw, cq->sq.head, 0);
 442         wr32(hw, cq->sq.tail, 0);
 443         wr32(hw, cq->sq.len, 0);
 444         wr32(hw, cq->sq.bal, 0);
 445         wr32(hw, cq->sq.bah, 0);
 446
 447         cq->sq.count = 0;       /* to indicate uninitialized queue */
 448
 449         /* free ring buffers and the ring itself */
 450         ICE_FREE_CQ_BUFS(hw, cq, sq);
 451         ice_free_cq_ring(hw, &cq->sq);
 452
 453 shutdown_sq_out:
 454         ice_release_lock(&cq->sq_lock);
 455         return ret_code;
 456 }
 457
 458 /**
 459  * ice_aq_ver_check - Check the reported AQ API version.
 460  * @hw: pointer to the hardware structure
 461  *
 462  * Checks if the driver should load on a given AQ API version.
 463  *
 464  * Return: 'true' iff the driver should attempt to load. 'false' otherwise.
 465  */
 466 static bool ice_aq_ver_check(struct ice_hw *hw)
 467 {
 468         if (hw->api_maj_ver > EXP_FW_API_VER_MAJOR) {
 469                 /* Major API version is newer than expected, don't load */
 470                 ice_warn(hw, "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
 471                 return false;
 472         } else if (hw->api_maj_ver == EXP_FW_API_VER_MAJOR) {
 473                 if (hw->api_min_ver > (EXP_FW_API_VER_MINOR + 2))
 474                         ice_info(hw, "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
 475                 else if ((hw->api_min_ver + 2) < EXP_FW_API_VER_MINOR)
 476                         ice_info(hw, "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
 477         } else {
 478                 /* Major API version is older than expected, log a warning */
 479                 ice_info(hw, "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
 480         }
 481         return true;
 482 }
 483
 484 /**
 485  * ice_shutdown_rq - shutdown Control ARQ
 486  * @hw: pointer to the hardware structure
 487  * @cq: pointer to the specific Control queue
 488  *
 489  * The main shutdown routine for the Control Receive Queue
 490  */
 491 static enum ice_status
 492 ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 493 {
 494         enum ice_status ret_code = ICE_SUCCESS;
 495
 496         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 497
 498         ice_acquire_lock(&cq->rq_lock);
 499
 500         if (!cq->rq.count) {
 501                 ret_code = ICE_ERR_NOT_READY;
 502                 goto shutdown_rq_out;
 503         }
 504
 505         /* Stop Control Queue processing */
 506         wr32(hw, cq->rq.head, 0);
 507         wr32(hw, cq->rq.tail, 0);
 508         wr32(hw, cq->rq.len, 0);
 509         wr32(hw, cq->rq.bal, 0);
 510         wr32(hw, cq->rq.bah, 0);
 511
 512         /* set rq.count to 0 to indicate uninitialized queue */
 513         cq->rq.count = 0;
 514
 515         /* free ring buffers and the ring itself */
 516         ICE_FREE_CQ_BUFS(hw, cq, rq);
 517         ice_free_cq_ring(hw, &cq->rq);
 518
 519 shutdown_rq_out:
 520         ice_release_lock(&cq->rq_lock);
 521         return ret_code;
 522 }
 523
 524
 525 /**
 526  * ice_init_check_adminq - Check version for Admin Queue to know if its alive
 527  * @hw: pointer to the hardware structure
 528  */
 529 static enum ice_status ice_init_check_adminq(struct ice_hw *hw)
 530 {
 531         struct ice_ctl_q_info *cq = &hw->adminq;
 532         enum ice_status status;
 533
 534         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 535
 536
 537         status = ice_aq_get_fw_ver(hw, NULL);
 538         if (status)
 539                 goto init_ctrlq_free_rq;
 540
 541
 542         if (!ice_aq_ver_check(hw)) {
 543                 status = ICE_ERR_FW_API_VER;
 544                 goto init_ctrlq_free_rq;
 545         }
 546
 547         return ICE_SUCCESS;
 548
 549 init_ctrlq_free_rq:
 550         ice_shutdown_rq(hw, cq);
 551         ice_shutdown_sq(hw, cq);
 552         return status;
 553 }
 554
 555 /**
 556  * ice_init_ctrlq - main initialization routine for any control Queue
 557  * @hw: pointer to the hardware structure
 558  * @q_type: specific Control queue type
 559  *
 560  * Prior to calling this function, the driver *MUST* set the following fields
 561  * in the cq->structure:
 562  *     - cq->num_sq_entries
 563  *     - cq->num_rq_entries
 564  *     - cq->rq_buf_size
 565  *     - cq->sq_buf_size
 566  *
 567  * NOTE: this function does not initialize the controlq locks
 568  */
 569 static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
 570 {
 571         struct ice_ctl_q_info *cq;
 572         enum ice_status ret_code;
 573
 574         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 575
 576         switch (q_type) {
 577         case ICE_CTL_Q_ADMIN:
 578                 ice_adminq_init_regs(hw);
 579                 cq = &hw->adminq;
 580                 break;
 581         case ICE_CTL_Q_MAILBOX:
 582                 ice_mailbox_init_regs(hw);
 583                 cq = &hw->mailboxq;
 584                 break;
 585         default:
 586                 return ICE_ERR_PARAM;
 587         }
 588         cq->qtype = q_type;
 589
 590         /* verify input for valid configuration */
 591         if (!cq->num_rq_entries || !cq->num_sq_entries ||
 592             !cq->rq_buf_size || !cq->sq_buf_size) {
 593                 return ICE_ERR_CFG;
 594         }
 595
 596         /* setup SQ command write back timeout */
 597         cq->sq_cmd_timeout = ICE_CTL_Q_SQ_CMD_TIMEOUT;
 598
 599         /* allocate the ATQ */
 600         ret_code = ice_init_sq(hw, cq);
 601         if (ret_code)
 602                 return ret_code;
 603
 604         /* allocate the ARQ */
 605         ret_code = ice_init_rq(hw, cq);
 606         if (ret_code)
 607                 goto init_ctrlq_free_sq;
 608
 609         /* success! */
 610         return ICE_SUCCESS;
 611
 612 init_ctrlq_free_sq:
 613         ice_shutdown_sq(hw, cq);
 614         return ret_code;
 615 }
 616
 617 /**
 618  * ice_init_all_ctrlq - main initialization routine for all control queues
 619  * @hw: pointer to the hardware structure
 620  *
 621  * Prior to calling this function, the driver MUST* set the following fields
 622  * in the cq->structure for all control queues:
 623  *     - cq->num_sq_entries
 624  *     - cq->num_rq_entries
 625  *     - cq->rq_buf_size
 626  *     - cq->sq_buf_size
 627  *
 628  * NOTE: this function does not initialize the controlq locks.
 629  */
 630 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)
 631 {
 632         enum ice_status ret_code;
 633
 634         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 635
 636
 637         /* Init FW admin queue */
 638         ret_code = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);
 639         if (ret_code)
 640                 return ret_code;
 641
 642         ret_code = ice_init_check_adminq(hw);
 643         if (ret_code)
 644                 return ret_code;
 645         /* Init Mailbox queue */
 646         return ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);
 647 }
 648
 649 /**
 650  * ice_init_ctrlq_locks - Initialize locks for a control queue
 651  * @cq: pointer to the control queue
 652  *
 653  * Initializes the send and receive queue locks for a given control queue.
 654  */
 655 static void ice_init_ctrlq_locks(struct ice_ctl_q_info *cq)
 656 {
 657         ice_init_lock(&cq->sq_lock);
 658         ice_init_lock(&cq->rq_lock);
 659 }
 660
 661 /**
 662  * ice_create_all_ctrlq - main initialization routine for all control queues
 663  * @hw: pointer to the hardware structure
 664  *
 665  * Prior to calling this function, the driver *MUST* set the following fields
 666  * in the cq->structure for all control queues:
 667  *     - cq->num_sq_entries
 668  *     - cq->num_rq_entries
 669  *     - cq->rq_buf_size
 670  *     - cq->sq_buf_size
 671  *
 672  * This function creates all the control queue locks and then calls
 673  * ice_init_all_ctrlq. It should be called once during driver load. If the
 674  * driver needs to re-initialize control queues at run time it should call
 675  * ice_init_all_ctrlq instead.
 676  */
 677 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw)
 678 {
 679         ice_init_ctrlq_locks(&hw->adminq);
 680         ice_init_ctrlq_locks(&hw->mailboxq);
 681
 682         return ice_init_all_ctrlq(hw);
 683 }
 684
 685 /**
 686  * ice_shutdown_ctrlq - shutdown routine for any control queue
 687  * @hw: pointer to the hardware structure
 688  * @q_type: specific Control queue type
 689  *
 690  * NOTE: this function does not destroy the control queue locks.
 691  */
 692 static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
 693 {
 694         struct ice_ctl_q_info *cq;
 695
 696         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 697
 698         switch (q_type) {
 699         case ICE_CTL_Q_ADMIN:
 700                 cq = &hw->adminq;
 701                 if (ice_check_sq_alive(hw, cq))
 702                         ice_aq_q_shutdown(hw, true);
 703                 break;
 704         case ICE_CTL_Q_MAILBOX:
 705                 cq = &hw->mailboxq;
 706                 break;
 707         default:
 708                 return;
 709         }
 710
 711         ice_shutdown_sq(hw, cq);
 712         ice_shutdown_rq(hw, cq);
 713 }
 714
 715 /**
 716  * ice_shutdown_all_ctrlq - shutdown routine for all control queues
 717  * @hw: pointer to the hardware structure
 718  *
 719  * NOTE: this function does not destroy the control queue locks. The driver
 720  * may call this at runtime to shutdown and later restart control queues, such
 721  * as in response to a reset event.
 722  */
 723 void ice_shutdown_all_ctrlq(struct ice_hw *hw)
 724 {
 725         ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 726         /* Shutdown FW admin queue */
 727         ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
 728         /* Shutdown PF-VF Mailbox */
 729         ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);
 730 }
 731
 732 /**
 733  * ice_destroy_ctrlq_locks - Destroy locks for a control queue
 734  * @cq: pointer to the control queue
 735  *
 736  * Destroys the send and receive queue locks for a given control queue.
 737  */
 738 static void
 739 ice_destroy_ctrlq_locks(struct ice_ctl_q_info *cq)
 740 {
 741         ice_destroy_lock(&cq->sq_lock);
 742         ice_destroy_lock(&cq->rq_lock);
 743 }
 744
 745 /**
 746  * ice_destroy_all_ctrlq - exit routine for all control queues
 747  * @hw: pointer to the hardware structure
 748  *
 749  * This function shuts down all the control queues and then destroys the
 750  * control queue locks. It should be called once during driver unload. The
 751  * driver should call ice_shutdown_all_ctrlq if it needs to shut down and
 752  * reinitialize control queues, such as in response to a reset event.
 753  */
 754 void ice_destroy_all_ctrlq(struct ice_hw *hw)
 755 {
 756         /* shut down all the control queues first */
 757         ice_shutdown_all_ctrlq(hw);
 758
 759         ice_destroy_ctrlq_locks(&hw->adminq);
 760         ice_destroy_ctrlq_locks(&hw->mailboxq);
 761 }
 762
 763 /**
 764  * ice_clean_sq - cleans Admin send queue (ATQ)
 765  * @hw: pointer to the hardware structure
 766  * @cq: pointer to the specific Control queue
 767  *
 768  * returns the number of free desc
 769  */
 770 static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 771 {
 772         struct ice_ctl_q_ring *sq = &cq->sq;
 773         u16 ntc = sq->next_to_clean;
 774         struct ice_sq_cd *details;
 775         struct ice_aq_desc *desc;
 776
 777         desc = ICE_CTL_Q_DESC(*sq, ntc);
 778         details = ICE_CTL_Q_DETAILS(*sq, ntc);
 779
 780         while (rd32(hw, cq->sq.head) != ntc) {
 781                 ice_debug(hw, ICE_DBG_AQ_MSG,
 782                           "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
 783                 ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
 784                 ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
 785                 ntc++;
 786                 if (ntc == sq->count)
 787                         ntc = 0;
 788                 desc = ICE_CTL_Q_DESC(*sq, ntc);
 789                 details = ICE_CTL_Q_DETAILS(*sq, ntc);
 790         }
 791
 792         sq->next_to_clean = ntc;
 793
 794         return ICE_CTL_Q_DESC_UNUSED(sq);
 795 }
 796
 797 /**
 798  * ice_debug_cq
 799  * @hw: pointer to the hardware structure
 800  * @desc: pointer to control queue descriptor
 801  * @buf: pointer to command buffer
 802  * @buf_len: max length of buf
 803  *
 804  * Dumps debug log about control command with descriptor contents.
 805  */
 806 static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
 807 {
 808         struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
 809         u16 datalen, flags;
 810
 811         if (!((ICE_DBG_AQ_DESC | ICE_DBG_AQ_DESC_BUF) & hw->debug_mask))
 812                 return;
 813
 814         if (!desc)
 815                 return;
 816
 817         datalen = LE16_TO_CPU(cq_desc->datalen);
 818         flags = LE16_TO_CPU(cq_desc->flags);
 819
 820         ice_debug(hw, ICE_DBG_AQ_DESC,
 821                   "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 822                   LE16_TO_CPU(cq_desc->opcode), flags, datalen,
 823                   LE16_TO_CPU(cq_desc->retval));
 824         ice_debug(hw, ICE_DBG_AQ_DESC, "\tcookie (h,l) 0x%08X 0x%08X\n",
 825                   LE32_TO_CPU(cq_desc->cookie_high),
 826                   LE32_TO_CPU(cq_desc->cookie_low));
 827         ice_debug(hw, ICE_DBG_AQ_DESC, "\tparam (0,1)  0x%08X 0x%08X\n",
 828                   LE32_TO_CPU(cq_desc->params.generic.param0),
 829                   LE32_TO_CPU(cq_desc->params.generic.param1));
 830         ice_debug(hw, ICE_DBG_AQ_DESC, "\taddr (h,l)   0x%08X 0x%08X\n",
 831                   LE32_TO_CPU(cq_desc->params.generic.addr_high),
 832                   LE32_TO_CPU(cq_desc->params.generic.addr_low));
 833         /* Dump buffer iff 1) one exists and 2) is either a response indicated
 834          * by the DD and/or CMP flag set or a command with the RD flag set.
 835          */
 836         if (buf && cq_desc->datalen != 0 &&
 837             (flags & (ICE_AQ_FLAG_DD | ICE_AQ_FLAG_CMP) ||
 838              flags & ICE_AQ_FLAG_RD)) {
 839                 ice_debug(hw, ICE_DBG_AQ_DESC_BUF, "Buffer:\n");
 840                 ice_debug_array(hw, ICE_DBG_AQ_DESC_BUF, 16, 1, (u8 *)buf,
 841                                 min(buf_len, datalen));
 842         }
 843 }
 844
 845 /**
 846  * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)
 847  * @hw: pointer to the HW struct
 848  * @cq: pointer to the specific Control queue
 849  *
 850  * Returns true if the firmware has processed all descriptors on the
 851  * admin send queue. Returns false if there are still requests pending.
 852  */
 853 static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 854 {
 855         /* AQ designers suggest use of head for better
 856          * timing reliability than DD bit
 857          */
 858         return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
 859 }
 860
 861 /**
 862  * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
 863  * @hw: pointer to the HW struct
 864  * @cq: pointer to the specific Control queue
 865  * @desc: prefilled descriptor describing the command (non DMA mem)
 866  * @buf: buffer to use for indirect commands (or NULL for direct commands)
 867  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
 868  * @cd: pointer to command details structure
 869  *
 870  * This is the main send command routine for the ATQ. It runs the queue,
 871  * cleans the queue, etc.
 872  */
 873 static enum ice_status
 874 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 875                        struct ice_aq_desc *desc, void *buf, u16 buf_size,
 876                        struct ice_sq_cd *cd)
 877 {
 878         struct ice_dma_mem *dma_buf = NULL;
 879         struct ice_aq_desc *desc_on_ring;
 880         bool cmd_completed = false;
 881         enum ice_status status = ICE_SUCCESS;
 882         struct ice_sq_cd *details;
 883         u32 total_delay = 0;
 884         u16 retval = 0;
 885         u32 val = 0;
 886
 887         /* if reset is in progress return a soft error */
 888         if (hw->reset_ongoing)
 889                 return ICE_ERR_RESET_ONGOING;
 890
 891         cq->sq_last_status = ICE_AQ_RC_OK;
 892
 893         if (!cq->sq.count) {
 894                 ice_debug(hw, ICE_DBG_AQ_MSG,
 895                           "Control Send queue not initialized.\n");
 896                 status = ICE_ERR_AQ_EMPTY;
 897                 goto sq_send_command_error;
 898         }
 899
 900         if ((buf && !buf_size) || (!buf && buf_size)) {
 901                 status = ICE_ERR_PARAM;
 902                 goto sq_send_command_error;
 903         }
 904
 905         if (buf) {
 906                 if (buf_size > cq->sq_buf_size) {
 907                         ice_debug(hw, ICE_DBG_AQ_MSG,
 908                                   "Invalid buffer size for Control Send queue: %d.\n",
 909                                   buf_size);
 910                         status = ICE_ERR_INVAL_SIZE;
 911                         goto sq_send_command_error;
 912                 }
 913
 914                 desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
 915                 if (buf_size > ICE_AQ_LG_BUF)
 916                         desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
 917         }
 918
 919         val = rd32(hw, cq->sq.head);
 920         if (val >= cq->num_sq_entries) {
 921                 ice_debug(hw, ICE_DBG_AQ_MSG,
 922                           "head overrun at %d in the Control Send Queue ring\n",
 923                           val);
 924                 status = ICE_ERR_AQ_EMPTY;
 925                 goto sq_send_command_error;
 926         }
 927
 928         details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);
 929         if (cd)
 930                 *details = *cd;
 931         else
 932                 ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);
 933
 934         /* Call clean and check queue available function to reclaim the
 935          * descriptors that were processed by FW/MBX; the function returns the
 936          * number of desc available. The clean function called here could be
 937          * called in a separate thread in case of asynchronous completions.
 938          */
 939         if (ice_clean_sq(hw, cq) == 0) {
 940                 ice_debug(hw, ICE_DBG_AQ_MSG,
 941                           "Error: Control Send Queue is full.\n");
 942                 status = ICE_ERR_AQ_FULL;
 943                 goto sq_send_command_error;
 944         }
 945
 946         /* initialize the temp desc pointer with the right desc */
 947         desc_on_ring = ICE_CTL_Q_DESC(cq->sq, cq->sq.next_to_use);
 948
 949         /* if the desc is available copy the temp desc to the right place */
 950         ice_memcpy(desc_on_ring, desc, sizeof(*desc_on_ring),
 951                    ICE_NONDMA_TO_DMA);
 952
 953         /* if buf is not NULL assume indirect command */
 954         if (buf) {
 955                 dma_buf = &cq->sq.r.sq_bi[cq->sq.next_to_use];
 956                 /* copy the user buf into the respective DMA buf */
 957                 ice_memcpy(dma_buf->va, buf, buf_size, ICE_NONDMA_TO_DMA);
 958                 desc_on_ring->datalen = CPU_TO_LE16(buf_size);
 959
 960                 /* Update the address values in the desc with the pa value
 961                  * for respective buffer
 962                  */
 963                 desc_on_ring->params.generic.addr_high =
 964                         CPU_TO_LE32(ICE_HI_DWORD(dma_buf->pa));
 965                 desc_on_ring->params.generic.addr_low =
 966                         CPU_TO_LE32(ICE_LO_DWORD(dma_buf->pa));
 967         }
 968
 969         /* Debug desc and buffer */
 970         ice_debug(hw, ICE_DBG_AQ_DESC,
 971                   "ATQ: Control Send queue desc and buffer:\n");
 972
 973         ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
 974
 975
 976         (cq->sq.next_to_use)++;
 977         if (cq->sq.next_to_use == cq->sq.count)
 978                 cq->sq.next_to_use = 0;
 979         wr32(hw, cq->sq.tail, cq->sq.next_to_use);
 980
 981         do {
 982                 if (ice_sq_done(hw, cq))
 983                         break;
 984
 985                 ice_msec_delay(1, false);
 986                 total_delay++;
 987         } while (total_delay < cq->sq_cmd_timeout);
 988
 989         /* if ready, copy the desc back to temp */
 990         if (ice_sq_done(hw, cq)) {
 991                 ice_memcpy(desc, desc_on_ring, sizeof(*desc),
 992                            ICE_DMA_TO_NONDMA);
 993                 if (buf) {
 994                         /* get returned length to copy */
 995                         u16 copy_size = LE16_TO_CPU(desc->datalen);
 996
 997                         if (copy_size > buf_size) {
 998                                 ice_debug(hw, ICE_DBG_AQ_MSG,
 999                                           "Return len %d > than buf len %d\n",
1000                                           copy_size, buf_size);
1001                                 status = ICE_ERR_AQ_ERROR;
1002                         } else {
1003                                 ice_memcpy(buf, dma_buf->va, copy_size,
1004                                            ICE_DMA_TO_NONDMA);
1005                         }
1006                 }
1007                 retval = LE16_TO_CPU(desc->retval);
1008                 if (retval) {
1009                         ice_debug(hw, ICE_DBG_AQ_MSG,
1010                                   "Control Send Queue command 0x%04X completed with error 0x%X\n",
1011                                   LE16_TO_CPU(desc->opcode),
1012                                   retval);
1013
1014                         /* strip off FW internal code */
1015                         retval &= 0xff;
1016                 }
1017                 cmd_completed = true;
1018                 if (!status && retval != ICE_AQ_RC_OK)
1019                         status = ICE_ERR_AQ_ERROR;
1020                 cq->sq_last_status = (enum ice_aq_err)retval;
1021         }
1022
1023         ice_debug(hw, ICE_DBG_AQ_MSG,
1024                   "ATQ: desc and buffer writeback:\n");
1025
1026         ice_debug_cq(hw, (void *)desc, buf, buf_size);
1027
1028
1029         /* save writeback AQ if requested */
1030         if (details->wb_desc)
1031                 ice_memcpy(details->wb_desc, desc_on_ring,
1032                            sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA);
1033
1034         /* update the error if time out occurred */
1035         if (!cmd_completed) {
1036                 ice_debug(hw, ICE_DBG_AQ_MSG,
1037                           "Control Send Queue Writeback timeout.\n");
1038                 status = ICE_ERR_AQ_TIMEOUT;
1039         }
1040
1041 sq_send_command_error:
1042         return status;
1043 }
1044
1045 /**
1046  * ice_sq_send_cmd - send command to Control Queue (ATQ)
1047  * @hw: pointer to the HW struct
1048  * @cq: pointer to the specific Control queue
1049  * @desc: prefilled descriptor describing the command (non DMA mem)
1050  * @buf: buffer to use for indirect commands (or NULL for direct commands)
1051  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1052  * @cd: pointer to command details structure
1053  *
1054  * This is the main send command routine for the ATQ. It runs the queue,
1055  * cleans the queue, etc.
1056  */
1057 enum ice_status
1058 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1059                 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1060                 struct ice_sq_cd *cd)
1061 {
1062         enum ice_status status = ICE_SUCCESS;
1063
1064         /* if reset is in progress return a soft error */
1065         if (hw->reset_ongoing)
1066                 return ICE_ERR_RESET_ONGOING;
1067
1068         ice_acquire_lock(&cq->sq_lock);
1069         status = ice_sq_send_cmd_nolock(hw, cq, desc, buf, buf_size, cd);
1070         ice_release_lock(&cq->sq_lock);
1071
1072         return status;
1073 }
1074
1075 /**
1076  * ice_fill_dflt_direct_cmd_desc - AQ descriptor helper function
1077  * @desc: pointer to the temp descriptor (non DMA mem)
1078  * @opcode: the opcode can be used to decide which flags to turn off or on
1079  *
1080  * Fill the desc with default values
1081  */
1082 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)
1083 {
1084         /* zero out the desc */
1085         ice_memset(desc, 0, sizeof(*desc), ICE_NONDMA_MEM);
1086         desc->opcode = CPU_TO_LE16(opcode);
1087         desc->flags = CPU_TO_LE16(ICE_AQ_FLAG_SI);
1088 }
1089
1090 /**
1091  * ice_clean_rq_elem
1092  * @hw: pointer to the HW struct
1093  * @cq: pointer to the specific Control queue
1094  * @e: event info from the receive descriptor, includes any buffers
1095  * @pending: number of events that could be left to process
1096  *
1097  * This function cleans one Admin Receive Queue element and returns
1098  * the contents through e. It can also return how many events are
1099  * left to process through 'pending'.
1100  */
1101 enum ice_status
1102 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1103                   struct ice_rq_event_info *e, u16 *pending)
1104 {
1105         u16 ntc = cq->rq.next_to_clean;
1106         enum ice_status ret_code = ICE_SUCCESS;
1107         struct ice_aq_desc *desc;
1108         struct ice_dma_mem *bi;
1109         u16 desc_idx;
1110         u16 datalen;
1111         u16 flags;
1112         u16 ntu;
1113
1114         /* pre-clean the event info */
1115         ice_memset(&e->desc, 0, sizeof(e->desc), ICE_NONDMA_MEM);
1116
1117         /* take the lock before we start messing with the ring */
1118         ice_acquire_lock(&cq->rq_lock);
1119
1120         if (!cq->rq.count) {
1121                 ice_debug(hw, ICE_DBG_AQ_MSG,
1122                           "Control Receive queue not initialized.\n");
1123                 ret_code = ICE_ERR_AQ_EMPTY;
1124                 goto clean_rq_elem_err;
1125         }
1126
1127         /* set next_to_use to head */
1128         ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1129
1130         if (ntu == ntc) {
1131                 /* nothing to do - shouldn't need to update ring's values */
1132                 ret_code = ICE_ERR_AQ_NO_WORK;
1133                 goto clean_rq_elem_out;
1134         }
1135
1136         /* now clean the next descriptor */
1137         desc = ICE_CTL_Q_DESC(cq->rq, ntc);
1138         desc_idx = ntc;
1139
1140         cq->rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);
1141         flags = LE16_TO_CPU(desc->flags);
1142         if (flags & ICE_AQ_FLAG_ERR) {
1143                 ret_code = ICE_ERR_AQ_ERROR;
1144                 ice_debug(hw, ICE_DBG_AQ_MSG,
1145                           "Control Receive Queue Event 0x%04X received with error 0x%X\n",
1146                           LE16_TO_CPU(desc->opcode),
1147                           cq->rq_last_status);
1148         }
1149         ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);
1150         datalen = LE16_TO_CPU(desc->datalen);
1151         e->msg_len = min(datalen, e->buf_len);
1152         if (e->msg_buf && e->msg_len)
1153                 ice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,
1154                            e->msg_len, ICE_DMA_TO_NONDMA);
1155
1156         ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
1157
1158         ice_debug_cq(hw, (void *)desc, e->msg_buf,
1159                      cq->rq_buf_size);
1160
1161
1162         /* Restore the original datalen and buffer address in the desc,
1163          * FW updates datalen to indicate the event message size
1164          */
1165         bi = &cq->rq.r.rq_bi[ntc];
1166         ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
1167
1168         desc->flags = CPU_TO_LE16(ICE_AQ_FLAG_BUF);
1169         if (cq->rq_buf_size > ICE_AQ_LG_BUF)
1170                 desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);
1171         desc->datalen = CPU_TO_LE16(bi->size);
1172         desc->params.generic.addr_high = CPU_TO_LE32(ICE_HI_DWORD(bi->pa));
1173         desc->params.generic.addr_low = CPU_TO_LE32(ICE_LO_DWORD(bi->pa));
1174
1175         /* set tail = the last cleaned desc index. */
1176         wr32(hw, cq->rq.tail, ntc);
1177         /* ntc is updated to tail + 1 */
1178         ntc++;
1179         if (ntc == cq->num_rq_entries)
1180                 ntc = 0;
1181         cq->rq.next_to_clean = ntc;
1182         cq->rq.next_to_use = ntu;
1183
1184 clean_rq_elem_out:
1185         /* Set pending if needed, unlock and return */
1186         if (pending) {
1187                 /* re-read HW head to calculate actual pending messages */
1188                 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1189                 *pending = (u16)((ntc > ntu ? cq->rq.count : 0) + (ntu - ntc));
1190         }
1191 clean_rq_elem_err:
1192         ice_release_lock(&cq->rq_lock);
1193
1194         return ret_code;
1195 }