drivers/net/ice/base/ice_controlq.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2019
   3  */
   4
   5 #ifndef _ICE_CONTROLQ_H_
   6 #define _ICE_CONTROLQ_H_
   7
   8 #include "ice_adminq_cmd.h"
   9
  10
  11 /* Maximum buffer lengths for all control queue types */
  12 #define ICE_AQ_MAX_BUF_LEN 4096
  13 #define ICE_MBXQ_MAX_BUF_LEN 4096
  14
  15 #define ICE_CTL_Q_DESC(R, i) \
  16         (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
  17
  18 #define ICE_CTL_Q_DESC_UNUSED(R) \
  19         (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  20               (R)->next_to_clean - (R)->next_to_use - 1)
  21
  22 /* Defines that help manage the driver vs FW API checks.
  23  * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
  24  */
  25 #define EXP_FW_API_VER_BRANCH           0x00
  26 #define EXP_FW_API_VER_MAJOR            0x01
  27 #define EXP_FW_API_VER_MINOR            0x03
  28
  29 /* Different control queue types: These are mainly for SW consumption. */
  30 enum ice_ctl_q {
  31         ICE_CTL_Q_UNKNOWN = 0,
  32         ICE_CTL_Q_ADMIN,
  33         ICE_CTL_Q_MAILBOX,
  34 };
  35
  36 /* Control Queue timeout settings - max delay 250ms */
  37 #define ICE_CTL_Q_SQ_CMD_TIMEOUT        2500  /* Count 2500 times */
  38 #define ICE_CTL_Q_SQ_CMD_USEC           100   /* Check every 100usec */
  39
  40 struct ice_ctl_q_ring {
  41         void *dma_head;                 /* Virtual address to DMA head */
  42         struct ice_dma_mem desc_buf;    /* descriptor ring memory */
  43         void *cmd_buf;                  /* command buffer memory */
  44
  45         union {
  46                 struct ice_dma_mem *sq_bi;
  47                 struct ice_dma_mem *rq_bi;
  48         } r;
  49
  50         u16 count;              /* Number of descriptors */
  51
  52         /* used for interrupt processing */
  53         u16 next_to_use;
  54         u16 next_to_clean;
  55
  56         /* used for queue tracking */
  57         u32 head;
  58         u32 tail;
  59         u32 len;
  60         u32 bah;
  61         u32 bal;
  62         u32 len_mask;
  63         u32 len_ena_mask;
  64         u32 head_mask;
  65 };
  66
  67 /* sq transaction details */
  68 struct ice_sq_cd {
  69         struct ice_aq_desc *wb_desc;
  70 };
  71
  72 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
  73
  74 /* rq event information */
  75 struct ice_rq_event_info {
  76         struct ice_aq_desc desc;
  77         u16 msg_len;
  78         u16 buf_len;
  79         u8 *msg_buf;
  80 };
  81
  82 /* Control Queue information */
  83 struct ice_ctl_q_info {
  84         enum ice_ctl_q qtype;
  85         enum ice_aq_err rq_last_status; /* last status on receive queue */
  86         struct ice_ctl_q_ring rq;       /* receive queue */
  87         struct ice_ctl_q_ring sq;       /* send queue */
  88         u32 sq_cmd_timeout;             /* send queue cmd write back timeout */
  89         u16 num_rq_entries;             /* receive queue depth */
  90         u16 num_sq_entries;             /* send queue depth */
  91         u16 rq_buf_size;                /* receive queue buffer size */
  92         u16 sq_buf_size;                /* send queue buffer size */
  93         enum ice_aq_err sq_last_status; /* last status on send queue */
  94         struct ice_lock sq_lock;                /* Send queue lock */
  95         struct ice_lock rq_lock;                /* Receive queue lock */
  96 };
  97
  98 #endif /* _ICE_CONTROLQ_H_ */