1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ice_common.h"
9 * @hw: pointer to the HW struct
10 * @module_typeid: module pointer location in words from the NVM beginning
11 * @offset: byte offset from the module beginning
12 * @length: length of the section to be read (in bytes from the offset)
13 * @data: command buffer (size [bytes] = length)
14 * @last_command: tells if this is the last command in a series
15 * @read_shadow_ram: tell if this is a shadow RAM read
16 * @cd: pointer to command details structure or NULL
18 * Read the NVM using the admin queue commands (0x0701)
21 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
22 void *data, bool last_command, bool read_shadow_ram,
25 struct ice_aq_desc desc;
26 struct ice_aqc_nvm *cmd;
28 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
30 cmd = &desc.params.nvm;
32 if (offset > ICE_AQC_NVM_MAX_OFFSET)
35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
37 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
38 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
40 /* If this is the last command in a series, set the proper flag. */
42 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
43 cmd->module_typeid = CPU_TO_LE16(module_typeid);
44 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
45 cmd->offset_high = (offset >> 16) & 0xFF;
46 cmd->length = CPU_TO_LE16(length);
48 return ice_aq_send_cmd(hw, &desc, data, length, cd);
52 * ice_read_flat_nvm - Read portion of NVM by flat offset
53 * @hw: pointer to the HW struct
54 * @offset: offset from beginning of NVM
55 * @length: (in) number of bytes to read; (out) number of bytes actually read
56 * @data: buffer to return data in (sized to fit the specified length)
57 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
59 * Reads a portion of the NVM, as a flat memory space. This function correctly
60 * breaks read requests across Shadow RAM sectors and ensures that no single
61 * read request exceeds the maximum 4KB read for a single AdminQ command.
63 * Returns a status code on failure. Note that the data pointer may be
64 * partially updated if some reads succeed before a failure.
67 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
70 enum ice_status status;
75 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
79 /* Verify the length of the read if this is for the Shadow RAM */
80 if (read_shadow_ram && ((offset + inlen) > (hw->nvm.sr_words * 2u))) {
81 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
86 u32 read_size, sector_offset;
88 /* ice_aq_read_nvm cannot read more than 4KB at a time.
89 * Additionally, a read from the Shadow RAM may not cross over
90 * a sector boundary. Conveniently, the sector size is also
93 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
94 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
97 last_cmd = !(bytes_read + read_size < inlen);
99 /* ice_aq_read_nvm takes the length as a u16. Our read_size is
100 * calculated using a u32, but the ICE_AQ_MAX_BUF_LEN maximum
101 * size guarantees that it will fit within the 2 bytes.
103 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
104 offset, (u16)read_size,
105 data + bytes_read, last_cmd,
106 read_shadow_ram, NULL);
110 bytes_read += read_size;
114 *length = bytes_read;
119 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
120 * @hw: pointer to the HW structure
121 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
122 * @data: word read from the Shadow RAM
124 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
126 static enum ice_status
127 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
129 u32 bytes = sizeof(u16);
130 enum ice_status status;
133 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
135 /* Note that ice_read_flat_nvm checks if the read is past the Shadow
136 * RAM size, and ensures we don't read across a Shadow RAM sector
139 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
140 (_FORCE_ u8 *)&data_local, true);
144 *data = LE16_TO_CPU(data_local);
149 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
150 * @hw: pointer to the HW structure
151 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
152 * @words: (in) number of words to read; (out) number of words actually read
153 * @data: words read from the Shadow RAM
155 * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is
156 * taken before reading the buffer and later released.
158 static enum ice_status
159 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
161 u32 bytes = *words * 2, i;
162 enum ice_status status;
164 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
166 /* ice_read_flat_nvm takes into account the 4KB AdminQ and Shadow RAM
167 * sector restrictions necessary when reading from the NVM.
169 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
171 /* Report the number of words successfully read */
174 /* Byte swap the words up to the amount we actually read */
175 for (i = 0; i < *words; i++)
176 data[i] = LE16_TO_CPU(((_FORCE_ __le16 *)data)[i]);
182 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
183 * @hw: pointer to the HW structure
184 * @access: NVM access type (read or write)
186 * This function will request NVM ownership.
189 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
191 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
193 if (hw->nvm.blank_nvm_mode)
196 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
200 * ice_release_nvm - Generic request for releasing the NVM ownership
201 * @hw: pointer to the HW structure
203 * This function will release NVM ownership.
205 void ice_release_nvm(struct ice_hw *hw)
207 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
209 if (hw->nvm.blank_nvm_mode)
212 ice_release_res(hw, ICE_NVM_RES_ID);
216 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
217 * @hw: pointer to the HW structure
218 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
219 * @data: word read from the Shadow RAM
221 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
223 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
225 enum ice_status status;
227 status = ice_acquire_nvm(hw, ICE_RES_READ);
229 status = ice_read_sr_word_aq(hw, offset, data);
237 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
238 * @hw: pointer to hardware structure
239 * @module_tlv: pointer to module TLV to return
240 * @module_tlv_len: pointer to module TLV length to return
241 * @module_type: module type requested
243 * Finds the requested sub module TLV type from the Preserved Field
244 * Area (PFA) and returns the TLV pointer and length. The caller can
245 * use these to read the variable length TLV value.
248 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
251 enum ice_status status;
252 u16 pfa_len, pfa_ptr;
255 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
256 if (status != ICE_SUCCESS) {
257 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
260 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
261 if (status != ICE_SUCCESS) {
262 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
265 /* Starting with first TLV after PFA length, iterate through the list
266 * of TLVs to find the requested one.
268 next_tlv = pfa_ptr + 1;
269 while (next_tlv < pfa_ptr + pfa_len) {
270 u16 tlv_sub_module_type;
274 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
275 if (status != ICE_SUCCESS) {
276 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
279 /* Read TLV length */
280 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
281 if (status != ICE_SUCCESS) {
282 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
285 if (tlv_sub_module_type == module_type) {
287 *module_tlv = next_tlv;
288 *module_tlv_len = tlv_len;
291 return ICE_ERR_INVAL_SIZE;
293 /* Check next TLV, i.e. current TLV pointer + length + 2 words
294 * (for current TLV's type and length)
296 next_tlv = next_tlv + tlv_len + 2;
298 /* Module does not exist */
299 return ICE_ERR_DOES_NOT_EXIST;
303 * ice_read_pba_string - Reads part number string from NVM
304 * @hw: pointer to hardware structure
305 * @pba_num: stores the part number string from the NVM
306 * @pba_num_size: part number string buffer length
308 * Reads the part number string from the NVM.
311 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
313 u16 pba_tlv, pba_tlv_len;
314 enum ice_status status;
315 u16 pba_word, pba_size;
318 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
319 ICE_SR_PBA_BLOCK_PTR);
320 if (status != ICE_SUCCESS) {
321 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
325 /* pba_size is the next word */
326 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
327 if (status != ICE_SUCCESS) {
328 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
332 if (pba_tlv_len < pba_size) {
333 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
334 return ICE_ERR_INVAL_SIZE;
337 /* Subtract one to get PBA word count (PBA Size word is included in
341 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
342 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
343 return ICE_ERR_PARAM;
346 for (i = 0; i < pba_size; i++) {
347 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
348 if (status != ICE_SUCCESS) {
349 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
353 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
354 pba_num[(i * 2) + 1] = pba_word & 0xFF;
356 pba_num[(pba_size * 2)] = '\0';
362 * ice_get_orom_ver_info - Read Option ROM version information
363 * @hw: pointer to the HW struct
365 * Read the Combo Image version data from the Boot Configuration TLV and fill
366 * in the option ROM version data.
368 static enum ice_status ice_get_orom_ver_info(struct ice_hw *hw)
370 u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len;
371 struct ice_orom_info *orom = &hw->nvm.orom;
372 enum ice_status status;
375 status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
376 ICE_SR_BOOT_CFG_PTR);
378 ice_debug(hw, ICE_DBG_INIT, "Failed to read Boot Configuration Block TLV.\n");
382 /* Boot Configuration Block must have length at least 2 words
383 * (Combo Image Version High and Combo Image Version Low)
385 if (boot_cfg_tlv_len < 2) {
386 ice_debug(hw, ICE_DBG_INIT, "Invalid Boot Configuration Block TLV size.\n");
387 return ICE_ERR_INVAL_SIZE;
390 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF),
393 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER hi.\n");
397 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF + 1),
400 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER lo.\n");
404 combo_ver = ((u32)combo_hi << 16) | combo_lo;
406 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >>
408 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
409 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >>
410 ICE_OROM_VER_BUILD_SHIFT);
416 * ice_discover_flash_size - Discover the available flash size.
417 * @hw: pointer to the HW struct
419 * The device flash could be up to 16MB in size. However, it is possible that
420 * the actual size is smaller. Use bisection to determine the accessible size
423 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
425 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
426 enum ice_status status;
428 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
430 status = ice_acquire_nvm(hw, ICE_RES_READ);
434 while ((max_size - min_size) > 1) {
435 u32 offset = (max_size + min_size) / 2;
439 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
440 if (status == ICE_ERR_AQ_ERROR &&
441 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
442 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
444 status = ICE_SUCCESS;
446 } else if (!status) {
447 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
451 /* an unexpected error occurred */
452 goto err_read_flat_nvm;
456 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
458 hw->nvm.flash_size = max_size;
467 * ice_init_nvm - initializes NVM setting
468 * @hw: pointer to the HW struct
470 * This function reads and populates NVM settings such as Shadow RAM size,
471 * max_timeout, and blank_nvm_mode
473 enum ice_status ice_init_nvm(struct ice_hw *hw)
475 struct ice_nvm_info *nvm = &hw->nvm;
476 u16 eetrack_lo, eetrack_hi, ver;
477 enum ice_status status;
481 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
483 /* The SR size is stored regardless of the NVM programming mode
484 * as the blank mode may be used in the factory line.
486 gens_stat = rd32(hw, GLNVM_GENS);
487 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
489 /* Switching to words (sr_size contains power of 2) */
490 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
492 /* Check if we are in the normal or blank NVM programming mode */
493 fla = rd32(hw, GLNVM_FLA);
494 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
495 nvm->blank_nvm_mode = false;
497 /* Blank programming mode */
498 nvm->blank_nvm_mode = true;
499 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
500 return ICE_ERR_NVM_BLANK_MODE;
503 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
505 ice_debug(hw, ICE_DBG_INIT,
506 "Failed to read DEV starter version.\n");
509 nvm->major_ver = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
510 nvm->minor_ver = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
512 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
514 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
517 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
519 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
523 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
525 status = ice_discover_flash_size(hw);
527 ice_debug(hw, ICE_DBG_NVM,
528 "NVM init error: failed to discover flash size.\n");
532 switch (hw->device_id) {
533 /* the following devices do not have boot_cfg_tlv yet */
534 case ICE_DEV_ID_E822C_BACKPLANE:
535 case ICE_DEV_ID_E822C_QSFP:
536 case ICE_DEV_ID_E822C_10G_BASE_T:
537 case ICE_DEV_ID_E822C_SGMII:
538 case ICE_DEV_ID_E822C_SFP:
539 case ICE_DEV_ID_E822L_BACKPLANE:
540 case ICE_DEV_ID_E822L_SFP:
541 case ICE_DEV_ID_E822L_10G_BASE_T:
542 case ICE_DEV_ID_E822L_SGMII:
543 case ICE_DEV_ID_E823L_BACKPLANE:
544 case ICE_DEV_ID_E823L_SFP:
545 case ICE_DEV_ID_E823L_10G_BASE_T:
546 case ICE_DEV_ID_E823L_1GBE:
547 case ICE_DEV_ID_E823L_QSFP:
553 status = ice_get_orom_ver_info(hw);
555 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
563 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
564 * @hw: pointer to the HW structure
565 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
566 * @words: (in) number of words to read; (out) number of words actually read
567 * @data: words read from the Shadow RAM
569 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
570 * method. The buf read is preceded by the NVM ownership take
571 * and followed by the release.
574 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
576 enum ice_status status;
578 status = ice_acquire_nvm(hw, ICE_RES_READ);
580 status = ice_read_sr_buf_aq(hw, offset, words, data);
588 * ice_nvm_validate_checksum
589 * @hw: pointer to the HW struct
591 * Verify NVM PFA checksum validity (0x0706)
593 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
595 struct ice_aqc_nvm_checksum *cmd;
596 struct ice_aq_desc desc;
597 enum ice_status status;
599 status = ice_acquire_nvm(hw, ICE_RES_READ);
603 cmd = &desc.params.nvm_checksum;
605 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
606 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
608 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
612 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
613 status = ICE_ERR_NVM_CHECKSUM;
619 * ice_nvm_access_get_features - Return the NVM access features structure
620 * @cmd: NVM access command to process
621 * @data: storage for the driver NVM features
623 * Fill in the data section of the NVM access request with a copy of the NVM
624 * features structure.
627 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
628 union ice_nvm_access_data *data)
630 /* The provided data_size must be at least as large as our NVM
631 * features structure. A larger size should not be treated as an
632 * error, to allow future extensions to to the features structure to
633 * work on older drivers.
635 if (cmd->data_size < sizeof(struct ice_nvm_features))
636 return ICE_ERR_NO_MEMORY;
638 /* Initialize the data buffer to zeros */
639 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
641 /* Fill in the features data */
642 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
643 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
644 data->drv_features.size = sizeof(struct ice_nvm_features);
645 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
651 * ice_nvm_access_get_module - Helper function to read module value
652 * @cmd: NVM access command structure
654 * Reads the module value out of the NVM access config field.
656 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
658 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
662 * ice_nvm_access_get_flags - Helper function to read flags value
663 * @cmd: NVM access command structure
665 * Reads the flags value out of the NVM access config field.
667 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
669 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
673 * ice_nvm_access_get_adapter - Helper function to read adapter info
674 * @cmd: NVM access command structure
676 * Read the adapter info value out of the NVM access config field.
678 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
680 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
681 ICE_NVM_CFG_ADAPTER_INFO_S);
685 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
686 * @cmd: NVM access command structure
688 * Validates that an NVM access structure is request to read or write a valid
689 * register offset. First validates that the module and flags are correct, and
690 * then ensures that the register offset is one of the accepted registers.
692 static enum ice_status
693 ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
695 u32 module, flags, offset;
698 module = ice_nvm_access_get_module(cmd);
699 flags = ice_nvm_access_get_flags(cmd);
700 offset = cmd->offset;
702 /* Make sure the module and flags indicate a read/write request */
703 if (module != ICE_NVM_REG_RW_MODULE ||
704 flags != ICE_NVM_REG_RW_FLAGS ||
705 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
706 return ICE_ERR_PARAM;
710 case GL_HICR_EN: /* Note, this register is read only */
713 case GLGEN_CSR_DEBUG_C:
724 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
725 if (offset == (u32)GL_HIDA(i))
728 for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
729 if (offset == (u32)GL_HIBA(i))
732 /* All other register offsets are not valid */
733 return ICE_ERR_OUT_OF_RANGE;
737 * ice_nvm_access_read - Handle an NVM read request
738 * @hw: pointer to the HW struct
739 * @cmd: NVM access command to process
740 * @data: storage for the register value read
742 * Process an NVM access request to read a register.
745 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
746 union ice_nvm_access_data *data)
748 enum ice_status status;
750 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
752 /* Always initialize the output data, even on failure */
753 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
755 /* Make sure this is a valid read/write access request */
756 status = ice_validate_nvm_rw_reg(cmd);
760 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
763 /* Read the register and store the contents in the data field */
764 data->regval = rd32(hw, cmd->offset);
770 * ice_nvm_access_write - Handle an NVM write request
771 * @hw: pointer to the HW struct
772 * @cmd: NVM access command to process
773 * @data: NVM access data to write
775 * Process an NVM access request to write a register.
778 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
779 union ice_nvm_access_data *data)
781 enum ice_status status;
783 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
785 /* Make sure this is a valid read/write access request */
786 status = ice_validate_nvm_rw_reg(cmd);
790 /* Reject requests to write to read-only registers */
791 switch (cmd->offset) {
794 return ICE_ERR_OUT_OF_RANGE;
799 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
800 cmd->offset, data->regval);
802 /* Write the data field to the specified register */
803 wr32(hw, cmd->offset, data->regval);
809 * ice_handle_nvm_access - Handle an NVM access request
810 * @hw: pointer to the HW struct
811 * @cmd: NVM access command info
812 * @data: pointer to read or return data
814 * Process an NVM access request. Read the command structure information and
815 * determine if it is valid. If not, report an error indicating the command
818 * For valid commands, perform the necessary function, copying the data into
819 * the provided data buffer.
822 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
823 union ice_nvm_access_data *data)
825 u32 module, flags, adapter_info;
827 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
829 /* Extended flags are currently reserved and must be zero */
830 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
831 return ICE_ERR_PARAM;
833 /* Adapter info must match the HW device ID */
834 adapter_info = ice_nvm_access_get_adapter(cmd);
835 if (adapter_info != hw->device_id)
836 return ICE_ERR_PARAM;
838 switch (cmd->command) {
839 case ICE_NVM_CMD_READ:
840 module = ice_nvm_access_get_module(cmd);
841 flags = ice_nvm_access_get_flags(cmd);
843 /* Getting the driver's NVM features structure shares the same
844 * command type as reading a register. Read the config field
845 * to determine if this is a request to get features.
847 if (module == ICE_NVM_GET_FEATURES_MODULE &&
848 flags == ICE_NVM_GET_FEATURES_FLAGS &&
850 return ice_nvm_access_get_features(cmd, data);
852 return ice_nvm_access_read(hw, cmd, data);
853 case ICE_NVM_CMD_WRITE:
854 return ice_nvm_access_write(hw, cmd, data);
856 return ICE_ERR_PARAM;