1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
17 #define ICE_BYTES_PER_WORD 2
18 #define ICE_BYTES_PER_DWORD 4
19 #define ICE_MAX_TRAFFIC_CLASS 8
22 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
26 #define IS_ASCII(_ch) ((_ch) < 0x80)
29 #include "ice_status.h"
30 #include "ice_hw_autogen.h"
31 #include "ice_devids.h"
32 #include "ice_osdep.h"
33 #include "ice_bitops.h" /* Must come before ice_controlq.h */
34 #include "ice_controlq.h"
35 #include "ice_lan_tx_rx.h"
36 #include "ice_flex_type.h"
37 #include "ice_protocol_type.h"
39 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
41 return ice_is_bit_set(&bitmap, tc);
45 #define DIV_64BIT(n, d) ((n) / (d))
46 #endif /* DIV_64BIT */
48 static inline u64 round_up_64bit(u64 a, u32 b)
50 return DIV_64BIT(((a) + (b) / 2), (b));
53 static inline u32 ice_round_to_num(u32 N, u32 R)
55 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
56 ((((N) + (R) - 1) / (R)) * (R)));
59 /* Driver always calls main vsi_handle first */
60 #define ICE_MAIN_VSI_HANDLE 0
62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
63 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
65 /* Data type manipulation macros. */
66 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
67 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
68 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
70 /* debug masks - set these bits in hw->debug_mask to control output */
71 #define ICE_DBG_INIT BIT_ULL(1)
72 #define ICE_DBG_RELEASE BIT_ULL(2)
74 #define ICE_DBG_LINK BIT_ULL(4)
75 #define ICE_DBG_PHY BIT_ULL(5)
76 #define ICE_DBG_QCTX BIT_ULL(6)
77 #define ICE_DBG_NVM BIT_ULL(7)
78 #define ICE_DBG_LAN BIT_ULL(8)
79 #define ICE_DBG_FLOW BIT_ULL(9)
80 #define ICE_DBG_DCB BIT_ULL(10)
81 #define ICE_DBG_DIAG BIT_ULL(11)
82 #define ICE_DBG_FD BIT_ULL(12)
83 #define ICE_DBG_SW BIT_ULL(13)
84 #define ICE_DBG_SCHED BIT_ULL(14)
86 #define ICE_DBG_PKG BIT_ULL(16)
87 #define ICE_DBG_RES BIT_ULL(17)
88 #define ICE_DBG_AQ_MSG BIT_ULL(24)
89 #define ICE_DBG_AQ_DESC BIT_ULL(25)
90 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
91 #define ICE_DBG_AQ_CMD BIT_ULL(27)
92 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
94 ICE_DBG_AQ_DESC_BUF | \
97 #define ICE_DBG_USER BIT_ULL(31)
98 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
105 enum ice_aq_res_ids {
108 ICE_CHANGE_LOCK_RES_ID,
109 ICE_GLOBAL_CFG_LOCK_RES_ID
112 /* FW update timeout definitions are in milliseconds */
113 #define ICE_NVM_TIMEOUT 180000
114 #define ICE_CHANGE_LOCK_TIMEOUT 1000
115 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
117 enum ice_aq_res_access_type {
122 struct ice_driver_ver {
127 u8 driver_string[32];
146 enum ice_set_fc_aq_failures {
147 ICE_SET_FC_AQ_FAIL_NONE = 0,
148 ICE_SET_FC_AQ_FAIL_GET,
149 ICE_SET_FC_AQ_FAIL_SET,
150 ICE_SET_FC_AQ_FAIL_UPDATE
153 /* These are structs for managing the hardware information and the operations */
161 enum ice_media_type {
162 ICE_MEDIA_UNKNOWN = 0,
169 /* Software VSI types. */
172 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
175 #endif /* ADQ_SUPPORT */
178 struct ice_link_status {
179 /* Refer to ice_aq_phy_type for bits definition */
182 u8 topo_media_conflict;
186 u8 lse_ena; /* Link Status Event notification */
192 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
193 * ice_aqc_get_phy_caps structure
195 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
198 /* Different data queue types: These are mainly for SW consumption. */
207 /* Different reset sources for which a disable queue AQ call has to be made in
208 * order to clean the Tx scheduler as a part of the reset
210 enum ice_disq_rst_src {
215 /* PHY info such as phy_type, etc... */
216 struct ice_phy_info {
217 struct ice_link_status link_info;
218 struct ice_link_status link_info_old;
221 enum ice_media_type media_type;
225 #define ICE_MAX_NUM_MIRROR_RULES 64
227 /* protocol enumeration for filters */
228 enum ice_fltr_ptype {
229 /* NONE - used for undef/error */
230 ICE_FLTR_PTYPE_NONF_NONE = 0,
231 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
232 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
233 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
234 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
235 ICE_FLTR_PTYPE_FRAG_IPV4,
236 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
237 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
238 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
239 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
243 /* 6 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + 4 ICE_VSI_CHNL */
244 #define ICE_MAX_FDIR_VSI_PER_FILTER 6
246 struct ice_fd_hw_prof {
247 struct ice_flow_seg_info *fdir_seg;
249 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER];
250 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
253 /* Common HW capabilities for SW use */
254 struct ice_hw_common_caps {
255 /* Write CSR protection */
258 /* switching mode supported - EVB switching (including cloud) */
259 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
261 /* Manageablity mode & supported protocols over MCTP */
263 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
264 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
265 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
267 u32 mgmt_protocols_mctp;
268 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
269 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
270 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
271 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
275 /* DCB capabilities */
276 u32 active_tc_bitmap;
279 /* RSS related capabilities */
280 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
281 u32 rss_table_entry_width; /* RSS Entry width in bits */
284 u32 num_rxq; /* Number/Total Rx queues */
285 u32 rxq_first_id; /* First queue ID for Rx queues */
286 u32 num_txq; /* Number/Total Tx queues */
287 u32 txq_first_id; /* First queue ID for Tx queues */
290 u32 num_msix_vectors;
291 u32 msix_vector_first_id;
293 /* Max MTU for function or device */
297 u32 num_wol_proxy_fltr;
298 u32 wol_proxy_vsi_seid;
300 /* LED/SDP pin count */
304 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
305 #define ICE_MAX_SUPPORTED_GPIO_LED 12
306 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
307 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
308 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
310 /* EVB capabilities */
311 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
312 u8 evb_802_1_qbh; /* Bridge Port Extension */
318 /* WoL and APM support */
319 #define ICE_WOL_SUPPORT_M BIT(0)
320 #define ICE_ACPI_PROG_MTHD_M BIT(1)
321 #define ICE_PROXY_SUPPORT_M BIT(2)
328 /* Function specific capabilities */
329 struct ice_hw_func_caps {
330 struct ice_hw_common_caps common_cap;
332 u32 fd_fltr_guar; /* Number of filters guaranteed */
333 u32 fd_fltr_best_effort; /* Number of best effort filters */
336 /* Device wide capabilities */
337 struct ice_hw_dev_caps {
338 struct ice_hw_common_caps common_cap;
339 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
340 u32 num_flow_director_fltr; /* Number of FD filters available */
344 /* Information about MAC such as address, etc... */
345 struct ice_mac_info {
346 u8 lan_addr[ETH_ALEN];
347 u8 perm_addr[ETH_ALEN];
348 u8 port_addr[ETH_ALEN];
349 u8 wol_addr[ETH_ALEN];
356 ice_bus_embedded, /* Is device Embedded versus card */
361 enum ice_pcie_bus_speed {
362 ice_pcie_speed_unknown = 0xff,
363 ice_pcie_speed_2_5GT = 0x14,
364 ice_pcie_speed_5_0GT = 0x15,
365 ice_pcie_speed_8_0GT = 0x16,
366 ice_pcie_speed_16_0GT = 0x17
370 enum ice_pcie_link_width {
371 ice_pcie_lnk_width_resrv = 0x00,
372 ice_pcie_lnk_x1 = 0x01,
373 ice_pcie_lnk_x2 = 0x02,
374 ice_pcie_lnk_x4 = 0x04,
375 ice_pcie_lnk_x8 = 0x08,
376 ice_pcie_lnk_x12 = 0x0C,
377 ice_pcie_lnk_x16 = 0x10,
378 ice_pcie_lnk_x32 = 0x20,
379 ice_pcie_lnk_width_unknown = 0xff,
382 /* Reset types used to determine which kind of reset was requested. These
383 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
384 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
385 * because its reset source is different than the other types listed.
397 struct ice_bus_info {
398 enum ice_pcie_bus_speed speed;
399 enum ice_pcie_link_width width;
400 enum ice_bus_type type;
407 /* Flow control (FC) parameters */
409 enum ice_fc_mode current_mode; /* FC mode in effect */
410 enum ice_fc_mode req_mode; /* FC mode requested by caller */
413 /* NVM Information */
414 struct ice_nvm_info {
415 u32 eetrack; /* NVM data version */
416 u32 oem_ver; /* OEM version info */
417 u16 sr_words; /* Shadow RAM size in words */
418 u16 ver; /* NVM package version */
419 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
422 /* Max number of port to queue branches w.r.t topology */
423 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
425 #define ice_for_each_traffic_class(_i) \
426 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
428 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
429 * to driver defined policy for default aggregator
431 #define ICE_INVAL_TEID 0xFFFFFFFF
432 #define ICE_DFLT_AGG_ID 0
434 struct ice_sched_node {
435 struct ice_sched_node *parent;
436 struct ice_sched_node *sibling; /* next sibling in the same layer */
437 struct ice_sched_node **children;
438 struct ice_aqc_txsched_elem_data info;
439 u32 agg_id; /* aggregator group ID */
441 u8 in_use; /* suspended or in use */
442 u8 tx_sched_layer; /* Logical Layer (1-9) */
446 #define ICE_SCHED_NODE_OWNER_LAN 0
447 #define ICE_SCHED_NODE_OWNER_AE 1
448 #define ICE_SCHED_NODE_OWNER_RDMA 2
451 /* Access Macros for Tx Sched Elements data */
452 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
453 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
454 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
455 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
456 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
457 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
458 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
459 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
460 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
461 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
462 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
464 struct ice_sched_rl_profle {
465 u32 rate; /* In Kbps */
466 struct ice_aqc_rl_profile_elem info;
469 /* The aggregator type determines if identifier is for a VSI group,
470 * aggregator group, aggregator of queues, or queue group.
473 ICE_AGG_TYPE_UNKNOWN = 0,
475 ICE_AGG_TYPE_AGG, /* aggregator */
481 /* Rate limit types */
484 ICE_MIN_BW, /* for CIR profile */
485 ICE_MAX_BW, /* for EIR profile */
486 ICE_SHARED_BW /* for shared profile */
489 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
490 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
491 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
492 #define ICE_SCHED_NO_PRIORITY 0
493 #define ICE_SCHED_NO_BW_WT 0
494 #define ICE_SCHED_DFLT_RL_PROF_ID 0
495 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
496 #define ICE_SCHED_DFLT_BW_WT 1
497 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
498 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
500 /* Access Macros for Tx Sched RL Profile data */
501 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
502 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
503 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
504 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
505 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
508 /* The following tree example shows the naming conventions followed under
509 * ice_port_info struct for default scheduler tree topology.
513 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
517 * / |-> num_elements (range:1 - 9)
518 * * | implies num_of_layers
522 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
523 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
524 * need TEID of (a) to add queues.
527 * -> has 8 branches (one for each TC)
528 * -> First branch (TC0) has 4 elements
530 * -> (a) is the topmost layer node created by firmware on branch 0
532 * Note: Above asterisk tree covers only basic terminology and scenario.
533 * Refer to the documentation for more info.
536 /* Data structure for saving BW information */
544 ICE_BW_TYPE_CNT /* This must be last */
552 struct ice_bw_type_info {
553 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
555 struct ice_bw cir_bw;
556 struct ice_bw eir_bw;
560 /* VSI queue context structure for given TC */
564 /* bw_t_info saves queue BW information */
565 struct ice_bw_type_info bw_t_info;
568 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
569 struct ice_sched_vsi_info {
570 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
571 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
572 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
573 /* bw_t_info saves VSI BW information */
574 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
577 /* CEE or IEEE 802.1Qaz ETS Configuration data */
578 struct ice_dcb_ets_cfg {
582 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
583 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
584 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
587 /* CEE or IEEE 802.1Qaz PFC Configuration data */
588 struct ice_dcb_pfc_cfg {
595 /* CEE or IEEE 802.1Qaz Application Priority data */
596 struct ice_dcb_app_priority_table {
602 #define ICE_MAX_USER_PRIORITY 8
603 #define ICE_DCBX_MAX_APPS 32
604 #define ICE_LLDPDU_SIZE 1500
605 #define ICE_TLV_STATUS_OPER 0x1
606 #define ICE_TLV_STATUS_SYNC 0x2
607 #define ICE_TLV_STATUS_ERR 0x4
608 #define ICE_APP_PROT_ID_FCOE 0x8906
609 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
610 #define ICE_APP_PROT_ID_FIP 0x8914
611 #define ICE_APP_SEL_ETHTYPE 0x1
612 #define ICE_APP_SEL_TCPIP 0x2
613 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
614 #define ICE_CEE_APP_SEL_TCPIP 0x1
616 struct ice_dcbx_cfg {
618 u32 tlv_status; /* CEE mode TLV status */
619 struct ice_dcb_ets_cfg etscfg;
620 struct ice_dcb_ets_cfg etsrec;
621 struct ice_dcb_pfc_cfg pfc;
622 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
624 #define ICE_DCBX_MODE_CEE 0x1
625 #define ICE_DCBX_MODE_IEEE 0x2
627 #define ICE_DCBX_APPS_NON_WILLING 0x1
630 struct ice_port_info {
631 struct ice_sched_node *root; /* Root Node per Port */
632 struct ice_hw *hw; /* back pointer to HW instance */
633 u32 last_node_teid; /* scheduler last node info */
634 u16 sw_id; /* Initial switch ID belongs to port */
637 #define ICE_SCHED_PORT_STATE_INIT 0x0
638 #define ICE_SCHED_PORT_STATE_READY 0x1
639 u16 dflt_tx_vsi_rule_id;
641 u16 dflt_rx_vsi_rule_id;
643 struct ice_fc_info fc;
644 struct ice_mac_info mac;
645 struct ice_phy_info phy;
646 struct ice_lock sched_lock; /* protect access to TXSched tree */
647 /* List contain profile ID(s) and other params per layer */
648 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
649 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
651 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
652 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
653 /* LLDP/DCBX Status */
657 #define ICE_LPORT_MASK 0xff
661 struct ice_switch_info {
662 struct LIST_HEAD_TYPE vsi_list_map_head;
663 struct ice_sw_recipe *recp_list;
666 /* FW logging configuration */
667 struct ice_fw_log_evnt {
668 u8 cfg : 4; /* New event enables to configure */
669 u8 cur : 4; /* Current/active event enables */
672 struct ice_fw_log_cfg {
673 u8 cq_en : 1; /* FW logging is enabled via the control queue */
674 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
675 u8 actv_evnts; /* Cumulation of currently enabled log events */
677 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
678 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
679 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
680 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
681 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
684 /* Port hardware description */
688 struct ice_aqc_layer_props *layer_info;
689 struct ice_port_info *port_info;
690 /* 2D Array for each Tx Sched RL Profile type */
691 struct ice_sched_rl_profile **cir_profiles;
692 struct ice_sched_rl_profile **eir_profiles;
693 struct ice_sched_rl_profile **srl_profiles;
694 u64 debug_mask; /* BITMAP for debug mask */
695 enum ice_mac_type mac_type;
697 u16 fd_ctr_base; /* FD counter base index */
701 u16 subsystem_device_id;
702 u16 subsystem_vendor_id;
705 u8 pf_id; /* device profile info */
707 u16 max_burst_size; /* driver sets this value */
708 /* Tx Scheduler values */
709 u16 num_tx_sched_layers;
710 u16 num_tx_sched_phys_layers;
713 u8 sw_entry_point_layer;
714 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
715 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
716 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
717 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
718 u8 evb_veb; /* true for VEB, false for VEPA */
719 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
720 struct ice_bus_info bus;
721 struct ice_nvm_info nvm;
722 struct ice_hw_dev_caps dev_caps; /* device capabilities */
723 struct ice_hw_func_caps func_caps; /* function capabilities */
725 struct ice_switch_info *switch_info; /* switch filter lists */
727 /* Control Queue info */
728 struct ice_ctl_q_info adminq;
729 struct ice_ctl_q_info mailboxq;
731 u8 api_branch; /* API branch version */
732 u8 api_maj_ver; /* API major version */
733 u8 api_min_ver; /* API minor version */
734 u8 api_patch; /* API patch version */
735 u8 fw_branch; /* firmware branch version */
736 u8 fw_maj_ver; /* firmware major version */
737 u8 fw_min_ver; /* firmware minor version */
738 u8 fw_patch; /* firmware patch version */
739 u32 fw_build; /* firmware build number */
741 struct ice_fw_log_cfg fw_log;
743 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
744 * register. Used for determining the itr/intrl granularity during
747 #define ICE_MAX_AGG_BW_200G 0x0
748 #define ICE_MAX_AGG_BW_100G 0X1
749 #define ICE_MAX_AGG_BW_50G 0x2
750 #define ICE_MAX_AGG_BW_25G 0x3
751 /* ITR granularity for different speeds */
752 #define ICE_ITR_GRAN_ABOVE_25 2
753 #define ICE_ITR_GRAN_MAX_25 4
754 /* ITR granularity in 1 us */
756 /* INTRL granularity for different speeds */
757 #define ICE_INTRL_GRAN_ABOVE_25 4
758 #define ICE_INTRL_GRAN_MAX_25 8
759 /* INTRL granularity in 1 us */
762 u8 ucast_shared; /* true if VSIs can share unicast addr */
764 /* Active package version (currently active) */
765 struct ice_pkg_ver active_pkg_ver;
766 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
768 /* Driver's package ver - (from the Metadata seg) */
769 struct ice_pkg_ver pkg_ver;
770 u8 pkg_name[ICE_PKG_NAME_SIZE];
772 /* Driver's Ice package version (from the Ice seg) */
773 struct ice_pkg_ver ice_pkg_ver;
774 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
776 /* Pointer to the ice segment */
779 /* Pointer to allocated copy of pkg memory */
784 struct ice_tunnel_table tnl;
786 #define ICE_PKG_FILENAME "package_file"
787 #define ICE_PKG_FILENAME_EXT "pkg"
788 #define ICE_PKG_FILE_MAJ_VER 1
789 #define ICE_PKG_FILE_MIN_VER 0
791 /* HW block tables */
792 struct ice_blk_info blk[ICE_BLK_COUNT];
793 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
794 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
795 /* Flow Director filter info */
796 int fdir_active_fltr;
798 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
799 struct LIST_HEAD_TYPE fdir_list_head;
801 /* Book-keeping of side-band filter count per flow-type.
802 * This is used to detect and handle input set changes for
803 * respective flow-type.
805 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
807 struct ice_fd_hw_prof **fdir_prof;
808 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
809 struct ice_lock rss_locks; /* protect RSS configuration */
810 struct LIST_HEAD_TYPE rss_list_head;
813 /* Statistics collected by each port, VSI, VEB, and S-channel */
814 struct ice_eth_stats {
815 u64 rx_bytes; /* gorc */
816 u64 rx_unicast; /* uprc */
817 u64 rx_multicast; /* mprc */
818 u64 rx_broadcast; /* bprc */
819 u64 rx_discards; /* rdpc */
820 u64 rx_unknown_protocol; /* rupp */
821 u64 tx_bytes; /* gotc */
822 u64 tx_unicast; /* uptc */
823 u64 tx_multicast; /* mptc */
824 u64 tx_broadcast; /* bptc */
825 u64 tx_discards; /* tdpc */
826 u64 tx_errors; /* tepc */
831 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
832 struct ice_veb_up_stats {
833 u64 up_rx_pkts[ICE_MAX_UP];
834 u64 up_rx_bytes[ICE_MAX_UP];
835 u64 up_tx_pkts[ICE_MAX_UP];
836 u64 up_tx_bytes[ICE_MAX_UP];
839 /* Statistics collected by the MAC */
840 struct ice_hw_port_stats {
841 /* eth stats collected by the port */
842 struct ice_eth_stats eth;
843 /* additional port specific stats */
844 u64 tx_dropped_link_down; /* tdold */
845 u64 crc_errors; /* crcerrs */
846 u64 illegal_bytes; /* illerrc */
847 u64 error_bytes; /* errbc */
848 u64 mac_local_faults; /* mlfc */
849 u64 mac_remote_faults; /* mrfc */
850 u64 rx_len_errors; /* rlec */
851 u64 link_xon_rx; /* lxonrxc */
852 u64 link_xoff_rx; /* lxoffrxc */
853 u64 link_xon_tx; /* lxontxc */
854 u64 link_xoff_tx; /* lxofftxc */
855 u64 priority_xon_rx[8]; /* pxonrxc[8] */
856 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
857 u64 priority_xon_tx[8]; /* pxontxc[8] */
858 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
859 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
860 u64 rx_size_64; /* prc64 */
861 u64 rx_size_127; /* prc127 */
862 u64 rx_size_255; /* prc255 */
863 u64 rx_size_511; /* prc511 */
864 u64 rx_size_1023; /* prc1023 */
865 u64 rx_size_1522; /* prc1522 */
866 u64 rx_size_big; /* prc9522 */
867 u64 rx_undersize; /* ruc */
868 u64 rx_fragments; /* rfc */
869 u64 rx_oversize; /* roc */
870 u64 rx_jabber; /* rjc */
871 u64 tx_size_64; /* ptc64 */
872 u64 tx_size_127; /* ptc127 */
873 u64 tx_size_255; /* ptc255 */
874 u64 tx_size_511; /* ptc511 */
875 u64 tx_size_1023; /* ptc1023 */
876 u64 tx_size_1522; /* ptc1522 */
877 u64 tx_size_big; /* ptc9522 */
878 u64 mac_short_pkt_dropped; /* mspdc */
879 /* flow director stats */
884 #endif /* ADQ_SUPPORT */
887 enum ice_sw_fwd_act_type {
889 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
896 /* Checksum and Shadow RAM pointers */
897 #define ICE_SR_NVM_CTRL_WORD 0x00
898 #define ICE_SR_PHY_ANALOG_PTR 0x04
899 #define ICE_SR_OPTION_ROM_PTR 0x05
900 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
901 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
902 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
903 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
904 #define ICE_SR_EMP_IMAGE_PTR 0x0B
905 #define ICE_SR_PE_IMAGE_PTR 0x0C
906 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
907 #define ICE_SR_MNG_CFG_PTR 0x0E
908 #define ICE_SR_EMP_MODULE_PTR 0x0F
909 #define ICE_SR_PBA_FLAGS 0x15
910 #define ICE_SR_PBA_BLOCK_PTR 0x16
911 #define ICE_SR_BOOT_CFG_PTR 0x17
912 #define ICE_SR_NVM_WOL_CFG 0x19
913 #define ICE_NVM_OEM_VER_OFF 0x83
914 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
915 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
916 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
917 #define ICE_SR_NVM_MAP_VER 0x29
918 #define ICE_SR_NVM_IMAGE_VER 0x2A
919 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
920 #define ICE_SR_NVM_EETRACK_LO 0x2D
921 #define ICE_SR_NVM_EETRACK_HI 0x2E
922 #define ICE_NVM_VER_LO_SHIFT 0
923 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
924 #define ICE_NVM_VER_HI_SHIFT 12
925 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
926 #define ICE_OEM_EETRACK_ID 0xffffffff
927 #define ICE_OEM_VER_PATCH_SHIFT 0
928 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
929 #define ICE_OEM_VER_BUILD_SHIFT 8
930 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
931 #define ICE_OEM_VER_SHIFT 24
932 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
933 #define ICE_SR_VPD_PTR 0x2F
934 #define ICE_SR_PXE_SETUP_PTR 0x30
935 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
936 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
937 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
938 #define ICE_SR_VLAN_CFG_PTR 0x37
939 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
940 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
941 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
942 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
943 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
944 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
945 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
946 #define ICE_SR_PFA_PTR 0x40
947 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
948 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
949 #define ICE_SR_NVM_BANK_SIZE 0x43
950 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
951 #define ICE_SR_OROM_BANK_SIZE 0x45
952 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
953 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
954 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
956 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
957 #define ICE_SR_VPD_SIZE_WORDS 512
958 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
959 #define ICE_SR_CTRL_WORD_1_S 0x06
960 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
962 /* Shadow RAM related */
963 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
964 #define ICE_SR_BUF_ALIGNMENT 4096
965 #define ICE_SR_WORDS_IN_1KB 512
966 /* Checksum should be calculated such that after adding all the words,
967 * including the checksum word itself, the sum should be 0xBABA.
969 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
971 #define ICE_PBA_FLAG_DFLT 0xFAFA
972 /* Hash redirection LUT for VSI - maximum array size */
973 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
976 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
977 * This is needed to determine the BAR0 space for the VFs
979 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
980 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
981 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
983 #endif /* _ICE_TYPE_H_ */