1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
17 #define ICE_BYTES_PER_WORD 2
18 #define ICE_BYTES_PER_DWORD 4
19 #define ICE_MAX_TRAFFIC_CLASS 8
22 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
25 #include "ice_status.h"
26 #include "ice_hw_autogen.h"
27 #include "ice_devids.h"
28 #include "ice_osdep.h"
29 #include "ice_bitops.h" /* Must come before ice_controlq.h */
30 #include "ice_controlq.h"
31 #include "ice_lan_tx_rx.h"
32 #include "ice_flex_type.h"
33 #include "ice_protocol_type.h"
35 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
37 return ice_is_bit_set(&bitmap, tc);
41 #define DIV_64BIT(n, d) ((n) / (d))
42 #endif /* DIV_64BIT */
44 static inline u64 round_up_64bit(u64 a, u32 b)
46 return DIV_64BIT(((a) + (b) / 2), (b));
49 static inline u32 ice_round_to_num(u32 N, u32 R)
51 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
52 ((((N) + (R) - 1) / (R)) * (R)));
55 /* Driver always calls main vsi_handle first */
56 #define ICE_MAIN_VSI_HANDLE 0
58 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
59 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
61 /* Data type manipulation macros. */
62 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
63 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
64 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
66 /* debug masks - set these bits in hw->debug_mask to control output */
67 #define ICE_DBG_INIT BIT_ULL(1)
68 #define ICE_DBG_RELEASE BIT_ULL(2)
70 #define ICE_DBG_LINK BIT_ULL(4)
71 #define ICE_DBG_PHY BIT_ULL(5)
72 #define ICE_DBG_QCTX BIT_ULL(6)
73 #define ICE_DBG_NVM BIT_ULL(7)
74 #define ICE_DBG_LAN BIT_ULL(8)
75 #define ICE_DBG_FLOW BIT_ULL(9)
76 #define ICE_DBG_DCB BIT_ULL(10)
77 #define ICE_DBG_DIAG BIT_ULL(11)
78 #define ICE_DBG_FD BIT_ULL(12)
79 #define ICE_DBG_SW BIT_ULL(13)
80 #define ICE_DBG_SCHED BIT_ULL(14)
82 #define ICE_DBG_PKG BIT_ULL(16)
83 #define ICE_DBG_RES BIT_ULL(17)
84 #define ICE_DBG_AQ_MSG BIT_ULL(24)
85 #define ICE_DBG_AQ_DESC BIT_ULL(25)
86 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
87 #define ICE_DBG_AQ_CMD BIT_ULL(27)
88 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
90 ICE_DBG_AQ_DESC_BUF | \
93 #define ICE_DBG_USER BIT_ULL(31)
94 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
101 enum ice_aq_res_ids {
104 ICE_CHANGE_LOCK_RES_ID,
105 ICE_GLOBAL_CFG_LOCK_RES_ID
108 /* FW update timeout definitions are in milliseconds */
109 #define ICE_NVM_TIMEOUT 180000
110 #define ICE_CHANGE_LOCK_TIMEOUT 1000
111 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
113 enum ice_aq_res_access_type {
118 struct ice_driver_ver {
123 u8 driver_string[32];
142 enum ice_set_fc_aq_failures {
143 ICE_SET_FC_AQ_FAIL_NONE = 0,
144 ICE_SET_FC_AQ_FAIL_GET,
145 ICE_SET_FC_AQ_FAIL_SET,
146 ICE_SET_FC_AQ_FAIL_UPDATE
149 /* These are structs for managing the hardware information and the operations */
157 enum ice_media_type {
158 ICE_MEDIA_UNKNOWN = 0,
165 /* Software VSI types. */
168 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
171 #endif /* ADQ_SUPPORT */
174 struct ice_link_status {
175 /* Refer to ice_aq_phy_type for bits definition */
178 u8 topo_media_conflict;
182 u8 lse_ena; /* Link Status Event notification */
188 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
189 * ice_aqc_get_phy_caps structure
191 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
194 /* Different data queue types: These are mainly for SW consumption. */
203 /* Different reset sources for which a disable queue AQ call has to be made in
204 * order to clean the Tx scheduler as a part of the reset
206 enum ice_disq_rst_src {
211 /* PHY info such as phy_type, etc... */
212 struct ice_phy_info {
213 struct ice_link_status link_info;
214 struct ice_link_status link_info_old;
217 enum ice_media_type media_type;
221 #define ICE_MAX_NUM_MIRROR_RULES 64
223 /* protocol enumeration for filters */
224 enum ice_fltr_ptype {
225 /* NONE - used for undef/error */
226 ICE_FLTR_PTYPE_NONF_NONE = 0,
227 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
228 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
229 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
230 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
231 ICE_FLTR_PTYPE_FRAG_IPV4,
232 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
233 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
234 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
235 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
239 /* 6 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + 4 ICE_VSI_CHNL */
240 #define ICE_MAX_FDIR_VSI_PER_FILTER 6
242 struct ice_fd_hw_prof {
243 struct ice_flow_seg_info *fdir_seg;
245 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER];
246 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
249 /* Common HW capabilities for SW use */
250 struct ice_hw_common_caps {
251 /* Write CSR protection */
254 /* switching mode supported - EVB switching (including cloud) */
255 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
257 /* Manageablity mode & supported protocols over MCTP */
259 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
260 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
261 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
263 u32 mgmt_protocols_mctp;
264 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
265 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
266 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
267 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
271 /* DCB capabilities */
272 u32 active_tc_bitmap;
275 /* RSS related capabilities */
276 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
277 u32 rss_table_entry_width; /* RSS Entry width in bits */
280 u32 num_rxq; /* Number/Total Rx queues */
281 u32 rxq_first_id; /* First queue ID for Rx queues */
282 u32 num_txq; /* Number/Total Tx queues */
283 u32 txq_first_id; /* First queue ID for Tx queues */
286 u32 num_msix_vectors;
287 u32 msix_vector_first_id;
289 /* Max MTU for function or device */
293 u32 num_wol_proxy_fltr;
294 u32 wol_proxy_vsi_seid;
296 /* LED/SDP pin count */
300 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
301 #define ICE_MAX_SUPPORTED_GPIO_LED 12
302 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
303 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
304 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
306 /* EVB capabilities */
307 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
308 u8 evb_802_1_qbh; /* Bridge Port Extension */
314 /* WoL and APM support */
315 #define ICE_WOL_SUPPORT_M BIT(0)
316 #define ICE_ACPI_PROG_MTHD_M BIT(1)
317 #define ICE_PROXY_SUPPORT_M BIT(2)
324 /* Function specific capabilities */
325 struct ice_hw_func_caps {
326 struct ice_hw_common_caps common_cap;
328 u32 fd_fltr_guar; /* Number of filters guaranteed */
329 u32 fd_fltr_best_effort; /* Number of best effort filters */
332 /* Device wide capabilities */
333 struct ice_hw_dev_caps {
334 struct ice_hw_common_caps common_cap;
335 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
336 u32 num_flow_director_fltr; /* Number of FD filters available */
340 /* Information about MAC such as address, etc... */
341 struct ice_mac_info {
342 u8 lan_addr[ETH_ALEN];
343 u8 perm_addr[ETH_ALEN];
344 u8 port_addr[ETH_ALEN];
345 u8 wol_addr[ETH_ALEN];
352 ice_bus_embedded, /* Is device Embedded versus card */
357 enum ice_pcie_bus_speed {
358 ice_pcie_speed_unknown = 0xff,
359 ice_pcie_speed_2_5GT = 0x14,
360 ice_pcie_speed_5_0GT = 0x15,
361 ice_pcie_speed_8_0GT = 0x16,
362 ice_pcie_speed_16_0GT = 0x17
366 enum ice_pcie_link_width {
367 ice_pcie_lnk_width_resrv = 0x00,
368 ice_pcie_lnk_x1 = 0x01,
369 ice_pcie_lnk_x2 = 0x02,
370 ice_pcie_lnk_x4 = 0x04,
371 ice_pcie_lnk_x8 = 0x08,
372 ice_pcie_lnk_x12 = 0x0C,
373 ice_pcie_lnk_x16 = 0x10,
374 ice_pcie_lnk_x32 = 0x20,
375 ice_pcie_lnk_width_unknown = 0xff,
378 /* Reset types used to determine which kind of reset was requested. These
379 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
380 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
381 * because its reset source is different than the other types listed.
393 struct ice_bus_info {
394 enum ice_pcie_bus_speed speed;
395 enum ice_pcie_link_width width;
396 enum ice_bus_type type;
403 /* Flow control (FC) parameters */
405 enum ice_fc_mode current_mode; /* FC mode in effect */
406 enum ice_fc_mode req_mode; /* FC mode requested by caller */
409 /* NVM Information */
410 struct ice_nvm_info {
411 u32 eetrack; /* NVM data version */
412 u32 oem_ver; /* OEM version info */
413 u16 sr_words; /* Shadow RAM size in words */
414 u16 ver; /* NVM package version */
415 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
418 /* Max number of port to queue branches w.r.t topology */
419 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
421 #define ice_for_each_traffic_class(_i) \
422 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
424 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
425 * to driver defined policy for default aggregator
427 #define ICE_INVAL_TEID 0xFFFFFFFF
428 #define ICE_DFLT_AGG_ID 0
430 struct ice_sched_node {
431 struct ice_sched_node *parent;
432 struct ice_sched_node *sibling; /* next sibling in the same layer */
433 struct ice_sched_node **children;
434 struct ice_aqc_txsched_elem_data info;
435 u32 agg_id; /* aggregator group ID */
437 u8 in_use; /* suspended or in use */
438 u8 tx_sched_layer; /* Logical Layer (1-9) */
442 #define ICE_SCHED_NODE_OWNER_LAN 0
443 #define ICE_SCHED_NODE_OWNER_AE 1
444 #define ICE_SCHED_NODE_OWNER_RDMA 2
447 /* Access Macros for Tx Sched Elements data */
448 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
449 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
450 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
451 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
452 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
453 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
454 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
455 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
456 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
457 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
458 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
460 struct ice_sched_rl_profle {
461 u32 rate; /* In Kbps */
462 struct ice_aqc_rl_profile_elem info;
465 /* The aggregator type determines if identifier is for a VSI group,
466 * aggregator group, aggregator of queues, or queue group.
469 ICE_AGG_TYPE_UNKNOWN = 0,
471 ICE_AGG_TYPE_AGG, /* aggregator */
477 /* Rate limit types */
480 ICE_MIN_BW, /* for CIR profile */
481 ICE_MAX_BW, /* for EIR profile */
482 ICE_SHARED_BW /* for shared profile */
485 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
486 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
487 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
488 #define ICE_SCHED_NO_PRIORITY 0
489 #define ICE_SCHED_NO_BW_WT 0
490 #define ICE_SCHED_DFLT_RL_PROF_ID 0
491 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
492 #define ICE_SCHED_DFLT_BW_WT 1
493 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
494 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
496 /* Access Macros for Tx Sched RL Profile data */
497 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
498 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
499 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
500 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
501 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
504 /* The following tree example shows the naming conventions followed under
505 * ice_port_info struct for default scheduler tree topology.
509 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
513 * / |-> num_elements (range:1 - 9)
514 * * | implies num_of_layers
518 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
519 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
520 * need TEID of (a) to add queues.
523 * -> has 8 branches (one for each TC)
524 * -> First branch (TC0) has 4 elements
526 * -> (a) is the topmost layer node created by firmware on branch 0
528 * Note: Above asterisk tree covers only basic terminology and scenario.
529 * Refer to the documentation for more info.
532 /* Data structure for saving BW information */
540 ICE_BW_TYPE_CNT /* This must be last */
548 struct ice_bw_type_info {
549 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
551 struct ice_bw cir_bw;
552 struct ice_bw eir_bw;
556 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
557 struct ice_sched_vsi_info {
558 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
559 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
560 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
561 /* bw_t_info saves VSI BW information */
562 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
565 /* CEE or IEEE 802.1Qaz ETS Configuration data */
566 struct ice_dcb_ets_cfg {
570 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
571 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
572 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
575 /* CEE or IEEE 802.1Qaz PFC Configuration data */
576 struct ice_dcb_pfc_cfg {
583 /* CEE or IEEE 802.1Qaz Application Priority data */
584 struct ice_dcb_app_priority_table {
590 #define ICE_MAX_USER_PRIORITY 8
591 #define ICE_DCBX_MAX_APPS 32
592 #define ICE_LLDPDU_SIZE 1500
593 #define ICE_TLV_STATUS_OPER 0x1
594 #define ICE_TLV_STATUS_SYNC 0x2
595 #define ICE_TLV_STATUS_ERR 0x4
596 #define ICE_APP_PROT_ID_FCOE 0x8906
597 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
598 #define ICE_APP_PROT_ID_FIP 0x8914
599 #define ICE_APP_SEL_ETHTYPE 0x1
600 #define ICE_APP_SEL_TCPIP 0x2
601 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
602 #define ICE_CEE_APP_SEL_TCPIP 0x1
604 struct ice_dcbx_cfg {
606 u32 tlv_status; /* CEE mode TLV status */
607 struct ice_dcb_ets_cfg etscfg;
608 struct ice_dcb_ets_cfg etsrec;
609 struct ice_dcb_pfc_cfg pfc;
610 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
612 #define ICE_DCBX_MODE_CEE 0x1
613 #define ICE_DCBX_MODE_IEEE 0x2
615 #define ICE_DCBX_APPS_NON_WILLING 0x1
618 struct ice_port_info {
619 struct ice_sched_node *root; /* Root Node per Port */
620 struct ice_hw *hw; /* back pointer to HW instance */
621 u32 last_node_teid; /* scheduler last node info */
622 u16 sw_id; /* Initial switch ID belongs to port */
625 #define ICE_SCHED_PORT_STATE_INIT 0x0
626 #define ICE_SCHED_PORT_STATE_READY 0x1
627 u16 dflt_tx_vsi_rule_id;
629 u16 dflt_rx_vsi_rule_id;
631 struct ice_fc_info fc;
632 struct ice_mac_info mac;
633 struct ice_phy_info phy;
634 struct ice_lock sched_lock; /* protect access to TXSched tree */
635 /* List contain profile ID(s) and other params per layer */
636 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
637 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
639 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
640 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
641 /* LLDP/DCBX Status */
645 #define ICE_LPORT_MASK 0xff
649 struct ice_switch_info {
650 struct LIST_HEAD_TYPE vsi_list_map_head;
651 struct ice_sw_recipe *recp_list;
654 /* FW logging configuration */
655 struct ice_fw_log_evnt {
656 u8 cfg : 4; /* New event enables to configure */
657 u8 cur : 4; /* Current/active event enables */
660 struct ice_fw_log_cfg {
661 u8 cq_en : 1; /* FW logging is enabled via the control queue */
662 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
663 u8 actv_evnts; /* Cumulation of currently enabled log events */
665 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
666 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
667 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
668 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
669 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
672 /* Port hardware description */
676 struct ice_aqc_layer_props *layer_info;
677 struct ice_port_info *port_info;
678 /* 2D Array for each Tx Sched RL Profile type */
679 struct ice_sched_rl_profile **cir_profiles;
680 struct ice_sched_rl_profile **eir_profiles;
681 struct ice_sched_rl_profile **srl_profiles;
682 u64 debug_mask; /* BITMAP for debug mask */
683 enum ice_mac_type mac_type;
685 u16 fd_ctr_base; /* FD counter base index */
689 u16 subsystem_device_id;
690 u16 subsystem_vendor_id;
693 u8 pf_id; /* device profile info */
695 u16 max_burst_size; /* driver sets this value */
696 /* Tx Scheduler values */
697 u16 num_tx_sched_layers;
698 u16 num_tx_sched_phys_layers;
701 u8 sw_entry_point_layer;
702 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
703 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
704 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
705 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
706 u8 evb_veb; /* true for VEB, false for VEPA */
707 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
708 struct ice_bus_info bus;
709 struct ice_nvm_info nvm;
710 struct ice_hw_dev_caps dev_caps; /* device capabilities */
711 struct ice_hw_func_caps func_caps; /* function capabilities */
713 struct ice_switch_info *switch_info; /* switch filter lists */
715 /* Control Queue info */
716 struct ice_ctl_q_info adminq;
717 struct ice_ctl_q_info mailboxq;
719 u8 api_branch; /* API branch version */
720 u8 api_maj_ver; /* API major version */
721 u8 api_min_ver; /* API minor version */
722 u8 api_patch; /* API patch version */
723 u8 fw_branch; /* firmware branch version */
724 u8 fw_maj_ver; /* firmware major version */
725 u8 fw_min_ver; /* firmware minor version */
726 u8 fw_patch; /* firmware patch version */
727 u32 fw_build; /* firmware build number */
729 struct ice_fw_log_cfg fw_log;
731 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
732 * register. Used for determining the itr/intrl granularity during
735 #define ICE_MAX_AGG_BW_200G 0x0
736 #define ICE_MAX_AGG_BW_100G 0X1
737 #define ICE_MAX_AGG_BW_50G 0x2
738 #define ICE_MAX_AGG_BW_25G 0x3
739 /* ITR granularity for different speeds */
740 #define ICE_ITR_GRAN_ABOVE_25 2
741 #define ICE_ITR_GRAN_MAX_25 4
742 /* ITR granularity in 1 us */
744 /* INTRL granularity for different speeds */
745 #define ICE_INTRL_GRAN_ABOVE_25 4
746 #define ICE_INTRL_GRAN_MAX_25 8
747 /* INTRL granularity in 1 us */
750 u8 ucast_shared; /* true if VSIs can share unicast addr */
752 /* Active package version (currently active) */
753 struct ice_pkg_ver active_pkg_ver;
754 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
756 /* Driver's package ver - (from the Metadata seg) */
757 struct ice_pkg_ver pkg_ver;
758 u8 pkg_name[ICE_PKG_NAME_SIZE];
760 /* Driver's Ice package version (from the Ice seg) */
761 struct ice_pkg_ver ice_pkg_ver;
762 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
764 /* Pointer to the ice segment */
767 /* Pointer to allocated copy of pkg memory */
772 struct ice_tunnel_table tnl;
774 #define ICE_PKG_FILENAME "package_file"
775 #define ICE_PKG_FILENAME_EXT "pkg"
776 #define ICE_PKG_FILE_MAJ_VER 1
777 #define ICE_PKG_FILE_MIN_VER 0
779 /* HW block tables */
780 struct ice_blk_info blk[ICE_BLK_COUNT];
781 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
782 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
783 /* Flow Director filter info */
784 int fdir_active_fltr;
786 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
787 struct LIST_HEAD_TYPE fdir_list_head;
789 /* Book-keeping of side-band filter count per flow-type.
790 * This is used to detect and handle input set changes for
791 * respective flow-type.
793 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
795 struct ice_fd_hw_prof **fdir_prof;
798 /* Statistics collected by each port, VSI, VEB, and S-channel */
799 struct ice_eth_stats {
800 u64 rx_bytes; /* gorc */
801 u64 rx_unicast; /* uprc */
802 u64 rx_multicast; /* mprc */
803 u64 rx_broadcast; /* bprc */
804 u64 rx_discards; /* rdpc */
805 u64 rx_unknown_protocol; /* rupp */
806 u64 tx_bytes; /* gotc */
807 u64 tx_unicast; /* uptc */
808 u64 tx_multicast; /* mptc */
809 u64 tx_broadcast; /* bptc */
810 u64 tx_discards; /* tdpc */
811 u64 tx_errors; /* tepc */
816 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
817 struct ice_veb_up_stats {
818 u64 up_rx_pkts[ICE_MAX_UP];
819 u64 up_rx_bytes[ICE_MAX_UP];
820 u64 up_tx_pkts[ICE_MAX_UP];
821 u64 up_tx_bytes[ICE_MAX_UP];
824 /* Statistics collected by the MAC */
825 struct ice_hw_port_stats {
826 /* eth stats collected by the port */
827 struct ice_eth_stats eth;
828 /* additional port specific stats */
829 u64 tx_dropped_link_down; /* tdold */
830 u64 crc_errors; /* crcerrs */
831 u64 illegal_bytes; /* illerrc */
832 u64 error_bytes; /* errbc */
833 u64 mac_local_faults; /* mlfc */
834 u64 mac_remote_faults; /* mrfc */
835 u64 rx_len_errors; /* rlec */
836 u64 link_xon_rx; /* lxonrxc */
837 u64 link_xoff_rx; /* lxoffrxc */
838 u64 link_xon_tx; /* lxontxc */
839 u64 link_xoff_tx; /* lxofftxc */
840 u64 priority_xon_rx[8]; /* pxonrxc[8] */
841 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
842 u64 priority_xon_tx[8]; /* pxontxc[8] */
843 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
844 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
845 u64 rx_size_64; /* prc64 */
846 u64 rx_size_127; /* prc127 */
847 u64 rx_size_255; /* prc255 */
848 u64 rx_size_511; /* prc511 */
849 u64 rx_size_1023; /* prc1023 */
850 u64 rx_size_1522; /* prc1522 */
851 u64 rx_size_big; /* prc9522 */
852 u64 rx_undersize; /* ruc */
853 u64 rx_fragments; /* rfc */
854 u64 rx_oversize; /* roc */
855 u64 rx_jabber; /* rjc */
856 u64 tx_size_64; /* ptc64 */
857 u64 tx_size_127; /* ptc127 */
858 u64 tx_size_255; /* ptc255 */
859 u64 tx_size_511; /* ptc511 */
860 u64 tx_size_1023; /* ptc1023 */
861 u64 tx_size_1522; /* ptc1522 */
862 u64 tx_size_big; /* ptc9522 */
863 u64 mac_short_pkt_dropped; /* mspdc */
864 /* flow director stats */
869 #endif /* ADQ_SUPPORT */
872 enum ice_sw_fwd_act_type {
874 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
881 /* Checksum and Shadow RAM pointers */
882 #define ICE_SR_NVM_CTRL_WORD 0x00
883 #define ICE_SR_PHY_ANALOG_PTR 0x04
884 #define ICE_SR_OPTION_ROM_PTR 0x05
885 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
886 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
887 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
888 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
889 #define ICE_SR_EMP_IMAGE_PTR 0x0B
890 #define ICE_SR_PE_IMAGE_PTR 0x0C
891 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
892 #define ICE_SR_MNG_CFG_PTR 0x0E
893 #define ICE_SR_EMP_MODULE_PTR 0x0F
894 #define ICE_SR_PBA_FLAGS 0x15
895 #define ICE_SR_PBA_BLOCK_PTR 0x16
896 #define ICE_SR_BOOT_CFG_PTR 0x17
897 #define ICE_SR_NVM_WOL_CFG 0x19
898 #define ICE_NVM_OEM_VER_OFF 0x83
899 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
900 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
901 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
902 #define ICE_SR_NVM_MAP_VER 0x29
903 #define ICE_SR_NVM_IMAGE_VER 0x2A
904 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
905 #define ICE_SR_NVM_EETRACK_LO 0x2D
906 #define ICE_SR_NVM_EETRACK_HI 0x2E
907 #define ICE_NVM_VER_LO_SHIFT 0
908 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
909 #define ICE_NVM_VER_HI_SHIFT 12
910 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
911 #define ICE_OEM_EETRACK_ID 0xffffffff
912 #define ICE_OEM_VER_PATCH_SHIFT 0
913 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
914 #define ICE_OEM_VER_BUILD_SHIFT 8
915 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
916 #define ICE_OEM_VER_SHIFT 24
917 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
918 #define ICE_SR_VPD_PTR 0x2F
919 #define ICE_SR_PXE_SETUP_PTR 0x30
920 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
921 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
922 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
923 #define ICE_SR_VLAN_CFG_PTR 0x37
924 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
925 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
926 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
927 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
928 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
929 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
930 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
931 #define ICE_SR_PFA_PTR 0x40
932 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
933 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
934 #define ICE_SR_NVM_BANK_SIZE 0x43
935 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
936 #define ICE_SR_OROM_BANK_SIZE 0x45
937 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
938 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
939 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
941 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
942 #define ICE_SR_VPD_SIZE_WORDS 512
943 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
944 #define ICE_SR_CTRL_WORD_1_S 0x06
945 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
947 /* Shadow RAM related */
948 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
949 #define ICE_SR_BUF_ALIGNMENT 4096
950 #define ICE_SR_WORDS_IN_1KB 512
951 /* Checksum should be calculated such that after adding all the words,
952 * including the checksum word itself, the sum should be 0xBABA.
954 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
956 #define ICE_PBA_FLAG_DFLT 0xFAFA
957 /* Hash redirection LUT for VSI - maximum array size */
958 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
961 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
962 * This is needed to determine the BAR0 space for the VFs
964 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
965 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
966 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
968 #endif /* _ICE_TYPE_H_ */