1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2021 Intel Corporation
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
37 #define STRUCT_HACK_VAR_LEN
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
47 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
49 #include "ice_status.h"
50 #include "ice_hw_autogen.h"
51 #include "ice_devids.h"
52 #include "ice_osdep.h"
53 #include "ice_bitops.h" /* Must come before ice_controlq.h */
54 #include "ice_controlq.h"
55 #include "ice_lan_tx_rx.h"
56 #include "ice_flex_type.h"
57 #include "ice_protocol_type.h"
58 #include "ice_sbq_cmd.h"
59 #include "ice_vlan_mode.h"
62 * ice_is_pow2 - check if integer value is a power of 2
63 * @val: unsigned integer to be validated
65 static inline bool ice_is_pow2(u64 val)
67 return (val && !(val & (val - 1)));
71 * ice_ilog2 - Calculates integer log base 2 of a number
72 * @n: number on which to perform operation
74 static inline int ice_ilog2(u64 n)
78 for (i = 63; i >= 0; i--)
79 if (((u64)1 << i) & n)
85 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
87 return ice_is_bit_set(&bitmap, tc);
90 #define DIV_64BIT(n, d) ((n) / (d))
92 static inline u64 round_up_64bit(u64 a, u32 b)
94 return DIV_64BIT(((a) + (b) / 2), (b));
97 static inline u32 ice_round_to_num(u32 N, u32 R)
99 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
100 ((((N) + (R) - 1) / (R)) * (R)));
103 /* Driver always calls main vsi_handle first */
104 #define ICE_MAIN_VSI_HANDLE 0
106 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
107 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
109 /* Data type manipulation macros. */
110 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
111 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
112 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
113 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
115 /* debug masks - set these bits in hw->debug_mask to control output */
116 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
117 #define ICE_DBG_INIT BIT_ULL(1)
118 #define ICE_DBG_RELEASE BIT_ULL(2)
119 #define ICE_DBG_FW_LOG BIT_ULL(3)
120 #define ICE_DBG_LINK BIT_ULL(4)
121 #define ICE_DBG_PHY BIT_ULL(5)
122 #define ICE_DBG_QCTX BIT_ULL(6)
123 #define ICE_DBG_NVM BIT_ULL(7)
124 #define ICE_DBG_LAN BIT_ULL(8)
125 #define ICE_DBG_FLOW BIT_ULL(9)
126 #define ICE_DBG_DCB BIT_ULL(10)
127 #define ICE_DBG_DIAG BIT_ULL(11)
128 #define ICE_DBG_FD BIT_ULL(12)
129 #define ICE_DBG_SW BIT_ULL(13)
130 #define ICE_DBG_SCHED BIT_ULL(14)
132 #define ICE_DBG_PKG BIT_ULL(16)
133 #define ICE_DBG_RES BIT_ULL(17)
134 #define ICE_DBG_ACL BIT_ULL(18)
135 #define ICE_DBG_PTP BIT_ULL(19)
136 #define ICE_DBG_AQ_MSG BIT_ULL(24)
137 #define ICE_DBG_AQ_DESC BIT_ULL(25)
138 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
139 #define ICE_DBG_AQ_CMD BIT_ULL(27)
140 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
142 ICE_DBG_AQ_DESC_BUF | \
145 #define ICE_DBG_USER BIT_ULL(31)
146 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
148 #define __ALWAYS_UNUSED
150 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
151 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
152 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
153 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
155 enum ice_aq_res_ids {
158 ICE_CHANGE_LOCK_RES_ID,
159 ICE_GLOBAL_CFG_LOCK_RES_ID
162 /* FW update timeout definitions are in milliseconds */
163 #define ICE_NVM_TIMEOUT 180000
164 #define ICE_CHANGE_LOCK_TIMEOUT 1000
165 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
167 enum ice_aq_res_access_type {
172 struct ice_driver_ver {
177 u8 driver_string[32];
190 enum ice_phy_cache_mode {
203 struct ice_phy_cache_mode_data {
205 enum ice_fec_mode curr_user_fec_req;
206 enum ice_fc_mode curr_user_fc_req;
207 u16 curr_user_speed_req;
211 enum ice_set_fc_aq_failures {
212 ICE_SET_FC_AQ_FAIL_NONE = 0,
213 ICE_SET_FC_AQ_FAIL_GET,
214 ICE_SET_FC_AQ_FAIL_SET,
215 ICE_SET_FC_AQ_FAIL_UPDATE
218 /* These are structs for managing the hardware information and the operations */
227 enum ice_media_type {
228 ICE_MEDIA_UNKNOWN = 0,
236 /* Software VSI types. */
239 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
243 struct ice_link_status {
244 /* Refer to ice_aq_phy_type for bits definition */
247 u8 topo_media_conflict;
252 u8 lse_ena; /* Link Status Event notification */
258 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
259 * ice_aqc_get_phy_caps structure
261 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
264 /* Different data queue types: These are mainly for SW consumption. */
273 /* Different reset sources for which a disable queue AQ call has to be made in
274 * order to clean the Tx scheduler as a part of the reset
276 enum ice_disq_rst_src {
281 /* PHY info such as phy_type, etc... */
282 struct ice_phy_info {
283 struct ice_link_status link_info;
284 struct ice_link_status link_info_old;
287 enum ice_media_type media_type;
289 /* Please refer to struct ice_aqc_get_link_status_data to get
290 * detail of enable bit in curr_user_speed_req
292 u16 curr_user_speed_req;
293 enum ice_fec_mode curr_user_fec_req;
294 enum ice_fc_mode curr_user_fc_req;
295 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
298 #define ICE_MAX_NUM_MIRROR_RULES 64
300 /* protocol enumeration for filters */
301 enum ice_fltr_ptype {
302 /* NONE - used for undef/error */
303 ICE_FLTR_PTYPE_NONF_NONE = 0,
304 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
305 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
306 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
307 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
308 ICE_FLTR_PTYPE_NONF_IPV4_GTPU,
309 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
310 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
311 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
312 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
313 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
314 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
315 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH,
316 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
317 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
318 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
319 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6,
320 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_UDP,
321 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV6_TCP,
322 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW,
323 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4,
324 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_UDP,
325 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV4_TCP,
326 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6,
327 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_UDP,
328 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_DW_IPV6_TCP,
329 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP,
330 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4,
331 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_UDP,
332 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV4_TCP,
333 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6,
334 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_UDP,
335 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_UP_IPV6_TCP,
336 ICE_FLTR_PTYPE_NONF_IPV6_GTPU,
337 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH,
338 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_DW,
339 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_UP,
340 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
341 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
342 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
343 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
344 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
345 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
346 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
347 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
348 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
349 ICE_FLTR_PTYPE_NONF_IPV4_AH,
350 ICE_FLTR_PTYPE_NONF_IPV6_AH,
351 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
352 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
353 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
354 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
355 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
356 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
357 ICE_FLTR_PTYPE_NON_IP_L2,
358 ICE_FLTR_PTYPE_NONF_ECPRI_TP0,
359 ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
360 ICE_FLTR_PTYPE_FRAG_IPV4,
361 ICE_FLTR_PTYPE_FRAG_IPV6,
362 ICE_FLTR_PTYPE_NONF_IPV4_GRE,
363 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4,
364 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_UDP,
365 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_TCP,
366 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6,
367 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_UDP,
368 ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_TCP,
369 ICE_FLTR_PTYPE_NONF_IPV6_GRE,
370 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4,
371 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_UDP,
372 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_TCP,
373 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6,
374 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP,
375 ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP,
376 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
377 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
378 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
379 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
380 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN,
381 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_UDP,
382 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_TCP,
383 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_SCTP,
384 ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN_IPV4_OTHER,
389 ICE_FD_HW_SEG_NON_TUN = 0,
394 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
395 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
397 struct ice_fd_hw_prof {
398 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
400 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
401 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
404 /* Common HW capabilities for SW use */
405 struct ice_hw_common_caps {
406 /* Write CSR protection */
409 /* switching mode supported - EVB switching (including cloud) */
410 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
412 /* Manageablity mode & supported protocols over MCTP */
414 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
415 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
416 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
418 u32 mgmt_protocols_mctp;
419 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
420 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
421 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
422 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
426 /* DCB capabilities */
427 u32 active_tc_bitmap;
430 /* RSS related capabilities */
431 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
432 u32 rss_table_entry_width; /* RSS Entry width in bits */
435 u32 num_rxq; /* Number/Total Rx queues */
436 u32 rxq_first_id; /* First queue ID for Rx queues */
437 u32 num_txq; /* Number/Total Tx queues */
438 u32 txq_first_id; /* First queue ID for Tx queues */
441 u32 num_msix_vectors;
442 u32 msix_vector_first_id;
444 /* Max MTU for function or device */
448 u32 num_wol_proxy_fltr;
449 u32 wol_proxy_vsi_seid;
451 /* LED/SDP pin count */
455 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
456 #define ICE_MAX_SUPPORTED_GPIO_LED 12
457 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
458 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
459 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
461 /* EVB capabilities */
462 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
463 u8 evb_802_1_qbh; /* Bridge Port Extension */
470 /* WoL and APM support */
471 #define ICE_WOL_SUPPORT_M BIT(0)
472 #define ICE_ACPI_PROG_MTHD_M BIT(1)
473 #define ICE_PROXY_SUPPORT_M BIT(2)
477 bool sec_rev_disabled;
478 bool update_disabled;
479 bool nvm_unified_update;
480 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
481 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
482 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
484 /* External topology device images within the NVM */
485 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4
486 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
487 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
488 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
489 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8
490 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \
491 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
492 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
493 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
494 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
495 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
498 /* IEEE 1588 TIME_SYNC specific info */
499 /* Function specific definitions */
500 #define ICE_TS_FUNC_ENA_M BIT(0)
501 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
502 #define ICE_TS_TMR_ENA_M BIT(2)
503 #define ICE_TS_TMR_IDX_OWND_S 4
504 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
505 #define ICE_TS_CLK_FREQ_S 16
506 #define ICE_TS_CLK_FREQ_M MAKEMASK(0x7, ICE_TS_CLK_FREQ_S)
507 #define ICE_TS_CLK_SRC_S 20
508 #define ICE_TS_CLK_SRC_M BIT(20)
509 #define ICE_TS_TMR_IDX_ASSOC_S 24
510 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
512 /* TIME_REF clock rate specification */
513 enum ice_time_ref_freq {
514 ICE_TIME_REF_FREQ_25_000 = 0,
515 ICE_TIME_REF_FREQ_122_880 = 1,
516 ICE_TIME_REF_FREQ_125_000 = 2,
517 ICE_TIME_REF_FREQ_153_600 = 3,
518 ICE_TIME_REF_FREQ_156_250 = 4,
519 ICE_TIME_REF_FREQ_245_760 = 5,
521 NUM_ICE_TIME_REF_FREQ
524 /* Clock source specification */
526 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
527 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
532 struct ice_ts_func_info {
533 /* Function specific info */
534 enum ice_time_ref_freq time_ref;
544 /* Device specific definitions */
545 #define ICE_TS_TMR0_OWNR_M 0x7
546 #define ICE_TS_TMR0_OWND_M BIT(3)
547 #define ICE_TS_TMR1_OWNR_S 4
548 #define ICE_TS_TMR1_OWNR_M MAKEMASK(0x7, ICE_TS_TMR1_OWNR_S)
549 #define ICE_TS_TMR1_OWND_M BIT(7)
550 #define ICE_TS_DEV_ENA_M BIT(24)
551 #define ICE_TS_TMR0_ENA_M BIT(25)
552 #define ICE_TS_TMR1_ENA_M BIT(26)
554 struct ice_ts_dev_info {
555 /* Device specific info */
567 /* Function specific capabilities */
568 struct ice_hw_func_caps {
569 struct ice_hw_common_caps common_cap;
571 u32 fd_fltr_guar; /* Number of filters guaranteed */
572 u32 fd_fltr_best_effort; /* Number of best effort filters */
573 struct ice_ts_func_info ts_func_info;
576 /* Device wide capabilities */
577 struct ice_hw_dev_caps {
578 struct ice_hw_common_caps common_cap;
579 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
580 u32 num_flow_director_fltr; /* Number of FD filters available */
581 struct ice_ts_dev_info ts_dev_info;
585 /* Information about MAC such as address, etc... */
586 struct ice_mac_info {
587 u8 lan_addr[ETH_ALEN];
588 u8 perm_addr[ETH_ALEN];
589 u8 port_addr[ETH_ALEN];
590 u8 wol_addr[ETH_ALEN];
597 ice_bus_embedded, /* Is device Embedded versus card */
602 enum ice_pcie_bus_speed {
603 ice_pcie_speed_unknown = 0xff,
604 ice_pcie_speed_2_5GT = 0x14,
605 ice_pcie_speed_5_0GT = 0x15,
606 ice_pcie_speed_8_0GT = 0x16,
607 ice_pcie_speed_16_0GT = 0x17
611 enum ice_pcie_link_width {
612 ice_pcie_lnk_width_resrv = 0x00,
613 ice_pcie_lnk_x1 = 0x01,
614 ice_pcie_lnk_x2 = 0x02,
615 ice_pcie_lnk_x4 = 0x04,
616 ice_pcie_lnk_x8 = 0x08,
617 ice_pcie_lnk_x12 = 0x0C,
618 ice_pcie_lnk_x16 = 0x10,
619 ice_pcie_lnk_x32 = 0x20,
620 ice_pcie_lnk_width_unknown = 0xff,
623 /* Reset types used to determine which kind of reset was requested. These
624 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
625 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
626 * because its reset source is different than the other types listed.
638 struct ice_bus_info {
639 enum ice_pcie_bus_speed speed;
640 enum ice_pcie_link_width width;
641 enum ice_bus_type type;
648 /* Flow control (FC) parameters */
650 enum ice_fc_mode current_mode; /* FC mode in effect */
651 enum ice_fc_mode req_mode; /* FC mode requested by caller */
654 /* Option ROM version information */
655 struct ice_orom_info {
656 u8 major; /* Major version of OROM */
657 u8 patch; /* Patch version of OROM */
658 u16 build; /* Build version of OROM */
659 u32 srev; /* Security revision */
662 /* NVM version information */
663 struct ice_nvm_info {
670 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
671 * of the flash image.
673 enum ice_flash_bank {
674 ICE_INVALID_FLASH_BANK,
679 /* Enumeration of which flash bank is desired to read from, either the active
680 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
681 * code which just wants to read the active or inactive flash bank.
683 enum ice_bank_select {
684 ICE_ACTIVE_FLASH_BANK,
685 ICE_INACTIVE_FLASH_BANK,
688 /* information for accessing NVM, OROM, and Netlist flash banks */
689 struct ice_bank_info {
690 u32 nvm_ptr; /* Pointer to 1st NVM bank */
691 u32 nvm_size; /* Size of NVM bank */
692 u32 orom_ptr; /* Pointer to 1st OROM bank */
693 u32 orom_size; /* Size of OROM bank */
694 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
695 u32 netlist_size; /* Size of Netlist bank */
696 enum ice_flash_bank nvm_bank; /* Active NVM bank */
697 enum ice_flash_bank orom_bank; /* Active OROM bank */
698 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
701 /* Flash Chip Information */
702 struct ice_flash_info {
703 struct ice_orom_info orom; /* Option ROM version info */
704 struct ice_nvm_info nvm; /* NVM version information */
705 struct ice_bank_info banks; /* Flash Bank information */
706 u16 sr_words; /* Shadow RAM size in words */
707 u32 flash_size; /* Size of available flash in bytes */
708 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
711 struct ice_link_default_override_tlv {
713 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
714 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
715 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
716 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
717 #define ICE_LINK_OVERRIDE_EN BIT(3)
718 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
719 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
721 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
722 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
723 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
724 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
725 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
727 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
733 #define ICE_NVM_VER_LEN 32
735 /* Max number of port to queue branches w.r.t topology */
736 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
738 #define ice_for_each_traffic_class(_i) \
739 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
741 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
742 * to driver defined policy for default aggregator
744 #define ICE_INVAL_TEID 0xFFFFFFFF
745 #define ICE_DFLT_AGG_ID 0
747 struct ice_sched_node {
748 struct ice_sched_node *parent;
749 struct ice_sched_node *sibling; /* next sibling in the same layer */
750 struct ice_sched_node **children;
751 struct ice_aqc_txsched_elem_data info;
752 u32 agg_id; /* aggregator group ID */
754 u8 in_use; /* suspended or in use */
755 u8 tx_sched_layer; /* Logical Layer (1-9) */
759 #define ICE_SCHED_NODE_OWNER_LAN 0
760 #define ICE_SCHED_NODE_OWNER_AE 1
761 #define ICE_SCHED_NODE_OWNER_RDMA 2
764 /* Access Macros for Tx Sched Elements data */
765 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
766 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
767 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
768 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
769 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
770 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
771 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
772 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
773 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
774 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
775 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
777 struct ice_sched_rl_profile {
778 u32 rate; /* In Kbps */
779 struct ice_aqc_rl_profile_elem info;
782 /* The aggregator type determines if identifier is for a VSI group,
783 * aggregator group, aggregator of queues, or queue group.
786 ICE_AGG_TYPE_UNKNOWN = 0,
788 ICE_AGG_TYPE_AGG, /* aggregator */
794 /* Rate limit types */
797 ICE_MIN_BW, /* for CIR profile */
798 ICE_MAX_BW, /* for EIR profile */
799 ICE_SHARED_BW /* for shared profile */
802 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
803 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
804 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
805 #define ICE_SCHED_NO_PRIORITY 0
806 #define ICE_SCHED_NO_BW_WT 0
807 #define ICE_SCHED_DFLT_RL_PROF_ID 0
808 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
809 #define ICE_SCHED_DFLT_BW_WT 4
810 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
811 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
813 /* Access Macros for Tx Sched RL Profile data */
814 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
815 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
816 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
817 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
818 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
820 /* The following tree example shows the naming conventions followed under
821 * ice_port_info struct for default scheduler tree topology.
825 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
829 * / |-> num_elements (range:1 - 9)
830 * * | implies num_of_layers
834 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
835 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
836 * need TEID of (a) to add queues.
839 * -> has 8 branches (one for each TC)
840 * -> First branch (TC0) has 4 elements
842 * -> (a) is the topmost layer node created by firmware on branch 0
844 * Note: Above asterisk tree covers only basic terminology and scenario.
845 * Refer to the documentation for more info.
848 /* Data structure for saving BW information */
856 ICE_BW_TYPE_CNT /* This must be last */
864 struct ice_bw_type_info {
865 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
867 struct ice_bw cir_bw;
868 struct ice_bw eir_bw;
872 /* VSI queue context structure for given TC */
876 /* bw_t_info saves queue BW information */
877 struct ice_bw_type_info bw_t_info;
880 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
881 struct ice_sched_vsi_info {
882 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
883 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
884 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
885 /* bw_t_info saves VSI BW information */
886 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
889 /* CEE or IEEE 802.1Qaz ETS Configuration data */
890 struct ice_dcb_ets_cfg {
894 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
895 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
896 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
899 /* CEE or IEEE 802.1Qaz PFC Configuration data */
900 struct ice_dcb_pfc_cfg {
907 /* CEE or IEEE 802.1Qaz Application Priority data */
908 struct ice_dcb_app_priority_table {
914 #define ICE_MAX_USER_PRIORITY 8
915 #define ICE_DCBX_MAX_APPS 64
916 #define ICE_DSCP_NUM_VAL 64
917 #define ICE_LLDPDU_SIZE 1500
918 #define ICE_TLV_STATUS_OPER 0x1
919 #define ICE_TLV_STATUS_SYNC 0x2
920 #define ICE_TLV_STATUS_ERR 0x4
921 #define ICE_APP_PROT_ID_FCOE 0x8906
922 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
923 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
924 #define ICE_APP_PROT_ID_FIP 0x8914
925 #define ICE_APP_SEL_ETHTYPE 0x1
926 #define ICE_APP_SEL_TCPIP 0x2
927 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
928 #define ICE_CEE_APP_SEL_TCPIP 0x1
930 struct ice_dcbx_cfg {
932 u32 tlv_status; /* CEE mode TLV status */
933 struct ice_dcb_ets_cfg etscfg;
934 struct ice_dcb_ets_cfg etsrec;
935 struct ice_dcb_pfc_cfg pfc;
936 #define ICE_QOS_MODE_VLAN 0x0
937 #define ICE_QOS_MODE_DSCP 0x1
939 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
940 /* when DSCP mapping defined by user set its bit to 1 */
941 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
942 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
943 u8 dscp_map[ICE_DSCP_NUM_VAL];
945 #define ICE_DCBX_MODE_CEE 0x1
946 #define ICE_DCBX_MODE_IEEE 0x2
948 #define ICE_DCBX_APPS_NON_WILLING 0x1
952 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
953 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
954 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
955 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
959 struct ice_port_info {
960 struct ice_sched_node *root; /* Root Node per Port */
961 struct ice_hw *hw; /* back pointer to HW instance */
962 u32 last_node_teid; /* scheduler last node info */
963 u16 sw_id; /* Initial switch ID belongs to port */
966 #define ICE_SCHED_PORT_STATE_INIT 0x0
967 #define ICE_SCHED_PORT_STATE_READY 0x1
969 #define ICE_LPORT_MASK 0xff
970 u16 dflt_tx_vsi_rule_id;
972 u16 dflt_rx_vsi_rule_id;
974 struct ice_fc_info fc;
975 struct ice_mac_info mac;
976 struct ice_phy_info phy;
977 struct ice_lock sched_lock; /* protect access to TXSched tree */
978 struct ice_sched_node *
979 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
980 struct ice_bw_type_info root_node_bw_t_info;
981 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
982 struct ice_qos_cfg qos_cfg;
986 struct ice_switch_info {
987 struct LIST_HEAD_TYPE vsi_list_map_head;
988 struct ice_sw_recipe *recp_list;
989 u16 prof_res_bm_init;
990 u16 max_used_prof_index;
992 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
995 /* Port hardware description */
999 struct ice_aqc_layer_props *layer_info;
1000 struct ice_port_info *port_info;
1001 /* 2D Array for each Tx Sched RL Profile type */
1002 struct ice_sched_rl_profile **cir_profiles;
1003 struct ice_sched_rl_profile **eir_profiles;
1004 struct ice_sched_rl_profile **srl_profiles;
1005 /* PSM clock frequency for calculating RL profile params */
1007 u64 debug_mask; /* BITMAP for debug mask */
1008 enum ice_mac_type mac_type;
1010 u16 fd_ctr_base; /* FD counter base index */
1014 u16 subsystem_device_id;
1015 u16 subsystem_vendor_id;
1018 u8 pf_id; /* device profile info */
1020 u16 max_burst_size; /* driver sets this value */
1022 /* Tx Scheduler values */
1023 u8 num_tx_sched_layers;
1024 u8 num_tx_sched_phys_layers;
1025 u8 flattened_layers;
1027 u8 sw_entry_point_layer;
1028 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1029 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
1030 /* List contain profile ID(s) and other params per layer */
1031 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1032 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
1033 u8 evb_veb; /* true for VEB, false for VEPA */
1034 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
1035 struct ice_bus_info bus;
1036 struct ice_flash_info flash;
1037 struct ice_hw_dev_caps dev_caps; /* device capabilities */
1038 struct ice_hw_func_caps func_caps; /* function capabilities */
1040 struct ice_switch_info *switch_info; /* switch filter lists */
1042 /* Control Queue info */
1043 struct ice_ctl_q_info adminq;
1044 struct ice_ctl_q_info sbq;
1045 struct ice_ctl_q_info mailboxq;
1046 /* Additional function to send AdminQ command */
1047 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
1048 void *buf, u16 buf_size);
1049 void *aq_send_cmd_param;
1050 u8 dcf_enabled; /* Device Config Function */
1052 u8 api_branch; /* API branch version */
1053 u8 api_maj_ver; /* API major version */
1054 u8 api_min_ver; /* API minor version */
1055 u8 api_patch; /* API patch version */
1056 u8 fw_branch; /* firmware branch version */
1057 u8 fw_maj_ver; /* firmware major version */
1058 u8 fw_min_ver; /* firmware minor version */
1059 u8 fw_patch; /* firmware patch version */
1060 u32 fw_build; /* firmware build number */
1062 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
1063 * register. Used for determining the ITR/INTRL granularity during
1066 #define ICE_MAX_AGG_BW_200G 0x0
1067 #define ICE_MAX_AGG_BW_100G 0X1
1068 #define ICE_MAX_AGG_BW_50G 0x2
1069 #define ICE_MAX_AGG_BW_25G 0x3
1070 /* ITR granularity for different speeds */
1071 #define ICE_ITR_GRAN_ABOVE_25 2
1072 #define ICE_ITR_GRAN_MAX_25 4
1073 /* ITR granularity in 1 us */
1075 /* INTRL granularity for different speeds */
1076 #define ICE_INTRL_GRAN_ABOVE_25 4
1077 #define ICE_INTRL_GRAN_MAX_25 8
1078 /* INTRL granularity in 1 us */
1081 u8 ucast_shared; /* true if VSIs can share unicast addr */
1083 #define ICE_PHY_PER_NAC 1
1084 #define ICE_MAX_QUAD 2
1085 #define ICE_NUM_QUAD_TYPE 2
1086 #define ICE_PORTS_PER_QUAD 4
1087 #define ICE_PHY_0_LAST_QUAD 1
1088 #define ICE_PORTS_PER_PHY 8
1089 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
1091 /* Active package version (currently active) */
1092 struct ice_pkg_ver active_pkg_ver;
1093 u32 active_track_id;
1094 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
1095 u8 active_pkg_in_nvm;
1097 enum ice_aq_err pkg_dwnld_status;
1099 /* Driver's package ver - (from the Ice Metadata section) */
1100 struct ice_pkg_ver pkg_ver;
1101 u8 pkg_name[ICE_PKG_NAME_SIZE];
1103 /* Driver's Ice segment format version and id (from the Ice seg) */
1104 struct ice_pkg_ver ice_seg_fmt_ver;
1105 u8 ice_seg_id[ICE_SEG_ID_SIZE];
1107 /* Pointer to the ice segment */
1108 struct ice_seg *seg;
1110 /* Pointer to allocated copy of pkg memory */
1114 /* tunneling info */
1115 struct ice_lock tnl_lock;
1116 struct ice_tunnel_table tnl;
1117 /* dvm boost update information */
1118 struct ice_dvm_table dvm_upd;
1120 struct ice_acl_tbl *acl_tbl;
1121 struct ice_fd_hw_prof **acl_prof;
1122 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1123 /* HW block tables */
1124 struct ice_blk_info blk[ICE_BLK_COUNT];
1125 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1126 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
1127 /* Flow Director filter info */
1128 int fdir_active_fltr;
1130 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
1131 struct LIST_HEAD_TYPE fdir_list_head;
1133 /* Book-keeping of side-band filter count per flow-type.
1134 * This is used to detect and handle input set changes for
1135 * respective flow-type.
1137 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1139 struct ice_fd_hw_prof **fdir_prof;
1140 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1141 struct ice_lock rss_locks; /* protect RSS configuration */
1142 struct LIST_HEAD_TYPE rss_list_head;
1143 ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
1147 /* Statistics collected by each port, VSI, VEB, and S-channel */
1148 struct ice_eth_stats {
1149 u64 rx_bytes; /* gorc */
1150 u64 rx_unicast; /* uprc */
1151 u64 rx_multicast; /* mprc */
1152 u64 rx_broadcast; /* bprc */
1153 u64 rx_discards; /* rdpc */
1154 u64 rx_unknown_protocol; /* rupp */
1155 u64 tx_bytes; /* gotc */
1156 u64 tx_unicast; /* uptc */
1157 u64 tx_multicast; /* mptc */
1158 u64 tx_broadcast; /* bptc */
1159 u64 tx_discards; /* tdpc */
1160 u64 tx_errors; /* tepc */
1161 u64 rx_no_desc; /* repc */
1162 u64 rx_errors; /* repc */
1165 #define ICE_MAX_UP 8
1167 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1168 struct ice_veb_up_stats {
1169 u64 up_rx_pkts[ICE_MAX_UP];
1170 u64 up_rx_bytes[ICE_MAX_UP];
1171 u64 up_tx_pkts[ICE_MAX_UP];
1172 u64 up_tx_bytes[ICE_MAX_UP];
1175 /* Statistics collected by the MAC */
1176 struct ice_hw_port_stats {
1177 /* eth stats collected by the port */
1178 struct ice_eth_stats eth;
1179 /* additional port specific stats */
1180 u64 tx_dropped_link_down; /* tdold */
1181 u64 crc_errors; /* crcerrs */
1182 u64 illegal_bytes; /* illerrc */
1183 u64 error_bytes; /* errbc */
1184 u64 mac_local_faults; /* mlfc */
1185 u64 mac_remote_faults; /* mrfc */
1186 u64 rx_len_errors; /* rlec */
1187 u64 link_xon_rx; /* lxonrxc */
1188 u64 link_xoff_rx; /* lxoffrxc */
1189 u64 link_xon_tx; /* lxontxc */
1190 u64 link_xoff_tx; /* lxofftxc */
1191 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1192 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1193 u64 priority_xon_tx[8]; /* pxontxc[8] */
1194 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1195 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1196 u64 rx_size_64; /* prc64 */
1197 u64 rx_size_127; /* prc127 */
1198 u64 rx_size_255; /* prc255 */
1199 u64 rx_size_511; /* prc511 */
1200 u64 rx_size_1023; /* prc1023 */
1201 u64 rx_size_1522; /* prc1522 */
1202 u64 rx_size_big; /* prc9522 */
1203 u64 rx_undersize; /* ruc */
1204 u64 rx_fragments; /* rfc */
1205 u64 rx_oversize; /* roc */
1206 u64 rx_jabber; /* rjc */
1207 u64 tx_size_64; /* ptc64 */
1208 u64 tx_size_127; /* ptc127 */
1209 u64 tx_size_255; /* ptc255 */
1210 u64 tx_size_511; /* ptc511 */
1211 u64 tx_size_1023; /* ptc1023 */
1212 u64 tx_size_1522; /* ptc1522 */
1213 u64 tx_size_big; /* ptc9522 */
1214 u64 mac_short_pkt_dropped; /* mspdc */
1215 /* flow director stats */
1220 enum ice_sw_fwd_act_type {
1222 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1229 struct ice_aq_get_set_rss_lut_params {
1230 u16 vsi_handle; /* software VSI handle */
1231 u16 lut_size; /* size of the LUT buffer */
1232 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1233 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1234 u8 global_lut_id; /* only valid when lut_type is global */
1237 /* Checksum and Shadow RAM pointers */
1238 #define ICE_SR_NVM_CTRL_WORD 0x00
1239 #define ICE_SR_PHY_ANALOG_PTR 0x04
1240 #define ICE_SR_OPTION_ROM_PTR 0x05
1241 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1242 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1243 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1244 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1245 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1246 #define ICE_SR_PE_IMAGE_PTR 0x0C
1247 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1248 #define ICE_SR_MNG_CFG_PTR 0x0E
1249 #define ICE_SR_EMP_MODULE_PTR 0x0F
1250 #define ICE_SR_PBA_BLOCK_PTR 0x16
1251 #define ICE_SR_BOOT_CFG_PTR 0x132
1252 #define ICE_SR_NVM_WOL_CFG 0x19
1253 #define ICE_NVM_OROM_VER_OFF 0x02
1254 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1255 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1256 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1257 #define ICE_SR_NVM_MAP_VER 0x29
1258 #define ICE_SR_NVM_IMAGE_VER 0x2A
1259 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1260 #define ICE_SR_NVM_EETRACK_LO 0x2D
1261 #define ICE_SR_NVM_EETRACK_HI 0x2E
1262 #define ICE_NVM_VER_LO_SHIFT 0
1263 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1264 #define ICE_NVM_VER_HI_SHIFT 12
1265 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1266 #define ICE_OEM_EETRACK_ID 0xffffffff
1267 #define ICE_OROM_VER_PATCH_SHIFT 0
1268 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1269 #define ICE_OROM_VER_BUILD_SHIFT 8
1270 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1271 #define ICE_OROM_VER_SHIFT 24
1272 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1273 #define ICE_SR_VPD_PTR 0x2F
1274 #define ICE_SR_PXE_SETUP_PTR 0x30
1275 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1276 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1277 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1278 #define ICE_SR_VLAN_CFG_PTR 0x37
1279 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1280 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1281 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1282 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1283 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1284 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1285 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1286 #define ICE_SR_PFA_PTR 0x40
1287 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1288 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1289 #define ICE_SR_NVM_BANK_SIZE 0x43
1290 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1291 #define ICE_SR_OROM_BANK_SIZE 0x45
1292 #define ICE_SR_NETLIST_BANK_PTR 0x46
1293 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1294 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1295 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1296 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1297 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1298 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1300 /* CSS Header words */
1301 #define ICE_NVM_CSS_SREV_L 0x14
1302 #define ICE_NVM_CSS_SREV_H 0x15
1304 /* Length of CSS header section in words */
1305 #define ICE_CSS_HEADER_LENGTH 330
1307 /* Offset of Shadow RAM copy in the NVM bank area. */
1308 #define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32)
1310 /* Size in bytes of Option ROM trailer */
1311 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1313 /* The Link Topology Netlist section is stored as a series of words. It is
1314 * stored in the NVM as a TLV, with the first two words containing the type
1317 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1318 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1319 #define ICE_NETLIST_LEN_OFFSET 0x0001
1321 /* The Link Topology section follows the TLV header. When reading the netlist
1322 * using ice_read_netlist_module, we need to account for the 2-word TLV
1325 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1327 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1328 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1330 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1332 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1333 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1334 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1336 /* netlist ID block field offsets (word offsets) */
1337 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1338 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1339 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1340 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1341 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1342 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1343 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1344 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1345 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1346 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1348 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1349 #define ICE_SR_VPD_SIZE_WORDS 512
1350 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1351 #define ICE_SR_CTRL_WORD_1_S 0x06
1352 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1353 #define ICE_SR_CTRL_WORD_VALID 0x1
1354 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1355 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1356 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1358 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1360 /* Shadow RAM related */
1361 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1362 #define ICE_SR_BUF_ALIGNMENT 4096
1363 #define ICE_SR_WORDS_IN_1KB 512
1364 /* Checksum should be calculated such that after adding all the words,
1365 * including the checksum word itself, the sum should be 0xBABA.
1367 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1369 /* Link override related */
1370 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1371 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1372 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1373 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1374 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1375 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1376 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1377 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1379 #define ICE_PBA_FLAG_DFLT 0xFAFA
1380 /* Hash redirection LUT for VSI - maximum array size */
1381 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1384 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1385 * This is needed to determine the BAR0 space for the VFs
1387 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1388 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1389 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1391 /* AQ API version for LLDP_FILTER_CONTROL */
1392 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1393 #define ICE_FW_API_LLDP_FLTR_MIN 7
1394 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1396 /* AQ API version for report default configuration */
1397 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1398 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1399 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1400 #endif /* _ICE_TYPE_H_ */