1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
21 #define ICE_BYTES_PER_WORD 2
22 #define ICE_BYTES_PER_DWORD 4
23 #define ICE_MAX_TRAFFIC_CLASS 8
26 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
30 #define IS_ASCII(_ch) ((_ch) < 0x80)
33 #include "ice_status.h"
34 #include "ice_hw_autogen.h"
35 #include "ice_devids.h"
36 #include "ice_osdep.h"
37 #include "ice_bitops.h" /* Must come before ice_controlq.h */
38 #include "ice_controlq.h"
39 #include "ice_lan_tx_rx.h"
40 #include "ice_flex_type.h"
41 #include "ice_protocol_type.h"
43 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
45 return ice_is_bit_set(&bitmap, tc);
49 #define DIV_64BIT(n, d) ((n) / (d))
50 #endif /* DIV_64BIT */
52 static inline u64 round_up_64bit(u64 a, u32 b)
54 return DIV_64BIT(((a) + (b) / 2), (b));
57 static inline u32 ice_round_to_num(u32 N, u32 R)
59 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
60 ((((N) + (R) - 1) / (R)) * (R)));
63 /* Driver always calls main vsi_handle first */
64 #define ICE_MAIN_VSI_HANDLE 0
66 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
67 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
69 /* Data type manipulation macros. */
70 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
71 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
72 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
74 /* debug masks - set these bits in hw->debug_mask to control output */
75 #define ICE_DBG_INIT BIT_ULL(1)
76 #define ICE_DBG_RELEASE BIT_ULL(2)
77 #define ICE_DBG_FW_LOG BIT_ULL(3)
78 #define ICE_DBG_LINK BIT_ULL(4)
79 #define ICE_DBG_PHY BIT_ULL(5)
80 #define ICE_DBG_QCTX BIT_ULL(6)
81 #define ICE_DBG_NVM BIT_ULL(7)
82 #define ICE_DBG_LAN BIT_ULL(8)
83 #define ICE_DBG_FLOW BIT_ULL(9)
84 #define ICE_DBG_DCB BIT_ULL(10)
85 #define ICE_DBG_DIAG BIT_ULL(11)
86 #define ICE_DBG_FD BIT_ULL(12)
87 #define ICE_DBG_SW BIT_ULL(13)
88 #define ICE_DBG_SCHED BIT_ULL(14)
90 #define ICE_DBG_PKG BIT_ULL(16)
91 #define ICE_DBG_RES BIT_ULL(17)
92 #define ICE_DBG_AQ_MSG BIT_ULL(24)
93 #define ICE_DBG_AQ_DESC BIT_ULL(25)
94 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
95 #define ICE_DBG_AQ_CMD BIT_ULL(27)
96 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
98 ICE_DBG_AQ_DESC_BUF | \
101 #define ICE_DBG_USER BIT_ULL(31)
102 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
109 enum ice_aq_res_ids {
112 ICE_CHANGE_LOCK_RES_ID,
113 ICE_GLOBAL_CFG_LOCK_RES_ID
116 /* FW update timeout definitions are in milliseconds */
117 #define ICE_NVM_TIMEOUT 180000
118 #define ICE_CHANGE_LOCK_TIMEOUT 1000
119 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
121 enum ice_aq_res_access_type {
126 struct ice_driver_ver {
131 u8 driver_string[32];
143 enum ice_phy_cache_mode {
156 struct ice_phy_cache_mode_data {
158 enum ice_fec_mode curr_user_fec_req;
159 enum ice_fc_mode curr_user_fc_req;
160 u16 curr_user_speed_req;
164 enum ice_set_fc_aq_failures {
165 ICE_SET_FC_AQ_FAIL_NONE = 0,
166 ICE_SET_FC_AQ_FAIL_GET,
167 ICE_SET_FC_AQ_FAIL_SET,
168 ICE_SET_FC_AQ_FAIL_UPDATE
171 /* These are structs for managing the hardware information and the operations */
179 enum ice_media_type {
180 ICE_MEDIA_UNKNOWN = 0,
187 /* Software VSI types. */
190 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
193 #endif /* ADQ_SUPPORT */
196 struct ice_link_status {
197 /* Refer to ice_aq_phy_type for bits definition */
200 u8 topo_media_conflict;
204 u8 lse_ena; /* Link Status Event notification */
210 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
211 * ice_aqc_get_phy_caps structure
213 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
216 /* Different data queue types: These are mainly for SW consumption. */
225 /* Different reset sources for which a disable queue AQ call has to be made in
226 * order to clean the Tx scheduler as a part of the reset
228 enum ice_disq_rst_src {
233 /* PHY info such as phy_type, etc... */
234 struct ice_phy_info {
235 struct ice_link_status link_info;
236 struct ice_link_status link_info_old;
239 enum ice_media_type media_type;
241 /* Please refer to struct ice_aqc_get_link_status_data to get
242 * detail of enable bit in curr_user_speed_req
244 u16 curr_user_speed_req;
245 enum ice_fec_mode curr_user_fec_req;
246 enum ice_fc_mode curr_user_fc_req;
247 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
250 #define ICE_MAX_NUM_MIRROR_RULES 64
252 /* protocol enumeration for filters */
253 enum ice_fltr_ptype {
254 /* NONE - used for undef/error */
255 ICE_FLTR_PTYPE_NONF_NONE = 0,
256 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
257 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
258 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
259 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
260 ICE_FLTR_PTYPE_FRAG_IPV4,
261 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
262 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
263 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
264 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
268 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
269 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
271 struct ice_fd_hw_prof {
272 struct ice_flow_seg_info *fdir_seg;
274 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER];
275 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
278 /* Common HW capabilities for SW use */
279 struct ice_hw_common_caps {
280 /* Write CSR protection */
283 /* switching mode supported - EVB switching (including cloud) */
284 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
286 /* Manageablity mode & supported protocols over MCTP */
288 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
289 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
290 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
292 u32 mgmt_protocols_mctp;
293 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
294 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
295 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
296 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
300 /* DCB capabilities */
301 u32 active_tc_bitmap;
304 /* RSS related capabilities */
305 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
306 u32 rss_table_entry_width; /* RSS Entry width in bits */
309 u32 num_rxq; /* Number/Total Rx queues */
310 u32 rxq_first_id; /* First queue ID for Rx queues */
311 u32 num_txq; /* Number/Total Tx queues */
312 u32 txq_first_id; /* First queue ID for Tx queues */
315 u32 num_msix_vectors;
316 u32 msix_vector_first_id;
318 /* Max MTU for function or device */
322 u32 num_wol_proxy_fltr;
323 u32 wol_proxy_vsi_seid;
325 /* LED/SDP pin count */
329 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
330 #define ICE_MAX_SUPPORTED_GPIO_LED 12
331 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
332 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
333 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
335 /* EVB capabilities */
336 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
337 u8 evb_802_1_qbh; /* Bridge Port Extension */
343 /* WoL and APM support */
344 #define ICE_WOL_SUPPORT_M BIT(0)
345 #define ICE_ACPI_PROG_MTHD_M BIT(1)
346 #define ICE_PROXY_SUPPORT_M BIT(2)
353 /* Function specific capabilities */
354 struct ice_hw_func_caps {
355 struct ice_hw_common_caps common_cap;
357 u32 fd_fltr_guar; /* Number of filters guaranteed */
358 u32 fd_fltr_best_effort; /* Number of best effort filters */
361 /* Device wide capabilities */
362 struct ice_hw_dev_caps {
363 struct ice_hw_common_caps common_cap;
364 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
365 u32 num_flow_director_fltr; /* Number of FD filters available */
369 /* Information about MAC such as address, etc... */
370 struct ice_mac_info {
371 u8 lan_addr[ETH_ALEN];
372 u8 perm_addr[ETH_ALEN];
373 u8 port_addr[ETH_ALEN];
374 u8 wol_addr[ETH_ALEN];
381 ice_bus_embedded, /* Is device Embedded versus card */
386 enum ice_pcie_bus_speed {
387 ice_pcie_speed_unknown = 0xff,
388 ice_pcie_speed_2_5GT = 0x14,
389 ice_pcie_speed_5_0GT = 0x15,
390 ice_pcie_speed_8_0GT = 0x16,
391 ice_pcie_speed_16_0GT = 0x17
395 enum ice_pcie_link_width {
396 ice_pcie_lnk_width_resrv = 0x00,
397 ice_pcie_lnk_x1 = 0x01,
398 ice_pcie_lnk_x2 = 0x02,
399 ice_pcie_lnk_x4 = 0x04,
400 ice_pcie_lnk_x8 = 0x08,
401 ice_pcie_lnk_x12 = 0x0C,
402 ice_pcie_lnk_x16 = 0x10,
403 ice_pcie_lnk_x32 = 0x20,
404 ice_pcie_lnk_width_unknown = 0xff,
407 /* Reset types used to determine which kind of reset was requested. These
408 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
409 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
410 * because its reset source is different than the other types listed.
422 struct ice_bus_info {
423 enum ice_pcie_bus_speed speed;
424 enum ice_pcie_link_width width;
425 enum ice_bus_type type;
432 /* Flow control (FC) parameters */
434 enum ice_fc_mode current_mode; /* FC mode in effect */
435 enum ice_fc_mode req_mode; /* FC mode requested by caller */
438 /* NVM Information */
439 struct ice_nvm_info {
440 u32 eetrack; /* NVM data version */
441 u32 oem_ver; /* OEM version info */
442 u16 sr_words; /* Shadow RAM size in words */
443 u16 ver; /* NVM package version */
444 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
447 /* Max number of port to queue branches w.r.t topology */
448 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
450 #define ice_for_each_traffic_class(_i) \
451 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
453 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
454 * to driver defined policy for default aggregator
456 #define ICE_INVAL_TEID 0xFFFFFFFF
457 #define ICE_DFLT_AGG_ID 0
459 struct ice_sched_node {
460 struct ice_sched_node *parent;
461 struct ice_sched_node *sibling; /* next sibling in the same layer */
462 struct ice_sched_node **children;
463 struct ice_aqc_txsched_elem_data info;
464 u32 agg_id; /* aggregator group ID */
466 u8 in_use; /* suspended or in use */
467 u8 tx_sched_layer; /* Logical Layer (1-9) */
471 #define ICE_SCHED_NODE_OWNER_LAN 0
472 #define ICE_SCHED_NODE_OWNER_AE 1
473 #define ICE_SCHED_NODE_OWNER_RDMA 2
476 /* Access Macros for Tx Sched Elements data */
477 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
478 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
479 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
480 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
481 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
482 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
483 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
484 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
485 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
486 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
487 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
489 struct ice_sched_rl_profle {
490 u32 rate; /* In Kbps */
491 struct ice_aqc_rl_profile_elem info;
494 /* The aggregator type determines if identifier is for a VSI group,
495 * aggregator group, aggregator of queues, or queue group.
498 ICE_AGG_TYPE_UNKNOWN = 0,
500 ICE_AGG_TYPE_AGG, /* aggregator */
506 /* Rate limit types */
509 ICE_MIN_BW, /* for CIR profile */
510 ICE_MAX_BW, /* for EIR profile */
511 ICE_SHARED_BW /* for shared profile */
514 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
515 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
516 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
517 #define ICE_SCHED_NO_PRIORITY 0
518 #define ICE_SCHED_NO_BW_WT 0
519 #define ICE_SCHED_DFLT_RL_PROF_ID 0
520 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
521 #define ICE_SCHED_DFLT_BW_WT 1
522 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
523 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
525 /* Access Macros for Tx Sched RL Profile data */
526 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
527 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
528 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
529 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
530 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
533 /* The following tree example shows the naming conventions followed under
534 * ice_port_info struct for default scheduler tree topology.
538 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
542 * / |-> num_elements (range:1 - 9)
543 * * | implies num_of_layers
547 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
548 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
549 * need TEID of (a) to add queues.
552 * -> has 8 branches (one for each TC)
553 * -> First branch (TC0) has 4 elements
555 * -> (a) is the topmost layer node created by firmware on branch 0
557 * Note: Above asterisk tree covers only basic terminology and scenario.
558 * Refer to the documentation for more info.
561 /* Data structure for saving BW information */
569 ICE_BW_TYPE_CNT /* This must be last */
577 struct ice_bw_type_info {
578 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
580 struct ice_bw cir_bw;
581 struct ice_bw eir_bw;
585 /* VSI queue context structure for given TC */
589 /* bw_t_info saves queue BW information */
590 struct ice_bw_type_info bw_t_info;
593 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
594 struct ice_sched_vsi_info {
595 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
596 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
597 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
598 /* bw_t_info saves VSI BW information */
599 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
602 /* CEE or IEEE 802.1Qaz ETS Configuration data */
603 struct ice_dcb_ets_cfg {
607 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
608 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
609 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
612 /* CEE or IEEE 802.1Qaz PFC Configuration data */
613 struct ice_dcb_pfc_cfg {
620 /* CEE or IEEE 802.1Qaz Application Priority data */
621 struct ice_dcb_app_priority_table {
627 #define ICE_MAX_USER_PRIORITY 8
628 #define ICE_DCBX_MAX_APPS 32
629 #define ICE_LLDPDU_SIZE 1500
630 #define ICE_TLV_STATUS_OPER 0x1
631 #define ICE_TLV_STATUS_SYNC 0x2
632 #define ICE_TLV_STATUS_ERR 0x4
633 #define ICE_APP_PROT_ID_FCOE 0x8906
634 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
635 #define ICE_APP_PROT_ID_FIP 0x8914
636 #define ICE_APP_SEL_ETHTYPE 0x1
637 #define ICE_APP_SEL_TCPIP 0x2
638 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
639 #define ICE_CEE_APP_SEL_TCPIP 0x1
641 struct ice_dcbx_cfg {
643 u32 tlv_status; /* CEE mode TLV status */
644 struct ice_dcb_ets_cfg etscfg;
645 struct ice_dcb_ets_cfg etsrec;
646 struct ice_dcb_pfc_cfg pfc;
647 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
649 #define ICE_DCBX_MODE_CEE 0x1
650 #define ICE_DCBX_MODE_IEEE 0x2
652 #define ICE_DCBX_APPS_NON_WILLING 0x1
655 struct ice_port_info {
656 struct ice_sched_node *root; /* Root Node per Port */
657 struct ice_hw *hw; /* back pointer to HW instance */
658 u32 last_node_teid; /* scheduler last node info */
659 u16 sw_id; /* Initial switch ID belongs to port */
662 #define ICE_SCHED_PORT_STATE_INIT 0x0
663 #define ICE_SCHED_PORT_STATE_READY 0x1
665 #define ICE_LPORT_MASK 0xff
666 u16 dflt_tx_vsi_rule_id;
668 u16 dflt_rx_vsi_rule_id;
670 struct ice_fc_info fc;
671 struct ice_mac_info mac;
672 struct ice_phy_info phy;
673 struct ice_lock sched_lock; /* protect access to TXSched tree */
674 struct ice_sched_node *
675 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
676 /* List contain profile ID(s) and other params per layer */
677 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
678 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
680 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
681 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
682 /* LLDP/DCBX Status */
683 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
688 struct ice_switch_info {
689 struct LIST_HEAD_TYPE vsi_list_map_head;
690 struct ice_sw_recipe *recp_list;
693 /* FW logging configuration */
694 struct ice_fw_log_evnt {
695 u8 cfg : 4; /* New event enables to configure */
696 u8 cur : 4; /* Current/active event enables */
699 struct ice_fw_log_cfg {
700 u8 cq_en : 1; /* FW logging is enabled via the control queue */
701 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
702 u8 actv_evnts; /* Cumulation of currently enabled log events */
704 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
705 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
706 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
707 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
708 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
711 /* Port hardware description */
715 struct ice_aqc_layer_props *layer_info;
716 struct ice_port_info *port_info;
717 /* 2D Array for each Tx Sched RL Profile type */
718 struct ice_sched_rl_profile **cir_profiles;
719 struct ice_sched_rl_profile **eir_profiles;
720 struct ice_sched_rl_profile **srl_profiles;
721 u64 debug_mask; /* BITMAP for debug mask */
722 enum ice_mac_type mac_type;
724 u16 fd_ctr_base; /* FD counter base index */
728 u16 subsystem_device_id;
729 u16 subsystem_vendor_id;
732 u8 pf_id; /* device profile info */
734 u16 max_burst_size; /* driver sets this value */
736 /* Tx Scheduler values */
737 u16 num_tx_sched_layers;
738 u16 num_tx_sched_phys_layers;
741 u8 sw_entry_point_layer;
742 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
743 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
744 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
745 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
746 u8 evb_veb; /* true for VEB, false for VEPA */
747 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
748 struct ice_bus_info bus;
749 struct ice_nvm_info nvm;
750 struct ice_hw_dev_caps dev_caps; /* device capabilities */
751 struct ice_hw_func_caps func_caps; /* function capabilities */
753 struct ice_switch_info *switch_info; /* switch filter lists */
755 /* Control Queue info */
756 struct ice_ctl_q_info adminq;
757 struct ice_ctl_q_info mailboxq;
759 u8 api_branch; /* API branch version */
760 u8 api_maj_ver; /* API major version */
761 u8 api_min_ver; /* API minor version */
762 u8 api_patch; /* API patch version */
763 u8 fw_branch; /* firmware branch version */
764 u8 fw_maj_ver; /* firmware major version */
765 u8 fw_min_ver; /* firmware minor version */
766 u8 fw_patch; /* firmware patch version */
767 u32 fw_build; /* firmware build number */
769 struct ice_fw_log_cfg fw_log;
771 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
772 * register. Used for determining the itr/intrl granularity during
775 #define ICE_MAX_AGG_BW_200G 0x0
776 #define ICE_MAX_AGG_BW_100G 0X1
777 #define ICE_MAX_AGG_BW_50G 0x2
778 #define ICE_MAX_AGG_BW_25G 0x3
779 /* ITR granularity for different speeds */
780 #define ICE_ITR_GRAN_ABOVE_25 2
781 #define ICE_ITR_GRAN_MAX_25 4
782 /* ITR granularity in 1 us */
784 /* INTRL granularity for different speeds */
785 #define ICE_INTRL_GRAN_ABOVE_25 4
786 #define ICE_INTRL_GRAN_MAX_25 8
787 /* INTRL granularity in 1 us */
790 u8 ucast_shared; /* true if VSIs can share unicast addr */
792 /* Active package version (currently active) */
793 struct ice_pkg_ver active_pkg_ver;
794 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
796 /* Driver's package ver - (from the Metadata seg) */
797 struct ice_pkg_ver pkg_ver;
798 u8 pkg_name[ICE_PKG_NAME_SIZE];
800 /* Driver's Ice package version (from the Ice seg) */
801 struct ice_pkg_ver ice_pkg_ver;
802 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
804 /* Pointer to the ice segment */
807 /* Pointer to allocated copy of pkg memory */
812 struct ice_tunnel_table tnl;
814 #define ICE_PKG_FILENAME "package_file"
815 #define ICE_PKG_FILENAME_EXT "pkg"
816 #define ICE_PKG_FILE_MAJ_VER 1
817 #define ICE_PKG_FILE_MIN_VER 0
819 /* HW block tables */
820 struct ice_blk_info blk[ICE_BLK_COUNT];
821 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
822 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
823 /* Flow Director filter info */
824 int fdir_active_fltr;
826 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
827 struct LIST_HEAD_TYPE fdir_list_head;
829 /* Book-keeping of side-band filter count per flow-type.
830 * This is used to detect and handle input set changes for
831 * respective flow-type.
833 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
835 struct ice_fd_hw_prof **fdir_prof;
836 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
837 struct ice_lock rss_locks; /* protect RSS configuration */
838 struct LIST_HEAD_TYPE rss_list_head;
841 /* Statistics collected by each port, VSI, VEB, and S-channel */
842 struct ice_eth_stats {
843 u64 rx_bytes; /* gorc */
844 u64 rx_unicast; /* uprc */
845 u64 rx_multicast; /* mprc */
846 u64 rx_broadcast; /* bprc */
847 u64 rx_discards; /* rdpc */
848 u64 rx_unknown_protocol; /* rupp */
849 u64 tx_bytes; /* gotc */
850 u64 tx_unicast; /* uptc */
851 u64 tx_multicast; /* mptc */
852 u64 tx_broadcast; /* bptc */
853 u64 tx_discards; /* tdpc */
854 u64 tx_errors; /* tepc */
859 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
860 struct ice_veb_up_stats {
861 u64 up_rx_pkts[ICE_MAX_UP];
862 u64 up_rx_bytes[ICE_MAX_UP];
863 u64 up_tx_pkts[ICE_MAX_UP];
864 u64 up_tx_bytes[ICE_MAX_UP];
867 /* Statistics collected by the MAC */
868 struct ice_hw_port_stats {
869 /* eth stats collected by the port */
870 struct ice_eth_stats eth;
871 /* additional port specific stats */
872 u64 tx_dropped_link_down; /* tdold */
873 u64 crc_errors; /* crcerrs */
874 u64 illegal_bytes; /* illerrc */
875 u64 error_bytes; /* errbc */
876 u64 mac_local_faults; /* mlfc */
877 u64 mac_remote_faults; /* mrfc */
878 u64 rx_len_errors; /* rlec */
879 u64 link_xon_rx; /* lxonrxc */
880 u64 link_xoff_rx; /* lxoffrxc */
881 u64 link_xon_tx; /* lxontxc */
882 u64 link_xoff_tx; /* lxofftxc */
883 u64 priority_xon_rx[8]; /* pxonrxc[8] */
884 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
885 u64 priority_xon_tx[8]; /* pxontxc[8] */
886 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
887 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
888 u64 rx_size_64; /* prc64 */
889 u64 rx_size_127; /* prc127 */
890 u64 rx_size_255; /* prc255 */
891 u64 rx_size_511; /* prc511 */
892 u64 rx_size_1023; /* prc1023 */
893 u64 rx_size_1522; /* prc1522 */
894 u64 rx_size_big; /* prc9522 */
895 u64 rx_undersize; /* ruc */
896 u64 rx_fragments; /* rfc */
897 u64 rx_oversize; /* roc */
898 u64 rx_jabber; /* rjc */
899 u64 tx_size_64; /* ptc64 */
900 u64 tx_size_127; /* ptc127 */
901 u64 tx_size_255; /* ptc255 */
902 u64 tx_size_511; /* ptc511 */
903 u64 tx_size_1023; /* ptc1023 */
904 u64 tx_size_1522; /* ptc1522 */
905 u64 tx_size_big; /* ptc9522 */
906 u64 mac_short_pkt_dropped; /* mspdc */
907 /* flow director stats */
912 #endif /* ADQ_SUPPORT */
915 enum ice_sw_fwd_act_type {
917 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
924 /* Checksum and Shadow RAM pointers */
925 #define ICE_SR_NVM_CTRL_WORD 0x00
926 #define ICE_SR_PHY_ANALOG_PTR 0x04
927 #define ICE_SR_OPTION_ROM_PTR 0x05
928 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
929 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
930 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
931 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
932 #define ICE_SR_EMP_IMAGE_PTR 0x0B
933 #define ICE_SR_PE_IMAGE_PTR 0x0C
934 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
935 #define ICE_SR_MNG_CFG_PTR 0x0E
936 #define ICE_SR_EMP_MODULE_PTR 0x0F
937 #define ICE_SR_PBA_FLAGS 0x15
938 #define ICE_SR_PBA_BLOCK_PTR 0x16
939 #define ICE_SR_BOOT_CFG_PTR 0x17
940 #define ICE_SR_NVM_WOL_CFG 0x19
941 #define ICE_NVM_OEM_VER_OFF 0x83
942 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
943 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
944 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
945 #define ICE_SR_NVM_MAP_VER 0x29
946 #define ICE_SR_NVM_IMAGE_VER 0x2A
947 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
948 #define ICE_SR_NVM_EETRACK_LO 0x2D
949 #define ICE_SR_NVM_EETRACK_HI 0x2E
950 #define ICE_NVM_VER_LO_SHIFT 0
951 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
952 #define ICE_NVM_VER_HI_SHIFT 12
953 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
954 #define ICE_OEM_EETRACK_ID 0xffffffff
955 #define ICE_OEM_VER_PATCH_SHIFT 0
956 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
957 #define ICE_OEM_VER_BUILD_SHIFT 8
958 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
959 #define ICE_OEM_VER_SHIFT 24
960 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
961 #define ICE_SR_VPD_PTR 0x2F
962 #define ICE_SR_PXE_SETUP_PTR 0x30
963 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
964 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
965 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
966 #define ICE_SR_VLAN_CFG_PTR 0x37
967 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
968 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
969 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
970 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
971 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
972 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
973 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
974 #define ICE_SR_PFA_PTR 0x40
975 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
976 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
977 #define ICE_SR_NVM_BANK_SIZE 0x43
978 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
979 #define ICE_SR_OROM_BANK_SIZE 0x45
980 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
981 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
982 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
984 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
985 #define ICE_SR_VPD_SIZE_WORDS 512
986 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
987 #define ICE_SR_CTRL_WORD_1_S 0x06
988 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
990 /* Shadow RAM related */
991 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
992 #define ICE_SR_BUF_ALIGNMENT 4096
993 #define ICE_SR_WORDS_IN_1KB 512
994 /* Checksum should be calculated such that after adding all the words,
995 * including the checksum word itself, the sum should be 0xBABA.
997 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
999 #define ICE_PBA_FLAG_DFLT 0xFAFA
1000 /* Hash redirection LUT for VSI - maximum array size */
1001 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1004 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1005 * This is needed to determine the BAR0 space for the VFs
1007 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1008 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1009 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1011 #endif /* _ICE_TYPE_H_ */