drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  72 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  73 #define ICE_MAX_RES_DESC_NUM        1024
  74
  75 static int ice_dev_configure(struct rte_eth_dev *dev);
  76 static int ice_dev_start(struct rte_eth_dev *dev);
  77 static int ice_dev_stop(struct rte_eth_dev *dev);
  78 static int ice_dev_close(struct rte_eth_dev *dev);
  79 static int ice_dev_reset(struct rte_eth_dev *dev);
  80 static int ice_dev_info_get(struct rte_eth_dev *dev,
  81                             struct rte_eth_dev_info *dev_info);
  82 static int ice_link_update(struct rte_eth_dev *dev,
  83                            int wait_to_complete);
  84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  86
  87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  90                                struct rte_eth_rss_reta_entry64 *reta_conf,
  91                                uint16_t reta_size);
  92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  93                               struct rte_eth_rss_reta_entry64 *reta_conf,
  94                               uint16_t reta_size);
  95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  96                                struct rte_eth_rss_conf *rss_conf);
  97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  98                                  struct rte_eth_rss_conf *rss_conf);
  99 static int ice_promisc_enable(struct rte_eth_dev *dev);
 100 static int ice_promisc_disable(struct rte_eth_dev *dev);
 101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 104                                uint16_t vlan_id,
 105                                int on);
 106 static int ice_macaddr_set(struct rte_eth_dev *dev,
 107                            struct rte_ether_addr *mac_addr);
 108 static int ice_macaddr_add(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr,
 110                            __rte_unused uint32_t index,
 111                            uint32_t pool);
 112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 114                                     uint16_t queue_id);
 115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 116                                      uint16_t queue_id);
 117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 118                               size_t fw_size);
 119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 120                              uint16_t pvid, int on);
 121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 122 static int ice_get_eeprom(struct rte_eth_dev *dev,
 123                           struct rte_dev_eeprom_info *eeprom);
 124 static int ice_stats_get(struct rte_eth_dev *dev,
 125                          struct rte_eth_stats *stats);
 126 static int ice_stats_reset(struct rte_eth_dev *dev);
 127 static int ice_xstats_get(struct rte_eth_dev *dev,
 128                           struct rte_eth_xstat *xstats, unsigned int n);
 129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 130                                 struct rte_eth_xstat_name *xstats_names,
 131                                 unsigned int limit);
 132 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
 133                                 const struct rte_flow_ops **ops);
 134 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 135                         struct rte_eth_udp_tunnel *udp_tunnel);
 136 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 137                         struct rte_eth_udp_tunnel *udp_tunnel);
 138
 139 static const struct rte_pci_id pci_id_ice_map[] = {
 140         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 141         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 142         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 143         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 165         { .vendor_id = 0, /* sentinel */ },
 166 };
 167
 168 static const struct eth_dev_ops ice_eth_dev_ops = {
 169         .dev_configure                = ice_dev_configure,
 170         .dev_start                    = ice_dev_start,
 171         .dev_stop                     = ice_dev_stop,
 172         .dev_close                    = ice_dev_close,
 173         .dev_reset                    = ice_dev_reset,
 174         .dev_set_link_up              = ice_dev_set_link_up,
 175         .dev_set_link_down            = ice_dev_set_link_down,
 176         .rx_queue_start               = ice_rx_queue_start,
 177         .rx_queue_stop                = ice_rx_queue_stop,
 178         .tx_queue_start               = ice_tx_queue_start,
 179         .tx_queue_stop                = ice_tx_queue_stop,
 180         .rx_queue_setup               = ice_rx_queue_setup,
 181         .rx_queue_release             = ice_rx_queue_release,
 182         .tx_queue_setup               = ice_tx_queue_setup,
 183         .tx_queue_release             = ice_tx_queue_release,
 184         .dev_infos_get                = ice_dev_info_get,
 185         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 186         .link_update                  = ice_link_update,
 187         .mtu_set                      = ice_mtu_set,
 188         .mac_addr_set                 = ice_macaddr_set,
 189         .mac_addr_add                 = ice_macaddr_add,
 190         .mac_addr_remove              = ice_macaddr_remove,
 191         .vlan_filter_set              = ice_vlan_filter_set,
 192         .vlan_offload_set             = ice_vlan_offload_set,
 193         .reta_update                  = ice_rss_reta_update,
 194         .reta_query                   = ice_rss_reta_query,
 195         .rss_hash_update              = ice_rss_hash_update,
 196         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 197         .promiscuous_enable           = ice_promisc_enable,
 198         .promiscuous_disable          = ice_promisc_disable,
 199         .allmulticast_enable          = ice_allmulti_enable,
 200         .allmulticast_disable         = ice_allmulti_disable,
 201         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 202         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 203         .fw_version_get               = ice_fw_version_get,
 204         .vlan_pvid_set                = ice_vlan_pvid_set,
 205         .rxq_info_get                 = ice_rxq_info_get,
 206         .txq_info_get                 = ice_txq_info_get,
 207         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 208         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 209         .get_eeprom_length            = ice_get_eeprom_length,
 210         .get_eeprom                   = ice_get_eeprom,
 211         .stats_get                    = ice_stats_get,
 212         .stats_reset                  = ice_stats_reset,
 213         .xstats_get                   = ice_xstats_get,
 214         .xstats_get_names             = ice_xstats_get_names,
 215         .xstats_reset                 = ice_stats_reset,
 216         .flow_ops_get                 = ice_dev_flow_ops_get,
 217         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 218         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 219         .tx_done_cleanup              = ice_tx_done_cleanup,
 220         .get_monitor_addr             = ice_get_monitor_addr,
 221 };
 222
 223 /* store statistics names and its offset in stats structure */
 224 struct ice_xstats_name_off {
 225         char name[RTE_ETH_XSTATS_NAME_SIZE];
 226         unsigned int offset;
 227 };
 228
 229 static const struct ice_xstats_name_off ice_stats_strings[] = {
 230         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 231         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 232         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 233         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 234         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 235                 rx_unknown_protocol)},
 236         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 237         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 238         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 239         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 240 };
 241
 242 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 243                 sizeof(ice_stats_strings[0]))
 244
 245 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 246         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 247                 tx_dropped_link_down)},
 248         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 249         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 250                 illegal_bytes)},
 251         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 252         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 253                 mac_local_faults)},
 254         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 255                 mac_remote_faults)},
 256         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 257                 rx_len_errors)},
 258         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 259         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 260         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 261         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 262         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 263         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_127)},
 265         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_255)},
 267         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_511)},
 269         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_1023)},
 271         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_1522)},
 273         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_big)},
 275         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 276                 rx_undersize)},
 277         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_oversize)},
 279         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 280                 mac_short_pkt_dropped)},
 281         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_fragments)},
 283         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 284         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 285         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_127)},
 287         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_255)},
 289         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_511)},
 291         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_1023)},
 293         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_1522)},
 295         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_big)},
 297 };
 298
 299 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 300                 sizeof(ice_hw_port_strings[0]))
 301
 302 static void
 303 ice_init_controlq_parameter(struct ice_hw *hw)
 304 {
 305         /* fields for adminq */
 306         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 307         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 308         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 309         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 310
 311         /* fields for mailboxq, DPDK used as PF host */
 312         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 313         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 314         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 315         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 316 }
 317
 318 static int
 319 lookup_proto_xtr_type(const char *xtr_name)
 320 {
 321         static struct {
 322                 const char *name;
 323                 enum proto_xtr_type type;
 324         } xtr_type_map[] = {
 325                 { "vlan",      PROTO_XTR_VLAN      },
 326                 { "ipv4",      PROTO_XTR_IPV4      },
 327                 { "ipv6",      PROTO_XTR_IPV6      },
 328                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 329                 { "tcp",       PROTO_XTR_TCP       },
 330                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 331         };
 332         uint32_t i;
 333
 334         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 335                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 336                         return xtr_type_map[i].type;
 337         }
 338
 339         return -1;
 340 }
 341
 342 /*
 343  * Parse elem, the elem could be single number/range or '(' ')' group
 344  * 1) A single number elem, it's just a simple digit. e.g. 9
 345  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 346  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 347  *    Within group elem, '-' used for a range separator;
 348  *                       ',' used for a single number.
 349  */
 350 static int
 351 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 352 {
 353         const char *str = input;
 354         char *end = NULL;
 355         uint32_t min, max;
 356         uint32_t idx;
 357
 358         while (isblank(*str))
 359                 str++;
 360
 361         if (!isdigit(*str) && *str != '(')
 362                 return -1;
 363
 364         /* process single number or single range of number */
 365         if (*str != '(') {
 366                 errno = 0;
 367                 idx = strtoul(str, &end, 10);
 368                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 369                         return -1;
 370
 371                 while (isblank(*end))
 372                         end++;
 373
 374                 min = idx;
 375                 max = idx;
 376
 377                 /* process single <number>-<number> */
 378                 if (*end == '-') {
 379                         end++;
 380                         while (isblank(*end))
 381                                 end++;
 382                         if (!isdigit(*end))
 383                                 return -1;
 384
 385                         errno = 0;
 386                         idx = strtoul(end, &end, 10);
 387                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 388                                 return -1;
 389
 390                         max = idx;
 391                         while (isblank(*end))
 392                                 end++;
 393                 }
 394
 395                 if (*end != ':')
 396                         return -1;
 397
 398                 for (idx = RTE_MIN(min, max);
 399                      idx <= RTE_MAX(min, max); idx++)
 400                         devargs->proto_xtr[idx] = xtr_type;
 401
 402                 return 0;
 403         }
 404
 405         /* process set within bracket */
 406         str++;
 407         while (isblank(*str))
 408                 str++;
 409         if (*str == '\0')
 410                 return -1;
 411
 412         min = ICE_MAX_QUEUE_NUM;
 413         do {
 414                 /* go ahead to the first digit */
 415                 while (isblank(*str))
 416                         str++;
 417                 if (!isdigit(*str))
 418                         return -1;
 419
 420                 /* get the digit value */
 421                 errno = 0;
 422                 idx = strtoul(str, &end, 10);
 423                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 424                         return -1;
 425
 426                 /* go ahead to separator '-',',' and ')' */
 427                 while (isblank(*end))
 428                         end++;
 429                 if (*end == '-') {
 430                         if (min == ICE_MAX_QUEUE_NUM)
 431                                 min = idx;
 432                         else /* avoid continuous '-' */
 433                                 return -1;
 434                 } else if (*end == ',' || *end == ')') {
 435                         max = idx;
 436                         if (min == ICE_MAX_QUEUE_NUM)
 437                                 min = idx;
 438
 439                         for (idx = RTE_MIN(min, max);
 440                              idx <= RTE_MAX(min, max); idx++)
 441                                 devargs->proto_xtr[idx] = xtr_type;
 442
 443                         min = ICE_MAX_QUEUE_NUM;
 444                 } else {
 445                         return -1;
 446                 }
 447
 448                 str = end + 1;
 449         } while (*end != ')' && *end != '\0');
 450
 451         return 0;
 452 }
 453
 454 static int
 455 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 456 {
 457         const char *queue_start;
 458         uint32_t idx;
 459         int xtr_type;
 460         char xtr_name[32];
 461
 462         while (isblank(*queues))
 463                 queues++;
 464
 465         if (*queues != '[') {
 466                 xtr_type = lookup_proto_xtr_type(queues);
 467                 if (xtr_type < 0)
 468                         return -1;
 469
 470                 devargs->proto_xtr_dflt = xtr_type;
 471
 472                 return 0;
 473         }
 474
 475         queues++;
 476         do {
 477                 while (isblank(*queues))
 478                         queues++;
 479                 if (*queues == '\0')
 480                         return -1;
 481
 482                 queue_start = queues;
 483
 484                 /* go across a complete bracket */
 485                 if (*queue_start == '(') {
 486                         queues += strcspn(queues, ")");
 487                         if (*queues != ')')
 488                                 return -1;
 489                 }
 490
 491                 /* scan the separator ':' */
 492                 queues += strcspn(queues, ":");
 493                 if (*queues++ != ':')
 494                         return -1;
 495                 while (isblank(*queues))
 496                         queues++;
 497
 498                 for (idx = 0; ; idx++) {
 499                         if (isblank(queues[idx]) ||
 500                             queues[idx] == ',' ||
 501                             queues[idx] == ']' ||
 502                             queues[idx] == '\0')
 503                                 break;
 504
 505                         if (idx > sizeof(xtr_name) - 2)
 506                                 return -1;
 507
 508                         xtr_name[idx] = queues[idx];
 509                 }
 510                 xtr_name[idx] = '\0';
 511                 xtr_type = lookup_proto_xtr_type(xtr_name);
 512                 if (xtr_type < 0)
 513                         return -1;
 514
 515                 queues += idx;
 516
 517                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 518                         queues++;
 519
 520                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 521                         return -1;
 522         } while (*queues != '\0');
 523
 524         return 0;
 525 }
 526
 527 static int
 528 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 529                      void *extra_args)
 530 {
 531         struct ice_devargs *devargs = extra_args;
 532
 533         if (value == NULL || extra_args == NULL)
 534                 return -EINVAL;
 535
 536         if (parse_queue_proto_xtr(value, devargs) < 0) {
 537                 PMD_DRV_LOG(ERR,
 538                             "The protocol extraction parameter is wrong : '%s'",
 539                             value);
 540                 return -1;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static void
 547 ice_check_proto_xtr_support(struct ice_hw *hw)
 548 {
 549 #define FLX_REG(val, fld, idx) \
 550         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 551          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 552         static struct {
 553                 uint32_t rxdid;
 554                 uint8_t opcode;
 555                 uint8_t protid_0;
 556                 uint8_t protid_1;
 557         } xtr_sets[] = {
 558                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 559                                      ICE_RX_OPC_EXTRACT,
 560                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 561                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 562                                      ICE_RX_OPC_EXTRACT,
 563                                      ICE_PROT_IPV4_OF_OR_S,
 564                                      ICE_PROT_IPV4_OF_OR_S },
 565                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 566                                      ICE_RX_OPC_EXTRACT,
 567                                      ICE_PROT_IPV6_OF_OR_S,
 568                                      ICE_PROT_IPV6_OF_OR_S },
 569                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 570                                           ICE_RX_OPC_EXTRACT,
 571                                           ICE_PROT_IPV6_OF_OR_S,
 572                                           ICE_PROT_IPV6_OF_OR_S },
 573                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 574                                     ICE_RX_OPC_EXTRACT,
 575                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 576                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 577                                           ICE_RX_OPC_PROTID,
 578                                           ICE_PROT_IPV4_OF_OR_S,
 579                                           ICE_PROT_IPV6_OF_OR_S },
 580         };
 581         uint32_t i;
 582
 583         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 584                 uint32_t rxdid = xtr_sets[i].rxdid;
 585                 uint32_t v;
 586
 587                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 588                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 589
 590                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 591                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 592                                 ice_proto_xtr_hw_support[i] = true;
 593                 }
 594
 595                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 596                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 597
 598                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 599                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 600                                 ice_proto_xtr_hw_support[i] = true;
 601                 }
 602         }
 603 }
 604
 605 static int
 606 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 607                   uint32_t num)
 608 {
 609         struct pool_entry *entry;
 610
 611         if (!pool || !num)
 612                 return -EINVAL;
 613
 614         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 615         if (!entry) {
 616                 PMD_INIT_LOG(ERR,
 617                              "Failed to allocate memory for resource pool");
 618                 return -ENOMEM;
 619         }
 620
 621         /* queue heap initialize */
 622         pool->num_free = num;
 623         pool->num_alloc = 0;
 624         pool->base = base;
 625         LIST_INIT(&pool->alloc_list);
 626         LIST_INIT(&pool->free_list);
 627
 628         /* Initialize element  */
 629         entry->base = 0;
 630         entry->len = num;
 631
 632         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 633         return 0;
 634 }
 635
 636 static int
 637 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 638                    uint16_t num)
 639 {
 640         struct pool_entry *entry, *valid_entry;
 641
 642         if (!pool || !num) {
 643                 PMD_INIT_LOG(ERR, "Invalid parameter");
 644                 return -EINVAL;
 645         }
 646
 647         if (pool->num_free < num) {
 648                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 649                              num, pool->num_free);
 650                 return -ENOMEM;
 651         }
 652
 653         valid_entry = NULL;
 654         /* Lookup  in free list and find most fit one */
 655         LIST_FOREACH(entry, &pool->free_list, next) {
 656                 if (entry->len >= num) {
 657                         /* Find best one */
 658                         if (entry->len == num) {
 659                                 valid_entry = entry;
 660                                 break;
 661                         }
 662                         if (!valid_entry ||
 663                             valid_entry->len > entry->len)
 664                                 valid_entry = entry;
 665                 }
 666         }
 667
 668         /* Not find one to satisfy the request, return */
 669         if (!valid_entry) {
 670                 PMD_INIT_LOG(ERR, "No valid entry found");
 671                 return -ENOMEM;
 672         }
 673         /**
 674          * The entry have equal queue number as requested,
 675          * remove it from alloc_list.
 676          */
 677         if (valid_entry->len == num) {
 678                 LIST_REMOVE(valid_entry, next);
 679         } else {
 680                 /**
 681                  * The entry have more numbers than requested,
 682                  * create a new entry for alloc_list and minus its
 683                  * queue base and number in free_list.
 684                  */
 685                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 686                 if (!entry) {
 687                         PMD_INIT_LOG(ERR,
 688                                      "Failed to allocate memory for "
 689                                      "resource pool");
 690                         return -ENOMEM;
 691                 }
 692                 entry->base = valid_entry->base;
 693                 entry->len = num;
 694                 valid_entry->base += num;
 695                 valid_entry->len -= num;
 696                 valid_entry = entry;
 697         }
 698
 699         /* Insert it into alloc list, not sorted */
 700         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 701
 702         pool->num_free -= valid_entry->len;
 703         pool->num_alloc += valid_entry->len;
 704
 705         return valid_entry->base + pool->base;
 706 }
 707
 708 static void
 709 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 710 {
 711         struct pool_entry *entry, *next_entry;
 712
 713         if (!pool)
 714                 return;
 715
 716         for (entry = LIST_FIRST(&pool->alloc_list);
 717              entry && (next_entry = LIST_NEXT(entry, next), 1);
 718              entry = next_entry) {
 719                 LIST_REMOVE(entry, next);
 720                 rte_free(entry);
 721         }
 722
 723         for (entry = LIST_FIRST(&pool->free_list);
 724              entry && (next_entry = LIST_NEXT(entry, next), 1);
 725              entry = next_entry) {
 726                 LIST_REMOVE(entry, next);
 727                 rte_free(entry);
 728         }
 729
 730         pool->num_free = 0;
 731         pool->num_alloc = 0;
 732         pool->base = 0;
 733         LIST_INIT(&pool->alloc_list);
 734         LIST_INIT(&pool->free_list);
 735 }
 736
 737 static void
 738 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 739 {
 740         /* Set VSI LUT selection */
 741         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 742                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 743         /* Set Hash scheme */
 744         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 745                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 746         /* enable TC */
 747         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 748 }
 749
 750 static enum ice_status
 751 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 752                                 struct ice_aqc_vsi_props *info,
 753                                 uint8_t enabled_tcmap)
 754 {
 755         uint16_t bsf, qp_idx;
 756
 757         /* default tc 0 now. Multi-TC supporting need to be done later.
 758          * Configure TC and queue mapping parameters, for enabled TC,
 759          * allocate qpnum_per_tc queues to this traffic.
 760          */
 761         if (enabled_tcmap != 0x01) {
 762                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 763                 return -ENOTSUP;
 764         }
 765
 766         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 767         bsf = rte_bsf32(vsi->nb_qps);
 768         /* Adjust the queue number to actual queues that can be applied */
 769         vsi->nb_qps = 0x1 << bsf;
 770
 771         qp_idx = 0;
 772         /* Set tc and queue mapping with VSI */
 773         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 774                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 775                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 776
 777         /* Associate queue number with VSI */
 778         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 779         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 780         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 781         info->valid_sections |=
 782                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 783         /* Set the info.ingress_table and info.egress_table
 784          * for UP translate table. Now just set it to 1:1 map by default
 785          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 786          */
 787 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 788         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 789         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 790         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 791         return 0;
 792 }
 793
 794 static int
 795 ice_init_mac_address(struct rte_eth_dev *dev)
 796 {
 797         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         if (!rte_is_unicast_ether_addr
 800                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 801                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 802                 return -EINVAL;
 803         }
 804
 805         rte_ether_addr_copy(
 806                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 807                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 808
 809         dev->data->mac_addrs =
 810                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
 811         if (!dev->data->mac_addrs) {
 812                 PMD_INIT_LOG(ERR,
 813                              "Failed to allocate memory to store mac address");
 814                 return -ENOMEM;
 815         }
 816         /* store it to dev data */
 817         rte_ether_addr_copy(
 818                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 819                 &dev->data->mac_addrs[0]);
 820         return 0;
 821 }
 822
 823 /* Find out specific MAC filter */
 824 static struct ice_mac_filter *
 825 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 826 {
 827         struct ice_mac_filter *f;
 828
 829         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 830                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 831                         return f;
 832         }
 833
 834         return NULL;
 835 }
 836
 837 static int
 838 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 839 {
 840         struct ice_fltr_list_entry *m_list_itr = NULL;
 841         struct ice_mac_filter *f;
 842         struct LIST_HEAD_TYPE list_head;
 843         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 844         int ret = 0;
 845
 846         /* If it's added and configured, return */
 847         f = ice_find_mac_filter(vsi, mac_addr);
 848         if (f) {
 849                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 850                 return 0;
 851         }
 852
 853         INIT_LIST_HEAD(&list_head);
 854
 855         m_list_itr = (struct ice_fltr_list_entry *)
 856                 ice_malloc(hw, sizeof(*m_list_itr));
 857         if (!m_list_itr) {
 858                 ret = -ENOMEM;
 859                 goto DONE;
 860         }
 861         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 862                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 863         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 864         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 865         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 866         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 867         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 868
 869         LIST_ADD(&m_list_itr->list_entry, &list_head);
 870
 871         /* Add the mac */
 872         ret = ice_add_mac(hw, &list_head);
 873         if (ret != ICE_SUCCESS) {
 874                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 875                 ret = -EINVAL;
 876                 goto DONE;
 877         }
 878         /* Add the mac addr into mac list */
 879         f = rte_zmalloc(NULL, sizeof(*f), 0);
 880         if (!f) {
 881                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 882                 ret = -ENOMEM;
 883                 goto DONE;
 884         }
 885         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 886         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 887         vsi->mac_num++;
 888
 889         ret = 0;
 890
 891 DONE:
 892         rte_free(m_list_itr);
 893         return ret;
 894 }
 895
 896 static int
 897 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 898 {
 899         struct ice_fltr_list_entry *m_list_itr = NULL;
 900         struct ice_mac_filter *f;
 901         struct LIST_HEAD_TYPE list_head;
 902         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 903         int ret = 0;
 904
 905         /* Can't find it, return an error */
 906         f = ice_find_mac_filter(vsi, mac_addr);
 907         if (!f)
 908                 return -EINVAL;
 909
 910         INIT_LIST_HEAD(&list_head);
 911
 912         m_list_itr = (struct ice_fltr_list_entry *)
 913                 ice_malloc(hw, sizeof(*m_list_itr));
 914         if (!m_list_itr) {
 915                 ret = -ENOMEM;
 916                 goto DONE;
 917         }
 918         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 919                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 920         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 921         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 922         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 923         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 924         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 925
 926         LIST_ADD(&m_list_itr->list_entry, &list_head);
 927
 928         /* remove the mac filter */
 929         ret = ice_remove_mac(hw, &list_head);
 930         if (ret != ICE_SUCCESS) {
 931                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 932                 ret = -EINVAL;
 933                 goto DONE;
 934         }
 935
 936         /* Remove the mac addr from mac list */
 937         TAILQ_REMOVE(&vsi->mac_list, f, next);
 938         rte_free(f);
 939         vsi->mac_num--;
 940
 941         ret = 0;
 942 DONE:
 943         rte_free(m_list_itr);
 944         return ret;
 945 }
 946
 947 /* Find out specific VLAN filter */
 948 static struct ice_vlan_filter *
 949 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 950 {
 951         struct ice_vlan_filter *f;
 952
 953         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 954                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 955                     vlan->vid == f->vlan_info.vlan.vid)
 956                         return f;
 957         }
 958
 959         return NULL;
 960 }
 961
 962 static int
 963 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 964 {
 965         struct ice_fltr_list_entry *v_list_itr = NULL;
 966         struct ice_vlan_filter *f;
 967         struct LIST_HEAD_TYPE list_head;
 968         struct ice_hw *hw;
 969         int ret = 0;
 970
 971         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 972                 return -EINVAL;
 973
 974         hw = ICE_VSI_TO_HW(vsi);
 975
 976         /* If it's added and configured, return. */
 977         f = ice_find_vlan_filter(vsi, vlan);
 978         if (f) {
 979                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 980                 return 0;
 981         }
 982
 983         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 984                 return 0;
 985
 986         INIT_LIST_HEAD(&list_head);
 987
 988         v_list_itr = (struct ice_fltr_list_entry *)
 989                       ice_malloc(hw, sizeof(*v_list_itr));
 990         if (!v_list_itr) {
 991                 ret = -ENOMEM;
 992                 goto DONE;
 993         }
 994         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
 995         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
 996         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
 997         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 998         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 999         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1000         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1001         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1002
1003         LIST_ADD(&v_list_itr->list_entry, &list_head);
1004
1005         /* Add the vlan */
1006         ret = ice_add_vlan(hw, &list_head);
1007         if (ret != ICE_SUCCESS) {
1008                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1009                 ret = -EINVAL;
1010                 goto DONE;
1011         }
1012
1013         /* Add vlan into vlan list */
1014         f = rte_zmalloc(NULL, sizeof(*f), 0);
1015         if (!f) {
1016                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1017                 ret = -ENOMEM;
1018                 goto DONE;
1019         }
1020         f->vlan_info.vlan.tpid = vlan->tpid;
1021         f->vlan_info.vlan.vid = vlan->vid;
1022         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1023         vsi->vlan_num++;
1024
1025         ret = 0;
1026
1027 DONE:
1028         rte_free(v_list_itr);
1029         return ret;
1030 }
1031
1032 static int
1033 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1034 {
1035         struct ice_fltr_list_entry *v_list_itr = NULL;
1036         struct ice_vlan_filter *f;
1037         struct LIST_HEAD_TYPE list_head;
1038         struct ice_hw *hw;
1039         int ret = 0;
1040
1041         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1042                 return -EINVAL;
1043
1044         hw = ICE_VSI_TO_HW(vsi);
1045
1046         /* Can't find it, return an error */
1047         f = ice_find_vlan_filter(vsi, vlan);
1048         if (!f)
1049                 return -EINVAL;
1050
1051         INIT_LIST_HEAD(&list_head);
1052
1053         v_list_itr = (struct ice_fltr_list_entry *)
1054                       ice_malloc(hw, sizeof(*v_list_itr));
1055         if (!v_list_itr) {
1056                 ret = -ENOMEM;
1057                 goto DONE;
1058         }
1059
1060         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1061         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1062         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1063         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1064         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1065         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1066         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1067         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1068
1069         LIST_ADD(&v_list_itr->list_entry, &list_head);
1070
1071         /* remove the vlan filter */
1072         ret = ice_remove_vlan(hw, &list_head);
1073         if (ret != ICE_SUCCESS) {
1074                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1075                 ret = -EINVAL;
1076                 goto DONE;
1077         }
1078
1079         /* Remove the vlan id from vlan list */
1080         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1081         rte_free(f);
1082         vsi->vlan_num--;
1083
1084         ret = 0;
1085 DONE:
1086         rte_free(v_list_itr);
1087         return ret;
1088 }
1089
1090 static int
1091 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1092 {
1093         struct ice_mac_filter *m_f;
1094         struct ice_vlan_filter *v_f;
1095         int ret = 0;
1096
1097         if (!vsi || !vsi->mac_num)
1098                 return -EINVAL;
1099
1100         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1101                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1102                 if (ret != ICE_SUCCESS) {
1103                         ret = -EINVAL;
1104                         goto DONE;
1105                 }
1106         }
1107
1108         if (vsi->vlan_num == 0)
1109                 return 0;
1110
1111         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1112                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1113                 if (ret != ICE_SUCCESS) {
1114                         ret = -EINVAL;
1115                         goto DONE;
1116                 }
1117         }
1118
1119 DONE:
1120         return ret;
1121 }
1122
1123 /* Enable IRQ0 */
1124 static void
1125 ice_pf_enable_irq0(struct ice_hw *hw)
1126 {
1127         /* reset the registers */
1128         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1129         ICE_READ_REG(hw, PFINT_OICR);
1130
1131 #ifdef ICE_LSE_SPT
1132         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1133                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1134                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1135
1136         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1137                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1138                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1139                        PFINT_OICR_CTL_ITR_INDX_M) |
1140                       PFINT_OICR_CTL_CAUSE_ENA_M);
1141
1142         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1143                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1144                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1145                        PFINT_FW_CTL_ITR_INDX_M) |
1146                       PFINT_FW_CTL_CAUSE_ENA_M);
1147 #else
1148         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1149 #endif
1150
1151         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1152                       GLINT_DYN_CTL_INTENA_M |
1153                       GLINT_DYN_CTL_CLEARPBA_M |
1154                       GLINT_DYN_CTL_ITR_INDX_M);
1155
1156         ice_flush(hw);
1157 }
1158
1159 /* Disable IRQ0 */
1160 static void
1161 ice_pf_disable_irq0(struct ice_hw *hw)
1162 {
1163         /* Disable all interrupt types */
1164         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1165         ice_flush(hw);
1166 }
1167
1168 #ifdef ICE_LSE_SPT
1169 static void
1170 ice_handle_aq_msg(struct rte_eth_dev *dev)
1171 {
1172         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1173         struct ice_ctl_q_info *cq = &hw->adminq;
1174         struct ice_rq_event_info event;
1175         uint16_t pending, opcode;
1176         int ret;
1177
1178         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1179         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1180         if (!event.msg_buf) {
1181                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1182                 return;
1183         }
1184
1185         pending = 1;
1186         while (pending) {
1187                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1188
1189                 if (ret != ICE_SUCCESS) {
1190                         PMD_DRV_LOG(INFO,
1191                                     "Failed to read msg from AdminQ, "
1192                                     "adminq_err: %u",
1193                                     hw->adminq.sq_last_status);
1194                         break;
1195                 }
1196                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1197
1198                 switch (opcode) {
1199                 case ice_aqc_opc_get_link_status:
1200                         ret = ice_link_update(dev, 0);
1201                         if (!ret)
1202                                 rte_eth_dev_callback_process
1203                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1204                         break;
1205                 default:
1206                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1207                                     opcode);
1208                         break;
1209                 }
1210         }
1211         rte_free(event.msg_buf);
1212 }
1213 #endif
1214
1215 /**
1216  * Interrupt handler triggered by NIC for handling
1217  * specific interrupt.
1218  *
1219  * @param handle
1220  *  Pointer to interrupt handle.
1221  * @param param
1222  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1223  *
1224  * @return
1225  *  void
1226  */
1227 static void
1228 ice_interrupt_handler(void *param)
1229 {
1230         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1231         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         uint32_t oicr;
1233         uint32_t reg;
1234         uint8_t pf_num;
1235         uint8_t event;
1236         uint16_t queue;
1237         int ret;
1238 #ifdef ICE_LSE_SPT
1239         uint32_t int_fw_ctl;
1240 #endif
1241
1242         /* Disable interrupt */
1243         ice_pf_disable_irq0(hw);
1244
1245         /* read out interrupt causes */
1246         oicr = ICE_READ_REG(hw, PFINT_OICR);
1247 #ifdef ICE_LSE_SPT
1248         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1249 #endif
1250
1251         /* No interrupt event indicated */
1252         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1253                 PMD_DRV_LOG(INFO, "No interrupt event");
1254                 goto done;
1255         }
1256
1257 #ifdef ICE_LSE_SPT
1258         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1259                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1260                 ice_handle_aq_msg(dev);
1261         }
1262 #else
1263         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1264                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1265                 ret = ice_link_update(dev, 0);
1266                 if (!ret)
1267                         rte_eth_dev_callback_process
1268                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1269         }
1270 #endif
1271
1272         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1273                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1274                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1275                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1276                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1277                                  GL_MDET_TX_PQM_PF_NUM_S;
1278                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1279                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1280                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1281                                 GL_MDET_TX_PQM_QNUM_S;
1282
1283                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1284                                     "%d by PQM on TX queue %d PF# %d",
1285                                     event, queue, pf_num);
1286                 }
1287
1288                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1289                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1290                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1291                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1292                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1293                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1294                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1295                                 GL_MDET_TX_TCLAN_QNUM_S;
1296
1297                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1298                                     "%d by TCLAN on TX queue %d PF# %d",
1299                                     event, queue, pf_num);
1300                 }
1301         }
1302 done:
1303         /* Enable interrupt */
1304         ice_pf_enable_irq0(hw);
1305         rte_intr_ack(dev->intr_handle);
1306 }
1307
1308 static void
1309 ice_init_proto_xtr(struct rte_eth_dev *dev)
1310 {
1311         struct ice_adapter *ad =
1312                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1313         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1314         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1315         const struct proto_xtr_ol_flag *ol_flag;
1316         bool proto_xtr_enable = false;
1317         int offset;
1318         uint16_t i;
1319
1320         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1321         if (unlikely(pf->proto_xtr == NULL)) {
1322                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1323                 return;
1324         }
1325
1326         for (i = 0; i < pf->lan_nb_qps; i++) {
1327                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1328                                    ad->devargs.proto_xtr[i] :
1329                                    ad->devargs.proto_xtr_dflt;
1330
1331                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1332                         uint8_t type = pf->proto_xtr[i];
1333
1334                         ice_proto_xtr_ol_flag_params[type].required = true;
1335                         proto_xtr_enable = true;
1336                 }
1337         }
1338
1339         if (likely(!proto_xtr_enable))
1340                 return;
1341
1342         ice_check_proto_xtr_support(hw);
1343
1344         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1345         if (unlikely(offset == -1)) {
1346                 PMD_DRV_LOG(ERR,
1347                             "Protocol extraction metadata is disabled in mbuf with error %d",
1348                             -rte_errno);
1349                 return;
1350         }
1351
1352         PMD_DRV_LOG(DEBUG,
1353                     "Protocol extraction metadata offset in mbuf is : %d",
1354                     offset);
1355         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1356
1357         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1358                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1359
1360                 if (!ol_flag->required)
1361                         continue;
1362
1363                 if (!ice_proto_xtr_hw_support[i]) {
1364                         PMD_DRV_LOG(ERR,
1365                                     "Protocol extraction type %u is not supported in hardware",
1366                                     i);
1367                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1368                         break;
1369                 }
1370
1371                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1372                 if (unlikely(offset == -1)) {
1373                         PMD_DRV_LOG(ERR,
1374                                     "Protocol extraction offload '%s' failed to register with error %d",
1375                                     ol_flag->param.name, -rte_errno);
1376
1377                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1378                         break;
1379                 }
1380
1381                 PMD_DRV_LOG(DEBUG,
1382                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1383                             ol_flag->param.name, offset);
1384                 *ol_flag->ol_flag = 1ULL << offset;
1385         }
1386 }
1387
1388 /*  Initialize SW parameters of PF */
1389 static int
1390 ice_pf_sw_init(struct rte_eth_dev *dev)
1391 {
1392         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1393         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1394
1395         pf->lan_nb_qp_max =
1396                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1397                                   hw->func_caps.common_cap.num_rxq);
1398
1399         pf->lan_nb_qps = pf->lan_nb_qp_max;
1400
1401         ice_init_proto_xtr(dev);
1402
1403         if (hw->func_caps.fd_fltr_guar > 0 ||
1404             hw->func_caps.fd_fltr_best_effort > 0) {
1405                 pf->flags |= ICE_FLAG_FDIR;
1406                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1407                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1408         } else {
1409                 pf->fdir_nb_qps = 0;
1410         }
1411         pf->fdir_qp_offset = 0;
1412
1413         return 0;
1414 }
1415
1416 struct ice_vsi *
1417 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1418 {
1419         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1420         struct ice_vsi *vsi = NULL;
1421         struct ice_vsi_ctx vsi_ctx;
1422         int ret;
1423         struct rte_ether_addr broadcast = {
1424                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1425         struct rte_ether_addr mac_addr;
1426         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1427         uint8_t tc_bitmap = 0x1;
1428         uint16_t cfg;
1429
1430         /* hw->num_lports = 1 in NIC mode */
1431         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1432         if (!vsi)
1433                 return NULL;
1434
1435         vsi->idx = pf->next_vsi_idx;
1436         pf->next_vsi_idx++;
1437         vsi->type = type;
1438         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1439         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1440         vsi->vlan_anti_spoof_on = 0;
1441         vsi->vlan_filter_on = 1;
1442         TAILQ_INIT(&vsi->mac_list);
1443         TAILQ_INIT(&vsi->vlan_list);
1444
1445         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1446         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1447                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1448                         hw->func_caps.common_cap.rss_table_size;
1449         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1450
1451         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1452         switch (type) {
1453         case ICE_VSI_PF:
1454                 vsi->nb_qps = pf->lan_nb_qps;
1455                 vsi->base_queue = 1;
1456                 ice_vsi_config_default_rss(&vsi_ctx.info);
1457                 vsi_ctx.alloc_from_pool = true;
1458                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1459                 /* switch_id is queried by get_switch_config aq, which is done
1460                  * by ice_init_hw
1461                  */
1462                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1463                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1464                 /* Allow all untagged or tagged packets */
1465                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1466                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1467                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1468                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1469                 if (ice_is_dvm_ena(hw)) {
1470                         vsi_ctx.info.outer_vlan_flags =
1471                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1472                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1473                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1474                         vsi_ctx.info.outer_vlan_flags |=
1475                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1476                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1477                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1478                 }
1479
1480                 /* FDIR */
1481                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1482                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1483                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1484                 cfg = ICE_AQ_VSI_FD_ENABLE;
1485                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1486                 vsi_ctx.info.max_fd_fltr_dedicated =
1487                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1488                 vsi_ctx.info.max_fd_fltr_shared =
1489                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1490
1491                 /* Enable VLAN/UP trip */
1492                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1493                                                       &vsi_ctx.info,
1494                                                       ICE_DEFAULT_TCMAP);
1495                 if (ret) {
1496                         PMD_INIT_LOG(ERR,
1497                                      "tc queue mapping with vsi failed, "
1498                                      "err = %d",
1499                                      ret);
1500                         goto fail_mem;
1501                 }
1502
1503                 break;
1504         case ICE_VSI_CTRL:
1505                 vsi->nb_qps = pf->fdir_nb_qps;
1506                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1507                 vsi_ctx.alloc_from_pool = true;
1508                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1509
1510                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1511                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1512                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1513                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1514                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1515                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1516                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1517                                                       &vsi_ctx.info,
1518                                                       ICE_DEFAULT_TCMAP);
1519                 if (ret) {
1520                         PMD_INIT_LOG(ERR,
1521                                      "tc queue mapping with vsi failed, "
1522                                      "err = %d",
1523                                      ret);
1524                         goto fail_mem;
1525                 }
1526                 break;
1527         default:
1528                 /* for other types of VSI */
1529                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1530                 goto fail_mem;
1531         }
1532
1533         /* VF has MSIX interrupt in VF range, don't allocate here */
1534         if (type == ICE_VSI_PF) {
1535                 ret = ice_res_pool_alloc(&pf->msix_pool,
1536                                          RTE_MIN(vsi->nb_qps,
1537                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1538                 if (ret < 0) {
1539                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1540                                      vsi->vsi_id, ret);
1541                 }
1542                 vsi->msix_intr = ret;
1543                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1544         } else if (type == ICE_VSI_CTRL) {
1545                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1546                 if (ret < 0) {
1547                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1548                                     vsi->vsi_id, ret);
1549                 }
1550                 vsi->msix_intr = ret;
1551                 vsi->nb_msix = 1;
1552         } else {
1553                 vsi->msix_intr = 0;
1554                 vsi->nb_msix = 0;
1555         }
1556         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1557         if (ret != ICE_SUCCESS) {
1558                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1559                 goto fail_mem;
1560         }
1561         /* store vsi information is SW structure */
1562         vsi->vsi_id = vsi_ctx.vsi_num;
1563         vsi->info = vsi_ctx.info;
1564         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1565         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1566
1567         if (type == ICE_VSI_PF) {
1568                 /* MAC configuration */
1569                 rte_ether_addr_copy((struct rte_ether_addr *)
1570                                         hw->port_info->mac.perm_addr,
1571                                     &pf->dev_addr);
1572
1573                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1574                 ret = ice_add_mac_filter(vsi, &mac_addr);
1575                 if (ret != ICE_SUCCESS)
1576                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1577
1578                 rte_ether_addr_copy(&broadcast, &mac_addr);
1579                 ret = ice_add_mac_filter(vsi, &mac_addr);
1580                 if (ret != ICE_SUCCESS)
1581                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1582         }
1583
1584         /* At the beginning, only TC0. */
1585         /* What we need here is the maximam number of the TX queues.
1586          * Currently vsi->nb_qps means it.
1587          * Correct it if any change.
1588          */
1589         max_txqs[0] = vsi->nb_qps;
1590         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1591                               tc_bitmap, max_txqs);
1592         if (ret != ICE_SUCCESS)
1593                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1594
1595         return vsi;
1596 fail_mem:
1597         rte_free(vsi);
1598         pf->next_vsi_idx--;
1599         return NULL;
1600 }
1601
1602 static int
1603 ice_send_driver_ver(struct ice_hw *hw)
1604 {
1605         struct ice_driver_ver dv;
1606
1607         /* we don't have driver version use 0 for dummy */
1608         dv.major_ver = 0;
1609         dv.minor_ver = 0;
1610         dv.build_ver = 0;
1611         dv.subbuild_ver = 0;
1612         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1613
1614         return ice_aq_send_driver_ver(hw, &dv, NULL);
1615 }
1616
1617 static int
1618 ice_pf_setup(struct ice_pf *pf)
1619 {
1620         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1621         struct ice_vsi *vsi;
1622         uint16_t unused;
1623
1624         /* Clear all stats counters */
1625         pf->offset_loaded = false;
1626         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1627         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1628         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1629         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1630
1631         /* force guaranteed filter pool for PF */
1632         ice_alloc_fd_guar_item(hw, &unused,
1633                                hw->func_caps.fd_fltr_guar);
1634         /* force shared filter pool for PF */
1635         ice_alloc_fd_shrd_item(hw, &unused,
1636                                hw->func_caps.fd_fltr_best_effort);
1637
1638         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1639         if (!vsi) {
1640                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1641                 return -EINVAL;
1642         }
1643
1644         pf->main_vsi = vsi;
1645
1646         return 0;
1647 }
1648
1649 /*
1650  * Extract device serial number from PCIe Configuration Space and
1651  * determine the pkg file path according to the DSN.
1652  */
1653 static int
1654 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1655 {
1656         off_t pos;
1657         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1658         uint32_t dsn_low, dsn_high;
1659         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1660
1661         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1662
1663         if (pos) {
1664                 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0) {
1665                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1666                         return -1;
1667                 }
1668                 if (rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
1669                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1670                         return -1;
1671                 }
1672                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1673                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1674         } else {
1675                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1676                 goto fail_dsn;
1677         }
1678
1679         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1680                 ICE_MAX_PKG_FILENAME_SIZE);
1681         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1682                 return 0;
1683
1684         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1685                 ICE_MAX_PKG_FILENAME_SIZE);
1686         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1687                 return 0;
1688
1689 fail_dsn:
1690         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1691         if (!access(pkg_file, 0))
1692                 return 0;
1693         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1694         return 0;
1695 }
1696
1697 enum ice_pkg_type
1698 ice_load_pkg_type(struct ice_hw *hw)
1699 {
1700         enum ice_pkg_type package_type;
1701
1702         /* store the activated package type (OS default or Comms) */
1703         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1704                 ICE_PKG_NAME_SIZE))
1705                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1706         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1707                 ICE_PKG_NAME_SIZE))
1708                 package_type = ICE_PKG_TYPE_COMMS;
1709         else
1710                 package_type = ICE_PKG_TYPE_UNKNOWN;
1711
1712         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1713                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1714                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1715                 hw->active_pkg_name,
1716                 ice_is_dvm_ena(hw) ? "double" : "single");
1717
1718         return package_type;
1719 }
1720
1721 static int ice_load_pkg(struct rte_eth_dev *dev)
1722 {
1723         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1725         int err;
1726         uint8_t *buf;
1727         int buf_len;
1728         FILE *file;
1729         struct stat fstat;
1730         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1731         struct ice_adapter *ad =
1732                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1733
1734         err = ice_pkg_file_search_path(pci_dev, pkg_file);
1735         if (err) {
1736                 PMD_INIT_LOG(ERR, "failed to search file path\n");
1737                 return err;
1738         }
1739
1740         file = fopen(pkg_file, "rb");
1741         if (!file)  {
1742                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1743                 return -1;
1744         }
1745
1746         err = stat(pkg_file, &fstat);
1747         if (err) {
1748                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1749                 fclose(file);
1750                 return err;
1751         }
1752
1753         buf_len = fstat.st_size;
1754         buf = rte_malloc(NULL, buf_len, 0);
1755
1756         if (!buf) {
1757                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1758                                 buf_len);
1759                 fclose(file);
1760                 return -1;
1761         }
1762
1763         err = fread(buf, buf_len, 1, file);
1764         if (err != 1) {
1765                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1766                 fclose(file);
1767                 err = -1;
1768                 goto fail_exit;
1769         }
1770
1771         fclose(file);
1772
1773         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1774         if (err) {
1775                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1776                 goto fail_exit;
1777         }
1778
1779         /* store the loaded pkg type info */
1780         ad->active_pkg_type = ice_load_pkg_type(hw);
1781
1782         err = ice_init_hw_tbls(hw);
1783         if (err) {
1784                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1785                 goto fail_init_tbls;
1786         }
1787
1788         return 0;
1789
1790 fail_init_tbls:
1791         rte_free(hw->pkg_copy);
1792 fail_exit:
1793         rte_free(buf);
1794         return err;
1795 }
1796
1797 static void
1798 ice_base_queue_get(struct ice_pf *pf)
1799 {
1800         uint32_t reg;
1801         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1802
1803         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1804         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1805                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1806         } else {
1807                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1808                                         " index");
1809         }
1810 }
1811
1812 static int
1813 parse_bool(const char *key, const char *value, void *args)
1814 {
1815         int *i = (int *)args;
1816         char *end;
1817         int num;
1818
1819         num = strtoul(value, &end, 10);
1820
1821         if (num != 0 && num != 1) {
1822                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1823                         "value must be 0 or 1",
1824                         value, key);
1825                 return -1;
1826         }
1827
1828         *i = num;
1829         return 0;
1830 }
1831
1832 static int ice_parse_devargs(struct rte_eth_dev *dev)
1833 {
1834         struct ice_adapter *ad =
1835                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1836         struct rte_devargs *devargs = dev->device->devargs;
1837         struct rte_kvargs *kvlist;
1838         int ret;
1839
1840         if (devargs == NULL)
1841                 return 0;
1842
1843         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1844         if (kvlist == NULL) {
1845                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1846                 return -EINVAL;
1847         }
1848
1849         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1850         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1851                sizeof(ad->devargs.proto_xtr));
1852
1853         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1854                                  &handle_proto_xtr_arg, &ad->devargs);
1855         if (ret)
1856                 goto bail;
1857
1858         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1859                                  &parse_bool, &ad->devargs.safe_mode_support);
1860         if (ret)
1861                 goto bail;
1862
1863         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1864                                  &parse_bool, &ad->devargs.pipe_mode_support);
1865         if (ret)
1866                 goto bail;
1867
1868 bail:
1869         rte_kvargs_free(kvlist);
1870         return ret;
1871 }
1872
1873 /* Forward LLDP packets to default VSI by set switch rules */
1874 static int
1875 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1876 {
1877         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1878         struct ice_fltr_list_entry *s_list_itr = NULL;
1879         struct LIST_HEAD_TYPE list_head;
1880         int ret = 0;
1881
1882         INIT_LIST_HEAD(&list_head);
1883
1884         s_list_itr = (struct ice_fltr_list_entry *)
1885                         ice_malloc(hw, sizeof(*s_list_itr));
1886         if (!s_list_itr)
1887                 return -ENOMEM;
1888         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1889         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1890         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1891                         RTE_ETHER_TYPE_LLDP;
1892         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1893         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1894         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1895         LIST_ADD(&s_list_itr->list_entry, &list_head);
1896         if (on)
1897                 ret = ice_add_eth_mac(hw, &list_head);
1898         else
1899                 ret = ice_remove_eth_mac(hw, &list_head);
1900
1901         rte_free(s_list_itr);
1902         return ret;
1903 }
1904
1905 static enum ice_status
1906 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1907                 uint16_t num, uint16_t desc_id,
1908                 uint16_t *prof_buf, uint16_t *num_prof)
1909 {
1910         struct ice_aqc_res_elem *resp_buf;
1911         int ret;
1912         uint16_t buf_len;
1913         bool res_shared = 1;
1914         struct ice_aq_desc aq_desc;
1915         struct ice_sq_cd *cd = NULL;
1916         struct ice_aqc_get_allocd_res_desc *cmd =
1917                         &aq_desc.params.get_res_desc;
1918
1919         buf_len = sizeof(*resp_buf) * num;
1920         resp_buf = ice_malloc(hw, buf_len);
1921         if (!resp_buf)
1922                 return -ENOMEM;
1923
1924         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1925                         ice_aqc_opc_get_allocd_res_desc);
1926
1927         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1928                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1929                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1930         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1931
1932         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1933         if (!ret)
1934                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1935         else
1936                 goto exit;
1937
1938         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1939                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1940
1941 exit:
1942         rte_free(resp_buf);
1943         return ret;
1944 }
1945 static int
1946 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1947 {
1948         int ret;
1949         uint16_t prof_id;
1950         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1951         uint16_t first_desc = 1;
1952         uint16_t num_prof = 0;
1953
1954         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1955                         first_desc, prof_buf, &num_prof);
1956         if (ret) {
1957                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1958                 return ret;
1959         }
1960
1961         for (prof_id = 0; prof_id < num_prof; prof_id++) {
1962                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1963                 if (ret) {
1964                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1965                         return ret;
1966                 }
1967         }
1968         return 0;
1969 }
1970
1971 static int
1972 ice_reset_fxp_resource(struct ice_hw *hw)
1973 {
1974         int ret;
1975
1976         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1977         if (ret) {
1978                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1979                 return ret;
1980         }
1981
1982         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1983         if (ret) {
1984                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1985                 return ret;
1986         }
1987
1988         return 0;
1989 }
1990
1991 static void
1992 ice_rss_ctx_init(struct ice_pf *pf)
1993 {
1994         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1995 }
1996
1997 static uint64_t
1998 ice_get_supported_rxdid(struct ice_hw *hw)
1999 {
2000         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2001         uint32_t regval;
2002         int i;
2003
2004         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2005
2006         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2007                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2008                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2009                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2010                         supported_rxdid |= BIT(i);
2011         }
2012         return supported_rxdid;
2013 }
2014
2015 static int
2016 ice_dev_init(struct rte_eth_dev *dev)
2017 {
2018         struct rte_pci_device *pci_dev;
2019         struct rte_intr_handle *intr_handle;
2020         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2022         struct ice_adapter *ad =
2023                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2024         struct ice_vsi *vsi;
2025         int ret;
2026
2027         dev->dev_ops = &ice_eth_dev_ops;
2028         dev->rx_queue_count = ice_rx_queue_count;
2029         dev->rx_descriptor_status = ice_rx_descriptor_status;
2030         dev->tx_descriptor_status = ice_tx_descriptor_status;
2031         dev->rx_pkt_burst = ice_recv_pkts;
2032         dev->tx_pkt_burst = ice_xmit_pkts;
2033         dev->tx_pkt_prepare = ice_prep_pkts;
2034
2035         /* for secondary processes, we don't initialise any further as primary
2036          * has already done this work.
2037          */
2038         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2039                 ice_set_rx_function(dev);
2040                 ice_set_tx_function(dev);
2041                 return 0;
2042         }
2043
2044         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2045
2046         ice_set_default_ptype_table(dev);
2047         pci_dev = RTE_DEV_TO_PCI(dev->device);
2048         intr_handle = &pci_dev->intr_handle;
2049
2050         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2051         pf->adapter->eth_dev = dev;
2052         pf->dev_data = dev->data;
2053         hw->back = pf->adapter;
2054         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2055         hw->vendor_id = pci_dev->id.vendor_id;
2056         hw->device_id = pci_dev->id.device_id;
2057         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2058         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2059         hw->bus.device = pci_dev->addr.devid;
2060         hw->bus.func = pci_dev->addr.function;
2061
2062         ret = ice_parse_devargs(dev);
2063         if (ret) {
2064                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2065                 return -EINVAL;
2066         }
2067
2068         ice_init_controlq_parameter(hw);
2069
2070         ret = ice_init_hw(hw);
2071         if (ret) {
2072                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2073                 return -EINVAL;
2074         }
2075
2076         ret = ice_load_pkg(dev);
2077         if (ret) {
2078                 if (ad->devargs.safe_mode_support == 0) {
2079                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2080                                         "Use safe-mode-support=1 to enter Safe Mode");
2081                         return ret;
2082                 }
2083
2084                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2085                                         "Entering Safe Mode");
2086                 ad->is_safe_mode = 1;
2087         }
2088
2089         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2090                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2091                      hw->api_maj_ver, hw->api_min_ver);
2092
2093         ice_pf_sw_init(dev);
2094         ret = ice_init_mac_address(dev);
2095         if (ret) {
2096                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2097                 goto err_init_mac;
2098         }
2099
2100         ret = ice_res_pool_init(&pf->msix_pool, 1,
2101                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2102         if (ret) {
2103                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2104                 goto err_msix_pool_init;
2105         }
2106
2107         ret = ice_pf_setup(pf);
2108         if (ret) {
2109                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2110                 goto err_pf_setup;
2111         }
2112
2113         ret = ice_send_driver_ver(hw);
2114         if (ret) {
2115                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2116                 goto err_pf_setup;
2117         }
2118
2119         vsi = pf->main_vsi;
2120
2121         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2122         if (ret != ICE_SUCCESS)
2123                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2124         ret = ice_init_dcb(hw, true);
2125         if (ret != ICE_SUCCESS)
2126                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2127         /* Forward LLDP packets to default VSI */
2128         ret = ice_vsi_config_sw_lldp(vsi, true);
2129         if (ret != ICE_SUCCESS)
2130                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2131         /* register callback func to eal lib */
2132         rte_intr_callback_register(intr_handle,
2133                                    ice_interrupt_handler, dev);
2134
2135         ice_pf_enable_irq0(hw);
2136
2137         /* enable uio intr after callback register */
2138         rte_intr_enable(intr_handle);
2139
2140         /* get base queue pairs index  in the device */
2141         ice_base_queue_get(pf);
2142
2143         /* Initialize RSS context for gtpu_eh */
2144         ice_rss_ctx_init(pf);
2145
2146         if (!ad->is_safe_mode) {
2147                 ret = ice_flow_init(ad);
2148                 if (ret) {
2149                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2150                         return ret;
2151                 }
2152         }
2153
2154         ret = ice_reset_fxp_resource(hw);
2155         if (ret) {
2156                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2157                 return ret;
2158         }
2159
2160         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2161
2162         return 0;
2163
2164 err_pf_setup:
2165         ice_res_pool_destroy(&pf->msix_pool);
2166 err_msix_pool_init:
2167         rte_free(dev->data->mac_addrs);
2168         dev->data->mac_addrs = NULL;
2169 err_init_mac:
2170         ice_sched_cleanup_all(hw);
2171         rte_free(hw->port_info);
2172         ice_shutdown_all_ctrlq(hw);
2173         rte_free(pf->proto_xtr);
2174
2175         return ret;
2176 }
2177
2178 int
2179 ice_release_vsi(struct ice_vsi *vsi)
2180 {
2181         struct ice_hw *hw;
2182         struct ice_vsi_ctx vsi_ctx;
2183         enum ice_status ret;
2184         int error = 0;
2185
2186         if (!vsi)
2187                 return error;
2188
2189         hw = ICE_VSI_TO_HW(vsi);
2190
2191         ice_remove_all_mac_vlan_filters(vsi);
2192
2193         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2194
2195         vsi_ctx.vsi_num = vsi->vsi_id;
2196         vsi_ctx.info = vsi->info;
2197         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2198         if (ret != ICE_SUCCESS) {
2199                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2200                 error = -1;
2201         }
2202
2203         rte_free(vsi->rss_lut);
2204         rte_free(vsi->rss_key);
2205         rte_free(vsi);
2206         return error;
2207 }
2208
2209 void
2210 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2211 {
2212         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2213         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2214         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2215         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2216         uint16_t msix_intr, i;
2217
2218         /* disable interrupt and also clear all the exist config */
2219         for (i = 0; i < vsi->nb_qps; i++) {
2220                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2221                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2222                 rte_wmb();
2223         }
2224
2225         if (rte_intr_allow_others(intr_handle))
2226                 /* vfio-pci */
2227                 for (i = 0; i < vsi->nb_msix; i++) {
2228                         msix_intr = vsi->msix_intr + i;
2229                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2230                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2231                 }
2232         else
2233                 /* igb_uio */
2234                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2235 }
2236
2237 static int
2238 ice_dev_stop(struct rte_eth_dev *dev)
2239 {
2240         struct rte_eth_dev_data *data = dev->data;
2241         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2242         struct ice_vsi *main_vsi = pf->main_vsi;
2243         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2244         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2245         uint16_t i;
2246
2247         /* avoid stopping again */
2248         if (pf->adapter_stopped)
2249                 return 0;
2250
2251         /* stop and clear all Rx queues */
2252         for (i = 0; i < data->nb_rx_queues; i++)
2253                 ice_rx_queue_stop(dev, i);
2254
2255         /* stop and clear all Tx queues */
2256         for (i = 0; i < data->nb_tx_queues; i++)
2257                 ice_tx_queue_stop(dev, i);
2258
2259         /* disable all queue interrupts */
2260         ice_vsi_disable_queues_intr(main_vsi);
2261
2262         if (pf->init_link_up)
2263                 ice_dev_set_link_up(dev);
2264         else
2265                 ice_dev_set_link_down(dev);
2266
2267         /* Clean datapath event and queue/vec mapping */
2268         rte_intr_efd_disable(intr_handle);
2269         if (intr_handle->intr_vec) {
2270                 rte_free(intr_handle->intr_vec);
2271                 intr_handle->intr_vec = NULL;
2272         }
2273
2274         pf->adapter_stopped = true;
2275         dev->data->dev_started = 0;
2276
2277         return 0;
2278 }
2279
2280 static int
2281 ice_dev_close(struct rte_eth_dev *dev)
2282 {
2283         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2284         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2286         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2287         struct ice_adapter *ad =
2288                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2289         int ret;
2290
2291         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2292                 return 0;
2293
2294         /* Since stop will make link down, then the link event will be
2295          * triggered, disable the irq firstly to avoid the port_infoe etc
2296          * resources deallocation causing the interrupt service thread
2297          * crash.
2298          */
2299         ice_pf_disable_irq0(hw);
2300
2301         ret = ice_dev_stop(dev);
2302
2303         if (!ad->is_safe_mode)
2304                 ice_flow_uninit(ad);
2305
2306         /* release all queue resource */
2307         ice_free_queues(dev);
2308
2309         ice_res_pool_destroy(&pf->msix_pool);
2310         ice_release_vsi(pf->main_vsi);
2311         ice_sched_cleanup_all(hw);
2312         ice_free_hw_tbls(hw);
2313         rte_free(hw->port_info);
2314         hw->port_info = NULL;
2315         ice_shutdown_all_ctrlq(hw);
2316         rte_free(pf->proto_xtr);
2317         pf->proto_xtr = NULL;
2318
2319         /* disable uio intr before callback unregister */
2320         rte_intr_disable(intr_handle);
2321
2322         /* unregister callback func from eal lib */
2323         rte_intr_callback_unregister(intr_handle,
2324                                      ice_interrupt_handler, dev);
2325
2326         return ret;
2327 }
2328
2329 static int
2330 ice_dev_uninit(struct rte_eth_dev *dev)
2331 {
2332         ice_dev_close(dev);
2333
2334         return 0;
2335 }
2336
2337 static bool
2338 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2339 {
2340         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2341 }
2342
2343 static void
2344 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2345 {
2346         cfg->hash_flds = 0;
2347         cfg->addl_hdrs = 0;
2348         cfg->symm = 0;
2349         cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2350 }
2351
2352 static int
2353 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2354 {
2355         enum ice_status status = ICE_SUCCESS;
2356         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2357         struct ice_vsi *vsi = pf->main_vsi;
2358
2359         if (!is_hash_cfg_valid(cfg))
2360                 return -ENOENT;
2361
2362         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2363         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2364                 PMD_DRV_LOG(ERR,
2365                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2366                             vsi->idx, status);
2367                 return -EBUSY;
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int
2374 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2375 {
2376         enum ice_status status = ICE_SUCCESS;
2377         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2378         struct ice_vsi *vsi = pf->main_vsi;
2379
2380         if (!is_hash_cfg_valid(cfg))
2381                 return -ENOENT;
2382
2383         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2384         if (status) {
2385                 PMD_DRV_LOG(ERR,
2386                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2387                             vsi->idx, status);
2388                 return -EBUSY;
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int
2395 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2396 {
2397         int ret;
2398
2399         ret = ice_hash_moveout(pf, cfg);
2400         if (ret && (ret != -ENOENT))
2401                 return ret;
2402
2403         hash_cfg_reset(cfg);
2404
2405         return 0;
2406 }
2407
2408 static int
2409 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2410                          u8 ctx_idx)
2411 {
2412         int ret;
2413
2414         switch (ctx_idx) {
2415         case ICE_HASH_GTPU_CTX_EH_IP:
2416                 ret = ice_hash_remove(pf,
2417                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2418                 if (ret && (ret != -ENOENT))
2419                         return ret;
2420
2421                 ret = ice_hash_remove(pf,
2422                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2423                 if (ret && (ret != -ENOENT))
2424                         return ret;
2425
2426                 ret = ice_hash_remove(pf,
2427                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2428                 if (ret && (ret != -ENOENT))
2429                         return ret;
2430
2431                 ret = ice_hash_remove(pf,
2432                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2433                 if (ret && (ret != -ENOENT))
2434                         return ret;
2435
2436                 ret = ice_hash_remove(pf,
2437                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2438                 if (ret && (ret != -ENOENT))
2439                         return ret;
2440
2441                 ret = ice_hash_remove(pf,
2442                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2443                 if (ret && (ret != -ENOENT))
2444                         return ret;
2445
2446                 ret = ice_hash_remove(pf,
2447                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2448                 if (ret && (ret != -ENOENT))
2449                         return ret;
2450
2451                 ret = ice_hash_remove(pf,
2452                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2453                 if (ret && (ret != -ENOENT))
2454                         return ret;
2455
2456                 break;
2457         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2458                 ret = ice_hash_remove(pf,
2459                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2460                 if (ret && (ret != -ENOENT))
2461                         return ret;
2462
2463                 ret = ice_hash_remove(pf,
2464                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2465                 if (ret && (ret != -ENOENT))
2466                         return ret;
2467
2468                 ret = ice_hash_moveout(pf,
2469                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2470                 if (ret && (ret != -ENOENT))
2471                         return ret;
2472
2473                 ret = ice_hash_moveout(pf,
2474                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2475                 if (ret && (ret != -ENOENT))
2476                         return ret;
2477
2478                 ret = ice_hash_moveout(pf,
2479                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2480                 if (ret && (ret != -ENOENT))
2481                         return ret;
2482
2483                 ret = ice_hash_moveout(pf,
2484                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2485                 if (ret && (ret != -ENOENT))
2486                         return ret;
2487
2488                 break;
2489         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2490                 ret = ice_hash_remove(pf,
2491                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2492                 if (ret && (ret != -ENOENT))
2493                         return ret;
2494
2495                 ret = ice_hash_remove(pf,
2496                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2497                 if (ret && (ret != -ENOENT))
2498                         return ret;
2499
2500                 ret = ice_hash_moveout(pf,
2501                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2502                 if (ret && (ret != -ENOENT))
2503                         return ret;
2504
2505                 ret = ice_hash_moveout(pf,
2506                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2507                 if (ret && (ret != -ENOENT))
2508                         return ret;
2509
2510                 ret = ice_hash_moveout(pf,
2511                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2512                 if (ret && (ret != -ENOENT))
2513                         return ret;
2514
2515                 ret = ice_hash_moveout(pf,
2516                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2517                 if (ret && (ret != -ENOENT))
2518                         return ret;
2519
2520                 break;
2521         case ICE_HASH_GTPU_CTX_UP_IP:
2522                 ret = ice_hash_remove(pf,
2523                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2524                 if (ret && (ret != -ENOENT))
2525                         return ret;
2526
2527                 ret = ice_hash_remove(pf,
2528                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2529                 if (ret && (ret != -ENOENT))
2530                         return ret;
2531
2532                 ret = ice_hash_moveout(pf,
2533                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2534                 if (ret && (ret != -ENOENT))
2535                         return ret;
2536
2537                 ret = ice_hash_moveout(pf,
2538                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2539                 if (ret && (ret != -ENOENT))
2540                         return ret;
2541
2542                 ret = ice_hash_moveout(pf,
2543                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2544                 if (ret && (ret != -ENOENT))
2545                         return ret;
2546
2547                 break;
2548         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2549         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2550                 ret = ice_hash_moveout(pf,
2551                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2552                 if (ret && (ret != -ENOENT))
2553                         return ret;
2554
2555                 ret = ice_hash_moveout(pf,
2556                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2557                 if (ret && (ret != -ENOENT))
2558                         return ret;
2559
2560                 ret = ice_hash_moveout(pf,
2561                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2562                 if (ret && (ret != -ENOENT))
2563                         return ret;
2564
2565                 break;
2566         case ICE_HASH_GTPU_CTX_DW_IP:
2567                 ret = ice_hash_remove(pf,
2568                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2569                 if (ret && (ret != -ENOENT))
2570                         return ret;
2571
2572                 ret = ice_hash_remove(pf,
2573                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2574                 if (ret && (ret != -ENOENT))
2575                         return ret;
2576
2577                 ret = ice_hash_moveout(pf,
2578                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2579                 if (ret && (ret != -ENOENT))
2580                         return ret;
2581
2582                 ret = ice_hash_moveout(pf,
2583                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2584                 if (ret && (ret != -ENOENT))
2585                         return ret;
2586
2587                 ret = ice_hash_moveout(pf,
2588                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2589                 if (ret && (ret != -ENOENT))
2590                         return ret;
2591
2592                 break;
2593         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2594         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2595                 ret = ice_hash_moveout(pf,
2596                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2597                 if (ret && (ret != -ENOENT))
2598                         return ret;
2599
2600                 ret = ice_hash_moveout(pf,
2601                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2602                 if (ret && (ret != -ENOENT))
2603                         return ret;
2604
2605                 ret = ice_hash_moveout(pf,
2606                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2607                 if (ret && (ret != -ENOENT))
2608                         return ret;
2609
2610                 break;
2611         default:
2612                 break;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2619 {
2620         u8 eh_idx, ip_idx;
2621
2622         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2623                 eh_idx = 0;
2624         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2625                 eh_idx = 1;
2626         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2627                 eh_idx = 2;
2628         else
2629                 return ICE_HASH_GTPU_CTX_MAX;
2630
2631         ip_idx = 0;
2632         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2633                 ip_idx = 1;
2634         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2635                 ip_idx = 2;
2636
2637         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2638                 return eh_idx * 3 + ip_idx;
2639         else
2640                 return ICE_HASH_GTPU_CTX_MAX;
2641 }
2642
2643 static int
2644 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2645 {
2646         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2647
2648         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2649                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2650                                                 gtpu_ctx_idx);
2651         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2652                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2653                                                 gtpu_ctx_idx);
2654
2655         return 0;
2656 }
2657
2658 static int
2659 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2660                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2661 {
2662         int ret;
2663
2664         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2665                 ctx->ctx[ctx_idx] = *cfg;
2666
2667         switch (ctx_idx) {
2668         case ICE_HASH_GTPU_CTX_EH_IP:
2669                 break;
2670         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2671                 ret = ice_hash_moveback(pf,
2672                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2673                 if (ret && (ret != -ENOENT))
2674                         return ret;
2675
2676                 ret = ice_hash_moveback(pf,
2677                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2678                 if (ret && (ret != -ENOENT))
2679                         return ret;
2680
2681                 ret = ice_hash_moveback(pf,
2682                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2683                 if (ret && (ret != -ENOENT))
2684                         return ret;
2685
2686                 ret = ice_hash_moveback(pf,
2687                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2688                 if (ret && (ret != -ENOENT))
2689                         return ret;
2690
2691                 break;
2692         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2693                 ret = ice_hash_moveback(pf,
2694                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2695                 if (ret && (ret != -ENOENT))
2696                         return ret;
2697
2698                 ret = ice_hash_moveback(pf,
2699                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2700                 if (ret && (ret != -ENOENT))
2701                         return ret;
2702
2703                 ret = ice_hash_moveback(pf,
2704                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2705                 if (ret && (ret != -ENOENT))
2706                         return ret;
2707
2708                 ret = ice_hash_moveback(pf,
2709                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2710                 if (ret && (ret != -ENOENT))
2711                         return ret;
2712
2713                 break;
2714         case ICE_HASH_GTPU_CTX_UP_IP:
2715         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2716         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2717         case ICE_HASH_GTPU_CTX_DW_IP:
2718         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2719         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2720                 ret = ice_hash_moveback(pf,
2721                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2722                 if (ret && (ret != -ENOENT))
2723                         return ret;
2724
2725                 ret = ice_hash_moveback(pf,
2726                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2727                 if (ret && (ret != -ENOENT))
2728                         return ret;
2729
2730                 ret = ice_hash_moveback(pf,
2731                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2732                 if (ret && (ret != -ENOENT))
2733                         return ret;
2734
2735                 break;
2736         default:
2737                 break;
2738         }
2739
2740         return 0;
2741 }
2742
2743 static int
2744 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2745 {
2746         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2747
2748         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2749                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2750                                                  gtpu_ctx_idx, cfg);
2751         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2752                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2753                                                  gtpu_ctx_idx, cfg);
2754
2755         return 0;
2756 }
2757
2758 static void
2759 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2760 {
2761         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2762
2763         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2764                 return;
2765
2766         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2767                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2768         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2769                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2770 }
2771
2772 int
2773 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2774                      struct ice_rss_hash_cfg *cfg)
2775 {
2776         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2777         int ret;
2778
2779         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2780         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2781                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2782
2783         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2784
2785         return 0;
2786 }
2787
2788 int
2789 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2790                      struct ice_rss_hash_cfg *cfg)
2791 {
2792         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2793         int ret;
2794
2795         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2796         if (ret)
2797                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2798
2799         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2800         if (ret)
2801                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2802
2803         ret = ice_add_rss_cfg_post(pf, cfg);
2804         if (ret)
2805                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2806
2807         return 0;
2808 }
2809
2810 static void
2811 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2812 {
2813         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2814         struct ice_vsi *vsi = pf->main_vsi;
2815         struct ice_rss_hash_cfg cfg;
2816         int ret;
2817
2818 #define ICE_RSS_HF_ALL ( \
2819         ETH_RSS_IPV4 | \
2820         ETH_RSS_IPV6 | \
2821         ETH_RSS_NONFRAG_IPV4_UDP | \
2822         ETH_RSS_NONFRAG_IPV6_UDP | \
2823         ETH_RSS_NONFRAG_IPV4_TCP | \
2824         ETH_RSS_NONFRAG_IPV6_TCP | \
2825         ETH_RSS_NONFRAG_IPV4_SCTP | \
2826         ETH_RSS_NONFRAG_IPV6_SCTP)
2827
2828         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2829         if (ret)
2830                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2831                             __func__, ret);
2832
2833         cfg.symm = 0;
2834         cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2835         /* Configure RSS for IPv4 with src/dst addr as input set */
2836         if (rss_hf & ETH_RSS_IPV4) {
2837                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2838                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2839                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2840                 if (ret)
2841                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2842                                     __func__, ret);
2843         }
2844
2845         /* Configure RSS for IPv6 with src/dst addr as input set */
2846         if (rss_hf & ETH_RSS_IPV6) {
2847                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2848                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2849                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2850                 if (ret)
2851                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2852                                     __func__, ret);
2853         }
2854
2855         /* Configure RSS for udp4 with src/dst addr and port as input set */
2856         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2857                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2858                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2859                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2860                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2861                 if (ret)
2862                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2863                                     __func__, ret);
2864         }
2865
2866         /* Configure RSS for udp6 with src/dst addr and port as input set */
2867         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2868                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2869                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2870                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2871                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2872                 if (ret)
2873                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2874                                     __func__, ret);
2875         }
2876
2877         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2878         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2879                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2880                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2881                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2882                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2883                 if (ret)
2884                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2885                                     __func__, ret);
2886         }
2887
2888         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2889         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2890                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2891                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2892                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2893                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2894                 if (ret)
2895                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2896                                     __func__, ret);
2897         }
2898
2899         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2900         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2901                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2902                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2903                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2904                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2905                 if (ret)
2906                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2907                                     __func__, ret);
2908         }
2909
2910         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2911         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2912                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2913                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2914                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2915                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2916                 if (ret)
2917                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2918                                     __func__, ret);
2919         }
2920
2921         if (rss_hf & ETH_RSS_IPV4) {
2922                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2923                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2924                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2925                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2926                 if (ret)
2927                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2928                                     __func__, ret);
2929
2930                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2931                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2932                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2933                 if (ret)
2934                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2935                                     __func__, ret);
2936
2937                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2938                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2939                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2940                 if (ret)
2941                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2942                                     __func__, ret);
2943         }
2944
2945         if (rss_hf & ETH_RSS_IPV6) {
2946                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2947                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2948                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2949                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2950                 if (ret)
2951                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2952                                     __func__, ret);
2953
2954                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2955                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2956                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2957                 if (ret)
2958                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2959                                     __func__, ret);
2960
2961                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2962                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2963                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2964                 if (ret)
2965                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2966                                     __func__, ret);
2967         }
2968
2969         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2970                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2971                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2972                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2973                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2974                 if (ret)
2975                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2976                                     __func__, ret);
2977
2978                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2979                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2980                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2981                 if (ret)
2982                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2983                                     __func__, ret);
2984
2985                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2986                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2987                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2988                 if (ret)
2989                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2990                                     __func__, ret);
2991         }
2992
2993         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2994                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2995                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2996                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2997                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2998                 if (ret)
2999                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3000                                     __func__, ret);
3001
3002                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3003                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3004                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3005                 if (ret)
3006                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3007                                     __func__, ret);
3008
3009                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3010                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3011                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3012                 if (ret)
3013                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3014                                     __func__, ret);
3015         }
3016
3017         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3018                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3019                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3020                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3021                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3022                 if (ret)
3023                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3024                                     __func__, ret);
3025
3026                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3027                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3028                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3029                 if (ret)
3030                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3031                                     __func__, ret);
3032
3033                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3034                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3035                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3036                 if (ret)
3037                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3038                                     __func__, ret);
3039         }
3040
3041         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3042                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3043                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3044                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3045                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3046                 if (ret)
3047                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3048                                     __func__, ret);
3049
3050                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3051                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3052                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3053                 if (ret)
3054                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3055                                     __func__, ret);
3056
3057                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3058                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3059                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3060                 if (ret)
3061                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3062                                     __func__, ret);
3063         }
3064
3065         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3066 }
3067
3068 static int ice_init_rss(struct ice_pf *pf)
3069 {
3070         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3071         struct ice_vsi *vsi = pf->main_vsi;
3072         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3073         struct ice_aq_get_set_rss_lut_params lut_params;
3074         struct rte_eth_rss_conf *rss_conf;
3075         struct ice_aqc_get_set_rss_keys key;
3076         uint16_t i, nb_q;
3077         int ret = 0;
3078         bool is_safe_mode = pf->adapter->is_safe_mode;
3079         uint32_t reg;
3080
3081         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3082         nb_q = dev->data->nb_rx_queues;
3083         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3084         vsi->rss_lut_size = pf->hash_lut_size;
3085
3086         if (nb_q == 0) {
3087                 PMD_DRV_LOG(WARNING,
3088                         "RSS is not supported as rx queues number is zero\n");
3089                 return 0;
3090         }
3091
3092         if (is_safe_mode) {
3093                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3094                 return 0;
3095         }
3096
3097         if (!vsi->rss_key) {
3098                 vsi->rss_key = rte_zmalloc(NULL,
3099                                            vsi->rss_key_size, 0);
3100                 if (vsi->rss_key == NULL) {
3101                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3102                         return -ENOMEM;
3103                 }
3104         }
3105         if (!vsi->rss_lut) {
3106                 vsi->rss_lut = rte_zmalloc(NULL,
3107                                            vsi->rss_lut_size, 0);
3108                 if (vsi->rss_lut == NULL) {
3109                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3110                         rte_free(vsi->rss_key);
3111                         vsi->rss_key = NULL;
3112                         return -ENOMEM;
3113                 }
3114         }
3115         /* configure RSS key */
3116         if (!rss_conf->rss_key) {
3117                 /* Calculate the default hash key */
3118                 for (i = 0; i <= vsi->rss_key_size; i++)
3119                         vsi->rss_key[i] = (uint8_t)rte_rand();
3120         } else {
3121                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3122                            RTE_MIN(rss_conf->rss_key_len,
3123                                    vsi->rss_key_size));
3124         }
3125         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3126         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3127         if (ret)
3128                 goto out;
3129
3130         /* init RSS LUT table */
3131         for (i = 0; i < vsi->rss_lut_size; i++)
3132                 vsi->rss_lut[i] = i % nb_q;
3133
3134         lut_params.vsi_handle = vsi->idx;
3135         lut_params.lut_size = vsi->rss_lut_size;
3136         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3137         lut_params.lut = vsi->rss_lut;
3138         lut_params.global_lut_id = 0;
3139         ret = ice_aq_set_rss_lut(hw, &lut_params);
3140         if (ret)
3141                 goto out;
3142
3143         /* Enable registers for symmetric_toeplitz function. */
3144         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3145         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3146                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3147         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3148
3149         /* RSS hash configuration */
3150         ice_rss_hash_set(pf, rss_conf->rss_hf);
3151
3152         return 0;
3153 out:
3154         rte_free(vsi->rss_key);
3155         vsi->rss_key = NULL;
3156         rte_free(vsi->rss_lut);
3157         vsi->rss_lut = NULL;
3158         return -EINVAL;
3159 }
3160
3161 static int
3162 ice_dev_configure(struct rte_eth_dev *dev)
3163 {
3164         struct ice_adapter *ad =
3165                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3166         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3167         int ret;
3168
3169         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3170          * bulk allocation or vector Rx preconditions we will reset it.
3171          */
3172         ad->rx_bulk_alloc_allowed = true;
3173         ad->tx_simple_allowed = true;
3174
3175         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3176                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3177
3178         if (dev->data->nb_rx_queues) {
3179                 ret = ice_init_rss(pf);
3180                 if (ret) {
3181                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3182                         return ret;
3183                 }
3184         }
3185
3186         return 0;
3187 }
3188
3189 static void
3190 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3191                        int base_queue, int nb_queue)
3192 {
3193         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3194         uint32_t val, val_tx;
3195         int i;
3196
3197         for (i = 0; i < nb_queue; i++) {
3198                 /*do actual bind*/
3199                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3200                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3201                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3202                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3203
3204                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3205                             base_queue + i, msix_vect);
3206                 /* set ITR0 value */
3207                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3208                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3209                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3210         }
3211 }
3212
3213 void
3214 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3215 {
3216         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3217         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3218         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3219         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3220         uint16_t msix_vect = vsi->msix_intr;
3221         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3222         uint16_t queue_idx = 0;
3223         int record = 0;
3224         int i;
3225
3226         /* clear Rx/Tx queue interrupt */
3227         for (i = 0; i < vsi->nb_used_qps; i++) {
3228                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3229                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3230         }
3231
3232         /* PF bind interrupt */
3233         if (rte_intr_dp_is_en(intr_handle)) {
3234                 queue_idx = 0;
3235                 record = 1;
3236         }
3237
3238         for (i = 0; i < vsi->nb_used_qps; i++) {
3239                 if (nb_msix <= 1) {
3240                         if (!rte_intr_allow_others(intr_handle))
3241                                 msix_vect = ICE_MISC_VEC_ID;
3242
3243                         /* uio mapping all queue to one msix_vect */
3244                         __vsi_queues_bind_intr(vsi, msix_vect,
3245                                                vsi->base_queue + i,
3246                                                vsi->nb_used_qps - i);
3247
3248                         for (; !!record && i < vsi->nb_used_qps; i++)
3249                                 intr_handle->intr_vec[queue_idx + i] =
3250                                         msix_vect;
3251                         break;
3252                 }
3253
3254                 /* vfio 1:1 queue/msix_vect mapping */
3255                 __vsi_queues_bind_intr(vsi, msix_vect,
3256                                        vsi->base_queue + i, 1);
3257
3258                 if (!!record)
3259                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3260
3261                 msix_vect++;
3262                 nb_msix--;
3263         }
3264 }
3265
3266 void
3267 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3268 {
3269         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3270         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3271         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3272         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3273         uint16_t msix_intr, i;
3274
3275         if (rte_intr_allow_others(intr_handle))
3276                 for (i = 0; i < vsi->nb_used_qps; i++) {
3277                         msix_intr = vsi->msix_intr + i;
3278                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3279                                       GLINT_DYN_CTL_INTENA_M |
3280                                       GLINT_DYN_CTL_CLEARPBA_M |
3281                                       GLINT_DYN_CTL_ITR_INDX_M |
3282                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3283                 }
3284         else
3285                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3286                               GLINT_DYN_CTL_INTENA_M |
3287                               GLINT_DYN_CTL_CLEARPBA_M |
3288                               GLINT_DYN_CTL_ITR_INDX_M |
3289                               GLINT_DYN_CTL_WB_ON_ITR_M);
3290 }
3291
3292 static int
3293 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3294 {
3295         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3296         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3297         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3298         struct ice_vsi *vsi = pf->main_vsi;
3299         uint32_t intr_vector = 0;
3300
3301         rte_intr_disable(intr_handle);
3302
3303         /* check and configure queue intr-vector mapping */
3304         if ((rte_intr_cap_multiple(intr_handle) ||
3305              !RTE_ETH_DEV_SRIOV(dev).active) &&
3306             dev->data->dev_conf.intr_conf.rxq != 0) {
3307                 intr_vector = dev->data->nb_rx_queues;
3308                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3309                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3310                                     ICE_MAX_INTR_QUEUE_NUM);
3311                         return -ENOTSUP;
3312                 }
3313                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3314                         return -1;
3315         }
3316
3317         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3318                 intr_handle->intr_vec =
3319                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3320                             0);
3321                 if (!intr_handle->intr_vec) {
3322                         PMD_DRV_LOG(ERR,
3323                                     "Failed to allocate %d rx_queues intr_vec",
3324                                     dev->data->nb_rx_queues);
3325                         return -ENOMEM;
3326                 }
3327         }
3328
3329         /* Map queues with MSIX interrupt */
3330         vsi->nb_used_qps = dev->data->nb_rx_queues;
3331         ice_vsi_queues_bind_intr(vsi);
3332
3333         /* Enable interrupts for all the queues */
3334         ice_vsi_enable_queues_intr(vsi);
3335
3336         rte_intr_enable(intr_handle);
3337
3338         return 0;
3339 }
3340
3341 static void
3342 ice_get_init_link_status(struct rte_eth_dev *dev)
3343 {
3344         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3345         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3346         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3347         struct ice_link_status link_status;
3348         int ret;
3349
3350         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3351                                    &link_status, NULL);
3352         if (ret != ICE_SUCCESS) {
3353                 PMD_DRV_LOG(ERR, "Failed to get link info");
3354                 pf->init_link_up = false;
3355                 return;
3356         }
3357
3358         if (link_status.link_info & ICE_AQ_LINK_UP)
3359                 pf->init_link_up = true;
3360 }
3361
3362 static int
3363 ice_dev_start(struct rte_eth_dev *dev)
3364 {
3365         struct rte_eth_dev_data *data = dev->data;
3366         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368         struct ice_vsi *vsi = pf->main_vsi;
3369         uint16_t nb_rxq = 0;
3370         uint16_t nb_txq, i;
3371         uint16_t max_frame_size;
3372         int mask, ret;
3373
3374         /* program Tx queues' context in hardware */
3375         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3376                 ret = ice_tx_queue_start(dev, nb_txq);
3377                 if (ret) {
3378                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3379                         goto tx_err;
3380                 }
3381         }
3382
3383         /* program Rx queues' context in hardware*/
3384         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3385                 ret = ice_rx_queue_start(dev, nb_rxq);
3386                 if (ret) {
3387                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3388                         goto rx_err;
3389                 }
3390         }
3391
3392         ice_set_rx_function(dev);
3393         ice_set_tx_function(dev);
3394
3395         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3396                         ETH_VLAN_EXTEND_MASK;
3397         ret = ice_vlan_offload_set(dev, mask);
3398         if (ret) {
3399                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3400                 goto rx_err;
3401         }
3402
3403         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3404         if (ice_rxq_intr_setup(dev))
3405                 return -EIO;
3406
3407         /* Enable receiving broadcast packets and transmitting packets */
3408         ret = ice_set_vsi_promisc(hw, vsi->idx,
3409                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3410                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3411                                   0);
3412         if (ret != ICE_SUCCESS)
3413                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3414
3415         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3416                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3417                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3418                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3419                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3420                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3421                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3422                                      NULL);
3423         if (ret != ICE_SUCCESS)
3424                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3425
3426         ice_get_init_link_status(dev);
3427
3428         ice_dev_set_link_up(dev);
3429
3430         /* Call get_link_info aq commond to enable/disable LSE */
3431         ice_link_update(dev, 0);
3432
3433         pf->adapter_stopped = false;
3434
3435         /* Set the max frame size to default value*/
3436         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3437                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3438                 ICE_FRAME_SIZE_MAX;
3439
3440         /* Set the max frame size to HW*/
3441         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3442
3443         return 0;
3444
3445         /* stop the started queues if failed to start all queues */
3446 rx_err:
3447         for (i = 0; i < nb_rxq; i++)
3448                 ice_rx_queue_stop(dev, i);
3449 tx_err:
3450         for (i = 0; i < nb_txq; i++)
3451                 ice_tx_queue_stop(dev, i);
3452
3453         return -EIO;
3454 }
3455
3456 static int
3457 ice_dev_reset(struct rte_eth_dev *dev)
3458 {
3459         int ret;
3460
3461         if (dev->data->sriov.active)
3462                 return -ENOTSUP;
3463
3464         ret = ice_dev_uninit(dev);
3465         if (ret) {
3466                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3467                 return -ENXIO;
3468         }
3469
3470         ret = ice_dev_init(dev);
3471         if (ret) {
3472                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3473                 return -ENXIO;
3474         }
3475
3476         return 0;
3477 }
3478
3479 static int
3480 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3481 {
3482         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3483         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484         struct ice_vsi *vsi = pf->main_vsi;
3485         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3486         bool is_safe_mode = pf->adapter->is_safe_mode;
3487         u64 phy_type_low;
3488         u64 phy_type_high;
3489
3490         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3491         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3492         dev_info->max_rx_queues = vsi->nb_qps;
3493         dev_info->max_tx_queues = vsi->nb_qps;
3494         dev_info->max_mac_addrs = vsi->max_macaddrs;
3495         dev_info->max_vfs = pci_dev->max_vfs;
3496         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3497         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3498
3499         dev_info->rx_offload_capa =
3500                 DEV_RX_OFFLOAD_VLAN_STRIP |
3501                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3502                 DEV_RX_OFFLOAD_KEEP_CRC |
3503                 DEV_RX_OFFLOAD_SCATTER |
3504                 DEV_RX_OFFLOAD_VLAN_FILTER;
3505         dev_info->tx_offload_capa =
3506                 DEV_TX_OFFLOAD_VLAN_INSERT |
3507                 DEV_TX_OFFLOAD_TCP_TSO |
3508                 DEV_TX_OFFLOAD_MULTI_SEGS |
3509                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3510         dev_info->flow_type_rss_offloads = 0;
3511
3512         if (!is_safe_mode) {
3513                 dev_info->rx_offload_capa |=
3514                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3515                         DEV_RX_OFFLOAD_UDP_CKSUM |
3516                         DEV_RX_OFFLOAD_TCP_CKSUM |
3517                         DEV_RX_OFFLOAD_QINQ_STRIP |
3518                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3519                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3520                         DEV_RX_OFFLOAD_RSS_HASH;
3521                 dev_info->tx_offload_capa |=
3522                         DEV_TX_OFFLOAD_QINQ_INSERT |
3523                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3524                         DEV_TX_OFFLOAD_UDP_CKSUM |
3525                         DEV_TX_OFFLOAD_TCP_CKSUM |
3526                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3527                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3528                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3529                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3530         }
3531
3532         dev_info->rx_queue_offload_capa = 0;
3533         dev_info->tx_queue_offload_capa = 0;
3534
3535         dev_info->reta_size = pf->hash_lut_size;
3536         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3537
3538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3539                 .rx_thresh = {
3540                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3541                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3542                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3543                 },
3544                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3545                 .rx_drop_en = 0,
3546                 .offloads = 0,
3547         };
3548
3549         dev_info->default_txconf = (struct rte_eth_txconf) {
3550                 .tx_thresh = {
3551                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3552                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3553                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3554                 },
3555                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3556                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3557                 .offloads = 0,
3558         };
3559
3560         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3561                 .nb_max = ICE_MAX_RING_DESC,
3562                 .nb_min = ICE_MIN_RING_DESC,
3563                 .nb_align = ICE_ALIGN_RING_DESC,
3564         };
3565
3566         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3567                 .nb_max = ICE_MAX_RING_DESC,
3568                 .nb_min = ICE_MIN_RING_DESC,
3569                 .nb_align = ICE_ALIGN_RING_DESC,
3570         };
3571
3572         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3573                                ETH_LINK_SPEED_100M |
3574                                ETH_LINK_SPEED_1G |
3575                                ETH_LINK_SPEED_2_5G |
3576                                ETH_LINK_SPEED_5G |
3577                                ETH_LINK_SPEED_10G |
3578                                ETH_LINK_SPEED_20G |
3579                                ETH_LINK_SPEED_25G;
3580
3581         phy_type_low = hw->port_info->phy.phy_type_low;
3582         phy_type_high = hw->port_info->phy.phy_type_high;
3583
3584         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3585                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3586
3587         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3588                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3589                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3590
3591         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3592         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3593
3594         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3595         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3596         dev_info->default_rxportconf.nb_queues = 1;
3597         dev_info->default_txportconf.nb_queues = 1;
3598         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3599         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3600
3601         return 0;
3602 }
3603
3604 static inline int
3605 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3606                             struct rte_eth_link *link)
3607 {
3608         struct rte_eth_link *dst = link;
3609         struct rte_eth_link *src = &dev->data->dev_link;
3610
3611         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3612                                 *(uint64_t *)src) == 0)
3613                 return -1;
3614
3615         return 0;
3616 }
3617
3618 static inline int
3619 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3620                              struct rte_eth_link *link)
3621 {
3622         struct rte_eth_link *dst = &dev->data->dev_link;
3623         struct rte_eth_link *src = link;
3624
3625         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3626                                 *(uint64_t *)src) == 0)
3627                 return -1;
3628
3629         return 0;
3630 }
3631
3632 static int
3633 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3634 {
3635 #define CHECK_INTERVAL 100  /* 100ms */
3636 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3637         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638         struct ice_link_status link_status;
3639         struct rte_eth_link link, old;
3640         int status;
3641         unsigned int rep_cnt = MAX_REPEAT_TIME;
3642         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3643
3644         memset(&link, 0, sizeof(link));
3645         memset(&old, 0, sizeof(old));
3646         memset(&link_status, 0, sizeof(link_status));
3647         ice_atomic_read_link_status(dev, &old);
3648
3649         do {
3650                 /* Get link status information from hardware */
3651                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3652                                               &link_status, NULL);
3653                 if (status != ICE_SUCCESS) {
3654                         link.link_speed = ETH_SPEED_NUM_100M;
3655                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3656                         PMD_DRV_LOG(ERR, "Failed to get link info");
3657                         goto out;
3658                 }
3659
3660                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3661                 if (!wait_to_complete || link.link_status)
3662                         break;
3663
3664                 rte_delay_ms(CHECK_INTERVAL);
3665         } while (--rep_cnt);
3666
3667         if (!link.link_status)
3668                 goto out;
3669
3670         /* Full-duplex operation at all supported speeds */
3671         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3672
3673         /* Parse the link status */
3674         switch (link_status.link_speed) {
3675         case ICE_AQ_LINK_SPEED_10MB:
3676                 link.link_speed = ETH_SPEED_NUM_10M;
3677                 break;
3678         case ICE_AQ_LINK_SPEED_100MB:
3679                 link.link_speed = ETH_SPEED_NUM_100M;
3680                 break;
3681         case ICE_AQ_LINK_SPEED_1000MB:
3682                 link.link_speed = ETH_SPEED_NUM_1G;
3683                 break;
3684         case ICE_AQ_LINK_SPEED_2500MB:
3685                 link.link_speed = ETH_SPEED_NUM_2_5G;
3686                 break;
3687         case ICE_AQ_LINK_SPEED_5GB:
3688                 link.link_speed = ETH_SPEED_NUM_5G;
3689                 break;
3690         case ICE_AQ_LINK_SPEED_10GB:
3691                 link.link_speed = ETH_SPEED_NUM_10G;
3692                 break;
3693         case ICE_AQ_LINK_SPEED_20GB:
3694                 link.link_speed = ETH_SPEED_NUM_20G;
3695                 break;
3696         case ICE_AQ_LINK_SPEED_25GB:
3697                 link.link_speed = ETH_SPEED_NUM_25G;
3698                 break;
3699         case ICE_AQ_LINK_SPEED_40GB:
3700                 link.link_speed = ETH_SPEED_NUM_40G;
3701                 break;
3702         case ICE_AQ_LINK_SPEED_50GB:
3703                 link.link_speed = ETH_SPEED_NUM_50G;
3704                 break;
3705         case ICE_AQ_LINK_SPEED_100GB:
3706                 link.link_speed = ETH_SPEED_NUM_100G;
3707                 break;
3708         case ICE_AQ_LINK_SPEED_UNKNOWN:
3709                 PMD_DRV_LOG(ERR, "Unknown link speed");
3710                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3711                 break;
3712         default:
3713                 PMD_DRV_LOG(ERR, "None link speed");
3714                 link.link_speed = ETH_SPEED_NUM_NONE;
3715                 break;
3716         }
3717
3718         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3719                               ETH_LINK_SPEED_FIXED);
3720
3721 out:
3722         ice_atomic_write_link_status(dev, &link);
3723         if (link.link_status == old.link_status)
3724                 return -1;
3725
3726         return 0;
3727 }
3728
3729 /* Force the physical link state by getting the current PHY capabilities from
3730  * hardware and setting the PHY config based on the determined capabilities. If
3731  * link changes, link event will be triggered because both the Enable Automatic
3732  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3733  */
3734 static enum ice_status
3735 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3736 {
3737         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3738         struct ice_aqc_get_phy_caps_data *pcaps;
3739         struct ice_port_info *pi;
3740         enum ice_status status;
3741
3742         if (!hw || !hw->port_info)
3743                 return ICE_ERR_PARAM;
3744
3745         pi = hw->port_info;
3746
3747         pcaps = (struct ice_aqc_get_phy_caps_data *)
3748                 ice_malloc(hw, sizeof(*pcaps));
3749         if (!pcaps)
3750                 return ICE_ERR_NO_MEMORY;
3751
3752         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3753                                      pcaps, NULL);
3754         if (status)
3755                 goto out;
3756
3757         /* No change in link */
3758         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3759             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3760                 goto out;
3761
3762         cfg.phy_type_low = pcaps->phy_type_low;
3763         cfg.phy_type_high = pcaps->phy_type_high;
3764         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3765         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3766         cfg.eee_cap = pcaps->eee_cap;
3767         cfg.eeer_value = pcaps->eeer_value;
3768         cfg.link_fec_opt = pcaps->link_fec_options;
3769         if (link_up)
3770                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3771         else
3772                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3773
3774         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3775
3776 out:
3777         ice_free(hw, pcaps);
3778         return status;
3779 }
3780
3781 static int
3782 ice_dev_set_link_up(struct rte_eth_dev *dev)
3783 {
3784         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785
3786         return ice_force_phys_link_state(hw, true);
3787 }
3788
3789 static int
3790 ice_dev_set_link_down(struct rte_eth_dev *dev)
3791 {
3792         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793
3794         return ice_force_phys_link_state(hw, false);
3795 }
3796
3797 static int
3798 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3799 {
3800         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3801         struct rte_eth_dev_data *dev_data = pf->dev_data;
3802         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3803
3804         /* check if mtu is within the allowed range */
3805         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3806                 return -EINVAL;
3807
3808         /* mtu setting is forbidden if port is start */
3809         if (dev_data->dev_started) {
3810                 PMD_DRV_LOG(ERR,
3811                             "port %d must be stopped before configuration",
3812                             dev_data->port_id);
3813                 return -EBUSY;
3814         }
3815
3816         if (frame_size > ICE_ETH_MAX_LEN)
3817                 dev_data->dev_conf.rxmode.offloads |=
3818                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3819         else
3820                 dev_data->dev_conf.rxmode.offloads &=
3821                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3822
3823         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3824
3825         return 0;
3826 }
3827
3828 static int ice_macaddr_set(struct rte_eth_dev *dev,
3829                            struct rte_ether_addr *mac_addr)
3830 {
3831         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3833         struct ice_vsi *vsi = pf->main_vsi;
3834         struct ice_mac_filter *f;
3835         uint8_t flags = 0;
3836         int ret;
3837
3838         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3839                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3840                 return -EINVAL;
3841         }
3842
3843         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3844                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3845                         break;
3846         }
3847
3848         if (!f) {
3849                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3850                 return -EIO;
3851         }
3852
3853         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3854         if (ret != ICE_SUCCESS) {
3855                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3856                 return -EIO;
3857         }
3858         ret = ice_add_mac_filter(vsi, mac_addr);
3859         if (ret != ICE_SUCCESS) {
3860                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3861                 return -EIO;
3862         }
3863         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3864
3865         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3866         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3867         if (ret != ICE_SUCCESS)
3868                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3869
3870         return 0;
3871 }
3872
3873 /* Add a MAC address, and update filters */
3874 static int
3875 ice_macaddr_add(struct rte_eth_dev *dev,
3876                 struct rte_ether_addr *mac_addr,
3877                 __rte_unused uint32_t index,
3878                 __rte_unused uint32_t pool)
3879 {
3880         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3881         struct ice_vsi *vsi = pf->main_vsi;
3882         int ret;
3883
3884         ret = ice_add_mac_filter(vsi, mac_addr);
3885         if (ret != ICE_SUCCESS) {
3886                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3887                 return -EINVAL;
3888         }
3889
3890         return ICE_SUCCESS;
3891 }
3892
3893 /* Remove a MAC address, and update filters */
3894 static void
3895 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3896 {
3897         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3898         struct ice_vsi *vsi = pf->main_vsi;
3899         struct rte_eth_dev_data *data = dev->data;
3900         struct rte_ether_addr *macaddr;
3901         int ret;
3902
3903         macaddr = &data->mac_addrs[index];
3904         ret = ice_remove_mac_filter(vsi, macaddr);
3905         if (ret) {
3906                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3907                 return;
3908         }
3909 }
3910
3911 static int
3912 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3913 {
3914         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3915         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3916         struct ice_vsi *vsi = pf->main_vsi;
3917         int ret;
3918
3919         PMD_INIT_FUNC_TRACE();
3920
3921         /**
3922          * Vlan 0 is the generic filter for untagged packets
3923          * and can't be removed or added by user.
3924          */
3925         if (vlan_id == 0)
3926                 return 0;
3927
3928         if (on) {
3929                 ret = ice_add_vlan_filter(vsi, &vlan);
3930                 if (ret < 0) {
3931                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3932                         return -EINVAL;
3933                 }
3934         } else {
3935                 ret = ice_remove_vlan_filter(vsi, &vlan);
3936                 if (ret < 0) {
3937                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3938                         return -EINVAL;
3939                 }
3940         }
3941
3942         return 0;
3943 }
3944
3945 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3946  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3947  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3948  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3949  *
3950  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3951  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3952  * traffic in SVM, since the VLAN TPID isn't part of filtering.
3953  *
3954  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3955  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3956  * part of filtering.
3957  */
3958 static int
3959 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3960 {
3961         struct ice_vlan vlan;
3962         int err;
3963
3964         vlan = ICE_VLAN(0, 0);
3965         err = ice_add_vlan_filter(vsi, &vlan);
3966         if (err) {
3967                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3968                 return err;
3969         }
3970
3971         /* in SVM both VLAN 0 filters are identical */
3972         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3973                 return 0;
3974
3975         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3976         err = ice_add_vlan_filter(vsi, &vlan);
3977         if (err) {
3978                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3979                 return err;
3980         }
3981
3982         return 0;
3983 }
3984
3985 /*
3986  * Delete the VLAN 0 filters in the same manner that they were added in
3987  * ice_vsi_add_vlan_zero.
3988  */
3989 static int
3990 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3991 {
3992         struct ice_vlan vlan;
3993         int err;
3994
3995         vlan = ICE_VLAN(0, 0);
3996         err = ice_remove_vlan_filter(vsi, &vlan);
3997         if (err) {
3998                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
3999                 return err;
4000         }
4001
4002         /* in SVM both VLAN 0 filters are identical */
4003         if (!ice_is_dvm_ena(&vsi->adapter->hw))
4004                 return 0;
4005
4006         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4007         err = ice_remove_vlan_filter(vsi, &vlan);
4008         if (err) {
4009                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4010                 return err;
4011         }
4012
4013         return 0;
4014 }
4015
4016 /* Configure vlan filter on or off */
4017 static int
4018 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4019 {
4020         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4021         struct ice_vsi_ctx ctxt;
4022         uint8_t sw_flags2;
4023         int ret = 0;
4024
4025         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4026
4027         if (on)
4028                 vsi->info.sw_flags2 |= sw_flags2;
4029         else
4030                 vsi->info.sw_flags2 &= ~sw_flags2;
4031
4032         vsi->info.sw_id = hw->port_info->sw_id;
4033         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4034         ctxt.info.valid_sections =
4035                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4036                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4037         ctxt.vsi_num = vsi->vsi_id;
4038
4039         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4040         if (ret) {
4041                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4042                             on ? "enable" : "disable");
4043                 return -EINVAL;
4044         } else {
4045                 vsi->info.valid_sections |=
4046                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4047                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4048         }
4049
4050         /* consist with other drivers, allow untagged packet when vlan filter on */
4051         if (on)
4052                 ret = ice_vsi_add_vlan_zero(vsi);
4053         else
4054                 ret = ice_vsi_del_vlan_zero(vsi);
4055
4056         return 0;
4057 }
4058
4059 /* Manage VLAN stripping for the VSI for Rx */
4060 static int
4061 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4062 {
4063         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4064         struct ice_vsi_ctx ctxt;
4065         enum ice_status status;
4066         int err = 0;
4067
4068         /* do not allow modifying VLAN stripping when a port VLAN is configured
4069          * on this VSI
4070          */
4071         if (vsi->info.port_based_inner_vlan)
4072                 return 0;
4073
4074         memset(&ctxt, 0, sizeof(ctxt));
4075
4076         if (ena)
4077                 /* Strip VLAN tag from Rx packet and put it in the desc */
4078                 ctxt.info.inner_vlan_flags =
4079                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4080         else
4081                 /* Disable stripping. Leave tag in packet */
4082                 ctxt.info.inner_vlan_flags =
4083                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4084
4085         /* Allow all packets untagged/tagged */
4086         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4087
4088         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4089
4090         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4091         if (status) {
4092                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4093                             ena ? "enable" : "disable");
4094                 err = -EIO;
4095         } else {
4096                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4097         }
4098
4099         return err;
4100 }
4101
4102 static int
4103 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4104 {
4105         return ice_vsi_manage_vlan_stripping(vsi, true);
4106 }
4107
4108 static int
4109 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4110 {
4111         return ice_vsi_manage_vlan_stripping(vsi, false);
4112 }
4113
4114 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4115 {
4116         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4117         struct ice_vsi_ctx ctxt;
4118         enum ice_status status;
4119         int err = 0;
4120
4121         /* do not allow modifying VLAN stripping when a port VLAN is configured
4122          * on this VSI
4123          */
4124         if (vsi->info.port_based_outer_vlan)
4125                 return 0;
4126
4127         memset(&ctxt, 0, sizeof(ctxt));
4128
4129         ctxt.info.valid_sections =
4130                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4131         /* clear current outer VLAN strip settings */
4132         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4133                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4134         ctxt.info.outer_vlan_flags |=
4135                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4136                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4137                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4138                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4139
4140         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4141         if (status) {
4142                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4143                 err = -EIO;
4144         } else {
4145                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4146         }
4147
4148         return err;
4149 }
4150
4151 static int
4152 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4153 {
4154         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4155         struct ice_vsi_ctx ctxt;
4156         enum ice_status status;
4157         int err = 0;
4158
4159         if (vsi->info.port_based_outer_vlan)
4160                 return 0;
4161
4162         memset(&ctxt, 0, sizeof(ctxt));
4163
4164         ctxt.info.valid_sections =
4165                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4166         /* clear current outer VLAN strip settings */
4167         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4168                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4169         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4170                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4171
4172         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4173         if (status) {
4174                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4175                 err = -EIO;
4176         } else {
4177                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4178         }
4179
4180         return err;
4181 }
4182
4183 static int
4184 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4185 {
4186         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4187         int ret;
4188
4189         if (ice_is_dvm_ena(hw)) {
4190                 if (ena)
4191                         ret = ice_vsi_ena_outer_stripping(vsi);
4192                 else
4193                         ret = ice_vsi_dis_outer_stripping(vsi);
4194         } else {
4195                 if (ena)
4196                         ret = ice_vsi_ena_inner_stripping(vsi);
4197                 else
4198                         ret = ice_vsi_dis_inner_stripping(vsi);
4199         }
4200
4201         return ret;
4202 }
4203
4204 static int
4205 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4206 {
4207         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4208         struct ice_vsi *vsi = pf->main_vsi;
4209         struct rte_eth_rxmode *rxmode;
4210
4211         rxmode = &dev->data->dev_conf.rxmode;
4212         if (mask & ETH_VLAN_FILTER_MASK) {
4213                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4214                         ice_vsi_config_vlan_filter(vsi, true);
4215                 else
4216                         ice_vsi_config_vlan_filter(vsi, false);
4217         }
4218
4219         if (mask & ETH_VLAN_STRIP_MASK) {
4220                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4221                         ice_vsi_config_vlan_stripping(vsi, true);
4222                 else
4223                         ice_vsi_config_vlan_stripping(vsi, false);
4224         }
4225
4226         return 0;
4227 }
4228
4229 static int
4230 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4231 {
4232         struct ice_aq_get_set_rss_lut_params lut_params;
4233         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4234         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4235         int ret;
4236
4237         if (!lut)
4238                 return -EINVAL;
4239
4240         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4241                 lut_params.vsi_handle = vsi->idx;
4242                 lut_params.lut_size = lut_size;
4243                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4244                 lut_params.lut = lut;
4245                 lut_params.global_lut_id = 0;
4246                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4247                 if (ret) {
4248                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4249                         return -EINVAL;
4250                 }
4251         } else {
4252                 uint64_t *lut_dw = (uint64_t *)lut;
4253                 uint16_t i, lut_size_dw = lut_size / 4;
4254
4255                 for (i = 0; i < lut_size_dw; i++)
4256                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4257         }
4258
4259         return 0;
4260 }
4261
4262 static int
4263 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4264 {
4265         struct ice_aq_get_set_rss_lut_params lut_params;
4266         struct ice_pf *pf;
4267         struct ice_hw *hw;
4268         int ret;
4269
4270         if (!vsi || !lut)
4271                 return -EINVAL;
4272
4273         pf = ICE_VSI_TO_PF(vsi);
4274         hw = ICE_VSI_TO_HW(vsi);
4275
4276         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4277                 lut_params.vsi_handle = vsi->idx;
4278                 lut_params.lut_size = lut_size;
4279                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4280                 lut_params.lut = lut;
4281                 lut_params.global_lut_id = 0;
4282                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4283                 if (ret) {
4284                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4285                         return -EINVAL;
4286                 }
4287         } else {
4288                 uint64_t *lut_dw = (uint64_t *)lut;
4289                 uint16_t i, lut_size_dw = lut_size / 4;
4290
4291                 for (i = 0; i < lut_size_dw; i++)
4292                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4293
4294                 ice_flush(hw);
4295         }
4296
4297         return 0;
4298 }
4299
4300 static int
4301 ice_rss_reta_update(struct rte_eth_dev *dev,
4302                     struct rte_eth_rss_reta_entry64 *reta_conf,
4303                     uint16_t reta_size)
4304 {
4305         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4306         uint16_t i, lut_size = pf->hash_lut_size;
4307         uint16_t idx, shift;
4308         uint8_t *lut;
4309         int ret;
4310
4311         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4312             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4313             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4314                 PMD_DRV_LOG(ERR,
4315                             "The size of hash lookup table configured (%d)"
4316                             "doesn't match the number hardware can "
4317                             "supported (128, 512, 2048)",
4318                             reta_size);
4319                 return -EINVAL;
4320         }
4321
4322         /* It MUST use the current LUT size to get the RSS lookup table,
4323          * otherwise if will fail with -100 error code.
4324          */
4325         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4326         if (!lut) {
4327                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4328                 return -ENOMEM;
4329         }
4330         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4331         if (ret)
4332                 goto out;
4333
4334         for (i = 0; i < reta_size; i++) {
4335                 idx = i / RTE_RETA_GROUP_SIZE;
4336                 shift = i % RTE_RETA_GROUP_SIZE;
4337                 if (reta_conf[idx].mask & (1ULL << shift))
4338                         lut[i] = reta_conf[idx].reta[shift];
4339         }
4340         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4341         if (ret == 0 && lut_size != reta_size) {
4342                 PMD_DRV_LOG(INFO,
4343                             "The size of hash lookup table is changed from (%d) to (%d)",
4344                             lut_size, reta_size);
4345                 pf->hash_lut_size = reta_size;
4346         }
4347
4348 out:
4349         rte_free(lut);
4350
4351         return ret;
4352 }
4353
4354 static int
4355 ice_rss_reta_query(struct rte_eth_dev *dev,
4356                    struct rte_eth_rss_reta_entry64 *reta_conf,
4357                    uint16_t reta_size)
4358 {
4359         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4360         uint16_t i, lut_size = pf->hash_lut_size;
4361         uint16_t idx, shift;
4362         uint8_t *lut;
4363         int ret;
4364
4365         if (reta_size != lut_size) {
4366                 PMD_DRV_LOG(ERR,
4367                             "The size of hash lookup table configured (%d)"
4368                             "doesn't match the number hardware can "
4369                             "supported (%d)",
4370                             reta_size, lut_size);
4371                 return -EINVAL;
4372         }
4373
4374         lut = rte_zmalloc(NULL, reta_size, 0);
4375         if (!lut) {
4376                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4377                 return -ENOMEM;
4378         }
4379
4380         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4381         if (ret)
4382                 goto out;
4383
4384         for (i = 0; i < reta_size; i++) {
4385                 idx = i / RTE_RETA_GROUP_SIZE;
4386                 shift = i % RTE_RETA_GROUP_SIZE;
4387                 if (reta_conf[idx].mask & (1ULL << shift))
4388                         reta_conf[idx].reta[shift] = lut[i];
4389         }
4390
4391 out:
4392         rte_free(lut);
4393
4394         return ret;
4395 }
4396
4397 static int
4398 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4399 {
4400         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4401         int ret = 0;
4402
4403         if (!key || key_len == 0) {
4404                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4405                 return 0;
4406         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4407                    sizeof(uint32_t)) {
4408                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4409                 return -EINVAL;
4410         }
4411
4412         struct ice_aqc_get_set_rss_keys *key_dw =
4413                 (struct ice_aqc_get_set_rss_keys *)key;
4414
4415         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4416         if (ret) {
4417                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4418                 ret = -EINVAL;
4419         }
4420
4421         return ret;
4422 }
4423
4424 static int
4425 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4426 {
4427         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4428         int ret;
4429
4430         if (!key || !key_len)
4431                 return -EINVAL;
4432
4433         ret = ice_aq_get_rss_key
4434                 (hw, vsi->idx,
4435                  (struct ice_aqc_get_set_rss_keys *)key);
4436         if (ret) {
4437                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4438                 return -EINVAL;
4439         }
4440         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4441
4442         return 0;
4443 }
4444
4445 static int
4446 ice_rss_hash_update(struct rte_eth_dev *dev,
4447                     struct rte_eth_rss_conf *rss_conf)
4448 {
4449         enum ice_status status = ICE_SUCCESS;
4450         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4451         struct ice_vsi *vsi = pf->main_vsi;
4452
4453         /* set hash key */
4454         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4455         if (status)
4456                 return status;
4457
4458         if (rss_conf->rss_hf == 0) {
4459                 pf->rss_hf = 0;
4460                 return 0;
4461         }
4462
4463         /* RSS hash configuration */
4464         ice_rss_hash_set(pf, rss_conf->rss_hf);
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4471                       struct rte_eth_rss_conf *rss_conf)
4472 {
4473         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4474         struct ice_vsi *vsi = pf->main_vsi;
4475
4476         ice_get_rss_key(vsi, rss_conf->rss_key,
4477                         &rss_conf->rss_key_len);
4478
4479         rss_conf->rss_hf = pf->rss_hf;
4480         return 0;
4481 }
4482
4483 static int
4484 ice_promisc_enable(struct rte_eth_dev *dev)
4485 {
4486         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4487         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488         struct ice_vsi *vsi = pf->main_vsi;
4489         enum ice_status status;
4490         uint8_t pmask;
4491         int ret = 0;
4492
4493         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4494                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4495
4496         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4497         switch (status) {
4498         case ICE_ERR_ALREADY_EXISTS:
4499                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4500         case ICE_SUCCESS:
4501                 break;
4502         default:
4503                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4504                 ret = -EAGAIN;
4505         }
4506
4507         return ret;
4508 }
4509
4510 static int
4511 ice_promisc_disable(struct rte_eth_dev *dev)
4512 {
4513         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4514         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515         struct ice_vsi *vsi = pf->main_vsi;
4516         enum ice_status status;
4517         uint8_t pmask;
4518         int ret = 0;
4519
4520         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4521                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4522
4523         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4524         if (status != ICE_SUCCESS) {
4525                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4526                 ret = -EAGAIN;
4527         }
4528
4529         return ret;
4530 }
4531
4532 static int
4533 ice_allmulti_enable(struct rte_eth_dev *dev)
4534 {
4535         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4536         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4537         struct ice_vsi *vsi = pf->main_vsi;
4538         enum ice_status status;
4539         uint8_t pmask;
4540         int ret = 0;
4541
4542         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4543
4544         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4545
4546         switch (status) {
4547         case ICE_ERR_ALREADY_EXISTS:
4548                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4549         case ICE_SUCCESS:
4550                 break;
4551         default:
4552                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4553                 ret = -EAGAIN;
4554         }
4555
4556         return ret;
4557 }
4558
4559 static int
4560 ice_allmulti_disable(struct rte_eth_dev *dev)
4561 {
4562         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564         struct ice_vsi *vsi = pf->main_vsi;
4565         enum ice_status status;
4566         uint8_t pmask;
4567         int ret = 0;
4568
4569         if (dev->data->promiscuous == 1)
4570                 return 0; /* must remain in all_multicast mode */
4571
4572         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4573
4574         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4575         if (status != ICE_SUCCESS) {
4576                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4577                 ret = -EAGAIN;
4578         }
4579
4580         return ret;
4581 }
4582
4583 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4584                                     uint16_t queue_id)
4585 {
4586         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4588         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589         uint32_t val;
4590         uint16_t msix_intr;
4591
4592         msix_intr = intr_handle->intr_vec[queue_id];
4593
4594         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4595               GLINT_DYN_CTL_ITR_INDX_M;
4596         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4597
4598         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4599         rte_intr_ack(&pci_dev->intr_handle);
4600
4601         return 0;
4602 }
4603
4604 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4605                                      uint16_t queue_id)
4606 {
4607         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4608         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4609         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610         uint16_t msix_intr;
4611
4612         msix_intr = intr_handle->intr_vec[queue_id];
4613
4614         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4615
4616         return 0;
4617 }
4618
4619 static int
4620 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4621 {
4622         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623         u8 ver, patch;
4624         u16 build;
4625         int ret;
4626
4627         ver = hw->flash.orom.major;
4628         patch = hw->flash.orom.patch;
4629         build = hw->flash.orom.build;
4630
4631         ret = snprintf(fw_version, fw_size,
4632                         "%x.%02x 0x%08x %d.%d.%d",
4633                         hw->flash.nvm.major,
4634                         hw->flash.nvm.minor,
4635                         hw->flash.nvm.eetrack,
4636                         ver, build, patch);
4637
4638         /* add the size of '\0' */
4639         ret += 1;
4640         if (fw_size < (u32)ret)
4641                 return ret;
4642         else
4643                 return 0;
4644 }
4645
4646 static int
4647 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4648 {
4649         struct ice_hw *hw;
4650         struct ice_vsi_ctx ctxt;
4651         uint8_t vlan_flags = 0;
4652         int ret;
4653
4654         if (!vsi || !info) {
4655                 PMD_DRV_LOG(ERR, "invalid parameters");
4656                 return -EINVAL;
4657         }
4658
4659         if (info->on) {
4660                 vsi->info.port_based_inner_vlan = info->config.pvid;
4661                 /**
4662                  * If insert pvid is enabled, only tagged pkts are
4663                  * allowed to be sent out.
4664                  */
4665                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4666                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4667         } else {
4668                 vsi->info.port_based_inner_vlan = 0;
4669                 if (info->config.reject.tagged == 0)
4670                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4671
4672                 if (info->config.reject.untagged == 0)
4673                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4674         }
4675         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4676                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4677         vsi->info.inner_vlan_flags |= vlan_flags;
4678         memset(&ctxt, 0, sizeof(ctxt));
4679         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4680         ctxt.info.valid_sections =
4681                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4682         ctxt.vsi_num = vsi->vsi_id;
4683
4684         hw = ICE_VSI_TO_HW(vsi);
4685         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4686         if (ret != ICE_SUCCESS) {
4687                 PMD_DRV_LOG(ERR,
4688                             "update VSI for VLAN insert failed, err %d",
4689                             ret);
4690                 return -EINVAL;
4691         }
4692
4693         vsi->info.valid_sections |=
4694                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4695
4696         return ret;
4697 }
4698
4699 static int
4700 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4701 {
4702         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4703         struct ice_vsi *vsi = pf->main_vsi;
4704         struct rte_eth_dev_data *data = pf->dev_data;
4705         struct ice_vsi_vlan_pvid_info info;
4706         int ret;
4707
4708         memset(&info, 0, sizeof(info));
4709         info.on = on;
4710         if (info.on) {
4711                 info.config.pvid = pvid;
4712         } else {
4713                 info.config.reject.tagged =
4714                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4715                 info.config.reject.untagged =
4716                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4717         }
4718
4719         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4720         if (ret < 0) {
4721                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4722                 return -EINVAL;
4723         }
4724
4725         return 0;
4726 }
4727
4728 static int
4729 ice_get_eeprom_length(struct rte_eth_dev *dev)
4730 {
4731         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4732
4733         return hw->flash.flash_size;
4734 }
4735
4736 static int
4737 ice_get_eeprom(struct rte_eth_dev *dev,
4738                struct rte_dev_eeprom_info *eeprom)
4739 {
4740         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         enum ice_status status = ICE_SUCCESS;
4742         uint8_t *data = eeprom->data;
4743
4744         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4745
4746         status = ice_acquire_nvm(hw, ICE_RES_READ);
4747         if (status) {
4748                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4749                 return -EIO;
4750         }
4751
4752         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4753                                    data, false);
4754
4755         ice_release_nvm(hw);
4756
4757         if (status) {
4758                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4759                 return -EIO;
4760         }
4761
4762         return 0;
4763 }
4764
4765 static void
4766 ice_stat_update_32(struct ice_hw *hw,
4767                    uint32_t reg,
4768                    bool offset_loaded,
4769                    uint64_t *offset,
4770                    uint64_t *stat)
4771 {
4772         uint64_t new_data;
4773
4774         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4775         if (!offset_loaded)
4776                 *offset = new_data;
4777
4778         if (new_data >= *offset)
4779                 *stat = (uint64_t)(new_data - *offset);
4780         else
4781                 *stat = (uint64_t)((new_data +
4782                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4783                                    - *offset);
4784 }
4785
4786 static void
4787 ice_stat_update_40(struct ice_hw *hw,
4788                    uint32_t hireg,
4789                    uint32_t loreg,
4790                    bool offset_loaded,
4791                    uint64_t *offset,
4792                    uint64_t *stat)
4793 {
4794         uint64_t new_data;
4795
4796         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4797         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4798                     ICE_32_BIT_WIDTH;
4799
4800         if (!offset_loaded)
4801                 *offset = new_data;
4802
4803         if (new_data >= *offset)
4804                 *stat = new_data - *offset;
4805         else
4806                 *stat = (uint64_t)((new_data +
4807                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4808                                    *offset);
4809
4810         *stat &= ICE_40_BIT_MASK;
4811 }
4812
4813 /* Get all the statistics of a VSI */
4814 static void
4815 ice_update_vsi_stats(struct ice_vsi *vsi)
4816 {
4817         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4818         struct ice_eth_stats *nes = &vsi->eth_stats;
4819         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4820         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4821
4822         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4823                            vsi->offset_loaded, &oes->rx_bytes,
4824                            &nes->rx_bytes);
4825         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4826                            vsi->offset_loaded, &oes->rx_unicast,
4827                            &nes->rx_unicast);
4828         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4829                            vsi->offset_loaded, &oes->rx_multicast,
4830                            &nes->rx_multicast);
4831         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4832                            vsi->offset_loaded, &oes->rx_broadcast,
4833                            &nes->rx_broadcast);
4834         /* enlarge the limitation when rx_bytes overflowed */
4835         if (vsi->offset_loaded) {
4836                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4837                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4838                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4839         }
4840         vsi->old_rx_bytes = nes->rx_bytes;
4841         /* exclude CRC bytes */
4842         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4843                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4844
4845         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4846                            &oes->rx_discards, &nes->rx_discards);
4847         /* GLV_REPC not supported */
4848         /* GLV_RMPC not supported */
4849         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4850                            &oes->rx_unknown_protocol,
4851                            &nes->rx_unknown_protocol);
4852         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4853                            vsi->offset_loaded, &oes->tx_bytes,
4854                            &nes->tx_bytes);
4855         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4856                            vsi->offset_loaded, &oes->tx_unicast,
4857                            &nes->tx_unicast);
4858         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4859                            vsi->offset_loaded, &oes->tx_multicast,
4860                            &nes->tx_multicast);
4861         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4862                            vsi->offset_loaded,  &oes->tx_broadcast,
4863                            &nes->tx_broadcast);
4864         /* GLV_TDPC not supported */
4865         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4866                            &oes->tx_errors, &nes->tx_errors);
4867         /* enlarge the limitation when tx_bytes overflowed */
4868         if (vsi->offset_loaded) {
4869                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4870                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4871                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4872         }
4873         vsi->old_tx_bytes = nes->tx_bytes;
4874         vsi->offset_loaded = true;
4875
4876         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4877                     vsi->vsi_id);
4878         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4879         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4880         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4881         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4882         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4883         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4884                     nes->rx_unknown_protocol);
4885         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4886         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4887         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4888         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4889         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4890         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4891         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4892                     vsi->vsi_id);
4893 }
4894
4895 static void
4896 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4897 {
4898         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4899         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4900
4901         /* Get statistics of struct ice_eth_stats */
4902         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4903                            GLPRT_GORCL(hw->port_info->lport),
4904                            pf->offset_loaded, &os->eth.rx_bytes,
4905                            &ns->eth.rx_bytes);
4906         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4907                            GLPRT_UPRCL(hw->port_info->lport),
4908                            pf->offset_loaded, &os->eth.rx_unicast,
4909                            &ns->eth.rx_unicast);
4910         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4911                            GLPRT_MPRCL(hw->port_info->lport),
4912                            pf->offset_loaded, &os->eth.rx_multicast,
4913                            &ns->eth.rx_multicast);
4914         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4915                            GLPRT_BPRCL(hw->port_info->lport),
4916                            pf->offset_loaded, &os->eth.rx_broadcast,
4917                            &ns->eth.rx_broadcast);
4918         ice_stat_update_32(hw, PRTRPB_RDPC,
4919                            pf->offset_loaded, &os->eth.rx_discards,
4920                            &ns->eth.rx_discards);
4921         /* enlarge the limitation when rx_bytes overflowed */
4922         if (pf->offset_loaded) {
4923                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4924                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4925                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4926         }
4927         pf->old_rx_bytes = ns->eth.rx_bytes;
4928
4929         /* Workaround: CRC size should not be included in byte statistics,
4930          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4931          * packet.
4932          */
4933         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4934                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4935
4936         /* GLPRT_REPC not supported */
4937         /* GLPRT_RMPC not supported */
4938         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4939                            pf->offset_loaded,
4940                            &os->eth.rx_unknown_protocol,
4941                            &ns->eth.rx_unknown_protocol);
4942         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4943                            GLPRT_GOTCL(hw->port_info->lport),
4944                            pf->offset_loaded, &os->eth.tx_bytes,
4945                            &ns->eth.tx_bytes);
4946         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4947                            GLPRT_UPTCL(hw->port_info->lport),
4948                            pf->offset_loaded, &os->eth.tx_unicast,
4949                            &ns->eth.tx_unicast);
4950         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4951                            GLPRT_MPTCL(hw->port_info->lport),
4952                            pf->offset_loaded, &os->eth.tx_multicast,
4953                            &ns->eth.tx_multicast);
4954         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4955                            GLPRT_BPTCL(hw->port_info->lport),
4956                            pf->offset_loaded, &os->eth.tx_broadcast,
4957                            &ns->eth.tx_broadcast);
4958         /* enlarge the limitation when tx_bytes overflowed */
4959         if (pf->offset_loaded) {
4960                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4961                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4962                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4963         }
4964         pf->old_tx_bytes = ns->eth.tx_bytes;
4965         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4966                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4967
4968         /* GLPRT_TEPC not supported */
4969
4970         /* additional port specific stats */
4971         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4972                            pf->offset_loaded, &os->tx_dropped_link_down,
4973                            &ns->tx_dropped_link_down);
4974         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4975                            pf->offset_loaded, &os->crc_errors,
4976                            &ns->crc_errors);
4977         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4978                            pf->offset_loaded, &os->illegal_bytes,
4979                            &ns->illegal_bytes);
4980         /* GLPRT_ERRBC not supported */
4981         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4982                            pf->offset_loaded, &os->mac_local_faults,
4983                            &ns->mac_local_faults);
4984         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4985                            pf->offset_loaded, &os->mac_remote_faults,
4986                            &ns->mac_remote_faults);
4987
4988         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4989                            pf->offset_loaded, &os->rx_len_errors,
4990                            &ns->rx_len_errors);
4991
4992         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4993                            pf->offset_loaded, &os->link_xon_rx,
4994                            &ns->link_xon_rx);
4995         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4996                            pf->offset_loaded, &os->link_xoff_rx,
4997                            &ns->link_xoff_rx);
4998         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4999                            pf->offset_loaded, &os->link_xon_tx,
5000                            &ns->link_xon_tx);
5001         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5002                            pf->offset_loaded, &os->link_xoff_tx,
5003                            &ns->link_xoff_tx);
5004         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5005                            GLPRT_PRC64L(hw->port_info->lport),
5006                            pf->offset_loaded, &os->rx_size_64,
5007                            &ns->rx_size_64);
5008         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5009                            GLPRT_PRC127L(hw->port_info->lport),
5010                            pf->offset_loaded, &os->rx_size_127,
5011                            &ns->rx_size_127);
5012         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5013                            GLPRT_PRC255L(hw->port_info->lport),
5014                            pf->offset_loaded, &os->rx_size_255,
5015                            &ns->rx_size_255);
5016         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5017                            GLPRT_PRC511L(hw->port_info->lport),
5018                            pf->offset_loaded, &os->rx_size_511,
5019                            &ns->rx_size_511);
5020         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5021                            GLPRT_PRC1023L(hw->port_info->lport),
5022                            pf->offset_loaded, &os->rx_size_1023,
5023                            &ns->rx_size_1023);
5024         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5025                            GLPRT_PRC1522L(hw->port_info->lport),
5026                            pf->offset_loaded, &os->rx_size_1522,
5027                            &ns->rx_size_1522);
5028         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5029                            GLPRT_PRC9522L(hw->port_info->lport),
5030                            pf->offset_loaded, &os->rx_size_big,
5031                            &ns->rx_size_big);
5032         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5033                            pf->offset_loaded, &os->rx_undersize,
5034                            &ns->rx_undersize);
5035         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5036                            pf->offset_loaded, &os->rx_fragments,
5037                            &ns->rx_fragments);
5038         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5039                            pf->offset_loaded, &os->rx_oversize,
5040                            &ns->rx_oversize);
5041         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5042                            pf->offset_loaded, &os->rx_jabber,
5043                            &ns->rx_jabber);
5044         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5045                            GLPRT_PTC64L(hw->port_info->lport),
5046                            pf->offset_loaded, &os->tx_size_64,
5047                            &ns->tx_size_64);
5048         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5049                            GLPRT_PTC127L(hw->port_info->lport),
5050                            pf->offset_loaded, &os->tx_size_127,
5051                            &ns->tx_size_127);
5052         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5053                            GLPRT_PTC255L(hw->port_info->lport),
5054                            pf->offset_loaded, &os->tx_size_255,
5055                            &ns->tx_size_255);
5056         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5057                            GLPRT_PTC511L(hw->port_info->lport),
5058                            pf->offset_loaded, &os->tx_size_511,
5059                            &ns->tx_size_511);
5060         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5061                            GLPRT_PTC1023L(hw->port_info->lport),
5062                            pf->offset_loaded, &os->tx_size_1023,
5063                            &ns->tx_size_1023);
5064         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5065                            GLPRT_PTC1522L(hw->port_info->lport),
5066                            pf->offset_loaded, &os->tx_size_1522,
5067                            &ns->tx_size_1522);
5068         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5069                            GLPRT_PTC9522L(hw->port_info->lport),
5070                            pf->offset_loaded, &os->tx_size_big,
5071                            &ns->tx_size_big);
5072
5073         /* GLPRT_MSPDC not supported */
5074         /* GLPRT_XEC not supported */
5075
5076         pf->offset_loaded = true;
5077
5078         if (pf->main_vsi)
5079                 ice_update_vsi_stats(pf->main_vsi);
5080 }
5081
5082 /* Get all statistics of a port */
5083 static int
5084 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5085 {
5086         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5087         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5089
5090         /* call read registers - updates values, now write them to struct */
5091         ice_read_stats_registers(pf, hw);
5092
5093         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5094                           pf->main_vsi->eth_stats.rx_multicast +
5095                           pf->main_vsi->eth_stats.rx_broadcast -
5096                           pf->main_vsi->eth_stats.rx_discards;
5097         stats->opackets = ns->eth.tx_unicast +
5098                           ns->eth.tx_multicast +
5099                           ns->eth.tx_broadcast;
5100         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5101         stats->obytes   = ns->eth.tx_bytes;
5102         stats->oerrors  = ns->eth.tx_errors +
5103                           pf->main_vsi->eth_stats.tx_errors;
5104
5105         /* Rx Errors */
5106         stats->imissed  = ns->eth.rx_discards +
5107                           pf->main_vsi->eth_stats.rx_discards;
5108         stats->ierrors  = ns->crc_errors +
5109                           ns->rx_undersize +
5110                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5111
5112         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5113         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5114         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5115         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5116         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5117         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5118         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5119                     pf->main_vsi->eth_stats.rx_discards);
5120         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5121                     ns->eth.rx_unknown_protocol);
5122         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5123         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5124         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5125         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5126         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5127         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5128                     pf->main_vsi->eth_stats.tx_discards);
5129         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5130
5131         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5132                     ns->tx_dropped_link_down);
5133         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5134         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5135                     ns->illegal_bytes);
5136         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5137         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5138                     ns->mac_local_faults);
5139         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5140                     ns->mac_remote_faults);
5141         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5142         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5143         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5144         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5145         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5146         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5147         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5148         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5149         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5150         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5151         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5152         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5153         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5154         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5155         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5156         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5157         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5158         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5159         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5160         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5161         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5162         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5163         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5164         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5165         return 0;
5166 }
5167
5168 /* Reset the statistics */
5169 static int
5170 ice_stats_reset(struct rte_eth_dev *dev)
5171 {
5172         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5173         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174
5175         /* Mark PF and VSI stats to update the offset, aka "reset" */
5176         pf->offset_loaded = false;
5177         if (pf->main_vsi)
5178                 pf->main_vsi->offset_loaded = false;
5179
5180         /* read the stats, reading current register values into offset */
5181         ice_read_stats_registers(pf, hw);
5182
5183         return 0;
5184 }
5185
5186 static uint32_t
5187 ice_xstats_calc_num(void)
5188 {
5189         uint32_t num;
5190
5191         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5192
5193         return num;
5194 }
5195
5196 static int
5197 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5198                unsigned int n)
5199 {
5200         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5201         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202         unsigned int i;
5203         unsigned int count;
5204         struct ice_hw_port_stats *hw_stats = &pf->stats;
5205
5206         count = ice_xstats_calc_num();
5207         if (n < count)
5208                 return count;
5209
5210         ice_read_stats_registers(pf, hw);
5211
5212         if (!xstats)
5213                 return 0;
5214
5215         count = 0;
5216
5217         /* Get stats from ice_eth_stats struct */
5218         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5219                 xstats[count].value =
5220                         *(uint64_t *)((char *)&hw_stats->eth +
5221                                       ice_stats_strings[i].offset);
5222                 xstats[count].id = count;
5223                 count++;
5224         }
5225
5226         /* Get individiual stats from ice_hw_port struct */
5227         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5228                 xstats[count].value =
5229                         *(uint64_t *)((char *)hw_stats +
5230                                       ice_hw_port_strings[i].offset);
5231                 xstats[count].id = count;
5232                 count++;
5233         }
5234
5235         return count;
5236 }
5237
5238 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5239                                 struct rte_eth_xstat_name *xstats_names,
5240                                 __rte_unused unsigned int limit)
5241 {
5242         unsigned int count = 0;
5243         unsigned int i;
5244
5245         if (!xstats_names)
5246                 return ice_xstats_calc_num();
5247
5248         /* Note: limit checked in rte_eth_xstats_names() */
5249
5250         /* Get stats from ice_eth_stats struct */
5251         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5252                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5253                         sizeof(xstats_names[count].name));
5254                 count++;
5255         }
5256
5257         /* Get individiual stats from ice_hw_port struct */
5258         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5259                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5260                         sizeof(xstats_names[count].name));
5261                 count++;
5262         }
5263
5264         return count;
5265 }
5266
5267 static int
5268 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5269                      const struct rte_flow_ops **ops)
5270 {
5271         if (!dev)
5272                 return -EINVAL;
5273
5274         *ops = &ice_flow_ops;
5275         return 0;
5276 }
5277
5278 /* Add UDP tunneling port */
5279 static int
5280 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5281                              struct rte_eth_udp_tunnel *udp_tunnel)
5282 {
5283         int ret = 0;
5284         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5285
5286         if (udp_tunnel == NULL)
5287                 return -EINVAL;
5288
5289         switch (udp_tunnel->prot_type) {
5290         case RTE_TUNNEL_TYPE_VXLAN:
5291                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5292                 break;
5293         default:
5294                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5295                 ret = -EINVAL;
5296                 break;
5297         }
5298
5299         return ret;
5300 }
5301
5302 /* Delete UDP tunneling port */
5303 static int
5304 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5305                              struct rte_eth_udp_tunnel *udp_tunnel)
5306 {
5307         int ret = 0;
5308         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309
5310         if (udp_tunnel == NULL)
5311                 return -EINVAL;
5312
5313         switch (udp_tunnel->prot_type) {
5314         case RTE_TUNNEL_TYPE_VXLAN:
5315                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5316                 break;
5317         default:
5318                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5319                 ret = -EINVAL;
5320                 break;
5321         }
5322
5323         return ret;
5324 }
5325
5326 static int
5327 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5328               struct rte_pci_device *pci_dev)
5329 {
5330         return rte_eth_dev_pci_generic_probe(pci_dev,
5331                                              sizeof(struct ice_adapter),
5332                                              ice_dev_init);
5333 }
5334
5335 static int
5336 ice_pci_remove(struct rte_pci_device *pci_dev)
5337 {
5338         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5339 }
5340
5341 static struct rte_pci_driver rte_ice_pmd = {
5342         .id_table = pci_id_ice_map,
5343         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5344         .probe = ice_pci_probe,
5345         .remove = ice_pci_remove,
5346 };
5347
5348 /**
5349  * Driver initialization routine.
5350  * Invoked once at EAL init time.
5351  * Register itself as the [Poll Mode] Driver of PCI devices.
5352  */
5353 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5354 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5355 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5356 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5357                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5358                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5359                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5360
5361 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5362 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5363 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5364 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5365 #endif
5366 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5367 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5368 #endif
5369 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5370 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5371 #endif