drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66 };
  67
  68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  69
  70 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  71 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  72 #define ICE_MAX_RES_DESC_NUM        1024
  73
  74 int ice_logtype_init;
  75 int ice_logtype_driver;
  76 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
  77 int ice_logtype_rx;
  78 #endif
  79 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
  80 int ice_logtype_tx;
  81 #endif
  82 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
  83 int ice_logtype_tx_free;
  84 #endif
  85
  86 static int ice_dev_configure(struct rte_eth_dev *dev);
  87 static int ice_dev_start(struct rte_eth_dev *dev);
  88 static void ice_dev_stop(struct rte_eth_dev *dev);
  89 static void ice_dev_close(struct rte_eth_dev *dev);
  90 static int ice_dev_reset(struct rte_eth_dev *dev);
  91 static int ice_dev_info_get(struct rte_eth_dev *dev,
  92                             struct rte_eth_dev_info *dev_info);
  93 static int ice_link_update(struct rte_eth_dev *dev,
  94                            int wait_to_complete);
  95 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  97
  98 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 100 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 101                                struct rte_eth_rss_reta_entry64 *reta_conf,
 102                                uint16_t reta_size);
 103 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 104                               struct rte_eth_rss_reta_entry64 *reta_conf,
 105                               uint16_t reta_size);
 106 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 107                                struct rte_eth_rss_conf *rss_conf);
 108 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 109                                  struct rte_eth_rss_conf *rss_conf);
 110 static int ice_promisc_enable(struct rte_eth_dev *dev);
 111 static int ice_promisc_disable(struct rte_eth_dev *dev);
 112 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 113 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 114 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 115                                uint16_t vlan_id,
 116                                int on);
 117 static int ice_macaddr_set(struct rte_eth_dev *dev,
 118                            struct rte_ether_addr *mac_addr);
 119 static int ice_macaddr_add(struct rte_eth_dev *dev,
 120                            struct rte_ether_addr *mac_addr,
 121                            __rte_unused uint32_t index,
 122                            uint32_t pool);
 123 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 124 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 125                                     uint16_t queue_id);
 126 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 127                                      uint16_t queue_id);
 128 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 129                               size_t fw_size);
 130 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 131                              uint16_t pvid, int on);
 132 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 133 static int ice_get_eeprom(struct rte_eth_dev *dev,
 134                           struct rte_dev_eeprom_info *eeprom);
 135 static int ice_stats_get(struct rte_eth_dev *dev,
 136                          struct rte_eth_stats *stats);
 137 static int ice_stats_reset(struct rte_eth_dev *dev);
 138 static int ice_xstats_get(struct rte_eth_dev *dev,
 139                           struct rte_eth_xstat *xstats, unsigned int n);
 140 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 141                                 struct rte_eth_xstat_name *xstats_names,
 142                                 unsigned int limit);
 143 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 144                         enum rte_filter_type filter_type,
 145                         enum rte_filter_op filter_op,
 146                         void *arg);
 147 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 148                         struct rte_eth_udp_tunnel *udp_tunnel);
 149 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 150                         struct rte_eth_udp_tunnel *udp_tunnel);
 151
 152 static const struct rte_pci_id pci_id_ice_map[] = {
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 169         { .vendor_id = 0, /* sentinel */ },
 170 };
 171
 172 static const struct eth_dev_ops ice_eth_dev_ops = {
 173         .dev_configure                = ice_dev_configure,
 174         .dev_start                    = ice_dev_start,
 175         .dev_stop                     = ice_dev_stop,
 176         .dev_close                    = ice_dev_close,
 177         .dev_reset                    = ice_dev_reset,
 178         .dev_set_link_up              = ice_dev_set_link_up,
 179         .dev_set_link_down            = ice_dev_set_link_down,
 180         .rx_queue_start               = ice_rx_queue_start,
 181         .rx_queue_stop                = ice_rx_queue_stop,
 182         .tx_queue_start               = ice_tx_queue_start,
 183         .tx_queue_stop                = ice_tx_queue_stop,
 184         .rx_queue_setup               = ice_rx_queue_setup,
 185         .rx_queue_release             = ice_rx_queue_release,
 186         .tx_queue_setup               = ice_tx_queue_setup,
 187         .tx_queue_release             = ice_tx_queue_release,
 188         .dev_infos_get                = ice_dev_info_get,
 189         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 190         .link_update                  = ice_link_update,
 191         .mtu_set                      = ice_mtu_set,
 192         .mac_addr_set                 = ice_macaddr_set,
 193         .mac_addr_add                 = ice_macaddr_add,
 194         .mac_addr_remove              = ice_macaddr_remove,
 195         .vlan_filter_set              = ice_vlan_filter_set,
 196         .vlan_offload_set             = ice_vlan_offload_set,
 197         .reta_update                  = ice_rss_reta_update,
 198         .reta_query                   = ice_rss_reta_query,
 199         .rss_hash_update              = ice_rss_hash_update,
 200         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 201         .promiscuous_enable           = ice_promisc_enable,
 202         .promiscuous_disable          = ice_promisc_disable,
 203         .allmulticast_enable          = ice_allmulti_enable,
 204         .allmulticast_disable         = ice_allmulti_disable,
 205         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 206         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 207         .fw_version_get               = ice_fw_version_get,
 208         .vlan_pvid_set                = ice_vlan_pvid_set,
 209         .rxq_info_get                 = ice_rxq_info_get,
 210         .txq_info_get                 = ice_txq_info_get,
 211         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 212         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 213         .get_eeprom_length            = ice_get_eeprom_length,
 214         .get_eeprom                   = ice_get_eeprom,
 215         .rx_queue_count               = ice_rx_queue_count,
 216         .rx_descriptor_status         = ice_rx_descriptor_status,
 217         .tx_descriptor_status         = ice_tx_descriptor_status,
 218         .stats_get                    = ice_stats_get,
 219         .stats_reset                  = ice_stats_reset,
 220         .xstats_get                   = ice_xstats_get,
 221         .xstats_get_names             = ice_xstats_get_names,
 222         .xstats_reset                 = ice_stats_reset,
 223         .filter_ctrl                  = ice_dev_filter_ctrl,
 224         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 225         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 226         .tx_done_cleanup              = ice_tx_done_cleanup,
 227 };
 228
 229 /* store statistics names and its offset in stats structure */
 230 struct ice_xstats_name_off {
 231         char name[RTE_ETH_XSTATS_NAME_SIZE];
 232         unsigned int offset;
 233 };
 234
 235 static const struct ice_xstats_name_off ice_stats_strings[] = {
 236         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 237         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 238         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 239         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 240         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 241                 rx_unknown_protocol)},
 242         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 243         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 244         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 245         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 246 };
 247
 248 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 249                 sizeof(ice_stats_strings[0]))
 250
 251 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 252         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 253                 tx_dropped_link_down)},
 254         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 255         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 256                 illegal_bytes)},
 257         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 258         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 259                 mac_local_faults)},
 260         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 261                 mac_remote_faults)},
 262         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 263                 rx_len_errors)},
 264         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 265         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 266         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 267         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 268         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 269         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_127)},
 271         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_255)},
 273         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_511)},
 275         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_1023)},
 277         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 278                 rx_size_1522)},
 279         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 280                 rx_size_big)},
 281         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_undersize)},
 283         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_oversize)},
 285         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 286                 mac_short_pkt_dropped)},
 287         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 288                 rx_fragments)},
 289         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 290         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 291         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_127)},
 293         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_255)},
 295         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_511)},
 297         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_1023)},
 299         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 300                 tx_size_1522)},
 301         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 302                 tx_size_big)},
 303 };
 304
 305 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 306                 sizeof(ice_hw_port_strings[0]))
 307
 308 static void
 309 ice_init_controlq_parameter(struct ice_hw *hw)
 310 {
 311         /* fields for adminq */
 312         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 313         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 314         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 315         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 316
 317         /* fields for mailboxq, DPDK used as PF host */
 318         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 319         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 320         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 321         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 322 }
 323
 324 static int
 325 lookup_proto_xtr_type(const char *xtr_name)
 326 {
 327         static struct {
 328                 const char *name;
 329                 enum proto_xtr_type type;
 330         } xtr_type_map[] = {
 331                 { "vlan",      PROTO_XTR_VLAN      },
 332                 { "ipv4",      PROTO_XTR_IPV4      },
 333                 { "ipv6",      PROTO_XTR_IPV6      },
 334                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 335                 { "tcp",       PROTO_XTR_TCP       },
 336         };
 337         uint32_t i;
 338
 339         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 340                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 341                         return xtr_type_map[i].type;
 342         }
 343
 344         return -1;
 345 }
 346
 347 /*
 348  * Parse elem, the elem could be single number/range or '(' ')' group
 349  * 1) A single number elem, it's just a simple digit. e.g. 9
 350  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 351  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 352  *    Within group elem, '-' used for a range separator;
 353  *                       ',' used for a single number.
 354  */
 355 static int
 356 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 357 {
 358         const char *str = input;
 359         char *end = NULL;
 360         uint32_t min, max;
 361         uint32_t idx;
 362
 363         while (isblank(*str))
 364                 str++;
 365
 366         if (!isdigit(*str) && *str != '(')
 367                 return -1;
 368
 369         /* process single number or single range of number */
 370         if (*str != '(') {
 371                 errno = 0;
 372                 idx = strtoul(str, &end, 10);
 373                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 374                         return -1;
 375
 376                 while (isblank(*end))
 377                         end++;
 378
 379                 min = idx;
 380                 max = idx;
 381
 382                 /* process single <number>-<number> */
 383                 if (*end == '-') {
 384                         end++;
 385                         while (isblank(*end))
 386                                 end++;
 387                         if (!isdigit(*end))
 388                                 return -1;
 389
 390                         errno = 0;
 391                         idx = strtoul(end, &end, 10);
 392                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 393                                 return -1;
 394
 395                         max = idx;
 396                         while (isblank(*end))
 397                                 end++;
 398                 }
 399
 400                 if (*end != ':')
 401                         return -1;
 402
 403                 for (idx = RTE_MIN(min, max);
 404                      idx <= RTE_MAX(min, max); idx++)
 405                         devargs->proto_xtr[idx] = xtr_type;
 406
 407                 return 0;
 408         }
 409
 410         /* process set within bracket */
 411         str++;
 412         while (isblank(*str))
 413                 str++;
 414         if (*str == '\0')
 415                 return -1;
 416
 417         min = ICE_MAX_QUEUE_NUM;
 418         do {
 419                 /* go ahead to the first digit */
 420                 while (isblank(*str))
 421                         str++;
 422                 if (!isdigit(*str))
 423                         return -1;
 424
 425                 /* get the digit value */
 426                 errno = 0;
 427                 idx = strtoul(str, &end, 10);
 428                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 429                         return -1;
 430
 431                 /* go ahead to separator '-',',' and ')' */
 432                 while (isblank(*end))
 433                         end++;
 434                 if (*end == '-') {
 435                         if (min == ICE_MAX_QUEUE_NUM)
 436                                 min = idx;
 437                         else /* avoid continuous '-' */
 438                                 return -1;
 439                 } else if (*end == ',' || *end == ')') {
 440                         max = idx;
 441                         if (min == ICE_MAX_QUEUE_NUM)
 442                                 min = idx;
 443
 444                         for (idx = RTE_MIN(min, max);
 445                              idx <= RTE_MAX(min, max); idx++)
 446                                 devargs->proto_xtr[idx] = xtr_type;
 447
 448                         min = ICE_MAX_QUEUE_NUM;
 449                 } else {
 450                         return -1;
 451                 }
 452
 453                 str = end + 1;
 454         } while (*end != ')' && *end != '\0');
 455
 456         return 0;
 457 }
 458
 459 static int
 460 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 461 {
 462         const char *queue_start;
 463         uint32_t idx;
 464         int xtr_type;
 465         char xtr_name[32];
 466
 467         while (isblank(*queues))
 468                 queues++;
 469
 470         if (*queues != '[') {
 471                 xtr_type = lookup_proto_xtr_type(queues);
 472                 if (xtr_type < 0)
 473                         return -1;
 474
 475                 devargs->proto_xtr_dflt = xtr_type;
 476
 477                 return 0;
 478         }
 479
 480         queues++;
 481         do {
 482                 while (isblank(*queues))
 483                         queues++;
 484                 if (*queues == '\0')
 485                         return -1;
 486
 487                 queue_start = queues;
 488
 489                 /* go across a complete bracket */
 490                 if (*queue_start == '(') {
 491                         queues += strcspn(queues, ")");
 492                         if (*queues != ')')
 493                                 return -1;
 494                 }
 495
 496                 /* scan the separator ':' */
 497                 queues += strcspn(queues, ":");
 498                 if (*queues++ != ':')
 499                         return -1;
 500                 while (isblank(*queues))
 501                         queues++;
 502
 503                 for (idx = 0; ; idx++) {
 504                         if (isblank(queues[idx]) ||
 505                             queues[idx] == ',' ||
 506                             queues[idx] == ']' ||
 507                             queues[idx] == '\0')
 508                                 break;
 509
 510                         if (idx > sizeof(xtr_name) - 2)
 511                                 return -1;
 512
 513                         xtr_name[idx] = queues[idx];
 514                 }
 515                 xtr_name[idx] = '\0';
 516                 xtr_type = lookup_proto_xtr_type(xtr_name);
 517                 if (xtr_type < 0)
 518                         return -1;
 519
 520                 queues += idx;
 521
 522                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 523                         queues++;
 524
 525                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 526                         return -1;
 527         } while (*queues != '\0');
 528
 529         return 0;
 530 }
 531
 532 static int
 533 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 534                      void *extra_args)
 535 {
 536         struct ice_devargs *devargs = extra_args;
 537
 538         if (value == NULL || extra_args == NULL)
 539                 return -EINVAL;
 540
 541         if (parse_queue_proto_xtr(value, devargs) < 0) {
 542                 PMD_DRV_LOG(ERR,
 543                             "The protocol extraction parameter is wrong : '%s'",
 544                             value);
 545                 return -1;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static bool
 552 ice_proto_xtr_support(struct ice_hw *hw)
 553 {
 554 #define FLX_REG(val, fld, idx) \
 555         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 556          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 557         static struct {
 558                 uint32_t rxdid;
 559                 uint16_t protid_0;
 560                 uint16_t protid_1;
 561         } xtr_sets[] = {
 562                 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
 563                 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
 564                   ICE_PROT_IPV4_OF_OR_S },
 565                 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
 566                   ICE_PROT_IPV6_OF_OR_S },
 567                 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
 568                   ICE_PROT_IPV6_OF_OR_S },
 569                 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 570         };
 571         uint32_t i;
 572
 573         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 574                 uint32_t rxdid = xtr_sets[i].rxdid;
 575                 uint32_t v;
 576
 577                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 578                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 579
 580                         if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
 581                             FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
 582                                 return false;
 583                 }
 584
 585                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 586                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 587
 588                         if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
 589                             FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
 590                                 return false;
 591                 }
 592         }
 593
 594         return true;
 595 }
 596
 597 static int
 598 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 599                   uint32_t num)
 600 {
 601         struct pool_entry *entry;
 602
 603         if (!pool || !num)
 604                 return -EINVAL;
 605
 606         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 607         if (!entry) {
 608                 PMD_INIT_LOG(ERR,
 609                              "Failed to allocate memory for resource pool");
 610                 return -ENOMEM;
 611         }
 612
 613         /* queue heap initialize */
 614         pool->num_free = num;
 615         pool->num_alloc = 0;
 616         pool->base = base;
 617         LIST_INIT(&pool->alloc_list);
 618         LIST_INIT(&pool->free_list);
 619
 620         /* Initialize element  */
 621         entry->base = 0;
 622         entry->len = num;
 623
 624         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 625         return 0;
 626 }
 627
 628 static int
 629 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 630                    uint16_t num)
 631 {
 632         struct pool_entry *entry, *valid_entry;
 633
 634         if (!pool || !num) {
 635                 PMD_INIT_LOG(ERR, "Invalid parameter");
 636                 return -EINVAL;
 637         }
 638
 639         if (pool->num_free < num) {
 640                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 641                              num, pool->num_free);
 642                 return -ENOMEM;
 643         }
 644
 645         valid_entry = NULL;
 646         /* Lookup  in free list and find most fit one */
 647         LIST_FOREACH(entry, &pool->free_list, next) {
 648                 if (entry->len >= num) {
 649                         /* Find best one */
 650                         if (entry->len == num) {
 651                                 valid_entry = entry;
 652                                 break;
 653                         }
 654                         if (!valid_entry ||
 655                             valid_entry->len > entry->len)
 656                                 valid_entry = entry;
 657                 }
 658         }
 659
 660         /* Not find one to satisfy the request, return */
 661         if (!valid_entry) {
 662                 PMD_INIT_LOG(ERR, "No valid entry found");
 663                 return -ENOMEM;
 664         }
 665         /**
 666          * The entry have equal queue number as requested,
 667          * remove it from alloc_list.
 668          */
 669         if (valid_entry->len == num) {
 670                 LIST_REMOVE(valid_entry, next);
 671         } else {
 672                 /**
 673                  * The entry have more numbers than requested,
 674                  * create a new entry for alloc_list and minus its
 675                  * queue base and number in free_list.
 676                  */
 677                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 678                 if (!entry) {
 679                         PMD_INIT_LOG(ERR,
 680                                      "Failed to allocate memory for "
 681                                      "resource pool");
 682                         return -ENOMEM;
 683                 }
 684                 entry->base = valid_entry->base;
 685                 entry->len = num;
 686                 valid_entry->base += num;
 687                 valid_entry->len -= num;
 688                 valid_entry = entry;
 689         }
 690
 691         /* Insert it into alloc list, not sorted */
 692         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 693
 694         pool->num_free -= valid_entry->len;
 695         pool->num_alloc += valid_entry->len;
 696
 697         return valid_entry->base + pool->base;
 698 }
 699
 700 static void
 701 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 702 {
 703         struct pool_entry *entry, *next_entry;
 704
 705         if (!pool)
 706                 return;
 707
 708         for (entry = LIST_FIRST(&pool->alloc_list);
 709              entry && (next_entry = LIST_NEXT(entry, next), 1);
 710              entry = next_entry) {
 711                 LIST_REMOVE(entry, next);
 712                 rte_free(entry);
 713         }
 714
 715         for (entry = LIST_FIRST(&pool->free_list);
 716              entry && (next_entry = LIST_NEXT(entry, next), 1);
 717              entry = next_entry) {
 718                 LIST_REMOVE(entry, next);
 719                 rte_free(entry);
 720         }
 721
 722         pool->num_free = 0;
 723         pool->num_alloc = 0;
 724         pool->base = 0;
 725         LIST_INIT(&pool->alloc_list);
 726         LIST_INIT(&pool->free_list);
 727 }
 728
 729 static void
 730 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 731 {
 732         /* Set VSI LUT selection */
 733         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 734                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 735         /* Set Hash scheme */
 736         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 737                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 738         /* enable TC */
 739         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 740 }
 741
 742 static enum ice_status
 743 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 744                                 struct ice_aqc_vsi_props *info,
 745                                 uint8_t enabled_tcmap)
 746 {
 747         uint16_t bsf, qp_idx;
 748
 749         /* default tc 0 now. Multi-TC supporting need to be done later.
 750          * Configure TC and queue mapping parameters, for enabled TC,
 751          * allocate qpnum_per_tc queues to this traffic.
 752          */
 753         if (enabled_tcmap != 0x01) {
 754                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 755                 return -ENOTSUP;
 756         }
 757
 758         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 759         bsf = rte_bsf32(vsi->nb_qps);
 760         /* Adjust the queue number to actual queues that can be applied */
 761         vsi->nb_qps = 0x1 << bsf;
 762
 763         qp_idx = 0;
 764         /* Set tc and queue mapping with VSI */
 765         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 766                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 767                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 768
 769         /* Associate queue number with VSI */
 770         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 771         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 772         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 773         info->valid_sections |=
 774                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 775         /* Set the info.ingress_table and info.egress_table
 776          * for UP translate table. Now just set it to 1:1 map by default
 777          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 778          */
 779 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 780         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 781         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 782         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 783         return 0;
 784 }
 785
 786 static int
 787 ice_init_mac_address(struct rte_eth_dev *dev)
 788 {
 789         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 790
 791         if (!rte_is_unicast_ether_addr
 792                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 793                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 794                 return -EINVAL;
 795         }
 796
 797         rte_ether_addr_copy(
 798                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 799                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 800
 801         dev->data->mac_addrs =
 802                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 803         if (!dev->data->mac_addrs) {
 804                 PMD_INIT_LOG(ERR,
 805                              "Failed to allocate memory to store mac address");
 806                 return -ENOMEM;
 807         }
 808         /* store it to dev data */
 809         rte_ether_addr_copy(
 810                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 811                 &dev->data->mac_addrs[0]);
 812         return 0;
 813 }
 814
 815 /* Find out specific MAC filter */
 816 static struct ice_mac_filter *
 817 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 818 {
 819         struct ice_mac_filter *f;
 820
 821         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 822                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 823                         return f;
 824         }
 825
 826         return NULL;
 827 }
 828
 829 static int
 830 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 831 {
 832         struct ice_fltr_list_entry *m_list_itr = NULL;
 833         struct ice_mac_filter *f;
 834         struct LIST_HEAD_TYPE list_head;
 835         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 836         int ret = 0;
 837
 838         /* If it's added and configured, return */
 839         f = ice_find_mac_filter(vsi, mac_addr);
 840         if (f) {
 841                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 842                 return 0;
 843         }
 844
 845         INIT_LIST_HEAD(&list_head);
 846
 847         m_list_itr = (struct ice_fltr_list_entry *)
 848                 ice_malloc(hw, sizeof(*m_list_itr));
 849         if (!m_list_itr) {
 850                 ret = -ENOMEM;
 851                 goto DONE;
 852         }
 853         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 854                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 855         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 856         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 857         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 858         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 859         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 860
 861         LIST_ADD(&m_list_itr->list_entry, &list_head);
 862
 863         /* Add the mac */
 864         ret = ice_add_mac(hw, &list_head);
 865         if (ret != ICE_SUCCESS) {
 866                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 867                 ret = -EINVAL;
 868                 goto DONE;
 869         }
 870         /* Add the mac addr into mac list */
 871         f = rte_zmalloc(NULL, sizeof(*f), 0);
 872         if (!f) {
 873                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 874                 ret = -ENOMEM;
 875                 goto DONE;
 876         }
 877         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 878         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 879         vsi->mac_num++;
 880
 881         ret = 0;
 882
 883 DONE:
 884         rte_free(m_list_itr);
 885         return ret;
 886 }
 887
 888 static int
 889 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 890 {
 891         struct ice_fltr_list_entry *m_list_itr = NULL;
 892         struct ice_mac_filter *f;
 893         struct LIST_HEAD_TYPE list_head;
 894         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 895         int ret = 0;
 896
 897         /* Can't find it, return an error */
 898         f = ice_find_mac_filter(vsi, mac_addr);
 899         if (!f)
 900                 return -EINVAL;
 901
 902         INIT_LIST_HEAD(&list_head);
 903
 904         m_list_itr = (struct ice_fltr_list_entry *)
 905                 ice_malloc(hw, sizeof(*m_list_itr));
 906         if (!m_list_itr) {
 907                 ret = -ENOMEM;
 908                 goto DONE;
 909         }
 910         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 911                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 912         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 913         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 914         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 915         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 916         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 917
 918         LIST_ADD(&m_list_itr->list_entry, &list_head);
 919
 920         /* remove the mac filter */
 921         ret = ice_remove_mac(hw, &list_head);
 922         if (ret != ICE_SUCCESS) {
 923                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 924                 ret = -EINVAL;
 925                 goto DONE;
 926         }
 927
 928         /* Remove the mac addr from mac list */
 929         TAILQ_REMOVE(&vsi->mac_list, f, next);
 930         rte_free(f);
 931         vsi->mac_num--;
 932
 933         ret = 0;
 934 DONE:
 935         rte_free(m_list_itr);
 936         return ret;
 937 }
 938
 939 /* Find out specific VLAN filter */
 940 static struct ice_vlan_filter *
 941 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 942 {
 943         struct ice_vlan_filter *f;
 944
 945         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 946                 if (vlan_id == f->vlan_info.vlan_id)
 947                         return f;
 948         }
 949
 950         return NULL;
 951 }
 952
 953 static int
 954 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 955 {
 956         struct ice_fltr_list_entry *v_list_itr = NULL;
 957         struct ice_vlan_filter *f;
 958         struct LIST_HEAD_TYPE list_head;
 959         struct ice_hw *hw;
 960         int ret = 0;
 961
 962         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 963                 return -EINVAL;
 964
 965         hw = ICE_VSI_TO_HW(vsi);
 966
 967         /* If it's added and configured, return. */
 968         f = ice_find_vlan_filter(vsi, vlan_id);
 969         if (f) {
 970                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 971                 return 0;
 972         }
 973
 974         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 975                 return 0;
 976
 977         INIT_LIST_HEAD(&list_head);
 978
 979         v_list_itr = (struct ice_fltr_list_entry *)
 980                       ice_malloc(hw, sizeof(*v_list_itr));
 981         if (!v_list_itr) {
 982                 ret = -ENOMEM;
 983                 goto DONE;
 984         }
 985         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 986         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 987         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 988         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 989         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 990         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 991
 992         LIST_ADD(&v_list_itr->list_entry, &list_head);
 993
 994         /* Add the vlan */
 995         ret = ice_add_vlan(hw, &list_head);
 996         if (ret != ICE_SUCCESS) {
 997                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 998                 ret = -EINVAL;
 999                 goto DONE;
1000         }
1001
1002         /* Add vlan into vlan list */
1003         f = rte_zmalloc(NULL, sizeof(*f), 0);
1004         if (!f) {
1005                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1006                 ret = -ENOMEM;
1007                 goto DONE;
1008         }
1009         f->vlan_info.vlan_id = vlan_id;
1010         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1011         vsi->vlan_num++;
1012
1013         ret = 0;
1014
1015 DONE:
1016         rte_free(v_list_itr);
1017         return ret;
1018 }
1019
1020 static int
1021 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1022 {
1023         struct ice_fltr_list_entry *v_list_itr = NULL;
1024         struct ice_vlan_filter *f;
1025         struct LIST_HEAD_TYPE list_head;
1026         struct ice_hw *hw;
1027         int ret = 0;
1028
1029         /**
1030          * Vlan 0 is the generic filter for untagged packets
1031          * and can't be removed.
1032          */
1033         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1034                 return -EINVAL;
1035
1036         hw = ICE_VSI_TO_HW(vsi);
1037
1038         /* Can't find it, return an error */
1039         f = ice_find_vlan_filter(vsi, vlan_id);
1040         if (!f)
1041                 return -EINVAL;
1042
1043         INIT_LIST_HEAD(&list_head);
1044
1045         v_list_itr = (struct ice_fltr_list_entry *)
1046                       ice_malloc(hw, sizeof(*v_list_itr));
1047         if (!v_list_itr) {
1048                 ret = -ENOMEM;
1049                 goto DONE;
1050         }
1051
1052         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1053         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1054         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1055         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1056         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1057         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1058
1059         LIST_ADD(&v_list_itr->list_entry, &list_head);
1060
1061         /* remove the vlan filter */
1062         ret = ice_remove_vlan(hw, &list_head);
1063         if (ret != ICE_SUCCESS) {
1064                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1065                 ret = -EINVAL;
1066                 goto DONE;
1067         }
1068
1069         /* Remove the vlan id from vlan list */
1070         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1071         rte_free(f);
1072         vsi->vlan_num--;
1073
1074         ret = 0;
1075 DONE:
1076         rte_free(v_list_itr);
1077         return ret;
1078 }
1079
1080 static int
1081 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1082 {
1083         struct ice_mac_filter *m_f;
1084         struct ice_vlan_filter *v_f;
1085         int ret = 0;
1086
1087         if (!vsi || !vsi->mac_num)
1088                 return -EINVAL;
1089
1090         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1091                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1092                 if (ret != ICE_SUCCESS) {
1093                         ret = -EINVAL;
1094                         goto DONE;
1095                 }
1096         }
1097
1098         if (vsi->vlan_num == 0)
1099                 return 0;
1100
1101         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1102                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1103                 if (ret != ICE_SUCCESS) {
1104                         ret = -EINVAL;
1105                         goto DONE;
1106                 }
1107         }
1108
1109 DONE:
1110         return ret;
1111 }
1112
1113 static int
1114 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1115 {
1116         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1117         struct ice_vsi_ctx ctxt;
1118         uint8_t qinq_flags;
1119         int ret = 0;
1120
1121         /* Check if it has been already on or off */
1122         if (vsi->info.valid_sections &
1123                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1124                 if (on) {
1125                         if ((vsi->info.outer_tag_flags &
1126                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1127                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1128                                 return 0; /* already on */
1129                 } else {
1130                         if (!(vsi->info.outer_tag_flags &
1131                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1132                                 return 0; /* already off */
1133                 }
1134         }
1135
1136         if (on)
1137                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1138         else
1139                 qinq_flags = 0;
1140         /* clear global insertion and use per packet insertion */
1141         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1142         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1143         vsi->info.outer_tag_flags |= qinq_flags;
1144         /* use default vlan type 0x8100 */
1145         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1146         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1147                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1148         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1149         ctxt.info.valid_sections =
1150                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1151         ctxt.vsi_num = vsi->vsi_id;
1152         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1153         if (ret) {
1154                 PMD_DRV_LOG(INFO,
1155                             "Update VSI failed to %s qinq stripping",
1156                             on ? "enable" : "disable");
1157                 return -EINVAL;
1158         }
1159
1160         vsi->info.valid_sections |=
1161                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1162
1163         return ret;
1164 }
1165
1166 static int
1167 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1168 {
1169         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1170         struct ice_vsi_ctx ctxt;
1171         uint8_t qinq_flags;
1172         int ret = 0;
1173
1174         /* Check if it has been already on or off */
1175         if (vsi->info.valid_sections &
1176                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1177                 if (on) {
1178                         if ((vsi->info.outer_tag_flags &
1179                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1180                             ICE_AQ_VSI_OUTER_TAG_COPY)
1181                                 return 0; /* already on */
1182                 } else {
1183                         if ((vsi->info.outer_tag_flags &
1184                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1185                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1186                                 return 0; /* already off */
1187                 }
1188         }
1189
1190         if (on)
1191                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1192         else
1193                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1194         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1195         vsi->info.outer_tag_flags |= qinq_flags;
1196         /* use default vlan type 0x8100 */
1197         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1198         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1199                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1200         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1201         ctxt.info.valid_sections =
1202                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1203         ctxt.vsi_num = vsi->vsi_id;
1204         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1205         if (ret) {
1206                 PMD_DRV_LOG(INFO,
1207                             "Update VSI failed to %s qinq stripping",
1208                             on ? "enable" : "disable");
1209                 return -EINVAL;
1210         }
1211
1212         vsi->info.valid_sections |=
1213                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1214
1215         return ret;
1216 }
1217
1218 static int
1219 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1220 {
1221         int ret;
1222
1223         ret = ice_vsi_config_qinq_stripping(vsi, on);
1224         if (ret)
1225                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1226
1227         ret = ice_vsi_config_qinq_insertion(vsi, on);
1228         if (ret)
1229                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1230
1231         return ret;
1232 }
1233
1234 /* Enable IRQ0 */
1235 static void
1236 ice_pf_enable_irq0(struct ice_hw *hw)
1237 {
1238         /* reset the registers */
1239         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1240         ICE_READ_REG(hw, PFINT_OICR);
1241
1242 #ifdef ICE_LSE_SPT
1243         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1244                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1245                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1246
1247         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1248                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1249                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1250                        PFINT_OICR_CTL_ITR_INDX_M) |
1251                       PFINT_OICR_CTL_CAUSE_ENA_M);
1252
1253         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1254                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1255                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1256                        PFINT_FW_CTL_ITR_INDX_M) |
1257                       PFINT_FW_CTL_CAUSE_ENA_M);
1258 #else
1259         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1260 #endif
1261
1262         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1263                       GLINT_DYN_CTL_INTENA_M |
1264                       GLINT_DYN_CTL_CLEARPBA_M |
1265                       GLINT_DYN_CTL_ITR_INDX_M);
1266
1267         ice_flush(hw);
1268 }
1269
1270 /* Disable IRQ0 */
1271 static void
1272 ice_pf_disable_irq0(struct ice_hw *hw)
1273 {
1274         /* Disable all interrupt types */
1275         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1276         ice_flush(hw);
1277 }
1278
1279 #ifdef ICE_LSE_SPT
1280 static void
1281 ice_handle_aq_msg(struct rte_eth_dev *dev)
1282 {
1283         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284         struct ice_ctl_q_info *cq = &hw->adminq;
1285         struct ice_rq_event_info event;
1286         uint16_t pending, opcode;
1287         int ret;
1288
1289         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1290         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1291         if (!event.msg_buf) {
1292                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1293                 return;
1294         }
1295
1296         pending = 1;
1297         while (pending) {
1298                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1299
1300                 if (ret != ICE_SUCCESS) {
1301                         PMD_DRV_LOG(INFO,
1302                                     "Failed to read msg from AdminQ, "
1303                                     "adminq_err: %u",
1304                                     hw->adminq.sq_last_status);
1305                         break;
1306                 }
1307                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1308
1309                 switch (opcode) {
1310                 case ice_aqc_opc_get_link_status:
1311                         ret = ice_link_update(dev, 0);
1312                         if (!ret)
1313                                 _rte_eth_dev_callback_process
1314                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1315                         break;
1316                 default:
1317                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1318                                     opcode);
1319                         break;
1320                 }
1321         }
1322         rte_free(event.msg_buf);
1323 }
1324 #endif
1325
1326 /**
1327  * Interrupt handler triggered by NIC for handling
1328  * specific interrupt.
1329  *
1330  * @param handle
1331  *  Pointer to interrupt handle.
1332  * @param param
1333  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1334  *
1335  * @return
1336  *  void
1337  */
1338 static void
1339 ice_interrupt_handler(void *param)
1340 {
1341         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1342         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         uint32_t oicr;
1344         uint32_t reg;
1345         uint8_t pf_num;
1346         uint8_t event;
1347         uint16_t queue;
1348         int ret;
1349 #ifdef ICE_LSE_SPT
1350         uint32_t int_fw_ctl;
1351 #endif
1352
1353         /* Disable interrupt */
1354         ice_pf_disable_irq0(hw);
1355
1356         /* read out interrupt causes */
1357         oicr = ICE_READ_REG(hw, PFINT_OICR);
1358 #ifdef ICE_LSE_SPT
1359         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1360 #endif
1361
1362         /* No interrupt event indicated */
1363         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1364                 PMD_DRV_LOG(INFO, "No interrupt event");
1365                 goto done;
1366         }
1367
1368 #ifdef ICE_LSE_SPT
1369         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1370                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1371                 ice_handle_aq_msg(dev);
1372         }
1373 #else
1374         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1375                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1376                 ret = ice_link_update(dev, 0);
1377                 if (!ret)
1378                         _rte_eth_dev_callback_process
1379                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1380         }
1381 #endif
1382
1383         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1384                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1385                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1386                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1387                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1388                                  GL_MDET_TX_PQM_PF_NUM_S;
1389                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1390                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1391                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1392                                 GL_MDET_TX_PQM_QNUM_S;
1393
1394                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1395                                     "%d by PQM on TX queue %d PF# %d",
1396                                     event, queue, pf_num);
1397                 }
1398
1399                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1400                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1401                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1402                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1403                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1404                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1405                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1406                                 GL_MDET_TX_TCLAN_QNUM_S;
1407
1408                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1409                                     "%d by TCLAN on TX queue %d PF# %d",
1410                                     event, queue, pf_num);
1411                 }
1412         }
1413 done:
1414         /* Enable interrupt */
1415         ice_pf_enable_irq0(hw);
1416         rte_intr_ack(dev->intr_handle);
1417 }
1418
1419 static void
1420 ice_init_proto_xtr(struct rte_eth_dev *dev)
1421 {
1422         struct ice_adapter *ad =
1423                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1424         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1425         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1426         const struct proto_xtr_ol_flag *ol_flag;
1427         bool proto_xtr_enable = false;
1428         int offset;
1429         uint16_t i;
1430
1431         if (!ice_proto_xtr_support(hw)) {
1432                 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1433                 return;
1434         }
1435
1436         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1437         if (unlikely(pf->proto_xtr == NULL)) {
1438                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1439                 return;
1440         }
1441
1442         for (i = 0; i < pf->lan_nb_qps; i++) {
1443                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1444                                    ad->devargs.proto_xtr[i] :
1445                                    ad->devargs.proto_xtr_dflt;
1446
1447                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1448                         uint8_t type = pf->proto_xtr[i];
1449
1450                         ice_proto_xtr_ol_flag_params[type].required = true;
1451                         proto_xtr_enable = true;
1452                 }
1453         }
1454
1455         if (likely(!proto_xtr_enable))
1456                 return;
1457
1458         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1459         if (unlikely(offset == -1)) {
1460                 PMD_DRV_LOG(ERR,
1461                             "Protocol extraction metadata is disabled in mbuf with error %d",
1462                             -rte_errno);
1463                 return;
1464         }
1465
1466         PMD_DRV_LOG(DEBUG,
1467                     "Protocol extraction metadata offset in mbuf is : %d",
1468                     offset);
1469         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1470
1471         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1472                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1473
1474                 if (!ol_flag->required)
1475                         continue;
1476
1477                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1478                 if (unlikely(offset == -1)) {
1479                         PMD_DRV_LOG(ERR,
1480                                     "Protocol extraction offload '%s' failed to register with error %d",
1481                                     ol_flag->param.name, -rte_errno);
1482
1483                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1484                         break;
1485                 }
1486
1487                 PMD_DRV_LOG(DEBUG,
1488                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1489                             ol_flag->param.name, offset);
1490                 *ol_flag->ol_flag = 1ULL << offset;
1491         }
1492 }
1493
1494 /*  Initialize SW parameters of PF */
1495 static int
1496 ice_pf_sw_init(struct rte_eth_dev *dev)
1497 {
1498         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1499         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1500
1501         pf->lan_nb_qp_max =
1502                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1503                                   hw->func_caps.common_cap.num_rxq);
1504
1505         pf->lan_nb_qps = pf->lan_nb_qp_max;
1506
1507         ice_init_proto_xtr(dev);
1508
1509         if (hw->func_caps.fd_fltr_guar > 0 ||
1510             hw->func_caps.fd_fltr_best_effort > 0) {
1511                 pf->flags |= ICE_FLAG_FDIR;
1512                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1513                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1514         } else {
1515                 pf->fdir_nb_qps = 0;
1516         }
1517         pf->fdir_qp_offset = 0;
1518
1519         return 0;
1520 }
1521
1522 struct ice_vsi *
1523 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1524 {
1525         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1526         struct ice_vsi *vsi = NULL;
1527         struct ice_vsi_ctx vsi_ctx;
1528         int ret;
1529         struct rte_ether_addr broadcast = {
1530                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1531         struct rte_ether_addr mac_addr;
1532         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1533         uint8_t tc_bitmap = 0x1;
1534         uint16_t cfg;
1535
1536         /* hw->num_lports = 1 in NIC mode */
1537         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1538         if (!vsi)
1539                 return NULL;
1540
1541         vsi->idx = pf->next_vsi_idx;
1542         pf->next_vsi_idx++;
1543         vsi->type = type;
1544         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1545         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1546         vsi->vlan_anti_spoof_on = 0;
1547         vsi->vlan_filter_on = 1;
1548         TAILQ_INIT(&vsi->mac_list);
1549         TAILQ_INIT(&vsi->vlan_list);
1550
1551         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1552         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1553                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1554                         hw->func_caps.common_cap.rss_table_size;
1555         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1556
1557         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1558         switch (type) {
1559         case ICE_VSI_PF:
1560                 vsi->nb_qps = pf->lan_nb_qps;
1561                 vsi->base_queue = 1;
1562                 ice_vsi_config_default_rss(&vsi_ctx.info);
1563                 vsi_ctx.alloc_from_pool = true;
1564                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1565                 /* switch_id is queried by get_switch_config aq, which is done
1566                  * by ice_init_hw
1567                  */
1568                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1569                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1570                 /* Allow all untagged or tagged packets */
1571                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1572                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1573                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1574                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1575
1576                 /* FDIR */
1577                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1578                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1579                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1580                 cfg = ICE_AQ_VSI_FD_ENABLE;
1581                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1582                 vsi_ctx.info.max_fd_fltr_dedicated =
1583                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1584                 vsi_ctx.info.max_fd_fltr_shared =
1585                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1586
1587                 /* Enable VLAN/UP trip */
1588                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1589                                                       &vsi_ctx.info,
1590                                                       ICE_DEFAULT_TCMAP);
1591                 if (ret) {
1592                         PMD_INIT_LOG(ERR,
1593                                      "tc queue mapping with vsi failed, "
1594                                      "err = %d",
1595                                      ret);
1596                         goto fail_mem;
1597                 }
1598
1599                 break;
1600         case ICE_VSI_CTRL:
1601                 vsi->nb_qps = pf->fdir_nb_qps;
1602                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1603                 vsi_ctx.alloc_from_pool = true;
1604                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1605
1606                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1607                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1608                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1609                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1610                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1611                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1612                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1613                                                       &vsi_ctx.info,
1614                                                       ICE_DEFAULT_TCMAP);
1615                 if (ret) {
1616                         PMD_INIT_LOG(ERR,
1617                                      "tc queue mapping with vsi failed, "
1618                                      "err = %d",
1619                                      ret);
1620                         goto fail_mem;
1621                 }
1622                 break;
1623         default:
1624                 /* for other types of VSI */
1625                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1626                 goto fail_mem;
1627         }
1628
1629         /* VF has MSIX interrupt in VF range, don't allocate here */
1630         if (type == ICE_VSI_PF) {
1631                 ret = ice_res_pool_alloc(&pf->msix_pool,
1632                                          RTE_MIN(vsi->nb_qps,
1633                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1634                 if (ret < 0) {
1635                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1636                                      vsi->vsi_id, ret);
1637                 }
1638                 vsi->msix_intr = ret;
1639                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1640         } else if (type == ICE_VSI_CTRL) {
1641                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1642                 if (ret < 0) {
1643                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1644                                     vsi->vsi_id, ret);
1645                 }
1646                 vsi->msix_intr = ret;
1647                 vsi->nb_msix = 1;
1648         } else {
1649                 vsi->msix_intr = 0;
1650                 vsi->nb_msix = 0;
1651         }
1652         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1653         if (ret != ICE_SUCCESS) {
1654                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1655                 goto fail_mem;
1656         }
1657         /* store vsi information is SW structure */
1658         vsi->vsi_id = vsi_ctx.vsi_num;
1659         vsi->info = vsi_ctx.info;
1660         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1661         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1662
1663         if (type == ICE_VSI_PF) {
1664                 /* MAC configuration */
1665                 rte_ether_addr_copy((struct rte_ether_addr *)
1666                                         hw->port_info->mac.perm_addr,
1667                                     &pf->dev_addr);
1668
1669                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1670                 ret = ice_add_mac_filter(vsi, &mac_addr);
1671                 if (ret != ICE_SUCCESS)
1672                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1673
1674                 rte_ether_addr_copy(&broadcast, &mac_addr);
1675                 ret = ice_add_mac_filter(vsi, &mac_addr);
1676                 if (ret != ICE_SUCCESS)
1677                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1678         }
1679
1680         /* At the beginning, only TC0. */
1681         /* What we need here is the maximam number of the TX queues.
1682          * Currently vsi->nb_qps means it.
1683          * Correct it if any change.
1684          */
1685         max_txqs[0] = vsi->nb_qps;
1686         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1687                               tc_bitmap, max_txqs);
1688         if (ret != ICE_SUCCESS)
1689                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1690
1691         return vsi;
1692 fail_mem:
1693         rte_free(vsi);
1694         pf->next_vsi_idx--;
1695         return NULL;
1696 }
1697
1698 static int
1699 ice_send_driver_ver(struct ice_hw *hw)
1700 {
1701         struct ice_driver_ver dv;
1702
1703         /* we don't have driver version use 0 for dummy */
1704         dv.major_ver = 0;
1705         dv.minor_ver = 0;
1706         dv.build_ver = 0;
1707         dv.subbuild_ver = 0;
1708         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1709
1710         return ice_aq_send_driver_ver(hw, &dv, NULL);
1711 }
1712
1713 static int
1714 ice_pf_setup(struct ice_pf *pf)
1715 {
1716         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1717         struct ice_vsi *vsi;
1718         uint16_t unused;
1719
1720         /* Clear all stats counters */
1721         pf->offset_loaded = false;
1722         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1723         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1724         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1725         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1726
1727         /* force guaranteed filter pool for PF */
1728         ice_alloc_fd_guar_item(hw, &unused,
1729                                hw->func_caps.fd_fltr_guar);
1730         /* force shared filter pool for PF */
1731         ice_alloc_fd_shrd_item(hw, &unused,
1732                                hw->func_caps.fd_fltr_best_effort);
1733
1734         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1735         if (!vsi) {
1736                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1737                 return -EINVAL;
1738         }
1739
1740         pf->main_vsi = vsi;
1741
1742         return 0;
1743 }
1744
1745 /* PCIe configuration space setting */
1746 #define PCI_CFG_SPACE_SIZE          256
1747 #define PCI_CFG_SPACE_EXP_SIZE      4096
1748 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1749 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1750 #define PCI_EXT_CAP_ID_DSN          0x03
1751
1752 static int
1753 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1754 {
1755         uint32_t header;
1756         int ttl;
1757         int pos = PCI_CFG_SPACE_SIZE;
1758
1759         /* minimum 8 bytes per capability */
1760         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1761
1762         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1763                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1764                 return -1;
1765         }
1766
1767         /*
1768          * If we have no capabilities, this is indicated by cap ID,
1769          * cap version and next pointer all being 0.
1770          */
1771         if (header == 0)
1772                 return 0;
1773
1774         while (ttl-- > 0) {
1775                 if (PCI_EXT_CAP_ID(header) == cap)
1776                         return pos;
1777
1778                 pos = PCI_EXT_CAP_NEXT(header);
1779
1780                 if (pos < PCI_CFG_SPACE_SIZE)
1781                         break;
1782
1783                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1784                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1785                         return -1;
1786                 }
1787         }
1788
1789         return 0;
1790 }
1791
1792 /*
1793  * Extract device serial number from PCIe Configuration Space and
1794  * determine the pkg file path according to the DSN.
1795  */
1796 static int
1797 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1798 {
1799         int pos;
1800         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1801         uint32_t dsn_low, dsn_high;
1802         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1803
1804         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1805
1806         if (pos) {
1807                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1808                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1809                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1810                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1811         } else {
1812                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1813                 goto fail_dsn;
1814         }
1815
1816         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1817                 ICE_MAX_PKG_FILENAME_SIZE);
1818         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1819                 return 0;
1820
1821         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1822                 ICE_MAX_PKG_FILENAME_SIZE);
1823         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1824                 return 0;
1825
1826 fail_dsn:
1827         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1828         if (!access(pkg_file, 0))
1829                 return 0;
1830         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1831         return 0;
1832 }
1833
1834 enum ice_pkg_type
1835 ice_load_pkg_type(struct ice_hw *hw)
1836 {
1837         enum ice_pkg_type package_type;
1838
1839         /* store the activated package type (OS default or Comms) */
1840         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1841                 ICE_PKG_NAME_SIZE))
1842                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1843         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1844                 ICE_PKG_NAME_SIZE))
1845                 package_type = ICE_PKG_TYPE_COMMS;
1846         else
1847                 package_type = ICE_PKG_TYPE_UNKNOWN;
1848
1849         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1850                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1851                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1852                 hw->active_pkg_name);
1853
1854         return package_type;
1855 }
1856
1857 static int ice_load_pkg(struct rte_eth_dev *dev)
1858 {
1859         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1861         int err;
1862         uint8_t *buf;
1863         int buf_len;
1864         FILE *file;
1865         struct stat fstat;
1866         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1867         struct ice_adapter *ad =
1868                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1869
1870         ice_pkg_file_search_path(pci_dev, pkg_file);
1871
1872         file = fopen(pkg_file, "rb");
1873         if (!file)  {
1874                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1875                 return -1;
1876         }
1877
1878         err = stat(pkg_file, &fstat);
1879         if (err) {
1880                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1881                 fclose(file);
1882                 return err;
1883         }
1884
1885         buf_len = fstat.st_size;
1886         buf = rte_malloc(NULL, buf_len, 0);
1887
1888         if (!buf) {
1889                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1890                                 buf_len);
1891                 fclose(file);
1892                 return -1;
1893         }
1894
1895         err = fread(buf, buf_len, 1, file);
1896         if (err != 1) {
1897                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1898                 fclose(file);
1899                 err = -1;
1900                 goto fail_exit;
1901         }
1902
1903         fclose(file);
1904
1905         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1906         if (err) {
1907                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1908                 goto fail_exit;
1909         }
1910
1911         /* store the loaded pkg type info */
1912         ad->active_pkg_type = ice_load_pkg_type(hw);
1913
1914         err = ice_init_hw_tbls(hw);
1915         if (err) {
1916                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1917                 goto fail_init_tbls;
1918         }
1919
1920         return 0;
1921
1922 fail_init_tbls:
1923         rte_free(hw->pkg_copy);
1924 fail_exit:
1925         rte_free(buf);
1926         return err;
1927 }
1928
1929 static void
1930 ice_base_queue_get(struct ice_pf *pf)
1931 {
1932         uint32_t reg;
1933         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1934
1935         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1936         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1937                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1938         } else {
1939                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1940                                         " index");
1941         }
1942 }
1943
1944 static int
1945 parse_bool(const char *key, const char *value, void *args)
1946 {
1947         int *i = (int *)args;
1948         char *end;
1949         int num;
1950
1951         num = strtoul(value, &end, 10);
1952
1953         if (num != 0 && num != 1) {
1954                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1955                         "value must be 0 or 1",
1956                         value, key);
1957                 return -1;
1958         }
1959
1960         *i = num;
1961         return 0;
1962 }
1963
1964 static int ice_parse_devargs(struct rte_eth_dev *dev)
1965 {
1966         struct ice_adapter *ad =
1967                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1968         struct rte_devargs *devargs = dev->device->devargs;
1969         struct rte_kvargs *kvlist;
1970         int ret;
1971
1972         if (devargs == NULL)
1973                 return 0;
1974
1975         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1976         if (kvlist == NULL) {
1977                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1978                 return -EINVAL;
1979         }
1980
1981         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1982         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1983                sizeof(ad->devargs.proto_xtr));
1984
1985         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1986                                  &handle_proto_xtr_arg, &ad->devargs);
1987         if (ret)
1988                 goto bail;
1989
1990         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1991                                  &parse_bool, &ad->devargs.safe_mode_support);
1992         if (ret)
1993                 goto bail;
1994
1995         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1996                                  &parse_bool, &ad->devargs.pipe_mode_support);
1997         if (ret)
1998                 goto bail;
1999
2000         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2001                                  &parse_bool, &ad->devargs.flow_mark_support);
2002         if (ret)
2003                 goto bail;
2004
2005 bail:
2006         rte_kvargs_free(kvlist);
2007         return ret;
2008 }
2009
2010 /* Forward LLDP packets to default VSI by set switch rules */
2011 static int
2012 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2013 {
2014         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2015         struct ice_fltr_list_entry *s_list_itr = NULL;
2016         struct LIST_HEAD_TYPE list_head;
2017         int ret = 0;
2018
2019         INIT_LIST_HEAD(&list_head);
2020
2021         s_list_itr = (struct ice_fltr_list_entry *)
2022                         ice_malloc(hw, sizeof(*s_list_itr));
2023         if (!s_list_itr)
2024                 return -ENOMEM;
2025         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2026         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2027         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2028                         RTE_ETHER_TYPE_LLDP;
2029         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2030         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2031         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2032         LIST_ADD(&s_list_itr->list_entry, &list_head);
2033         if (on)
2034                 ret = ice_add_eth_mac(hw, &list_head);
2035         else
2036                 ret = ice_remove_eth_mac(hw, &list_head);
2037
2038         rte_free(s_list_itr);
2039         return ret;
2040 }
2041
2042 static enum ice_status
2043 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2044                 uint16_t num, uint16_t desc_id,
2045                 uint16_t *prof_buf, uint16_t *num_prof)
2046 {
2047         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2048         int ret;
2049         uint16_t buf_len;
2050         bool res_shared = 1;
2051         struct ice_aq_desc aq_desc;
2052         struct ice_sq_cd *cd = NULL;
2053         struct ice_aqc_get_allocd_res_desc *cmd =
2054                         &aq_desc.params.get_res_desc;
2055
2056         buf_len = sizeof(resp_buf->elem) * num;
2057         resp_buf = ice_malloc(hw, buf_len);
2058         if (!resp_buf)
2059                 return -ENOMEM;
2060
2061         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2062                         ice_aqc_opc_get_allocd_res_desc);
2063
2064         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2065                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2066                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2067         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2068
2069         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2070         if (!ret)
2071                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2072         else
2073                 goto exit;
2074
2075         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2076                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2077
2078 exit:
2079         rte_free(resp_buf);
2080         return ret;
2081 }
2082 static int
2083 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2084 {
2085         int ret;
2086         uint16_t prof_id;
2087         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2088         uint16_t first_desc = 1;
2089         uint16_t num_prof = 0;
2090
2091         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2092                         first_desc, prof_buf, &num_prof);
2093         if (ret) {
2094                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2095                 return ret;
2096         }
2097
2098         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2099                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2100                 if (ret) {
2101                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2102                         return ret;
2103                 }
2104         }
2105         return 0;
2106 }
2107
2108 static int
2109 ice_reset_fxp_resource(struct ice_hw *hw)
2110 {
2111         int ret;
2112
2113         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2114         if (ret) {
2115                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2116                 return ret;
2117         }
2118
2119         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2120         if (ret) {
2121                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2122                 return ret;
2123         }
2124
2125         return 0;
2126 }
2127
2128 static int
2129 ice_dev_init(struct rte_eth_dev *dev)
2130 {
2131         struct rte_pci_device *pci_dev;
2132         struct rte_intr_handle *intr_handle;
2133         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2135         struct ice_adapter *ad =
2136                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2137         struct ice_vsi *vsi;
2138         int ret;
2139
2140         dev->dev_ops = &ice_eth_dev_ops;
2141         dev->rx_pkt_burst = ice_recv_pkts;
2142         dev->tx_pkt_burst = ice_xmit_pkts;
2143         dev->tx_pkt_prepare = ice_prep_pkts;
2144
2145         /* for secondary processes, we don't initialise any further as primary
2146          * has already done this work.
2147          */
2148         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2149                 ice_set_rx_function(dev);
2150                 ice_set_tx_function(dev);
2151                 return 0;
2152         }
2153
2154         ice_set_default_ptype_table(dev);
2155         pci_dev = RTE_DEV_TO_PCI(dev->device);
2156         intr_handle = &pci_dev->intr_handle;
2157
2158         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2159         pf->adapter->eth_dev = dev;
2160         pf->dev_data = dev->data;
2161         hw->back = pf->adapter;
2162         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2163         hw->vendor_id = pci_dev->id.vendor_id;
2164         hw->device_id = pci_dev->id.device_id;
2165         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2166         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2167         hw->bus.device = pci_dev->addr.devid;
2168         hw->bus.func = pci_dev->addr.function;
2169
2170         ret = ice_parse_devargs(dev);
2171         if (ret) {
2172                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2173                 return -EINVAL;
2174         }
2175
2176         ice_init_controlq_parameter(hw);
2177
2178         ret = ice_init_hw(hw);
2179         if (ret) {
2180                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2181                 return -EINVAL;
2182         }
2183
2184         ret = ice_load_pkg(dev);
2185         if (ret) {
2186                 if (ad->devargs.safe_mode_support == 0) {
2187                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2188                                         "Use safe-mode-support=1 to enter Safe Mode");
2189                         return ret;
2190                 }
2191
2192                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2193                                         "Entering Safe Mode");
2194                 ad->is_safe_mode = 1;
2195         }
2196
2197         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2198                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2199                      hw->api_maj_ver, hw->api_min_ver);
2200
2201         ice_pf_sw_init(dev);
2202         ret = ice_init_mac_address(dev);
2203         if (ret) {
2204                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2205                 goto err_init_mac;
2206         }
2207
2208         /* Pass the information to the rte_eth_dev_close() that it should also
2209          * release the private port resources.
2210          */
2211         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2212
2213         ret = ice_res_pool_init(&pf->msix_pool, 1,
2214                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2215         if (ret) {
2216                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2217                 goto err_msix_pool_init;
2218         }
2219
2220         ret = ice_pf_setup(pf);
2221         if (ret) {
2222                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2223                 goto err_pf_setup;
2224         }
2225
2226         ret = ice_send_driver_ver(hw);
2227         if (ret) {
2228                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2229                 goto err_pf_setup;
2230         }
2231
2232         vsi = pf->main_vsi;
2233
2234         /* Disable double vlan by default */
2235         ice_vsi_config_double_vlan(vsi, false);
2236
2237         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2238         if (ret != ICE_SUCCESS)
2239                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2240         ret = ice_init_dcb(hw, true);
2241         if (ret != ICE_SUCCESS)
2242                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2243         /* Forward LLDP packets to default VSI */
2244         ret = ice_vsi_config_sw_lldp(vsi, true);
2245         if (ret != ICE_SUCCESS)
2246                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2247         /* register callback func to eal lib */
2248         rte_intr_callback_register(intr_handle,
2249                                    ice_interrupt_handler, dev);
2250
2251         ice_pf_enable_irq0(hw);
2252
2253         /* enable uio intr after callback register */
2254         rte_intr_enable(intr_handle);
2255
2256         /* get base queue pairs index  in the device */
2257         ice_base_queue_get(pf);
2258
2259         if (!ad->is_safe_mode) {
2260                 ret = ice_flow_init(ad);
2261                 if (ret) {
2262                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2263                         return ret;
2264                 }
2265         }
2266
2267         ret = ice_reset_fxp_resource(hw);
2268         if (ret) {
2269                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2270                 return ret;
2271         }
2272
2273         return 0;
2274
2275 err_pf_setup:
2276         ice_res_pool_destroy(&pf->msix_pool);
2277 err_msix_pool_init:
2278         rte_free(dev->data->mac_addrs);
2279         dev->data->mac_addrs = NULL;
2280 err_init_mac:
2281         ice_sched_cleanup_all(hw);
2282         rte_free(hw->port_info);
2283         ice_shutdown_all_ctrlq(hw);
2284         rte_free(pf->proto_xtr);
2285
2286         return ret;
2287 }
2288
2289 int
2290 ice_release_vsi(struct ice_vsi *vsi)
2291 {
2292         struct ice_hw *hw;
2293         struct ice_vsi_ctx vsi_ctx;
2294         enum ice_status ret;
2295
2296         if (!vsi)
2297                 return 0;
2298
2299         hw = ICE_VSI_TO_HW(vsi);
2300
2301         ice_remove_all_mac_vlan_filters(vsi);
2302
2303         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2304
2305         vsi_ctx.vsi_num = vsi->vsi_id;
2306         vsi_ctx.info = vsi->info;
2307         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2308         if (ret != ICE_SUCCESS) {
2309                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2310                 rte_free(vsi);
2311                 return -1;
2312         }
2313
2314         rte_free(vsi);
2315         return 0;
2316 }
2317
2318 void
2319 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2320 {
2321         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2322         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2323         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2324         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2325         uint16_t msix_intr, i;
2326
2327         /* disable interrupt and also clear all the exist config */
2328         for (i = 0; i < vsi->nb_qps; i++) {
2329                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2330                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2331                 rte_wmb();
2332         }
2333
2334         if (rte_intr_allow_others(intr_handle))
2335                 /* vfio-pci */
2336                 for (i = 0; i < vsi->nb_msix; i++) {
2337                         msix_intr = vsi->msix_intr + i;
2338                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2339                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2340                 }
2341         else
2342                 /* igb_uio */
2343                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2344 }
2345
2346 static void
2347 ice_dev_stop(struct rte_eth_dev *dev)
2348 {
2349         struct rte_eth_dev_data *data = dev->data;
2350         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2351         struct ice_vsi *main_vsi = pf->main_vsi;
2352         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2354         uint16_t i;
2355
2356         /* avoid stopping again */
2357         if (pf->adapter_stopped)
2358                 return;
2359
2360         /* stop and clear all Rx queues */
2361         for (i = 0; i < data->nb_rx_queues; i++)
2362                 ice_rx_queue_stop(dev, i);
2363
2364         /* stop and clear all Tx queues */
2365         for (i = 0; i < data->nb_tx_queues; i++)
2366                 ice_tx_queue_stop(dev, i);
2367
2368         /* disable all queue interrupts */
2369         ice_vsi_disable_queues_intr(main_vsi);
2370
2371         if (pf->init_link_up)
2372                 ice_dev_set_link_up(dev);
2373         else
2374                 ice_dev_set_link_down(dev);
2375
2376         /* Clean datapath event and queue/vec mapping */
2377         rte_intr_efd_disable(intr_handle);
2378         if (intr_handle->intr_vec) {
2379                 rte_free(intr_handle->intr_vec);
2380                 intr_handle->intr_vec = NULL;
2381         }
2382
2383         pf->adapter_stopped = true;
2384 }
2385
2386 static void
2387 ice_dev_close(struct rte_eth_dev *dev)
2388 {
2389         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2390         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2392         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2393         struct ice_adapter *ad =
2394                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2395
2396         /* Since stop will make link down, then the link event will be
2397          * triggered, disable the irq firstly to avoid the port_infoe etc
2398          * resources deallocation causing the interrupt service thread
2399          * crash.
2400          */
2401         ice_pf_disable_irq0(hw);
2402
2403         ice_dev_stop(dev);
2404
2405         if (!ad->is_safe_mode)
2406                 ice_flow_uninit(ad);
2407
2408         /* release all queue resource */
2409         ice_free_queues(dev);
2410
2411         ice_res_pool_destroy(&pf->msix_pool);
2412         ice_release_vsi(pf->main_vsi);
2413         ice_sched_cleanup_all(hw);
2414         ice_free_hw_tbls(hw);
2415         rte_free(hw->port_info);
2416         hw->port_info = NULL;
2417         ice_shutdown_all_ctrlq(hw);
2418         rte_free(pf->proto_xtr);
2419         pf->proto_xtr = NULL;
2420
2421         dev->dev_ops = NULL;
2422         dev->rx_pkt_burst = NULL;
2423         dev->tx_pkt_burst = NULL;
2424
2425         rte_free(dev->data->mac_addrs);
2426         dev->data->mac_addrs = NULL;
2427
2428         /* disable uio intr before callback unregister */
2429         rte_intr_disable(intr_handle);
2430
2431         /* unregister callback func from eal lib */
2432         rte_intr_callback_unregister(intr_handle,
2433                                      ice_interrupt_handler, dev);
2434 }
2435
2436 static int
2437 ice_dev_uninit(struct rte_eth_dev *dev)
2438 {
2439         ice_dev_close(dev);
2440
2441         return 0;
2442 }
2443
2444 static int ice_init_rss(struct ice_pf *pf)
2445 {
2446         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2447         struct ice_vsi *vsi = pf->main_vsi;
2448         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2449         struct rte_eth_rss_conf *rss_conf;
2450         struct ice_aqc_get_set_rss_keys key;
2451         uint16_t i, nb_q;
2452         int ret = 0;
2453         bool is_safe_mode = pf->adapter->is_safe_mode;
2454         uint32_t reg;
2455
2456         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2457         nb_q = dev->data->nb_rx_queues;
2458         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2459         vsi->rss_lut_size = pf->hash_lut_size;
2460
2461         if (is_safe_mode) {
2462                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2463                 return 0;
2464         }
2465
2466         if (!vsi->rss_key)
2467                 vsi->rss_key = rte_zmalloc(NULL,
2468                                            vsi->rss_key_size, 0);
2469         if (!vsi->rss_lut)
2470                 vsi->rss_lut = rte_zmalloc(NULL,
2471                                            vsi->rss_lut_size, 0);
2472
2473         /* configure RSS key */
2474         if (!rss_conf->rss_key) {
2475                 /* Calculate the default hash key */
2476                 for (i = 0; i <= vsi->rss_key_size; i++)
2477                         vsi->rss_key[i] = (uint8_t)rte_rand();
2478         } else {
2479                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2480                            RTE_MIN(rss_conf->rss_key_len,
2481                                    vsi->rss_key_size));
2482         }
2483         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2484         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2485         if (ret)
2486                 return -EINVAL;
2487
2488         /* init RSS LUT table */
2489         for (i = 0; i < vsi->rss_lut_size; i++)
2490                 vsi->rss_lut[i] = i % nb_q;
2491
2492         ret = ice_aq_set_rss_lut(hw, vsi->idx,
2493                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2494                                  vsi->rss_lut, vsi->rss_lut_size);
2495         if (ret)
2496                 return -EINVAL;
2497
2498         /* Enable registers for symmetric_toeplitz function. */
2499         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2500         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2501                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2502         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2503
2504         /* configure RSS for IPv4 with input set IPv4 src/dst */
2505         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2506                               ICE_FLOW_SEG_HDR_IPV4, 0);
2507         if (ret)
2508                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2509
2510         /* configure RSS for IPv6 with input set IPv6 src/dst */
2511         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2512                               ICE_FLOW_SEG_HDR_IPV6, 0);
2513         if (ret)
2514                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2515
2516         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2517         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2518                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2519         if (ret)
2520                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2521
2522         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2523         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2524                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2525         if (ret)
2526                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2527
2528         /* configure RSS for sctp6 with input set IPv6 src/dst */
2529         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2530                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2531         if (ret)
2532                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2533                                 __func__, ret);
2534
2535         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2536         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2537                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2538         if (ret)
2539                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2540
2541         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2542         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2543                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2544         if (ret)
2545                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2546
2547         /* configure RSS for sctp4 with input set IP src/dst */
2548         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2549                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2550         if (ret)
2551                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2552                                 __func__, ret);
2553
2554         /* configure RSS for gtpu with input set TEID */
2555         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2556                                 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2557         if (ret)
2558                 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2559                                 __func__, ret);
2560
2561         /**
2562          * configure RSS for pppoe/pppod with input set
2563          * Source MAC and Session ID
2564          */
2565         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2566                                 ICE_FLOW_SEG_HDR_PPPOE, 0);
2567         if (ret)
2568                 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2569                                 __func__, ret);
2570
2571         return 0;
2572 }
2573
2574 static int
2575 ice_dev_configure(struct rte_eth_dev *dev)
2576 {
2577         struct ice_adapter *ad =
2578                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2579         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2580         int ret;
2581
2582         /* Initialize to TRUE. If any of Rx queues doesn't meet the
2583          * bulk allocation or vector Rx preconditions we will reset it.
2584          */
2585         ad->rx_bulk_alloc_allowed = true;
2586         ad->tx_simple_allowed = true;
2587
2588         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2589                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2590
2591         ret = ice_init_rss(pf);
2592         if (ret) {
2593                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2594                 return ret;
2595         }
2596
2597         return 0;
2598 }
2599
2600 static void
2601 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2602                        int base_queue, int nb_queue)
2603 {
2604         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2605         uint32_t val, val_tx;
2606         int i;
2607
2608         for (i = 0; i < nb_queue; i++) {
2609                 /*do actual bind*/
2610                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2611                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2612                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2613                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2614
2615                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2616                             base_queue + i, msix_vect);
2617                 /* set ITR0 value */
2618                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2619                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2620                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2621         }
2622 }
2623
2624 void
2625 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2626 {
2627         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2628         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2629         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2630         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2631         uint16_t msix_vect = vsi->msix_intr;
2632         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2633         uint16_t queue_idx = 0;
2634         int record = 0;
2635         int i;
2636
2637         /* clear Rx/Tx queue interrupt */
2638         for (i = 0; i < vsi->nb_used_qps; i++) {
2639                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2640                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2641         }
2642
2643         /* PF bind interrupt */
2644         if (rte_intr_dp_is_en(intr_handle)) {
2645                 queue_idx = 0;
2646                 record = 1;
2647         }
2648
2649         for (i = 0; i < vsi->nb_used_qps; i++) {
2650                 if (nb_msix <= 1) {
2651                         if (!rte_intr_allow_others(intr_handle))
2652                                 msix_vect = ICE_MISC_VEC_ID;
2653
2654                         /* uio mapping all queue to one msix_vect */
2655                         __vsi_queues_bind_intr(vsi, msix_vect,
2656                                                vsi->base_queue + i,
2657                                                vsi->nb_used_qps - i);
2658
2659                         for (; !!record && i < vsi->nb_used_qps; i++)
2660                                 intr_handle->intr_vec[queue_idx + i] =
2661                                         msix_vect;
2662                         break;
2663                 }
2664
2665                 /* vfio 1:1 queue/msix_vect mapping */
2666                 __vsi_queues_bind_intr(vsi, msix_vect,
2667                                        vsi->base_queue + i, 1);
2668
2669                 if (!!record)
2670                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2671
2672                 msix_vect++;
2673                 nb_msix--;
2674         }
2675 }
2676
2677 void
2678 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2679 {
2680         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2681         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2682         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2683         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2684         uint16_t msix_intr, i;
2685
2686         if (rte_intr_allow_others(intr_handle))
2687                 for (i = 0; i < vsi->nb_used_qps; i++) {
2688                         msix_intr = vsi->msix_intr + i;
2689                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2690                                       GLINT_DYN_CTL_INTENA_M |
2691                                       GLINT_DYN_CTL_CLEARPBA_M |
2692                                       GLINT_DYN_CTL_ITR_INDX_M |
2693                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2694                 }
2695         else
2696                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2697                               GLINT_DYN_CTL_INTENA_M |
2698                               GLINT_DYN_CTL_CLEARPBA_M |
2699                               GLINT_DYN_CTL_ITR_INDX_M |
2700                               GLINT_DYN_CTL_WB_ON_ITR_M);
2701 }
2702
2703 static int
2704 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2705 {
2706         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2707         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2709         struct ice_vsi *vsi = pf->main_vsi;
2710         uint32_t intr_vector = 0;
2711
2712         rte_intr_disable(intr_handle);
2713
2714         /* check and configure queue intr-vector mapping */
2715         if ((rte_intr_cap_multiple(intr_handle) ||
2716              !RTE_ETH_DEV_SRIOV(dev).active) &&
2717             dev->data->dev_conf.intr_conf.rxq != 0) {
2718                 intr_vector = dev->data->nb_rx_queues;
2719                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2720                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2721                                     ICE_MAX_INTR_QUEUE_NUM);
2722                         return -ENOTSUP;
2723                 }
2724                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2725                         return -1;
2726         }
2727
2728         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2729                 intr_handle->intr_vec =
2730                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2731                             0);
2732                 if (!intr_handle->intr_vec) {
2733                         PMD_DRV_LOG(ERR,
2734                                     "Failed to allocate %d rx_queues intr_vec",
2735                                     dev->data->nb_rx_queues);
2736                         return -ENOMEM;
2737                 }
2738         }
2739
2740         /* Map queues with MSIX interrupt */
2741         vsi->nb_used_qps = dev->data->nb_rx_queues;
2742         ice_vsi_queues_bind_intr(vsi);
2743
2744         /* Enable interrupts for all the queues */
2745         ice_vsi_enable_queues_intr(vsi);
2746
2747         rte_intr_enable(intr_handle);
2748
2749         return 0;
2750 }
2751
2752 static void
2753 ice_get_init_link_status(struct rte_eth_dev *dev)
2754 {
2755         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2756         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2757         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2758         struct ice_link_status link_status;
2759         int ret;
2760
2761         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2762                                    &link_status, NULL);
2763         if (ret != ICE_SUCCESS) {
2764                 PMD_DRV_LOG(ERR, "Failed to get link info");
2765                 pf->init_link_up = false;
2766                 return;
2767         }
2768
2769         if (link_status.link_info & ICE_AQ_LINK_UP)
2770                 pf->init_link_up = true;
2771 }
2772
2773 static int
2774 ice_dev_start(struct rte_eth_dev *dev)
2775 {
2776         struct rte_eth_dev_data *data = dev->data;
2777         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2779         struct ice_vsi *vsi = pf->main_vsi;
2780         uint16_t nb_rxq = 0;
2781         uint16_t nb_txq, i;
2782         uint16_t max_frame_size;
2783         int mask, ret;
2784
2785         /* program Tx queues' context in hardware */
2786         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2787                 ret = ice_tx_queue_start(dev, nb_txq);
2788                 if (ret) {
2789                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2790                         goto tx_err;
2791                 }
2792         }
2793
2794         /* program Rx queues' context in hardware*/
2795         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2796                 ret = ice_rx_queue_start(dev, nb_rxq);
2797                 if (ret) {
2798                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2799                         goto rx_err;
2800                 }
2801         }
2802
2803         ice_set_rx_function(dev);
2804         ice_set_tx_function(dev);
2805
2806         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2807                         ETH_VLAN_EXTEND_MASK;
2808         ret = ice_vlan_offload_set(dev, mask);
2809         if (ret) {
2810                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2811                 goto rx_err;
2812         }
2813
2814         /* enable Rx interrput and mapping Rx queue to interrupt vector */
2815         if (ice_rxq_intr_setup(dev))
2816                 return -EIO;
2817
2818         /* Enable receiving broadcast packets and transmitting packets */
2819         ret = ice_set_vsi_promisc(hw, vsi->idx,
2820                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2821                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2822                                   0);
2823         if (ret != ICE_SUCCESS)
2824                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2825
2826         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2827                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2828                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2829                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2830                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2831                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
2832                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2833                                      NULL);
2834         if (ret != ICE_SUCCESS)
2835                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2836
2837         ice_get_init_link_status(dev);
2838
2839         ice_dev_set_link_up(dev);
2840
2841         /* Call get_link_info aq commond to enable/disable LSE */
2842         ice_link_update(dev, 0);
2843
2844         pf->adapter_stopped = false;
2845
2846         /* Set the max frame size to default value*/
2847         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2848                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2849                 ICE_FRAME_SIZE_MAX;
2850
2851         /* Set the max frame size to HW*/
2852         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2853
2854         return 0;
2855
2856         /* stop the started queues if failed to start all queues */
2857 rx_err:
2858         for (i = 0; i < nb_rxq; i++)
2859                 ice_rx_queue_stop(dev, i);
2860 tx_err:
2861         for (i = 0; i < nb_txq; i++)
2862                 ice_tx_queue_stop(dev, i);
2863
2864         return -EIO;
2865 }
2866
2867 static int
2868 ice_dev_reset(struct rte_eth_dev *dev)
2869 {
2870         int ret;
2871
2872         if (dev->data->sriov.active)
2873                 return -ENOTSUP;
2874
2875         ret = ice_dev_uninit(dev);
2876         if (ret) {
2877                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2878                 return -ENXIO;
2879         }
2880
2881         ret = ice_dev_init(dev);
2882         if (ret) {
2883                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2884                 return -ENXIO;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int
2891 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2892 {
2893         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2894         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895         struct ice_vsi *vsi = pf->main_vsi;
2896         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2897         bool is_safe_mode = pf->adapter->is_safe_mode;
2898         u64 phy_type_low;
2899         u64 phy_type_high;
2900
2901         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2902         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2903         dev_info->max_rx_queues = vsi->nb_qps;
2904         dev_info->max_tx_queues = vsi->nb_qps;
2905         dev_info->max_mac_addrs = vsi->max_macaddrs;
2906         dev_info->max_vfs = pci_dev->max_vfs;
2907         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2908         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2909
2910         dev_info->rx_offload_capa =
2911                 DEV_RX_OFFLOAD_VLAN_STRIP |
2912                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2913                 DEV_RX_OFFLOAD_KEEP_CRC |
2914                 DEV_RX_OFFLOAD_SCATTER |
2915                 DEV_RX_OFFLOAD_VLAN_FILTER;
2916         dev_info->tx_offload_capa =
2917                 DEV_TX_OFFLOAD_VLAN_INSERT |
2918                 DEV_TX_OFFLOAD_TCP_TSO |
2919                 DEV_TX_OFFLOAD_MULTI_SEGS |
2920                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2921         dev_info->flow_type_rss_offloads = 0;
2922
2923         if (!is_safe_mode) {
2924                 dev_info->rx_offload_capa |=
2925                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2926                         DEV_RX_OFFLOAD_UDP_CKSUM |
2927                         DEV_RX_OFFLOAD_TCP_CKSUM |
2928                         DEV_RX_OFFLOAD_QINQ_STRIP |
2929                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2930                         DEV_RX_OFFLOAD_VLAN_EXTEND |
2931                         DEV_RX_OFFLOAD_RSS_HASH;
2932                 dev_info->tx_offload_capa |=
2933                         DEV_TX_OFFLOAD_QINQ_INSERT |
2934                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2935                         DEV_TX_OFFLOAD_UDP_CKSUM |
2936                         DEV_TX_OFFLOAD_TCP_CKSUM |
2937                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2938                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2939                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2940                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2941         }
2942
2943         dev_info->rx_queue_offload_capa = 0;
2944         dev_info->tx_queue_offload_capa = 0;
2945
2946         dev_info->reta_size = pf->hash_lut_size;
2947         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2948
2949         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2950                 .rx_thresh = {
2951                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2952                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2953                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2954                 },
2955                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2956                 .rx_drop_en = 0,
2957                 .offloads = 0,
2958         };
2959
2960         dev_info->default_txconf = (struct rte_eth_txconf) {
2961                 .tx_thresh = {
2962                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2963                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2964                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2965                 },
2966                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2967                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2968                 .offloads = 0,
2969         };
2970
2971         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2972                 .nb_max = ICE_MAX_RING_DESC,
2973                 .nb_min = ICE_MIN_RING_DESC,
2974                 .nb_align = ICE_ALIGN_RING_DESC,
2975         };
2976
2977         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2978                 .nb_max = ICE_MAX_RING_DESC,
2979                 .nb_min = ICE_MIN_RING_DESC,
2980                 .nb_align = ICE_ALIGN_RING_DESC,
2981         };
2982
2983         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2984                                ETH_LINK_SPEED_100M |
2985                                ETH_LINK_SPEED_1G |
2986                                ETH_LINK_SPEED_2_5G |
2987                                ETH_LINK_SPEED_5G |
2988                                ETH_LINK_SPEED_10G |
2989                                ETH_LINK_SPEED_20G |
2990                                ETH_LINK_SPEED_25G;
2991
2992         phy_type_low = hw->port_info->phy.phy_type_low;
2993         phy_type_high = hw->port_info->phy.phy_type_high;
2994
2995         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2996                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2997
2998         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2999                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3000                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3001
3002         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3003         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3004
3005         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3006         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3007         dev_info->default_rxportconf.nb_queues = 1;
3008         dev_info->default_txportconf.nb_queues = 1;
3009         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3010         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3011
3012         return 0;
3013 }
3014
3015 static inline int
3016 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3017                             struct rte_eth_link *link)
3018 {
3019         struct rte_eth_link *dst = link;
3020         struct rte_eth_link *src = &dev->data->dev_link;
3021
3022         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3023                                 *(uint64_t *)src) == 0)
3024                 return -1;
3025
3026         return 0;
3027 }
3028
3029 static inline int
3030 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3031                              struct rte_eth_link *link)
3032 {
3033         struct rte_eth_link *dst = &dev->data->dev_link;
3034         struct rte_eth_link *src = link;
3035
3036         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3037                                 *(uint64_t *)src) == 0)
3038                 return -1;
3039
3040         return 0;
3041 }
3042
3043 static int
3044 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3045 {
3046 #define CHECK_INTERVAL 100  /* 100ms */
3047 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3048         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049         struct ice_link_status link_status;
3050         struct rte_eth_link link, old;
3051         int status;
3052         unsigned int rep_cnt = MAX_REPEAT_TIME;
3053         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3054
3055         memset(&link, 0, sizeof(link));
3056         memset(&old, 0, sizeof(old));
3057         memset(&link_status, 0, sizeof(link_status));
3058         ice_atomic_read_link_status(dev, &old);
3059
3060         do {
3061                 /* Get link status information from hardware */
3062                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3063                                               &link_status, NULL);
3064                 if (status != ICE_SUCCESS) {
3065                         link.link_speed = ETH_SPEED_NUM_100M;
3066                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3067                         PMD_DRV_LOG(ERR, "Failed to get link info");
3068                         goto out;
3069                 }
3070
3071                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3072                 if (!wait_to_complete || link.link_status)
3073                         break;
3074
3075                 rte_delay_ms(CHECK_INTERVAL);
3076         } while (--rep_cnt);
3077
3078         if (!link.link_status)
3079                 goto out;
3080
3081         /* Full-duplex operation at all supported speeds */
3082         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3083
3084         /* Parse the link status */
3085         switch (link_status.link_speed) {
3086         case ICE_AQ_LINK_SPEED_10MB:
3087                 link.link_speed = ETH_SPEED_NUM_10M;
3088                 break;
3089         case ICE_AQ_LINK_SPEED_100MB:
3090                 link.link_speed = ETH_SPEED_NUM_100M;
3091                 break;
3092         case ICE_AQ_LINK_SPEED_1000MB:
3093                 link.link_speed = ETH_SPEED_NUM_1G;
3094                 break;
3095         case ICE_AQ_LINK_SPEED_2500MB:
3096                 link.link_speed = ETH_SPEED_NUM_2_5G;
3097                 break;
3098         case ICE_AQ_LINK_SPEED_5GB:
3099                 link.link_speed = ETH_SPEED_NUM_5G;
3100                 break;
3101         case ICE_AQ_LINK_SPEED_10GB:
3102                 link.link_speed = ETH_SPEED_NUM_10G;
3103                 break;
3104         case ICE_AQ_LINK_SPEED_20GB:
3105                 link.link_speed = ETH_SPEED_NUM_20G;
3106                 break;
3107         case ICE_AQ_LINK_SPEED_25GB:
3108                 link.link_speed = ETH_SPEED_NUM_25G;
3109                 break;
3110         case ICE_AQ_LINK_SPEED_40GB:
3111                 link.link_speed = ETH_SPEED_NUM_40G;
3112                 break;
3113         case ICE_AQ_LINK_SPEED_50GB:
3114                 link.link_speed = ETH_SPEED_NUM_50G;
3115                 break;
3116         case ICE_AQ_LINK_SPEED_100GB:
3117                 link.link_speed = ETH_SPEED_NUM_100G;
3118                 break;
3119         case ICE_AQ_LINK_SPEED_UNKNOWN:
3120         default:
3121                 PMD_DRV_LOG(ERR, "Unknown link speed");
3122                 link.link_speed = ETH_SPEED_NUM_NONE;
3123                 break;
3124         }
3125
3126         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3127                               ETH_LINK_SPEED_FIXED);
3128
3129 out:
3130         ice_atomic_write_link_status(dev, &link);
3131         if (link.link_status == old.link_status)
3132                 return -1;
3133
3134         return 0;
3135 }
3136
3137 /* Force the physical link state by getting the current PHY capabilities from
3138  * hardware and setting the PHY config based on the determined capabilities. If
3139  * link changes, link event will be triggered because both the Enable Automatic
3140  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3141  */
3142 static enum ice_status
3143 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3144 {
3145         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3146         struct ice_aqc_get_phy_caps_data *pcaps;
3147         struct ice_port_info *pi;
3148         enum ice_status status;
3149
3150         if (!hw || !hw->port_info)
3151                 return ICE_ERR_PARAM;
3152
3153         pi = hw->port_info;
3154
3155         pcaps = (struct ice_aqc_get_phy_caps_data *)
3156                 ice_malloc(hw, sizeof(*pcaps));
3157         if (!pcaps)
3158                 return ICE_ERR_NO_MEMORY;
3159
3160         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3161                                      NULL);
3162         if (status)
3163                 goto out;
3164
3165         /* No change in link */
3166         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3167             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3168                 goto out;
3169
3170         cfg.phy_type_low = pcaps->phy_type_low;
3171         cfg.phy_type_high = pcaps->phy_type_high;
3172         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3173         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3174         cfg.eee_cap = pcaps->eee_cap;
3175         cfg.eeer_value = pcaps->eeer_value;
3176         cfg.link_fec_opt = pcaps->link_fec_options;
3177         if (link_up)
3178                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3179         else
3180                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3181
3182         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3183
3184 out:
3185         ice_free(hw, pcaps);
3186         return status;
3187 }
3188
3189 static int
3190 ice_dev_set_link_up(struct rte_eth_dev *dev)
3191 {
3192         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3193
3194         return ice_force_phys_link_state(hw, true);
3195 }
3196
3197 static int
3198 ice_dev_set_link_down(struct rte_eth_dev *dev)
3199 {
3200         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3201
3202         return ice_force_phys_link_state(hw, false);
3203 }
3204
3205 static int
3206 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3207 {
3208         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209         struct rte_eth_dev_data *dev_data = pf->dev_data;
3210         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3211
3212         /* check if mtu is within the allowed range */
3213         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3214                 return -EINVAL;
3215
3216         /* mtu setting is forbidden if port is start */
3217         if (dev_data->dev_started) {
3218                 PMD_DRV_LOG(ERR,
3219                             "port %d must be stopped before configuration",
3220                             dev_data->port_id);
3221                 return -EBUSY;
3222         }
3223
3224         if (frame_size > RTE_ETHER_MAX_LEN)
3225                 dev_data->dev_conf.rxmode.offloads |=
3226                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3227         else
3228                 dev_data->dev_conf.rxmode.offloads &=
3229                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3230
3231         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3232
3233         return 0;
3234 }
3235
3236 static int ice_macaddr_set(struct rte_eth_dev *dev,
3237                            struct rte_ether_addr *mac_addr)
3238 {
3239         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3240         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3241         struct ice_vsi *vsi = pf->main_vsi;
3242         struct ice_mac_filter *f;
3243         uint8_t flags = 0;
3244         int ret;
3245
3246         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3247                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3248                 return -EINVAL;
3249         }
3250
3251         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3252                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3253                         break;
3254         }
3255
3256         if (!f) {
3257                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3258                 return -EIO;
3259         }
3260
3261         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3262         if (ret != ICE_SUCCESS) {
3263                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3264                 return -EIO;
3265         }
3266         ret = ice_add_mac_filter(vsi, mac_addr);
3267         if (ret != ICE_SUCCESS) {
3268                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3269                 return -EIO;
3270         }
3271         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3272
3273         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3274         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3275         if (ret != ICE_SUCCESS)
3276                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3277
3278         return 0;
3279 }
3280
3281 /* Add a MAC address, and update filters */
3282 static int
3283 ice_macaddr_add(struct rte_eth_dev *dev,
3284                 struct rte_ether_addr *mac_addr,
3285                 __rte_unused uint32_t index,
3286                 __rte_unused uint32_t pool)
3287 {
3288         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289         struct ice_vsi *vsi = pf->main_vsi;
3290         int ret;
3291
3292         ret = ice_add_mac_filter(vsi, mac_addr);
3293         if (ret != ICE_SUCCESS) {
3294                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3295                 return -EINVAL;
3296         }
3297
3298         return ICE_SUCCESS;
3299 }
3300
3301 /* Remove a MAC address, and update filters */
3302 static void
3303 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3304 {
3305         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3306         struct ice_vsi *vsi = pf->main_vsi;
3307         struct rte_eth_dev_data *data = dev->data;
3308         struct rte_ether_addr *macaddr;
3309         int ret;
3310
3311         macaddr = &data->mac_addrs[index];
3312         ret = ice_remove_mac_filter(vsi, macaddr);
3313         if (ret) {
3314                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3315                 return;
3316         }
3317 }
3318
3319 static int
3320 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3321 {
3322         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323         struct ice_vsi *vsi = pf->main_vsi;
3324         int ret;
3325
3326         PMD_INIT_FUNC_TRACE();
3327
3328         if (on) {
3329                 ret = ice_add_vlan_filter(vsi, vlan_id);
3330                 if (ret < 0) {
3331                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3332                         return -EINVAL;
3333                 }
3334         } else {
3335                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3336                 if (ret < 0) {
3337                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3338                         return -EINVAL;
3339                 }
3340         }
3341
3342         return 0;
3343 }
3344
3345 /* Configure vlan filter on or off */
3346 static int
3347 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3348 {
3349         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3350         struct ice_vsi_ctx ctxt;
3351         uint8_t sec_flags, sw_flags2;
3352         int ret = 0;
3353
3354         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3355                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3356         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3357
3358         if (on) {
3359                 vsi->info.sec_flags |= sec_flags;
3360                 vsi->info.sw_flags2 |= sw_flags2;
3361         } else {
3362                 vsi->info.sec_flags &= ~sec_flags;
3363                 vsi->info.sw_flags2 &= ~sw_flags2;
3364         }
3365         vsi->info.sw_id = hw->port_info->sw_id;
3366         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3367         ctxt.info.valid_sections =
3368                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3369                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3370         ctxt.vsi_num = vsi->vsi_id;
3371
3372         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3373         if (ret) {
3374                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3375                             on ? "enable" : "disable");
3376                 return -EINVAL;
3377         } else {
3378                 vsi->info.valid_sections |=
3379                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3380                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3381         }
3382
3383         /* consist with other drivers, allow untagged packet when vlan filter on */
3384         if (on)
3385                 ret = ice_add_vlan_filter(vsi, 0);
3386         else
3387                 ret = ice_remove_vlan_filter(vsi, 0);
3388
3389         return 0;
3390 }
3391
3392 static int
3393 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3394 {
3395         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3396         struct ice_vsi_ctx ctxt;
3397         uint8_t vlan_flags;
3398         int ret = 0;
3399
3400         /* Check if it has been already on or off */
3401         if (vsi->info.valid_sections &
3402                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3403                 if (on) {
3404                         if ((vsi->info.vlan_flags &
3405                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3406                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3407                                 return 0; /* already on */
3408                 } else {
3409                         if ((vsi->info.vlan_flags &
3410                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3411                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3412                                 return 0; /* already off */
3413                 }
3414         }
3415
3416         if (on)
3417                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3418         else
3419                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3420         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3421         vsi->info.vlan_flags |= vlan_flags;
3422         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3423         ctxt.info.valid_sections =
3424                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3425         ctxt.vsi_num = vsi->vsi_id;
3426         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3427         if (ret) {
3428                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3429                             on ? "enable" : "disable");
3430                 return -EINVAL;
3431         }
3432
3433         vsi->info.valid_sections |=
3434                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3435
3436         return ret;
3437 }
3438
3439 static int
3440 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3441 {
3442         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3443         struct ice_vsi *vsi = pf->main_vsi;
3444         struct rte_eth_rxmode *rxmode;
3445
3446         rxmode = &dev->data->dev_conf.rxmode;
3447         if (mask & ETH_VLAN_FILTER_MASK) {
3448                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3449                         ice_vsi_config_vlan_filter(vsi, true);
3450                 else
3451                         ice_vsi_config_vlan_filter(vsi, false);
3452         }
3453
3454         if (mask & ETH_VLAN_STRIP_MASK) {
3455                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3456                         ice_vsi_config_vlan_stripping(vsi, true);
3457                 else
3458                         ice_vsi_config_vlan_stripping(vsi, false);
3459         }
3460
3461         if (mask & ETH_VLAN_EXTEND_MASK) {
3462                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3463                         ice_vsi_config_double_vlan(vsi, true);
3464                 else
3465                         ice_vsi_config_double_vlan(vsi, false);
3466         }
3467
3468         return 0;
3469 }
3470
3471 static int
3472 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3473 {
3474         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3475         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3476         int ret;
3477
3478         if (!lut)
3479                 return -EINVAL;
3480
3481         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3482                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3483                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3484                 if (ret) {
3485                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3486                         return -EINVAL;
3487                 }
3488         } else {
3489                 uint64_t *lut_dw = (uint64_t *)lut;
3490                 uint16_t i, lut_size_dw = lut_size / 4;
3491
3492                 for (i = 0; i < lut_size_dw; i++)
3493                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3494         }
3495
3496         return 0;
3497 }
3498
3499 static int
3500 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3501 {
3502         struct ice_pf *pf;
3503         struct ice_hw *hw;
3504         int ret;
3505
3506         if (!vsi || !lut)
3507                 return -EINVAL;
3508
3509         pf = ICE_VSI_TO_PF(vsi);
3510         hw = ICE_VSI_TO_HW(vsi);
3511
3512         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3513                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3514                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3515                 if (ret) {
3516                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3517                         return -EINVAL;
3518                 }
3519         } else {
3520                 uint64_t *lut_dw = (uint64_t *)lut;
3521                 uint16_t i, lut_size_dw = lut_size / 4;
3522
3523                 for (i = 0; i < lut_size_dw; i++)
3524                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3525
3526                 ice_flush(hw);
3527         }
3528
3529         return 0;
3530 }
3531
3532 static int
3533 ice_rss_reta_update(struct rte_eth_dev *dev,
3534                     struct rte_eth_rss_reta_entry64 *reta_conf,
3535                     uint16_t reta_size)
3536 {
3537         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3538         uint16_t i, lut_size = pf->hash_lut_size;
3539         uint16_t idx, shift;
3540         uint8_t *lut;
3541         int ret;
3542
3543         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3544             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3545             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3546                 PMD_DRV_LOG(ERR,
3547                             "The size of hash lookup table configured (%d)"
3548                             "doesn't match the number hardware can "
3549                             "supported (128, 512, 2048)",
3550                             reta_size);
3551                 return -EINVAL;
3552         }
3553
3554         /* It MUST use the current LUT size to get the RSS lookup table,
3555          * otherwise if will fail with -100 error code.
3556          */
3557         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
3558         if (!lut) {
3559                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3560                 return -ENOMEM;
3561         }
3562         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3563         if (ret)
3564                 goto out;
3565
3566         for (i = 0; i < reta_size; i++) {
3567                 idx = i / RTE_RETA_GROUP_SIZE;
3568                 shift = i % RTE_RETA_GROUP_SIZE;
3569                 if (reta_conf[idx].mask & (1ULL << shift))
3570                         lut[i] = reta_conf[idx].reta[shift];
3571         }
3572         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3573         if (ret == 0 && lut_size != reta_size) {
3574                 PMD_DRV_LOG(INFO,
3575                             "The size of hash lookup table is changed from (%d) to (%d)",
3576                             lut_size, reta_size);
3577                 pf->hash_lut_size = reta_size;
3578         }
3579
3580 out:
3581         rte_free(lut);
3582
3583         return ret;
3584 }
3585
3586 static int
3587 ice_rss_reta_query(struct rte_eth_dev *dev,
3588                    struct rte_eth_rss_reta_entry64 *reta_conf,
3589                    uint16_t reta_size)
3590 {
3591         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3592         uint16_t i, lut_size = pf->hash_lut_size;
3593         uint16_t idx, shift;
3594         uint8_t *lut;
3595         int ret;
3596
3597         if (reta_size != lut_size) {
3598                 PMD_DRV_LOG(ERR,
3599                             "The size of hash lookup table configured (%d)"
3600                             "doesn't match the number hardware can "
3601                             "supported (%d)",
3602                             reta_size, lut_size);
3603                 return -EINVAL;
3604         }
3605
3606         lut = rte_zmalloc(NULL, reta_size, 0);
3607         if (!lut) {
3608                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3609                 return -ENOMEM;
3610         }
3611
3612         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3613         if (ret)
3614                 goto out;
3615
3616         for (i = 0; i < reta_size; i++) {
3617                 idx = i / RTE_RETA_GROUP_SIZE;
3618                 shift = i % RTE_RETA_GROUP_SIZE;
3619                 if (reta_conf[idx].mask & (1ULL << shift))
3620                         reta_conf[idx].reta[shift] = lut[i];
3621         }
3622
3623 out:
3624         rte_free(lut);
3625
3626         return ret;
3627 }
3628
3629 static int
3630 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3631 {
3632         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3633         int ret = 0;
3634
3635         if (!key || key_len == 0) {
3636                 PMD_DRV_LOG(DEBUG, "No key to be configured");
3637                 return 0;
3638         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3639                    sizeof(uint32_t)) {
3640                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3641                 return -EINVAL;
3642         }
3643
3644         struct ice_aqc_get_set_rss_keys *key_dw =
3645                 (struct ice_aqc_get_set_rss_keys *)key;
3646
3647         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3648         if (ret) {
3649                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3650                 ret = -EINVAL;
3651         }
3652
3653         return ret;
3654 }
3655
3656 static int
3657 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3658 {
3659         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3660         int ret;
3661
3662         if (!key || !key_len)
3663                 return -EINVAL;
3664
3665         ret = ice_aq_get_rss_key
3666                 (hw, vsi->idx,
3667                  (struct ice_aqc_get_set_rss_keys *)key);
3668         if (ret) {
3669                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3670                 return -EINVAL;
3671         }
3672         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3673
3674         return 0;
3675 }
3676
3677 static int
3678 ice_rss_hash_update(struct rte_eth_dev *dev,
3679                     struct rte_eth_rss_conf *rss_conf)
3680 {
3681         enum ice_status status = ICE_SUCCESS;
3682         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3683         struct ice_vsi *vsi = pf->main_vsi;
3684
3685         /* set hash key */
3686         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3687         if (status)
3688                 return status;
3689
3690         /* TODO: hash enable config, ice_add_rss_cfg */
3691         return 0;
3692 }
3693
3694 static int
3695 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3696                       struct rte_eth_rss_conf *rss_conf)
3697 {
3698         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3699         struct ice_vsi *vsi = pf->main_vsi;
3700
3701         ice_get_rss_key(vsi, rss_conf->rss_key,
3702                         &rss_conf->rss_key_len);
3703
3704         /* TODO: default set to 0 as hf config is not supported now */
3705         rss_conf->rss_hf = 0;
3706         return 0;
3707 }
3708
3709 static int
3710 ice_promisc_enable(struct rte_eth_dev *dev)
3711 {
3712         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3713         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         struct ice_vsi *vsi = pf->main_vsi;
3715         enum ice_status status;
3716         uint8_t pmask;
3717         int ret = 0;
3718
3719         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3720                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3721
3722         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3723         switch (status) {
3724         case ICE_ERR_ALREADY_EXISTS:
3725                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3726         case ICE_SUCCESS:
3727                 break;
3728         default:
3729                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3730                 ret = -EAGAIN;
3731         }
3732
3733         return ret;
3734 }
3735
3736 static int
3737 ice_promisc_disable(struct rte_eth_dev *dev)
3738 {
3739         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3740         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741         struct ice_vsi *vsi = pf->main_vsi;
3742         enum ice_status status;
3743         uint8_t pmask;
3744         int ret = 0;
3745
3746         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3747                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3748
3749         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3750         if (status != ICE_SUCCESS) {
3751                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3752                 ret = -EAGAIN;
3753         }
3754
3755         return ret;
3756 }
3757
3758 static int
3759 ice_allmulti_enable(struct rte_eth_dev *dev)
3760 {
3761         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3762         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763         struct ice_vsi *vsi = pf->main_vsi;
3764         enum ice_status status;
3765         uint8_t pmask;
3766         int ret = 0;
3767
3768         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3769
3770         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3771
3772         switch (status) {
3773         case ICE_ERR_ALREADY_EXISTS:
3774                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3775         case ICE_SUCCESS:
3776                 break;
3777         default:
3778                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3779                 ret = -EAGAIN;
3780         }
3781
3782         return ret;
3783 }
3784
3785 static int
3786 ice_allmulti_disable(struct rte_eth_dev *dev)
3787 {
3788         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3789         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790         struct ice_vsi *vsi = pf->main_vsi;
3791         enum ice_status status;
3792         uint8_t pmask;
3793         int ret = 0;
3794
3795         if (dev->data->promiscuous == 1)
3796                 return 0; /* must remain in all_multicast mode */
3797
3798         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3799
3800         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3801         if (status != ICE_SUCCESS) {
3802                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3803                 ret = -EAGAIN;
3804         }
3805
3806         return ret;
3807 }
3808
3809 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3810                                     uint16_t queue_id)
3811 {
3812         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3813         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3814         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         uint32_t val;
3816         uint16_t msix_intr;
3817
3818         msix_intr = intr_handle->intr_vec[queue_id];
3819
3820         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3821               GLINT_DYN_CTL_ITR_INDX_M;
3822         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3823
3824         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3825         rte_intr_ack(&pci_dev->intr_handle);
3826
3827         return 0;
3828 }
3829
3830 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3831                                      uint16_t queue_id)
3832 {
3833         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3834         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3835         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         uint16_t msix_intr;
3837
3838         msix_intr = intr_handle->intr_vec[queue_id];
3839
3840         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3841
3842         return 0;
3843 }
3844
3845 static int
3846 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3847 {
3848         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         u8 ver, patch;
3850         u16 build;
3851         int ret;
3852
3853         ver = hw->nvm.orom.major;
3854         patch = hw->nvm.orom.patch;
3855         build = hw->nvm.orom.build;
3856
3857         ret = snprintf(fw_version, fw_size,
3858                         "%d.%d 0x%08x %d.%d.%d",
3859                         hw->nvm.major_ver,
3860                         hw->nvm.minor_ver,
3861                         hw->nvm.eetrack,
3862                         ver, build, patch);
3863
3864         /* add the size of '\0' */
3865         ret += 1;
3866         if (fw_size < (u32)ret)
3867                 return ret;
3868         else
3869                 return 0;
3870 }
3871
3872 static int
3873 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3874 {
3875         struct ice_hw *hw;
3876         struct ice_vsi_ctx ctxt;
3877         uint8_t vlan_flags = 0;
3878         int ret;
3879
3880         if (!vsi || !info) {
3881                 PMD_DRV_LOG(ERR, "invalid parameters");
3882                 return -EINVAL;
3883         }
3884
3885         if (info->on) {
3886                 vsi->info.pvid = info->config.pvid;
3887                 /**
3888                  * If insert pvid is enabled, only tagged pkts are
3889                  * allowed to be sent out.
3890                  */
3891                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3892                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3893         } else {
3894                 vsi->info.pvid = 0;
3895                 if (info->config.reject.tagged == 0)
3896                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3897
3898                 if (info->config.reject.untagged == 0)
3899                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3900         }
3901         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3902                                   ICE_AQ_VSI_VLAN_MODE_M);
3903         vsi->info.vlan_flags |= vlan_flags;
3904         memset(&ctxt, 0, sizeof(ctxt));
3905         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3906         ctxt.info.valid_sections =
3907                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3908         ctxt.vsi_num = vsi->vsi_id;
3909
3910         hw = ICE_VSI_TO_HW(vsi);
3911         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3912         if (ret != ICE_SUCCESS) {
3913                 PMD_DRV_LOG(ERR,
3914                             "update VSI for VLAN insert failed, err %d",
3915                             ret);
3916                 return -EINVAL;
3917         }
3918
3919         vsi->info.valid_sections |=
3920                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3921
3922         return ret;
3923 }
3924
3925 static int
3926 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3927 {
3928         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3929         struct ice_vsi *vsi = pf->main_vsi;
3930         struct rte_eth_dev_data *data = pf->dev_data;
3931         struct ice_vsi_vlan_pvid_info info;
3932         int ret;
3933
3934         memset(&info, 0, sizeof(info));
3935         info.on = on;
3936         if (info.on) {
3937                 info.config.pvid = pvid;
3938         } else {
3939                 info.config.reject.tagged =
3940                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3941                 info.config.reject.untagged =
3942                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3943         }
3944
3945         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3946         if (ret < 0) {
3947                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3948                 return -EINVAL;
3949         }
3950
3951         return 0;
3952 }
3953
3954 static int
3955 ice_get_eeprom_length(struct rte_eth_dev *dev)
3956 {
3957         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958
3959         /* Convert word count to byte count */
3960         return hw->nvm.sr_words << 1;
3961 }
3962
3963 static int
3964 ice_get_eeprom(struct rte_eth_dev *dev,
3965                struct rte_dev_eeprom_info *eeprom)
3966 {
3967         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968         uint16_t *data = eeprom->data;
3969         uint16_t first_word, last_word, nwords;
3970         enum ice_status status = ICE_SUCCESS;
3971
3972         first_word = eeprom->offset >> 1;
3973         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3974         nwords = last_word - first_word + 1;
3975
3976         if (first_word >= hw->nvm.sr_words ||
3977             last_word >= hw->nvm.sr_words) {
3978                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3979                 return -EINVAL;
3980         }
3981
3982         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3983
3984         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3985         if (status) {
3986                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3987                 eeprom->length = sizeof(uint16_t) * nwords;
3988                 return -EIO;
3989         }
3990
3991         return 0;
3992 }
3993
3994 static void
3995 ice_stat_update_32(struct ice_hw *hw,
3996                    uint32_t reg,
3997                    bool offset_loaded,
3998                    uint64_t *offset,
3999                    uint64_t *stat)
4000 {
4001         uint64_t new_data;
4002
4003         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4004         if (!offset_loaded)
4005                 *offset = new_data;
4006
4007         if (new_data >= *offset)
4008                 *stat = (uint64_t)(new_data - *offset);
4009         else
4010                 *stat = (uint64_t)((new_data +
4011                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4012                                    - *offset);
4013 }
4014
4015 static void
4016 ice_stat_update_40(struct ice_hw *hw,
4017                    uint32_t hireg,
4018                    uint32_t loreg,
4019                    bool offset_loaded,
4020                    uint64_t *offset,
4021                    uint64_t *stat)
4022 {
4023         uint64_t new_data;
4024
4025         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4026         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4027                     ICE_32_BIT_WIDTH;
4028
4029         if (!offset_loaded)
4030                 *offset = new_data;
4031
4032         if (new_data >= *offset)
4033                 *stat = new_data - *offset;
4034         else
4035                 *stat = (uint64_t)((new_data +
4036                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4037                                    *offset);
4038
4039         *stat &= ICE_40_BIT_MASK;
4040 }
4041
4042 /* Get all the statistics of a VSI */
4043 static void
4044 ice_update_vsi_stats(struct ice_vsi *vsi)
4045 {
4046         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4047         struct ice_eth_stats *nes = &vsi->eth_stats;
4048         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4049         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4050
4051         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4052                            vsi->offset_loaded, &oes->rx_bytes,
4053                            &nes->rx_bytes);
4054         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4055                            vsi->offset_loaded, &oes->rx_unicast,
4056                            &nes->rx_unicast);
4057         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4058                            vsi->offset_loaded, &oes->rx_multicast,
4059                            &nes->rx_multicast);
4060         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4061                            vsi->offset_loaded, &oes->rx_broadcast,
4062                            &nes->rx_broadcast);
4063         /* exclude CRC bytes */
4064         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4065                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4066
4067         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4068                            &oes->rx_discards, &nes->rx_discards);
4069         /* GLV_REPC not supported */
4070         /* GLV_RMPC not supported */
4071         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4072                            &oes->rx_unknown_protocol,
4073                            &nes->rx_unknown_protocol);
4074         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4075                            vsi->offset_loaded, &oes->tx_bytes,
4076                            &nes->tx_bytes);
4077         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4078                            vsi->offset_loaded, &oes->tx_unicast,
4079                            &nes->tx_unicast);
4080         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4081                            vsi->offset_loaded, &oes->tx_multicast,
4082                            &nes->tx_multicast);
4083         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4084                            vsi->offset_loaded,  &oes->tx_broadcast,
4085                            &nes->tx_broadcast);
4086         /* GLV_TDPC not supported */
4087         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4088                            &oes->tx_errors, &nes->tx_errors);
4089         vsi->offset_loaded = true;
4090
4091         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4092                     vsi->vsi_id);
4093         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4094         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4095         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4096         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4097         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4098         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4099                     nes->rx_unknown_protocol);
4100         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4101         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4102         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4103         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4104         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4105         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4106         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4107                     vsi->vsi_id);
4108 }
4109
4110 static void
4111 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4112 {
4113         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4114         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4115
4116         /* Get statistics of struct ice_eth_stats */
4117         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4118                            GLPRT_GORCL(hw->port_info->lport),
4119                            pf->offset_loaded, &os->eth.rx_bytes,
4120                            &ns->eth.rx_bytes);
4121         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4122                            GLPRT_UPRCL(hw->port_info->lport),
4123                            pf->offset_loaded, &os->eth.rx_unicast,
4124                            &ns->eth.rx_unicast);
4125         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4126                            GLPRT_MPRCL(hw->port_info->lport),
4127                            pf->offset_loaded, &os->eth.rx_multicast,
4128                            &ns->eth.rx_multicast);
4129         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4130                            GLPRT_BPRCL(hw->port_info->lport),
4131                            pf->offset_loaded, &os->eth.rx_broadcast,
4132                            &ns->eth.rx_broadcast);
4133         ice_stat_update_32(hw, PRTRPB_RDPC,
4134                            pf->offset_loaded, &os->eth.rx_discards,
4135                            &ns->eth.rx_discards);
4136
4137         /* Workaround: CRC size should not be included in byte statistics,
4138          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4139          * packet.
4140          */
4141         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4142                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4143
4144         /* GLPRT_REPC not supported */
4145         /* GLPRT_RMPC not supported */
4146         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4147                            pf->offset_loaded,
4148                            &os->eth.rx_unknown_protocol,
4149                            &ns->eth.rx_unknown_protocol);
4150         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4151                            GLPRT_GOTCL(hw->port_info->lport),
4152                            pf->offset_loaded, &os->eth.tx_bytes,
4153                            &ns->eth.tx_bytes);
4154         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4155                            GLPRT_UPTCL(hw->port_info->lport),
4156                            pf->offset_loaded, &os->eth.tx_unicast,
4157                            &ns->eth.tx_unicast);
4158         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4159                            GLPRT_MPTCL(hw->port_info->lport),
4160                            pf->offset_loaded, &os->eth.tx_multicast,
4161                            &ns->eth.tx_multicast);
4162         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4163                            GLPRT_BPTCL(hw->port_info->lport),
4164                            pf->offset_loaded, &os->eth.tx_broadcast,
4165                            &ns->eth.tx_broadcast);
4166         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4167                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4168
4169         /* GLPRT_TEPC not supported */
4170
4171         /* additional port specific stats */
4172         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4173                            pf->offset_loaded, &os->tx_dropped_link_down,
4174                            &ns->tx_dropped_link_down);
4175         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4176                            pf->offset_loaded, &os->crc_errors,
4177                            &ns->crc_errors);
4178         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4179                            pf->offset_loaded, &os->illegal_bytes,
4180                            &ns->illegal_bytes);
4181         /* GLPRT_ERRBC not supported */
4182         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4183                            pf->offset_loaded, &os->mac_local_faults,
4184                            &ns->mac_local_faults);
4185         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4186                            pf->offset_loaded, &os->mac_remote_faults,
4187                            &ns->mac_remote_faults);
4188
4189         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4190                            pf->offset_loaded, &os->rx_len_errors,
4191                            &ns->rx_len_errors);
4192
4193         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4194                            pf->offset_loaded, &os->link_xon_rx,
4195                            &ns->link_xon_rx);
4196         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4197                            pf->offset_loaded, &os->link_xoff_rx,
4198                            &ns->link_xoff_rx);
4199         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4200                            pf->offset_loaded, &os->link_xon_tx,
4201                            &ns->link_xon_tx);
4202         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4203                            pf->offset_loaded, &os->link_xoff_tx,
4204                            &ns->link_xoff_tx);
4205         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4206                            GLPRT_PRC64L(hw->port_info->lport),
4207                            pf->offset_loaded, &os->rx_size_64,
4208                            &ns->rx_size_64);
4209         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4210                            GLPRT_PRC127L(hw->port_info->lport),
4211                            pf->offset_loaded, &os->rx_size_127,
4212                            &ns->rx_size_127);
4213         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4214                            GLPRT_PRC255L(hw->port_info->lport),
4215                            pf->offset_loaded, &os->rx_size_255,
4216                            &ns->rx_size_255);
4217         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4218                            GLPRT_PRC511L(hw->port_info->lport),
4219                            pf->offset_loaded, &os->rx_size_511,
4220                            &ns->rx_size_511);
4221         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4222                            GLPRT_PRC1023L(hw->port_info->lport),
4223                            pf->offset_loaded, &os->rx_size_1023,
4224                            &ns->rx_size_1023);
4225         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4226                            GLPRT_PRC1522L(hw->port_info->lport),
4227                            pf->offset_loaded, &os->rx_size_1522,
4228                            &ns->rx_size_1522);
4229         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4230                            GLPRT_PRC9522L(hw->port_info->lport),
4231                            pf->offset_loaded, &os->rx_size_big,
4232                            &ns->rx_size_big);
4233         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4234                            pf->offset_loaded, &os->rx_undersize,
4235                            &ns->rx_undersize);
4236         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4237                            pf->offset_loaded, &os->rx_fragments,
4238                            &ns->rx_fragments);
4239         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4240                            pf->offset_loaded, &os->rx_oversize,
4241                            &ns->rx_oversize);
4242         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4243                            pf->offset_loaded, &os->rx_jabber,
4244                            &ns->rx_jabber);
4245         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4246                            GLPRT_PTC64L(hw->port_info->lport),
4247                            pf->offset_loaded, &os->tx_size_64,
4248                            &ns->tx_size_64);
4249         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4250                            GLPRT_PTC127L(hw->port_info->lport),
4251                            pf->offset_loaded, &os->tx_size_127,
4252                            &ns->tx_size_127);
4253         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4254                            GLPRT_PTC255L(hw->port_info->lport),
4255                            pf->offset_loaded, &os->tx_size_255,
4256                            &ns->tx_size_255);
4257         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4258                            GLPRT_PTC511L(hw->port_info->lport),
4259                            pf->offset_loaded, &os->tx_size_511,
4260                            &ns->tx_size_511);
4261         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4262                            GLPRT_PTC1023L(hw->port_info->lport),
4263                            pf->offset_loaded, &os->tx_size_1023,
4264                            &ns->tx_size_1023);
4265         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4266                            GLPRT_PTC1522L(hw->port_info->lport),
4267                            pf->offset_loaded, &os->tx_size_1522,
4268                            &ns->tx_size_1522);
4269         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4270                            GLPRT_PTC9522L(hw->port_info->lport),
4271                            pf->offset_loaded, &os->tx_size_big,
4272                            &ns->tx_size_big);
4273
4274         /* GLPRT_MSPDC not supported */
4275         /* GLPRT_XEC not supported */
4276
4277         pf->offset_loaded = true;
4278
4279         if (pf->main_vsi)
4280                 ice_update_vsi_stats(pf->main_vsi);
4281 }
4282
4283 /* Get all statistics of a port */
4284 static int
4285 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4286 {
4287         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4288         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4290
4291         /* call read registers - updates values, now write them to struct */
4292         ice_read_stats_registers(pf, hw);
4293
4294         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4295                           pf->main_vsi->eth_stats.rx_multicast +
4296                           pf->main_vsi->eth_stats.rx_broadcast -
4297                           pf->main_vsi->eth_stats.rx_discards;
4298         stats->opackets = ns->eth.tx_unicast +
4299                           ns->eth.tx_multicast +
4300                           ns->eth.tx_broadcast;
4301         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4302         stats->obytes   = ns->eth.tx_bytes;
4303         stats->oerrors  = ns->eth.tx_errors +
4304                           pf->main_vsi->eth_stats.tx_errors;
4305
4306         /* Rx Errors */
4307         stats->imissed  = ns->eth.rx_discards +
4308                           pf->main_vsi->eth_stats.rx_discards;
4309         stats->ierrors  = ns->crc_errors +
4310                           ns->rx_undersize +
4311                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4312
4313         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4314         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4315         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4316         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4317         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4318         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4319         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4320                     pf->main_vsi->eth_stats.rx_discards);
4321         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4322                     ns->eth.rx_unknown_protocol);
4323         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4324         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4325         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4326         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4327         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4328         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4329                     pf->main_vsi->eth_stats.tx_discards);
4330         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4331
4332         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4333                     ns->tx_dropped_link_down);
4334         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4335         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4336                     ns->illegal_bytes);
4337         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4338         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4339                     ns->mac_local_faults);
4340         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4341                     ns->mac_remote_faults);
4342         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4343         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4344         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4345         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4346         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4347         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4348         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4349         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4350         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4351         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4352         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4353         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4354         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4355         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4356         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4357         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4358         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4359         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4360         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4361         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4362         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4363         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4364         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4365         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4366         return 0;
4367 }
4368
4369 /* Reset the statistics */
4370 static int
4371 ice_stats_reset(struct rte_eth_dev *dev)
4372 {
4373         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4374         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375
4376         /* Mark PF and VSI stats to update the offset, aka "reset" */
4377         pf->offset_loaded = false;
4378         if (pf->main_vsi)
4379                 pf->main_vsi->offset_loaded = false;
4380
4381         /* read the stats, reading current register values into offset */
4382         ice_read_stats_registers(pf, hw);
4383
4384         return 0;
4385 }
4386
4387 static uint32_t
4388 ice_xstats_calc_num(void)
4389 {
4390         uint32_t num;
4391
4392         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4393
4394         return num;
4395 }
4396
4397 static int
4398 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4399                unsigned int n)
4400 {
4401         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4402         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4403         unsigned int i;
4404         unsigned int count;
4405         struct ice_hw_port_stats *hw_stats = &pf->stats;
4406
4407         count = ice_xstats_calc_num();
4408         if (n < count)
4409                 return count;
4410
4411         ice_read_stats_registers(pf, hw);
4412
4413         if (!xstats)
4414                 return 0;
4415
4416         count = 0;
4417
4418         /* Get stats from ice_eth_stats struct */
4419         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4420                 xstats[count].value =
4421                         *(uint64_t *)((char *)&hw_stats->eth +
4422                                       ice_stats_strings[i].offset);
4423                 xstats[count].id = count;
4424                 count++;
4425         }
4426
4427         /* Get individiual stats from ice_hw_port struct */
4428         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4429                 xstats[count].value =
4430                         *(uint64_t *)((char *)hw_stats +
4431                                       ice_hw_port_strings[i].offset);
4432                 xstats[count].id = count;
4433                 count++;
4434         }
4435
4436         return count;
4437 }
4438
4439 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4440                                 struct rte_eth_xstat_name *xstats_names,
4441                                 __rte_unused unsigned int limit)
4442 {
4443         unsigned int count = 0;
4444         unsigned int i;
4445
4446         if (!xstats_names)
4447                 return ice_xstats_calc_num();
4448
4449         /* Note: limit checked in rte_eth_xstats_names() */
4450
4451         /* Get stats from ice_eth_stats struct */
4452         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4453                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4454                         sizeof(xstats_names[count].name));
4455                 count++;
4456         }
4457
4458         /* Get individiual stats from ice_hw_port struct */
4459         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4460                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4461                         sizeof(xstats_names[count].name));
4462                 count++;
4463         }
4464
4465         return count;
4466 }
4467
4468 static int
4469 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4470                      enum rte_filter_type filter_type,
4471                      enum rte_filter_op filter_op,
4472                      void *arg)
4473 {
4474         int ret = 0;
4475
4476         if (!dev)
4477                 return -EINVAL;
4478
4479         switch (filter_type) {
4480         case RTE_ETH_FILTER_GENERIC:
4481                 if (filter_op != RTE_ETH_FILTER_GET)
4482                         return -EINVAL;
4483                 *(const void **)arg = &ice_flow_ops;
4484                 break;
4485         default:
4486                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4487                                         filter_type);
4488                 ret = -EINVAL;
4489                 break;
4490         }
4491
4492         return ret;
4493 }
4494
4495 /* Add UDP tunneling port */
4496 static int
4497 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4498                              struct rte_eth_udp_tunnel *udp_tunnel)
4499 {
4500         int ret = 0;
4501         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4502
4503         if (udp_tunnel == NULL)
4504                 return -EINVAL;
4505
4506         switch (udp_tunnel->prot_type) {
4507         case RTE_TUNNEL_TYPE_VXLAN:
4508                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4509                 break;
4510         default:
4511                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4512                 ret = -EINVAL;
4513                 break;
4514         }
4515
4516         return ret;
4517 }
4518
4519 /* Delete UDP tunneling port */
4520 static int
4521 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4522                              struct rte_eth_udp_tunnel *udp_tunnel)
4523 {
4524         int ret = 0;
4525         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4526
4527         if (udp_tunnel == NULL)
4528                 return -EINVAL;
4529
4530         switch (udp_tunnel->prot_type) {
4531         case RTE_TUNNEL_TYPE_VXLAN:
4532                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4533                 break;
4534         default:
4535                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4536                 ret = -EINVAL;
4537                 break;
4538         }
4539
4540         return ret;
4541 }
4542
4543 static int
4544 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4545               struct rte_pci_device *pci_dev)
4546 {
4547         return rte_eth_dev_pci_generic_probe(pci_dev,
4548                                              sizeof(struct ice_adapter),
4549                                              ice_dev_init);
4550 }
4551
4552 static int
4553 ice_pci_remove(struct rte_pci_device *pci_dev)
4554 {
4555         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4556 }
4557
4558 static struct rte_pci_driver rte_ice_pmd = {
4559         .id_table = pci_id_ice_map,
4560         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4561         .probe = ice_pci_probe,
4562         .remove = ice_pci_remove,
4563 };
4564
4565 /**
4566  * Driver initialization routine.
4567  * Invoked once at EAL init time.
4568  * Register itself as the [Poll Mode] Driver of PCI devices.
4569  */
4570 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4571 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4572 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4573 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4574                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4575                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4576                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4577                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4578
4579 RTE_INIT(ice_init_log)
4580 {
4581         ice_logtype_init = rte_log_register("pmd.net.ice.init");
4582         if (ice_logtype_init >= 0)
4583                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4584         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4585         if (ice_logtype_driver >= 0)
4586                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4587
4588 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4589         ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4590         if (ice_logtype_rx >= 0)
4591                 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4592 #endif
4593
4594 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4595         ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4596         if (ice_logtype_tx >= 0)
4597                 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4598 #endif
4599
4600 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4601         ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4602         if (ice_logtype_tx_free >= 0)
4603                 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);
4604 #endif
4605 }