drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  72 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  73 #define ICE_MAX_RES_DESC_NUM        1024
  74
  75 static int ice_dev_configure(struct rte_eth_dev *dev);
  76 static int ice_dev_start(struct rte_eth_dev *dev);
  77 static int ice_dev_stop(struct rte_eth_dev *dev);
  78 static int ice_dev_close(struct rte_eth_dev *dev);
  79 static int ice_dev_reset(struct rte_eth_dev *dev);
  80 static int ice_dev_info_get(struct rte_eth_dev *dev,
  81                             struct rte_eth_dev_info *dev_info);
  82 static int ice_link_update(struct rte_eth_dev *dev,
  83                            int wait_to_complete);
  84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  86
  87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  90                                struct rte_eth_rss_reta_entry64 *reta_conf,
  91                                uint16_t reta_size);
  92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  93                               struct rte_eth_rss_reta_entry64 *reta_conf,
  94                               uint16_t reta_size);
  95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  96                                struct rte_eth_rss_conf *rss_conf);
  97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  98                                  struct rte_eth_rss_conf *rss_conf);
  99 static int ice_promisc_enable(struct rte_eth_dev *dev);
 100 static int ice_promisc_disable(struct rte_eth_dev *dev);
 101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 104                                uint16_t vlan_id,
 105                                int on);
 106 static int ice_macaddr_set(struct rte_eth_dev *dev,
 107                            struct rte_ether_addr *mac_addr);
 108 static int ice_macaddr_add(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr,
 110                            __rte_unused uint32_t index,
 111                            uint32_t pool);
 112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 114                                     uint16_t queue_id);
 115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 116                                      uint16_t queue_id);
 117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 118                               size_t fw_size);
 119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 120                              uint16_t pvid, int on);
 121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 122 static int ice_get_eeprom(struct rte_eth_dev *dev,
 123                           struct rte_dev_eeprom_info *eeprom);
 124 static int ice_stats_get(struct rte_eth_dev *dev,
 125                          struct rte_eth_stats *stats);
 126 static int ice_stats_reset(struct rte_eth_dev *dev);
 127 static int ice_xstats_get(struct rte_eth_dev *dev,
 128                           struct rte_eth_xstat *xstats, unsigned int n);
 129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 130                                 struct rte_eth_xstat_name *xstats_names,
 131                                 unsigned int limit);
 132 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
 133                                 const struct rte_flow_ops **ops);
 134 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 135                         struct rte_eth_udp_tunnel *udp_tunnel);
 136 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 137                         struct rte_eth_udp_tunnel *udp_tunnel);
 138
 139 static const struct rte_pci_id pci_id_ice_map[] = {
 140         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 141         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 142         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 143         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 165         { .vendor_id = 0, /* sentinel */ },
 166 };
 167
 168 static const struct eth_dev_ops ice_eth_dev_ops = {
 169         .dev_configure                = ice_dev_configure,
 170         .dev_start                    = ice_dev_start,
 171         .dev_stop                     = ice_dev_stop,
 172         .dev_close                    = ice_dev_close,
 173         .dev_reset                    = ice_dev_reset,
 174         .dev_set_link_up              = ice_dev_set_link_up,
 175         .dev_set_link_down            = ice_dev_set_link_down,
 176         .rx_queue_start               = ice_rx_queue_start,
 177         .rx_queue_stop                = ice_rx_queue_stop,
 178         .tx_queue_start               = ice_tx_queue_start,
 179         .tx_queue_stop                = ice_tx_queue_stop,
 180         .rx_queue_setup               = ice_rx_queue_setup,
 181         .rx_queue_release             = ice_rx_queue_release,
 182         .tx_queue_setup               = ice_tx_queue_setup,
 183         .tx_queue_release             = ice_tx_queue_release,
 184         .dev_infos_get                = ice_dev_info_get,
 185         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 186         .link_update                  = ice_link_update,
 187         .mtu_set                      = ice_mtu_set,
 188         .mac_addr_set                 = ice_macaddr_set,
 189         .mac_addr_add                 = ice_macaddr_add,
 190         .mac_addr_remove              = ice_macaddr_remove,
 191         .vlan_filter_set              = ice_vlan_filter_set,
 192         .vlan_offload_set             = ice_vlan_offload_set,
 193         .reta_update                  = ice_rss_reta_update,
 194         .reta_query                   = ice_rss_reta_query,
 195         .rss_hash_update              = ice_rss_hash_update,
 196         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 197         .promiscuous_enable           = ice_promisc_enable,
 198         .promiscuous_disable          = ice_promisc_disable,
 199         .allmulticast_enable          = ice_allmulti_enable,
 200         .allmulticast_disable         = ice_allmulti_disable,
 201         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 202         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 203         .fw_version_get               = ice_fw_version_get,
 204         .vlan_pvid_set                = ice_vlan_pvid_set,
 205         .rxq_info_get                 = ice_rxq_info_get,
 206         .txq_info_get                 = ice_txq_info_get,
 207         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 208         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 209         .get_eeprom_length            = ice_get_eeprom_length,
 210         .get_eeprom                   = ice_get_eeprom,
 211         .stats_get                    = ice_stats_get,
 212         .stats_reset                  = ice_stats_reset,
 213         .xstats_get                   = ice_xstats_get,
 214         .xstats_get_names             = ice_xstats_get_names,
 215         .xstats_reset                 = ice_stats_reset,
 216         .flow_ops_get                 = ice_dev_flow_ops_get,
 217         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 218         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 219         .tx_done_cleanup              = ice_tx_done_cleanup,
 220         .get_monitor_addr             = ice_get_monitor_addr,
 221 };
 222
 223 /* store statistics names and its offset in stats structure */
 224 struct ice_xstats_name_off {
 225         char name[RTE_ETH_XSTATS_NAME_SIZE];
 226         unsigned int offset;
 227 };
 228
 229 static const struct ice_xstats_name_off ice_stats_strings[] = {
 230         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 231         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 232         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 233         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 234         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 235                 rx_unknown_protocol)},
 236         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 237         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 238         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 239         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 240 };
 241
 242 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 243                 sizeof(ice_stats_strings[0]))
 244
 245 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 246         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 247                 tx_dropped_link_down)},
 248         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 249         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 250                 illegal_bytes)},
 251         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 252         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 253                 mac_local_faults)},
 254         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 255                 mac_remote_faults)},
 256         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 257                 rx_len_errors)},
 258         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 259         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 260         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 261         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 262         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 263         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_127)},
 265         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_255)},
 267         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_511)},
 269         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_1023)},
 271         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_1522)},
 273         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_big)},
 275         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 276                 rx_undersize)},
 277         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_oversize)},
 279         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 280                 mac_short_pkt_dropped)},
 281         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_fragments)},
 283         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 284         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 285         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_127)},
 287         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_255)},
 289         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_511)},
 291         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_1023)},
 293         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_1522)},
 295         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_big)},
 297 };
 298
 299 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 300                 sizeof(ice_hw_port_strings[0]))
 301
 302 static void
 303 ice_init_controlq_parameter(struct ice_hw *hw)
 304 {
 305         /* fields for adminq */
 306         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 307         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 308         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 309         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 310
 311         /* fields for mailboxq, DPDK used as PF host */
 312         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 313         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 314         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 315         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 316 }
 317
 318 static int
 319 lookup_proto_xtr_type(const char *xtr_name)
 320 {
 321         static struct {
 322                 const char *name;
 323                 enum proto_xtr_type type;
 324         } xtr_type_map[] = {
 325                 { "vlan",      PROTO_XTR_VLAN      },
 326                 { "ipv4",      PROTO_XTR_IPV4      },
 327                 { "ipv6",      PROTO_XTR_IPV6      },
 328                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 329                 { "tcp",       PROTO_XTR_TCP       },
 330                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 331         };
 332         uint32_t i;
 333
 334         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 335                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 336                         return xtr_type_map[i].type;
 337         }
 338
 339         return -1;
 340 }
 341
 342 /*
 343  * Parse elem, the elem could be single number/range or '(' ')' group
 344  * 1) A single number elem, it's just a simple digit. e.g. 9
 345  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 346  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 347  *    Within group elem, '-' used for a range separator;
 348  *                       ',' used for a single number.
 349  */
 350 static int
 351 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 352 {
 353         const char *str = input;
 354         char *end = NULL;
 355         uint32_t min, max;
 356         uint32_t idx;
 357
 358         while (isblank(*str))
 359                 str++;
 360
 361         if (!isdigit(*str) && *str != '(')
 362                 return -1;
 363
 364         /* process single number or single range of number */
 365         if (*str != '(') {
 366                 errno = 0;
 367                 idx = strtoul(str, &end, 10);
 368                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 369                         return -1;
 370
 371                 while (isblank(*end))
 372                         end++;
 373
 374                 min = idx;
 375                 max = idx;
 376
 377                 /* process single <number>-<number> */
 378                 if (*end == '-') {
 379                         end++;
 380                         while (isblank(*end))
 381                                 end++;
 382                         if (!isdigit(*end))
 383                                 return -1;
 384
 385                         errno = 0;
 386                         idx = strtoul(end, &end, 10);
 387                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 388                                 return -1;
 389
 390                         max = idx;
 391                         while (isblank(*end))
 392                                 end++;
 393                 }
 394
 395                 if (*end != ':')
 396                         return -1;
 397
 398                 for (idx = RTE_MIN(min, max);
 399                      idx <= RTE_MAX(min, max); idx++)
 400                         devargs->proto_xtr[idx] = xtr_type;
 401
 402                 return 0;
 403         }
 404
 405         /* process set within bracket */
 406         str++;
 407         while (isblank(*str))
 408                 str++;
 409         if (*str == '\0')
 410                 return -1;
 411
 412         min = ICE_MAX_QUEUE_NUM;
 413         do {
 414                 /* go ahead to the first digit */
 415                 while (isblank(*str))
 416                         str++;
 417                 if (!isdigit(*str))
 418                         return -1;
 419
 420                 /* get the digit value */
 421                 errno = 0;
 422                 idx = strtoul(str, &end, 10);
 423                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 424                         return -1;
 425
 426                 /* go ahead to separator '-',',' and ')' */
 427                 while (isblank(*end))
 428                         end++;
 429                 if (*end == '-') {
 430                         if (min == ICE_MAX_QUEUE_NUM)
 431                                 min = idx;
 432                         else /* avoid continuous '-' */
 433                                 return -1;
 434                 } else if (*end == ',' || *end == ')') {
 435                         max = idx;
 436                         if (min == ICE_MAX_QUEUE_NUM)
 437                                 min = idx;
 438
 439                         for (idx = RTE_MIN(min, max);
 440                              idx <= RTE_MAX(min, max); idx++)
 441                                 devargs->proto_xtr[idx] = xtr_type;
 442
 443                         min = ICE_MAX_QUEUE_NUM;
 444                 } else {
 445                         return -1;
 446                 }
 447
 448                 str = end + 1;
 449         } while (*end != ')' && *end != '\0');
 450
 451         return 0;
 452 }
 453
 454 static int
 455 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 456 {
 457         const char *queue_start;
 458         uint32_t idx;
 459         int xtr_type;
 460         char xtr_name[32];
 461
 462         while (isblank(*queues))
 463                 queues++;
 464
 465         if (*queues != '[') {
 466                 xtr_type = lookup_proto_xtr_type(queues);
 467                 if (xtr_type < 0)
 468                         return -1;
 469
 470                 devargs->proto_xtr_dflt = xtr_type;
 471
 472                 return 0;
 473         }
 474
 475         queues++;
 476         do {
 477                 while (isblank(*queues))
 478                         queues++;
 479                 if (*queues == '\0')
 480                         return -1;
 481
 482                 queue_start = queues;
 483
 484                 /* go across a complete bracket */
 485                 if (*queue_start == '(') {
 486                         queues += strcspn(queues, ")");
 487                         if (*queues != ')')
 488                                 return -1;
 489                 }
 490
 491                 /* scan the separator ':' */
 492                 queues += strcspn(queues, ":");
 493                 if (*queues++ != ':')
 494                         return -1;
 495                 while (isblank(*queues))
 496                         queues++;
 497
 498                 for (idx = 0; ; idx++) {
 499                         if (isblank(queues[idx]) ||
 500                             queues[idx] == ',' ||
 501                             queues[idx] == ']' ||
 502                             queues[idx] == '\0')
 503                                 break;
 504
 505                         if (idx > sizeof(xtr_name) - 2)
 506                                 return -1;
 507
 508                         xtr_name[idx] = queues[idx];
 509                 }
 510                 xtr_name[idx] = '\0';
 511                 xtr_type = lookup_proto_xtr_type(xtr_name);
 512                 if (xtr_type < 0)
 513                         return -1;
 514
 515                 queues += idx;
 516
 517                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 518                         queues++;
 519
 520                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 521                         return -1;
 522         } while (*queues != '\0');
 523
 524         return 0;
 525 }
 526
 527 static int
 528 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 529                      void *extra_args)
 530 {
 531         struct ice_devargs *devargs = extra_args;
 532
 533         if (value == NULL || extra_args == NULL)
 534                 return -EINVAL;
 535
 536         if (parse_queue_proto_xtr(value, devargs) < 0) {
 537                 PMD_DRV_LOG(ERR,
 538                             "The protocol extraction parameter is wrong : '%s'",
 539                             value);
 540                 return -1;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static void
 547 ice_check_proto_xtr_support(struct ice_hw *hw)
 548 {
 549 #define FLX_REG(val, fld, idx) \
 550         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 551          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 552         static struct {
 553                 uint32_t rxdid;
 554                 uint8_t opcode;
 555                 uint8_t protid_0;
 556                 uint8_t protid_1;
 557         } xtr_sets[] = {
 558                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 559                                      ICE_RX_OPC_EXTRACT,
 560                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 561                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 562                                      ICE_RX_OPC_EXTRACT,
 563                                      ICE_PROT_IPV4_OF_OR_S,
 564                                      ICE_PROT_IPV4_OF_OR_S },
 565                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 566                                      ICE_RX_OPC_EXTRACT,
 567                                      ICE_PROT_IPV6_OF_OR_S,
 568                                      ICE_PROT_IPV6_OF_OR_S },
 569                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 570                                           ICE_RX_OPC_EXTRACT,
 571                                           ICE_PROT_IPV6_OF_OR_S,
 572                                           ICE_PROT_IPV6_OF_OR_S },
 573                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 574                                     ICE_RX_OPC_EXTRACT,
 575                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 576                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 577                                           ICE_RX_OPC_PROTID,
 578                                           ICE_PROT_IPV4_OF_OR_S,
 579                                           ICE_PROT_IPV6_OF_OR_S },
 580         };
 581         uint32_t i;
 582
 583         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 584                 uint32_t rxdid = xtr_sets[i].rxdid;
 585                 uint32_t v;
 586
 587                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 588                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 589
 590                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 591                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 592                                 ice_proto_xtr_hw_support[i] = true;
 593                 }
 594
 595                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 596                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 597
 598                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 599                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 600                                 ice_proto_xtr_hw_support[i] = true;
 601                 }
 602         }
 603 }
 604
 605 static int
 606 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 607                   uint32_t num)
 608 {
 609         struct pool_entry *entry;
 610
 611         if (!pool || !num)
 612                 return -EINVAL;
 613
 614         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 615         if (!entry) {
 616                 PMD_INIT_LOG(ERR,
 617                              "Failed to allocate memory for resource pool");
 618                 return -ENOMEM;
 619         }
 620
 621         /* queue heap initialize */
 622         pool->num_free = num;
 623         pool->num_alloc = 0;
 624         pool->base = base;
 625         LIST_INIT(&pool->alloc_list);
 626         LIST_INIT(&pool->free_list);
 627
 628         /* Initialize element  */
 629         entry->base = 0;
 630         entry->len = num;
 631
 632         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 633         return 0;
 634 }
 635
 636 static int
 637 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 638                    uint16_t num)
 639 {
 640         struct pool_entry *entry, *valid_entry;
 641
 642         if (!pool || !num) {
 643                 PMD_INIT_LOG(ERR, "Invalid parameter");
 644                 return -EINVAL;
 645         }
 646
 647         if (pool->num_free < num) {
 648                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 649                              num, pool->num_free);
 650                 return -ENOMEM;
 651         }
 652
 653         valid_entry = NULL;
 654         /* Lookup  in free list and find most fit one */
 655         LIST_FOREACH(entry, &pool->free_list, next) {
 656                 if (entry->len >= num) {
 657                         /* Find best one */
 658                         if (entry->len == num) {
 659                                 valid_entry = entry;
 660                                 break;
 661                         }
 662                         if (!valid_entry ||
 663                             valid_entry->len > entry->len)
 664                                 valid_entry = entry;
 665                 }
 666         }
 667
 668         /* Not find one to satisfy the request, return */
 669         if (!valid_entry) {
 670                 PMD_INIT_LOG(ERR, "No valid entry found");
 671                 return -ENOMEM;
 672         }
 673         /**
 674          * The entry have equal queue number as requested,
 675          * remove it from alloc_list.
 676          */
 677         if (valid_entry->len == num) {
 678                 LIST_REMOVE(valid_entry, next);
 679         } else {
 680                 /**
 681                  * The entry have more numbers than requested,
 682                  * create a new entry for alloc_list and minus its
 683                  * queue base and number in free_list.
 684                  */
 685                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 686                 if (!entry) {
 687                         PMD_INIT_LOG(ERR,
 688                                      "Failed to allocate memory for "
 689                                      "resource pool");
 690                         return -ENOMEM;
 691                 }
 692                 entry->base = valid_entry->base;
 693                 entry->len = num;
 694                 valid_entry->base += num;
 695                 valid_entry->len -= num;
 696                 valid_entry = entry;
 697         }
 698
 699         /* Insert it into alloc list, not sorted */
 700         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 701
 702         pool->num_free -= valid_entry->len;
 703         pool->num_alloc += valid_entry->len;
 704
 705         return valid_entry->base + pool->base;
 706 }
 707
 708 static void
 709 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 710 {
 711         struct pool_entry *entry, *next_entry;
 712
 713         if (!pool)
 714                 return;
 715
 716         for (entry = LIST_FIRST(&pool->alloc_list);
 717              entry && (next_entry = LIST_NEXT(entry, next), 1);
 718              entry = next_entry) {
 719                 LIST_REMOVE(entry, next);
 720                 rte_free(entry);
 721         }
 722
 723         for (entry = LIST_FIRST(&pool->free_list);
 724              entry && (next_entry = LIST_NEXT(entry, next), 1);
 725              entry = next_entry) {
 726                 LIST_REMOVE(entry, next);
 727                 rte_free(entry);
 728         }
 729
 730         pool->num_free = 0;
 731         pool->num_alloc = 0;
 732         pool->base = 0;
 733         LIST_INIT(&pool->alloc_list);
 734         LIST_INIT(&pool->free_list);
 735 }
 736
 737 static void
 738 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 739 {
 740         /* Set VSI LUT selection */
 741         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 742                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 743         /* Set Hash scheme */
 744         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 745                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 746         /* enable TC */
 747         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 748 }
 749
 750 static enum ice_status
 751 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 752                                 struct ice_aqc_vsi_props *info,
 753                                 uint8_t enabled_tcmap)
 754 {
 755         uint16_t bsf, qp_idx;
 756
 757         /* default tc 0 now. Multi-TC supporting need to be done later.
 758          * Configure TC and queue mapping parameters, for enabled TC,
 759          * allocate qpnum_per_tc queues to this traffic.
 760          */
 761         if (enabled_tcmap != 0x01) {
 762                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 763                 return -ENOTSUP;
 764         }
 765
 766         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 767         bsf = rte_bsf32(vsi->nb_qps);
 768         /* Adjust the queue number to actual queues that can be applied */
 769         vsi->nb_qps = 0x1 << bsf;
 770
 771         qp_idx = 0;
 772         /* Set tc and queue mapping with VSI */
 773         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 774                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 775                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 776
 777         /* Associate queue number with VSI */
 778         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 779         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 780         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 781         info->valid_sections |=
 782                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 783         /* Set the info.ingress_table and info.egress_table
 784          * for UP translate table. Now just set it to 1:1 map by default
 785          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 786          */
 787 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 788         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 789         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 790         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 791         return 0;
 792 }
 793
 794 static int
 795 ice_init_mac_address(struct rte_eth_dev *dev)
 796 {
 797         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         if (!rte_is_unicast_ether_addr
 800                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 801                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 802                 return -EINVAL;
 803         }
 804
 805         rte_ether_addr_copy(
 806                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 807                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 808
 809         dev->data->mac_addrs =
 810                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
 811         if (!dev->data->mac_addrs) {
 812                 PMD_INIT_LOG(ERR,
 813                              "Failed to allocate memory to store mac address");
 814                 return -ENOMEM;
 815         }
 816         /* store it to dev data */
 817         rte_ether_addr_copy(
 818                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 819                 &dev->data->mac_addrs[0]);
 820         return 0;
 821 }
 822
 823 /* Find out specific MAC filter */
 824 static struct ice_mac_filter *
 825 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 826 {
 827         struct ice_mac_filter *f;
 828
 829         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 830                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 831                         return f;
 832         }
 833
 834         return NULL;
 835 }
 836
 837 static int
 838 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 839 {
 840         struct ice_fltr_list_entry *m_list_itr = NULL;
 841         struct ice_mac_filter *f;
 842         struct LIST_HEAD_TYPE list_head;
 843         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 844         int ret = 0;
 845
 846         /* If it's added and configured, return */
 847         f = ice_find_mac_filter(vsi, mac_addr);
 848         if (f) {
 849                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 850                 return 0;
 851         }
 852
 853         INIT_LIST_HEAD(&list_head);
 854
 855         m_list_itr = (struct ice_fltr_list_entry *)
 856                 ice_malloc(hw, sizeof(*m_list_itr));
 857         if (!m_list_itr) {
 858                 ret = -ENOMEM;
 859                 goto DONE;
 860         }
 861         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 862                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 863         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 864         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 865         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 866         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 867         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 868
 869         LIST_ADD(&m_list_itr->list_entry, &list_head);
 870
 871         /* Add the mac */
 872         ret = ice_add_mac(hw, &list_head);
 873         if (ret != ICE_SUCCESS) {
 874                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 875                 ret = -EINVAL;
 876                 goto DONE;
 877         }
 878         /* Add the mac addr into mac list */
 879         f = rte_zmalloc(NULL, sizeof(*f), 0);
 880         if (!f) {
 881                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 882                 ret = -ENOMEM;
 883                 goto DONE;
 884         }
 885         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 886         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 887         vsi->mac_num++;
 888
 889         ret = 0;
 890
 891 DONE:
 892         rte_free(m_list_itr);
 893         return ret;
 894 }
 895
 896 static int
 897 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 898 {
 899         struct ice_fltr_list_entry *m_list_itr = NULL;
 900         struct ice_mac_filter *f;
 901         struct LIST_HEAD_TYPE list_head;
 902         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 903         int ret = 0;
 904
 905         /* Can't find it, return an error */
 906         f = ice_find_mac_filter(vsi, mac_addr);
 907         if (!f)
 908                 return -EINVAL;
 909
 910         INIT_LIST_HEAD(&list_head);
 911
 912         m_list_itr = (struct ice_fltr_list_entry *)
 913                 ice_malloc(hw, sizeof(*m_list_itr));
 914         if (!m_list_itr) {
 915                 ret = -ENOMEM;
 916                 goto DONE;
 917         }
 918         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 919                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 920         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 921         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 922         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 923         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 924         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 925
 926         LIST_ADD(&m_list_itr->list_entry, &list_head);
 927
 928         /* remove the mac filter */
 929         ret = ice_remove_mac(hw, &list_head);
 930         if (ret != ICE_SUCCESS) {
 931                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 932                 ret = -EINVAL;
 933                 goto DONE;
 934         }
 935
 936         /* Remove the mac addr from mac list */
 937         TAILQ_REMOVE(&vsi->mac_list, f, next);
 938         rte_free(f);
 939         vsi->mac_num--;
 940
 941         ret = 0;
 942 DONE:
 943         rte_free(m_list_itr);
 944         return ret;
 945 }
 946
 947 /* Find out specific VLAN filter */
 948 static struct ice_vlan_filter *
 949 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 950 {
 951         struct ice_vlan_filter *f;
 952
 953         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 954                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 955                     vlan->vid == f->vlan_info.vlan.vid)
 956                         return f;
 957         }
 958
 959         return NULL;
 960 }
 961
 962 static int
 963 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 964 {
 965         struct ice_fltr_list_entry *v_list_itr = NULL;
 966         struct ice_vlan_filter *f;
 967         struct LIST_HEAD_TYPE list_head;
 968         struct ice_hw *hw;
 969         int ret = 0;
 970
 971         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 972                 return -EINVAL;
 973
 974         hw = ICE_VSI_TO_HW(vsi);
 975
 976         /* If it's added and configured, return. */
 977         f = ice_find_vlan_filter(vsi, vlan);
 978         if (f) {
 979                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 980                 return 0;
 981         }
 982
 983         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 984                 return 0;
 985
 986         INIT_LIST_HEAD(&list_head);
 987
 988         v_list_itr = (struct ice_fltr_list_entry *)
 989                       ice_malloc(hw, sizeof(*v_list_itr));
 990         if (!v_list_itr) {
 991                 ret = -ENOMEM;
 992                 goto DONE;
 993         }
 994         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
 995         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
 996         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
 997         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 998         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 999         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1000         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1001         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1002
1003         LIST_ADD(&v_list_itr->list_entry, &list_head);
1004
1005         /* Add the vlan */
1006         ret = ice_add_vlan(hw, &list_head);
1007         if (ret != ICE_SUCCESS) {
1008                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1009                 ret = -EINVAL;
1010                 goto DONE;
1011         }
1012
1013         /* Add vlan into vlan list */
1014         f = rte_zmalloc(NULL, sizeof(*f), 0);
1015         if (!f) {
1016                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1017                 ret = -ENOMEM;
1018                 goto DONE;
1019         }
1020         f->vlan_info.vlan.tpid = vlan->tpid;
1021         f->vlan_info.vlan.vid = vlan->vid;
1022         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1023         vsi->vlan_num++;
1024
1025         ret = 0;
1026
1027 DONE:
1028         rte_free(v_list_itr);
1029         return ret;
1030 }
1031
1032 static int
1033 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1034 {
1035         struct ice_fltr_list_entry *v_list_itr = NULL;
1036         struct ice_vlan_filter *f;
1037         struct LIST_HEAD_TYPE list_head;
1038         struct ice_hw *hw;
1039         int ret = 0;
1040
1041         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1042                 return -EINVAL;
1043
1044         hw = ICE_VSI_TO_HW(vsi);
1045
1046         /* Can't find it, return an error */
1047         f = ice_find_vlan_filter(vsi, vlan);
1048         if (!f)
1049                 return -EINVAL;
1050
1051         INIT_LIST_HEAD(&list_head);
1052
1053         v_list_itr = (struct ice_fltr_list_entry *)
1054                       ice_malloc(hw, sizeof(*v_list_itr));
1055         if (!v_list_itr) {
1056                 ret = -ENOMEM;
1057                 goto DONE;
1058         }
1059
1060         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1061         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1062         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1063         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1064         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1065         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1066         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1067         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1068
1069         LIST_ADD(&v_list_itr->list_entry, &list_head);
1070
1071         /* remove the vlan filter */
1072         ret = ice_remove_vlan(hw, &list_head);
1073         if (ret != ICE_SUCCESS) {
1074                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1075                 ret = -EINVAL;
1076                 goto DONE;
1077         }
1078
1079         /* Remove the vlan id from vlan list */
1080         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1081         rte_free(f);
1082         vsi->vlan_num--;
1083
1084         ret = 0;
1085 DONE:
1086         rte_free(v_list_itr);
1087         return ret;
1088 }
1089
1090 static int
1091 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1092 {
1093         struct ice_mac_filter *m_f;
1094         struct ice_vlan_filter *v_f;
1095         int ret = 0;
1096
1097         if (!vsi || !vsi->mac_num)
1098                 return -EINVAL;
1099
1100         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1101                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1102                 if (ret != ICE_SUCCESS) {
1103                         ret = -EINVAL;
1104                         goto DONE;
1105                 }
1106         }
1107
1108         if (vsi->vlan_num == 0)
1109                 return 0;
1110
1111         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1112                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1113                 if (ret != ICE_SUCCESS) {
1114                         ret = -EINVAL;
1115                         goto DONE;
1116                 }
1117         }
1118
1119 DONE:
1120         return ret;
1121 }
1122
1123 /* Enable IRQ0 */
1124 static void
1125 ice_pf_enable_irq0(struct ice_hw *hw)
1126 {
1127         /* reset the registers */
1128         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1129         ICE_READ_REG(hw, PFINT_OICR);
1130
1131 #ifdef ICE_LSE_SPT
1132         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1133                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1134                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1135
1136         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1137                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1138                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1139                        PFINT_OICR_CTL_ITR_INDX_M) |
1140                       PFINT_OICR_CTL_CAUSE_ENA_M);
1141
1142         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1143                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1144                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1145                        PFINT_FW_CTL_ITR_INDX_M) |
1146                       PFINT_FW_CTL_CAUSE_ENA_M);
1147 #else
1148         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1149 #endif
1150
1151         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1152                       GLINT_DYN_CTL_INTENA_M |
1153                       GLINT_DYN_CTL_CLEARPBA_M |
1154                       GLINT_DYN_CTL_ITR_INDX_M);
1155
1156         ice_flush(hw);
1157 }
1158
1159 /* Disable IRQ0 */
1160 static void
1161 ice_pf_disable_irq0(struct ice_hw *hw)
1162 {
1163         /* Disable all interrupt types */
1164         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1165         ice_flush(hw);
1166 }
1167
1168 #ifdef ICE_LSE_SPT
1169 static void
1170 ice_handle_aq_msg(struct rte_eth_dev *dev)
1171 {
1172         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1173         struct ice_ctl_q_info *cq = &hw->adminq;
1174         struct ice_rq_event_info event;
1175         uint16_t pending, opcode;
1176         int ret;
1177
1178         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1179         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1180         if (!event.msg_buf) {
1181                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1182                 return;
1183         }
1184
1185         pending = 1;
1186         while (pending) {
1187                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1188
1189                 if (ret != ICE_SUCCESS) {
1190                         PMD_DRV_LOG(INFO,
1191                                     "Failed to read msg from AdminQ, "
1192                                     "adminq_err: %u",
1193                                     hw->adminq.sq_last_status);
1194                         break;
1195                 }
1196                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1197
1198                 switch (opcode) {
1199                 case ice_aqc_opc_get_link_status:
1200                         ret = ice_link_update(dev, 0);
1201                         if (!ret)
1202                                 rte_eth_dev_callback_process
1203                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1204                         break;
1205                 default:
1206                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1207                                     opcode);
1208                         break;
1209                 }
1210         }
1211         rte_free(event.msg_buf);
1212 }
1213 #endif
1214
1215 /**
1216  * Interrupt handler triggered by NIC for handling
1217  * specific interrupt.
1218  *
1219  * @param handle
1220  *  Pointer to interrupt handle.
1221  * @param param
1222  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1223  *
1224  * @return
1225  *  void
1226  */
1227 static void
1228 ice_interrupt_handler(void *param)
1229 {
1230         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1231         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         uint32_t oicr;
1233         uint32_t reg;
1234         uint8_t pf_num;
1235         uint8_t event;
1236         uint16_t queue;
1237         int ret;
1238 #ifdef ICE_LSE_SPT
1239         uint32_t int_fw_ctl;
1240 #endif
1241
1242         /* Disable interrupt */
1243         ice_pf_disable_irq0(hw);
1244
1245         /* read out interrupt causes */
1246         oicr = ICE_READ_REG(hw, PFINT_OICR);
1247 #ifdef ICE_LSE_SPT
1248         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1249 #endif
1250
1251         /* No interrupt event indicated */
1252         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1253                 PMD_DRV_LOG(INFO, "No interrupt event");
1254                 goto done;
1255         }
1256
1257 #ifdef ICE_LSE_SPT
1258         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1259                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1260                 ice_handle_aq_msg(dev);
1261         }
1262 #else
1263         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1264                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1265                 ret = ice_link_update(dev, 0);
1266                 if (!ret)
1267                         rte_eth_dev_callback_process
1268                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1269         }
1270 #endif
1271
1272         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1273                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1274                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1275                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1276                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1277                                  GL_MDET_TX_PQM_PF_NUM_S;
1278                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1279                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1280                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1281                                 GL_MDET_TX_PQM_QNUM_S;
1282
1283                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1284                                     "%d by PQM on TX queue %d PF# %d",
1285                                     event, queue, pf_num);
1286                 }
1287
1288                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1289                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1290                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1291                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1292                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1293                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1294                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1295                                 GL_MDET_TX_TCLAN_QNUM_S;
1296
1297                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1298                                     "%d by TCLAN on TX queue %d PF# %d",
1299                                     event, queue, pf_num);
1300                 }
1301         }
1302 done:
1303         /* Enable interrupt */
1304         ice_pf_enable_irq0(hw);
1305         rte_intr_ack(dev->intr_handle);
1306 }
1307
1308 static void
1309 ice_init_proto_xtr(struct rte_eth_dev *dev)
1310 {
1311         struct ice_adapter *ad =
1312                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1313         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1314         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1315         const struct proto_xtr_ol_flag *ol_flag;
1316         bool proto_xtr_enable = false;
1317         int offset;
1318         uint16_t i;
1319
1320         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1321         if (unlikely(pf->proto_xtr == NULL)) {
1322                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1323                 return;
1324         }
1325
1326         for (i = 0; i < pf->lan_nb_qps; i++) {
1327                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1328                                    ad->devargs.proto_xtr[i] :
1329                                    ad->devargs.proto_xtr_dflt;
1330
1331                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1332                         uint8_t type = pf->proto_xtr[i];
1333
1334                         ice_proto_xtr_ol_flag_params[type].required = true;
1335                         proto_xtr_enable = true;
1336                 }
1337         }
1338
1339         if (likely(!proto_xtr_enable))
1340                 return;
1341
1342         ice_check_proto_xtr_support(hw);
1343
1344         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1345         if (unlikely(offset == -1)) {
1346                 PMD_DRV_LOG(ERR,
1347                             "Protocol extraction metadata is disabled in mbuf with error %d",
1348                             -rte_errno);
1349                 return;
1350         }
1351
1352         PMD_DRV_LOG(DEBUG,
1353                     "Protocol extraction metadata offset in mbuf is : %d",
1354                     offset);
1355         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1356
1357         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1358                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1359
1360                 if (!ol_flag->required)
1361                         continue;
1362
1363                 if (!ice_proto_xtr_hw_support[i]) {
1364                         PMD_DRV_LOG(ERR,
1365                                     "Protocol extraction type %u is not supported in hardware",
1366                                     i);
1367                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1368                         break;
1369                 }
1370
1371                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1372                 if (unlikely(offset == -1)) {
1373                         PMD_DRV_LOG(ERR,
1374                                     "Protocol extraction offload '%s' failed to register with error %d",
1375                                     ol_flag->param.name, -rte_errno);
1376
1377                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1378                         break;
1379                 }
1380
1381                 PMD_DRV_LOG(DEBUG,
1382                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1383                             ol_flag->param.name, offset);
1384                 *ol_flag->ol_flag = 1ULL << offset;
1385         }
1386 }
1387
1388 /*  Initialize SW parameters of PF */
1389 static int
1390 ice_pf_sw_init(struct rte_eth_dev *dev)
1391 {
1392         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1393         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1394
1395         pf->lan_nb_qp_max =
1396                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1397                                   hw->func_caps.common_cap.num_rxq);
1398
1399         pf->lan_nb_qps = pf->lan_nb_qp_max;
1400
1401         ice_init_proto_xtr(dev);
1402
1403         if (hw->func_caps.fd_fltr_guar > 0 ||
1404             hw->func_caps.fd_fltr_best_effort > 0) {
1405                 pf->flags |= ICE_FLAG_FDIR;
1406                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1407                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1408         } else {
1409                 pf->fdir_nb_qps = 0;
1410         }
1411         pf->fdir_qp_offset = 0;
1412
1413         return 0;
1414 }
1415
1416 struct ice_vsi *
1417 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1418 {
1419         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1420         struct ice_vsi *vsi = NULL;
1421         struct ice_vsi_ctx vsi_ctx;
1422         int ret;
1423         struct rte_ether_addr broadcast = {
1424                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1425         struct rte_ether_addr mac_addr;
1426         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1427         uint8_t tc_bitmap = 0x1;
1428         uint16_t cfg;
1429
1430         /* hw->num_lports = 1 in NIC mode */
1431         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1432         if (!vsi)
1433                 return NULL;
1434
1435         vsi->idx = pf->next_vsi_idx;
1436         pf->next_vsi_idx++;
1437         vsi->type = type;
1438         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1439         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1440         vsi->vlan_anti_spoof_on = 0;
1441         vsi->vlan_filter_on = 1;
1442         TAILQ_INIT(&vsi->mac_list);
1443         TAILQ_INIT(&vsi->vlan_list);
1444
1445         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1446         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1447                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1448                         hw->func_caps.common_cap.rss_table_size;
1449         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1450
1451         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1452         switch (type) {
1453         case ICE_VSI_PF:
1454                 vsi->nb_qps = pf->lan_nb_qps;
1455                 vsi->base_queue = 1;
1456                 ice_vsi_config_default_rss(&vsi_ctx.info);
1457                 vsi_ctx.alloc_from_pool = true;
1458                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1459                 /* switch_id is queried by get_switch_config aq, which is done
1460                  * by ice_init_hw
1461                  */
1462                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1463                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1464                 /* Allow all untagged or tagged packets */
1465                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1466                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1467                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1468                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1469                 if (ice_is_dvm_ena(hw)) {
1470                         vsi_ctx.info.outer_vlan_flags =
1471                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1472                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1473                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1474                         vsi_ctx.info.outer_vlan_flags |=
1475                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1476                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1477                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1478                 }
1479
1480                 /* FDIR */
1481                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1482                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1483                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1484                 cfg = ICE_AQ_VSI_FD_ENABLE;
1485                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1486                 vsi_ctx.info.max_fd_fltr_dedicated =
1487                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1488                 vsi_ctx.info.max_fd_fltr_shared =
1489                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1490
1491                 /* Enable VLAN/UP trip */
1492                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1493                                                       &vsi_ctx.info,
1494                                                       ICE_DEFAULT_TCMAP);
1495                 if (ret) {
1496                         PMD_INIT_LOG(ERR,
1497                                      "tc queue mapping with vsi failed, "
1498                                      "err = %d",
1499                                      ret);
1500                         goto fail_mem;
1501                 }
1502
1503                 break;
1504         case ICE_VSI_CTRL:
1505                 vsi->nb_qps = pf->fdir_nb_qps;
1506                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1507                 vsi_ctx.alloc_from_pool = true;
1508                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1509
1510                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1511                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1512                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1513                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1514                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1515                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1516                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1517                                                       &vsi_ctx.info,
1518                                                       ICE_DEFAULT_TCMAP);
1519                 if (ret) {
1520                         PMD_INIT_LOG(ERR,
1521                                      "tc queue mapping with vsi failed, "
1522                                      "err = %d",
1523                                      ret);
1524                         goto fail_mem;
1525                 }
1526                 break;
1527         default:
1528                 /* for other types of VSI */
1529                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1530                 goto fail_mem;
1531         }
1532
1533         /* VF has MSIX interrupt in VF range, don't allocate here */
1534         if (type == ICE_VSI_PF) {
1535                 ret = ice_res_pool_alloc(&pf->msix_pool,
1536                                          RTE_MIN(vsi->nb_qps,
1537                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1538                 if (ret < 0) {
1539                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1540                                      vsi->vsi_id, ret);
1541                 }
1542                 vsi->msix_intr = ret;
1543                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1544         } else if (type == ICE_VSI_CTRL) {
1545                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1546                 if (ret < 0) {
1547                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1548                                     vsi->vsi_id, ret);
1549                 }
1550                 vsi->msix_intr = ret;
1551                 vsi->nb_msix = 1;
1552         } else {
1553                 vsi->msix_intr = 0;
1554                 vsi->nb_msix = 0;
1555         }
1556         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1557         if (ret != ICE_SUCCESS) {
1558                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1559                 goto fail_mem;
1560         }
1561         /* store vsi information is SW structure */
1562         vsi->vsi_id = vsi_ctx.vsi_num;
1563         vsi->info = vsi_ctx.info;
1564         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1565         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1566
1567         if (type == ICE_VSI_PF) {
1568                 /* MAC configuration */
1569                 rte_ether_addr_copy((struct rte_ether_addr *)
1570                                         hw->port_info->mac.perm_addr,
1571                                     &pf->dev_addr);
1572
1573                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1574                 ret = ice_add_mac_filter(vsi, &mac_addr);
1575                 if (ret != ICE_SUCCESS)
1576                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1577
1578                 rte_ether_addr_copy(&broadcast, &mac_addr);
1579                 ret = ice_add_mac_filter(vsi, &mac_addr);
1580                 if (ret != ICE_SUCCESS)
1581                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1582         }
1583
1584         /* At the beginning, only TC0. */
1585         /* What we need here is the maximam number of the TX queues.
1586          * Currently vsi->nb_qps means it.
1587          * Correct it if any change.
1588          */
1589         max_txqs[0] = vsi->nb_qps;
1590         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1591                               tc_bitmap, max_txqs);
1592         if (ret != ICE_SUCCESS)
1593                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1594
1595         return vsi;
1596 fail_mem:
1597         rte_free(vsi);
1598         pf->next_vsi_idx--;
1599         return NULL;
1600 }
1601
1602 static int
1603 ice_send_driver_ver(struct ice_hw *hw)
1604 {
1605         struct ice_driver_ver dv;
1606
1607         /* we don't have driver version use 0 for dummy */
1608         dv.major_ver = 0;
1609         dv.minor_ver = 0;
1610         dv.build_ver = 0;
1611         dv.subbuild_ver = 0;
1612         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1613
1614         return ice_aq_send_driver_ver(hw, &dv, NULL);
1615 }
1616
1617 static int
1618 ice_pf_setup(struct ice_pf *pf)
1619 {
1620         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1621         struct ice_vsi *vsi;
1622         uint16_t unused;
1623
1624         /* Clear all stats counters */
1625         pf->offset_loaded = false;
1626         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1627         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1628         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1629         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1630
1631         /* force guaranteed filter pool for PF */
1632         ice_alloc_fd_guar_item(hw, &unused,
1633                                hw->func_caps.fd_fltr_guar);
1634         /* force shared filter pool for PF */
1635         ice_alloc_fd_shrd_item(hw, &unused,
1636                                hw->func_caps.fd_fltr_best_effort);
1637
1638         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1639         if (!vsi) {
1640                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1641                 return -EINVAL;
1642         }
1643
1644         pf->main_vsi = vsi;
1645
1646         return 0;
1647 }
1648
1649 /*
1650  * Extract device serial number from PCIe Configuration Space and
1651  * determine the pkg file path according to the DSN.
1652  */
1653 #ifndef RTE_EXEC_ENV_WINDOWS
1654 static int
1655 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1656 {
1657         off_t pos;
1658         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1659         uint32_t dsn_low, dsn_high;
1660         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1661
1662         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1663
1664         if (pos) {
1665                 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0) {
1666                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1667                         return -1;
1668                 }
1669                 if (rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
1670                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
1671                         return -1;
1672                 }
1673                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1674                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1675         } else {
1676                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1677                 goto fail_dsn;
1678         }
1679
1680         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1681                 ICE_MAX_PKG_FILENAME_SIZE);
1682         if (!ice_access(strcat(pkg_file, opt_ddp_filename), 0))
1683                 return 0;
1684
1685         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1686                 ICE_MAX_PKG_FILENAME_SIZE);
1687         if (!ice_access(strcat(pkg_file, opt_ddp_filename), 0))
1688                 return 0;
1689
1690 fail_dsn:
1691         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1692         if (!ice_access(pkg_file, 0))
1693                 return 0;
1694         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1695         return 0;
1696 }
1697 #endif
1698
1699 enum ice_pkg_type
1700 ice_load_pkg_type(struct ice_hw *hw)
1701 {
1702         enum ice_pkg_type package_type;
1703
1704         /* store the activated package type (OS default or Comms) */
1705         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1706                 ICE_PKG_NAME_SIZE))
1707                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1708         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1709                 ICE_PKG_NAME_SIZE))
1710                 package_type = ICE_PKG_TYPE_COMMS;
1711         else
1712                 package_type = ICE_PKG_TYPE_UNKNOWN;
1713
1714         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1715                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1716                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1717                 hw->active_pkg_name,
1718                 ice_is_dvm_ena(hw) ? "double" : "single");
1719
1720         return package_type;
1721 }
1722
1723 #ifndef RTE_EXEC_ENV_WINDOWS
1724 static int ice_load_pkg(struct rte_eth_dev *dev)
1725 {
1726         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1728         int err;
1729         uint8_t *buf;
1730         int buf_len;
1731         FILE *file;
1732         struct stat fstat;
1733         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1734         struct ice_adapter *ad =
1735                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1736
1737         err = ice_pkg_file_search_path(pci_dev, pkg_file);
1738         if (err) {
1739                 PMD_INIT_LOG(ERR, "failed to search file path\n");
1740                 return err;
1741         }
1742
1743         file = fopen(pkg_file, "rb");
1744         if (!file)  {
1745                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1746                 return -1;
1747         }
1748
1749         err = stat(pkg_file, &fstat);
1750         if (err) {
1751                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1752                 fclose(file);
1753                 return err;
1754         }
1755
1756         buf_len = fstat.st_size;
1757         buf = rte_malloc(NULL, buf_len, 0);
1758
1759         if (!buf) {
1760                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1761                                 buf_len);
1762                 fclose(file);
1763                 return -1;
1764         }
1765
1766         err = fread(buf, buf_len, 1, file);
1767         if (err != 1) {
1768                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1769                 fclose(file);
1770                 err = -1;
1771                 goto fail_exit;
1772         }
1773
1774         fclose(file);
1775
1776         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1777         if (err) {
1778                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1779                 goto fail_exit;
1780         }
1781
1782         /* store the loaded pkg type info */
1783         ad->active_pkg_type = ice_load_pkg_type(hw);
1784
1785         err = ice_init_hw_tbls(hw);
1786         if (err) {
1787                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1788                 goto fail_init_tbls;
1789         }
1790
1791         return 0;
1792
1793 fail_init_tbls:
1794         rte_free(hw->pkg_copy);
1795 fail_exit:
1796         rte_free(buf);
1797         return err;
1798 }
1799 #endif
1800
1801 static void
1802 ice_base_queue_get(struct ice_pf *pf)
1803 {
1804         uint32_t reg;
1805         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1806
1807         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1808         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1809                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1810         } else {
1811                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1812                                         " index");
1813         }
1814 }
1815
1816 static int
1817 parse_bool(const char *key, const char *value, void *args)
1818 {
1819         int *i = (int *)args;
1820         char *end;
1821         int num;
1822
1823         num = strtoul(value, &end, 10);
1824
1825         if (num != 0 && num != 1) {
1826                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1827                         "value must be 0 or 1",
1828                         value, key);
1829                 return -1;
1830         }
1831
1832         *i = num;
1833         return 0;
1834 }
1835
1836 static int ice_parse_devargs(struct rte_eth_dev *dev)
1837 {
1838         struct ice_adapter *ad =
1839                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1840         struct rte_devargs *devargs = dev->device->devargs;
1841         struct rte_kvargs *kvlist;
1842         int ret;
1843
1844         if (devargs == NULL)
1845                 return 0;
1846
1847         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1848         if (kvlist == NULL) {
1849                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1850                 return -EINVAL;
1851         }
1852
1853         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1854         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1855                sizeof(ad->devargs.proto_xtr));
1856
1857         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1858                                  &handle_proto_xtr_arg, &ad->devargs);
1859         if (ret)
1860                 goto bail;
1861
1862         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1863                                  &parse_bool, &ad->devargs.safe_mode_support);
1864         if (ret)
1865                 goto bail;
1866
1867         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1868                                  &parse_bool, &ad->devargs.pipe_mode_support);
1869         if (ret)
1870                 goto bail;
1871
1872 bail:
1873         rte_kvargs_free(kvlist);
1874         return ret;
1875 }
1876
1877 /* Forward LLDP packets to default VSI by set switch rules */
1878 static int
1879 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1880 {
1881         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1882         struct ice_fltr_list_entry *s_list_itr = NULL;
1883         struct LIST_HEAD_TYPE list_head;
1884         int ret = 0;
1885
1886         INIT_LIST_HEAD(&list_head);
1887
1888         s_list_itr = (struct ice_fltr_list_entry *)
1889                         ice_malloc(hw, sizeof(*s_list_itr));
1890         if (!s_list_itr)
1891                 return -ENOMEM;
1892         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1893         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1894         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1895                         RTE_ETHER_TYPE_LLDP;
1896         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1897         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1898         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1899         LIST_ADD(&s_list_itr->list_entry, &list_head);
1900         if (on)
1901                 ret = ice_add_eth_mac(hw, &list_head);
1902         else
1903                 ret = ice_remove_eth_mac(hw, &list_head);
1904
1905         rte_free(s_list_itr);
1906         return ret;
1907 }
1908
1909 static enum ice_status
1910 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1911                 uint16_t num, uint16_t desc_id,
1912                 uint16_t *prof_buf, uint16_t *num_prof)
1913 {
1914         struct ice_aqc_res_elem *resp_buf;
1915         int ret;
1916         uint16_t buf_len;
1917         bool res_shared = 1;
1918         struct ice_aq_desc aq_desc;
1919         struct ice_sq_cd *cd = NULL;
1920         struct ice_aqc_get_allocd_res_desc *cmd =
1921                         &aq_desc.params.get_res_desc;
1922
1923         buf_len = sizeof(*resp_buf) * num;
1924         resp_buf = ice_malloc(hw, buf_len);
1925         if (!resp_buf)
1926                 return -ENOMEM;
1927
1928         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1929                         ice_aqc_opc_get_allocd_res_desc);
1930
1931         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1932                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1933                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1934         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1935
1936         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1937         if (!ret)
1938                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1939         else
1940                 goto exit;
1941
1942         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1943                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1944
1945 exit:
1946         rte_free(resp_buf);
1947         return ret;
1948 }
1949 static int
1950 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1951 {
1952         int ret;
1953         uint16_t prof_id;
1954         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1955         uint16_t first_desc = 1;
1956         uint16_t num_prof = 0;
1957
1958         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1959                         first_desc, prof_buf, &num_prof);
1960         if (ret) {
1961                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1962                 return ret;
1963         }
1964
1965         for (prof_id = 0; prof_id < num_prof; prof_id++) {
1966                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1967                 if (ret) {
1968                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1969                         return ret;
1970                 }
1971         }
1972         return 0;
1973 }
1974
1975 static int
1976 ice_reset_fxp_resource(struct ice_hw *hw)
1977 {
1978         int ret;
1979
1980         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1981         if (ret) {
1982                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1983                 return ret;
1984         }
1985
1986         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1987         if (ret) {
1988                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1989                 return ret;
1990         }
1991
1992         return 0;
1993 }
1994
1995 static void
1996 ice_rss_ctx_init(struct ice_pf *pf)
1997 {
1998         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1999 }
2000
2001 static uint64_t
2002 ice_get_supported_rxdid(struct ice_hw *hw)
2003 {
2004         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2005         uint32_t regval;
2006         int i;
2007
2008         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2009
2010         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2011                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2012                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2013                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2014                         supported_rxdid |= BIT(i);
2015         }
2016         return supported_rxdid;
2017 }
2018
2019 static int
2020 ice_dev_init(struct rte_eth_dev *dev)
2021 {
2022         struct rte_pci_device *pci_dev;
2023         struct rte_intr_handle *intr_handle;
2024         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2026         struct ice_adapter *ad =
2027                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2028         struct ice_vsi *vsi;
2029         int ret;
2030
2031         dev->dev_ops = &ice_eth_dev_ops;
2032         dev->rx_queue_count = ice_rx_queue_count;
2033         dev->rx_descriptor_status = ice_rx_descriptor_status;
2034         dev->tx_descriptor_status = ice_tx_descriptor_status;
2035         dev->rx_pkt_burst = ice_recv_pkts;
2036         dev->tx_pkt_burst = ice_xmit_pkts;
2037         dev->tx_pkt_prepare = ice_prep_pkts;
2038
2039         /* for secondary processes, we don't initialise any further as primary
2040          * has already done this work.
2041          */
2042         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2043                 ice_set_rx_function(dev);
2044                 ice_set_tx_function(dev);
2045                 return 0;
2046         }
2047
2048         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2049
2050         ice_set_default_ptype_table(dev);
2051         pci_dev = RTE_DEV_TO_PCI(dev->device);
2052         intr_handle = &pci_dev->intr_handle;
2053
2054         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2055         pf->adapter->eth_dev = dev;
2056         pf->dev_data = dev->data;
2057         hw->back = pf->adapter;
2058         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2059         hw->vendor_id = pci_dev->id.vendor_id;
2060         hw->device_id = pci_dev->id.device_id;
2061         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2062         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2063         hw->bus.device = pci_dev->addr.devid;
2064         hw->bus.func = pci_dev->addr.function;
2065
2066         ret = ice_parse_devargs(dev);
2067         if (ret) {
2068                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2069                 return -EINVAL;
2070         }
2071
2072         ice_init_controlq_parameter(hw);
2073
2074         ret = ice_init_hw(hw);
2075         if (ret) {
2076                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2077                 return -EINVAL;
2078         }
2079
2080 #ifndef RTE_EXEC_ENV_WINDOWS
2081         ret = ice_load_pkg(dev);
2082         if (ret) {
2083                 if (ad->devargs.safe_mode_support == 0) {
2084                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2085                                         "Use safe-mode-support=1 to enter Safe Mode");
2086                         return ret;
2087                 }
2088
2089                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2090                                         "Entering Safe Mode");
2091                 ad->is_safe_mode = 1;
2092         }
2093 #endif
2094
2095         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2096                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2097                      hw->api_maj_ver, hw->api_min_ver);
2098
2099         ice_pf_sw_init(dev);
2100         ret = ice_init_mac_address(dev);
2101         if (ret) {
2102                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2103                 goto err_init_mac;
2104         }
2105
2106         ret = ice_res_pool_init(&pf->msix_pool, 1,
2107                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2108         if (ret) {
2109                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2110                 goto err_msix_pool_init;
2111         }
2112
2113         ret = ice_pf_setup(pf);
2114         if (ret) {
2115                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2116                 goto err_pf_setup;
2117         }
2118
2119         ret = ice_send_driver_ver(hw);
2120         if (ret) {
2121                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2122                 goto err_pf_setup;
2123         }
2124
2125         vsi = pf->main_vsi;
2126
2127         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2128         if (ret != ICE_SUCCESS)
2129                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2130         ret = ice_init_dcb(hw, true);
2131         if (ret != ICE_SUCCESS)
2132                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2133         /* Forward LLDP packets to default VSI */
2134         ret = ice_vsi_config_sw_lldp(vsi, true);
2135         if (ret != ICE_SUCCESS)
2136                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2137         /* register callback func to eal lib */
2138         rte_intr_callback_register(intr_handle,
2139                                    ice_interrupt_handler, dev);
2140
2141         ice_pf_enable_irq0(hw);
2142
2143         /* enable uio intr after callback register */
2144         rte_intr_enable(intr_handle);
2145
2146         /* get base queue pairs index  in the device */
2147         ice_base_queue_get(pf);
2148
2149         /* Initialize RSS context for gtpu_eh */
2150         ice_rss_ctx_init(pf);
2151
2152         if (!ad->is_safe_mode) {
2153                 ret = ice_flow_init(ad);
2154                 if (ret) {
2155                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2156                         return ret;
2157                 }
2158         }
2159
2160         ret = ice_reset_fxp_resource(hw);
2161         if (ret) {
2162                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2163                 return ret;
2164         }
2165
2166         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2167
2168         return 0;
2169
2170 err_pf_setup:
2171         ice_res_pool_destroy(&pf->msix_pool);
2172 err_msix_pool_init:
2173         rte_free(dev->data->mac_addrs);
2174         dev->data->mac_addrs = NULL;
2175 err_init_mac:
2176         ice_sched_cleanup_all(hw);
2177         rte_free(hw->port_info);
2178         ice_shutdown_all_ctrlq(hw);
2179         rte_free(pf->proto_xtr);
2180
2181         return ret;
2182 }
2183
2184 int
2185 ice_release_vsi(struct ice_vsi *vsi)
2186 {
2187         struct ice_hw *hw;
2188         struct ice_vsi_ctx vsi_ctx;
2189         enum ice_status ret;
2190         int error = 0;
2191
2192         if (!vsi)
2193                 return error;
2194
2195         hw = ICE_VSI_TO_HW(vsi);
2196
2197         ice_remove_all_mac_vlan_filters(vsi);
2198
2199         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2200
2201         vsi_ctx.vsi_num = vsi->vsi_id;
2202         vsi_ctx.info = vsi->info;
2203         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2204         if (ret != ICE_SUCCESS) {
2205                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2206                 error = -1;
2207         }
2208
2209         rte_free(vsi->rss_lut);
2210         rte_free(vsi->rss_key);
2211         rte_free(vsi);
2212         return error;
2213 }
2214
2215 void
2216 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2217 {
2218         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2219         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2220         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2221         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2222         uint16_t msix_intr, i;
2223
2224         /* disable interrupt and also clear all the exist config */
2225         for (i = 0; i < vsi->nb_qps; i++) {
2226                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2227                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2228                 rte_wmb();
2229         }
2230
2231         if (rte_intr_allow_others(intr_handle))
2232                 /* vfio-pci */
2233                 for (i = 0; i < vsi->nb_msix; i++) {
2234                         msix_intr = vsi->msix_intr + i;
2235                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2236                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2237                 }
2238         else
2239                 /* igb_uio */
2240                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2241 }
2242
2243 static int
2244 ice_dev_stop(struct rte_eth_dev *dev)
2245 {
2246         struct rte_eth_dev_data *data = dev->data;
2247         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2248         struct ice_vsi *main_vsi = pf->main_vsi;
2249         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2250         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2251         uint16_t i;
2252
2253         /* avoid stopping again */
2254         if (pf->adapter_stopped)
2255                 return 0;
2256
2257         /* stop and clear all Rx queues */
2258         for (i = 0; i < data->nb_rx_queues; i++)
2259                 ice_rx_queue_stop(dev, i);
2260
2261         /* stop and clear all Tx queues */
2262         for (i = 0; i < data->nb_tx_queues; i++)
2263                 ice_tx_queue_stop(dev, i);
2264
2265         /* disable all queue interrupts */
2266         ice_vsi_disable_queues_intr(main_vsi);
2267
2268         if (pf->init_link_up)
2269                 ice_dev_set_link_up(dev);
2270         else
2271                 ice_dev_set_link_down(dev);
2272
2273         /* Clean datapath event and queue/vec mapping */
2274         rte_intr_efd_disable(intr_handle);
2275         if (intr_handle->intr_vec) {
2276                 rte_free(intr_handle->intr_vec);
2277                 intr_handle->intr_vec = NULL;
2278         }
2279
2280         pf->adapter_stopped = true;
2281         dev->data->dev_started = 0;
2282
2283         return 0;
2284 }
2285
2286 static int
2287 ice_dev_close(struct rte_eth_dev *dev)
2288 {
2289         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2290         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2293         struct ice_adapter *ad =
2294                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2295         int ret;
2296
2297         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2298                 return 0;
2299
2300         /* Since stop will make link down, then the link event will be
2301          * triggered, disable the irq firstly to avoid the port_infoe etc
2302          * resources deallocation causing the interrupt service thread
2303          * crash.
2304          */
2305         ice_pf_disable_irq0(hw);
2306
2307         ret = ice_dev_stop(dev);
2308
2309         if (!ad->is_safe_mode)
2310                 ice_flow_uninit(ad);
2311
2312         /* release all queue resource */
2313         ice_free_queues(dev);
2314
2315         ice_res_pool_destroy(&pf->msix_pool);
2316         ice_release_vsi(pf->main_vsi);
2317         ice_sched_cleanup_all(hw);
2318         ice_free_hw_tbls(hw);
2319         rte_free(hw->port_info);
2320         hw->port_info = NULL;
2321         ice_shutdown_all_ctrlq(hw);
2322         rte_free(pf->proto_xtr);
2323         pf->proto_xtr = NULL;
2324
2325         /* disable uio intr before callback unregister */
2326         rte_intr_disable(intr_handle);
2327
2328         /* unregister callback func from eal lib */
2329         rte_intr_callback_unregister(intr_handle,
2330                                      ice_interrupt_handler, dev);
2331
2332         return ret;
2333 }
2334
2335 static int
2336 ice_dev_uninit(struct rte_eth_dev *dev)
2337 {
2338         ice_dev_close(dev);
2339
2340         return 0;
2341 }
2342
2343 static bool
2344 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2345 {
2346         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2347 }
2348
2349 static void
2350 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2351 {
2352         cfg->hash_flds = 0;
2353         cfg->addl_hdrs = 0;
2354         cfg->symm = 0;
2355         cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2356 }
2357
2358 static int
2359 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2360 {
2361         enum ice_status status = ICE_SUCCESS;
2362         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2363         struct ice_vsi *vsi = pf->main_vsi;
2364
2365         if (!is_hash_cfg_valid(cfg))
2366                 return -ENOENT;
2367
2368         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2369         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2370                 PMD_DRV_LOG(ERR,
2371                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2372                             vsi->idx, status);
2373                 return -EBUSY;
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int
2380 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2381 {
2382         enum ice_status status = ICE_SUCCESS;
2383         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2384         struct ice_vsi *vsi = pf->main_vsi;
2385
2386         if (!is_hash_cfg_valid(cfg))
2387                 return -ENOENT;
2388
2389         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2390         if (status) {
2391                 PMD_DRV_LOG(ERR,
2392                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2393                             vsi->idx, status);
2394                 return -EBUSY;
2395         }
2396
2397         return 0;
2398 }
2399
2400 static int
2401 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2402 {
2403         int ret;
2404
2405         ret = ice_hash_moveout(pf, cfg);
2406         if (ret && (ret != -ENOENT))
2407                 return ret;
2408
2409         hash_cfg_reset(cfg);
2410
2411         return 0;
2412 }
2413
2414 static int
2415 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2416                          u8 ctx_idx)
2417 {
2418         int ret;
2419
2420         switch (ctx_idx) {
2421         case ICE_HASH_GTPU_CTX_EH_IP:
2422                 ret = ice_hash_remove(pf,
2423                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2424                 if (ret && (ret != -ENOENT))
2425                         return ret;
2426
2427                 ret = ice_hash_remove(pf,
2428                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2429                 if (ret && (ret != -ENOENT))
2430                         return ret;
2431
2432                 ret = ice_hash_remove(pf,
2433                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2434                 if (ret && (ret != -ENOENT))
2435                         return ret;
2436
2437                 ret = ice_hash_remove(pf,
2438                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2439                 if (ret && (ret != -ENOENT))
2440                         return ret;
2441
2442                 ret = ice_hash_remove(pf,
2443                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2444                 if (ret && (ret != -ENOENT))
2445                         return ret;
2446
2447                 ret = ice_hash_remove(pf,
2448                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2449                 if (ret && (ret != -ENOENT))
2450                         return ret;
2451
2452                 ret = ice_hash_remove(pf,
2453                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2454                 if (ret && (ret != -ENOENT))
2455                         return ret;
2456
2457                 ret = ice_hash_remove(pf,
2458                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2459                 if (ret && (ret != -ENOENT))
2460                         return ret;
2461
2462                 break;
2463         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2464                 ret = ice_hash_remove(pf,
2465                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2466                 if (ret && (ret != -ENOENT))
2467                         return ret;
2468
2469                 ret = ice_hash_remove(pf,
2470                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2471                 if (ret && (ret != -ENOENT))
2472                         return ret;
2473
2474                 ret = ice_hash_moveout(pf,
2475                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2476                 if (ret && (ret != -ENOENT))
2477                         return ret;
2478
2479                 ret = ice_hash_moveout(pf,
2480                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2481                 if (ret && (ret != -ENOENT))
2482                         return ret;
2483
2484                 ret = ice_hash_moveout(pf,
2485                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2486                 if (ret && (ret != -ENOENT))
2487                         return ret;
2488
2489                 ret = ice_hash_moveout(pf,
2490                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2491                 if (ret && (ret != -ENOENT))
2492                         return ret;
2493
2494                 break;
2495         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2496                 ret = ice_hash_remove(pf,
2497                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2498                 if (ret && (ret != -ENOENT))
2499                         return ret;
2500
2501                 ret = ice_hash_remove(pf,
2502                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2503                 if (ret && (ret != -ENOENT))
2504                         return ret;
2505
2506                 ret = ice_hash_moveout(pf,
2507                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2508                 if (ret && (ret != -ENOENT))
2509                         return ret;
2510
2511                 ret = ice_hash_moveout(pf,
2512                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2513                 if (ret && (ret != -ENOENT))
2514                         return ret;
2515
2516                 ret = ice_hash_moveout(pf,
2517                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2518                 if (ret && (ret != -ENOENT))
2519                         return ret;
2520
2521                 ret = ice_hash_moveout(pf,
2522                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2523                 if (ret && (ret != -ENOENT))
2524                         return ret;
2525
2526                 break;
2527         case ICE_HASH_GTPU_CTX_UP_IP:
2528                 ret = ice_hash_remove(pf,
2529                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2530                 if (ret && (ret != -ENOENT))
2531                         return ret;
2532
2533                 ret = ice_hash_remove(pf,
2534                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2535                 if (ret && (ret != -ENOENT))
2536                         return ret;
2537
2538                 ret = ice_hash_moveout(pf,
2539                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2540                 if (ret && (ret != -ENOENT))
2541                         return ret;
2542
2543                 ret = ice_hash_moveout(pf,
2544                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2545                 if (ret && (ret != -ENOENT))
2546                         return ret;
2547
2548                 ret = ice_hash_moveout(pf,
2549                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2550                 if (ret && (ret != -ENOENT))
2551                         return ret;
2552
2553                 break;
2554         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2555         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2556                 ret = ice_hash_moveout(pf,
2557                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2558                 if (ret && (ret != -ENOENT))
2559                         return ret;
2560
2561                 ret = ice_hash_moveout(pf,
2562                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2563                 if (ret && (ret != -ENOENT))
2564                         return ret;
2565
2566                 ret = ice_hash_moveout(pf,
2567                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2568                 if (ret && (ret != -ENOENT))
2569                         return ret;
2570
2571                 break;
2572         case ICE_HASH_GTPU_CTX_DW_IP:
2573                 ret = ice_hash_remove(pf,
2574                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2575                 if (ret && (ret != -ENOENT))
2576                         return ret;
2577
2578                 ret = ice_hash_remove(pf,
2579                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2580                 if (ret && (ret != -ENOENT))
2581                         return ret;
2582
2583                 ret = ice_hash_moveout(pf,
2584                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2585                 if (ret && (ret != -ENOENT))
2586                         return ret;
2587
2588                 ret = ice_hash_moveout(pf,
2589                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2590                 if (ret && (ret != -ENOENT))
2591                         return ret;
2592
2593                 ret = ice_hash_moveout(pf,
2594                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2595                 if (ret && (ret != -ENOENT))
2596                         return ret;
2597
2598                 break;
2599         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2600         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2601                 ret = ice_hash_moveout(pf,
2602                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2603                 if (ret && (ret != -ENOENT))
2604                         return ret;
2605
2606                 ret = ice_hash_moveout(pf,
2607                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2608                 if (ret && (ret != -ENOENT))
2609                         return ret;
2610
2611                 ret = ice_hash_moveout(pf,
2612                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2613                 if (ret && (ret != -ENOENT))
2614                         return ret;
2615
2616                 break;
2617         default:
2618                 break;
2619         }
2620
2621         return 0;
2622 }
2623
2624 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2625 {
2626         u8 eh_idx, ip_idx;
2627
2628         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2629                 eh_idx = 0;
2630         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2631                 eh_idx = 1;
2632         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2633                 eh_idx = 2;
2634         else
2635                 return ICE_HASH_GTPU_CTX_MAX;
2636
2637         ip_idx = 0;
2638         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2639                 ip_idx = 1;
2640         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2641                 ip_idx = 2;
2642
2643         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2644                 return eh_idx * 3 + ip_idx;
2645         else
2646                 return ICE_HASH_GTPU_CTX_MAX;
2647 }
2648
2649 static int
2650 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2651 {
2652         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2653
2654         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2655                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2656                                                 gtpu_ctx_idx);
2657         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2658                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2659                                                 gtpu_ctx_idx);
2660
2661         return 0;
2662 }
2663
2664 static int
2665 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2666                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2667 {
2668         int ret;
2669
2670         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2671                 ctx->ctx[ctx_idx] = *cfg;
2672
2673         switch (ctx_idx) {
2674         case ICE_HASH_GTPU_CTX_EH_IP:
2675                 break;
2676         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2677                 ret = ice_hash_moveback(pf,
2678                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2679                 if (ret && (ret != -ENOENT))
2680                         return ret;
2681
2682                 ret = ice_hash_moveback(pf,
2683                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2684                 if (ret && (ret != -ENOENT))
2685                         return ret;
2686
2687                 ret = ice_hash_moveback(pf,
2688                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2689                 if (ret && (ret != -ENOENT))
2690                         return ret;
2691
2692                 ret = ice_hash_moveback(pf,
2693                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2694                 if (ret && (ret != -ENOENT))
2695                         return ret;
2696
2697                 break;
2698         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2699                 ret = ice_hash_moveback(pf,
2700                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2701                 if (ret && (ret != -ENOENT))
2702                         return ret;
2703
2704                 ret = ice_hash_moveback(pf,
2705                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2706                 if (ret && (ret != -ENOENT))
2707                         return ret;
2708
2709                 ret = ice_hash_moveback(pf,
2710                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2711                 if (ret && (ret != -ENOENT))
2712                         return ret;
2713
2714                 ret = ice_hash_moveback(pf,
2715                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2716                 if (ret && (ret != -ENOENT))
2717                         return ret;
2718
2719                 break;
2720         case ICE_HASH_GTPU_CTX_UP_IP:
2721         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2722         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2723         case ICE_HASH_GTPU_CTX_DW_IP:
2724         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2725         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2726                 ret = ice_hash_moveback(pf,
2727                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2728                 if (ret && (ret != -ENOENT))
2729                         return ret;
2730
2731                 ret = ice_hash_moveback(pf,
2732                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2733                 if (ret && (ret != -ENOENT))
2734                         return ret;
2735
2736                 ret = ice_hash_moveback(pf,
2737                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2738                 if (ret && (ret != -ENOENT))
2739                         return ret;
2740
2741                 break;
2742         default:
2743                 break;
2744         }
2745
2746         return 0;
2747 }
2748
2749 static int
2750 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2751 {
2752         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2753
2754         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2755                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2756                                                  gtpu_ctx_idx, cfg);
2757         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2758                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2759                                                  gtpu_ctx_idx, cfg);
2760
2761         return 0;
2762 }
2763
2764 static void
2765 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2766 {
2767         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2768
2769         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2770                 return;
2771
2772         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2773                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2774         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2775                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2776 }
2777
2778 int
2779 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2780                      struct ice_rss_hash_cfg *cfg)
2781 {
2782         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2783         int ret;
2784
2785         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2786         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2787                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2788
2789         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2790
2791         return 0;
2792 }
2793
2794 int
2795 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2796                      struct ice_rss_hash_cfg *cfg)
2797 {
2798         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2799         int ret;
2800
2801         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2802         if (ret)
2803                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2804
2805         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2806         if (ret)
2807                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2808
2809         ret = ice_add_rss_cfg_post(pf, cfg);
2810         if (ret)
2811                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2812
2813         return 0;
2814 }
2815
2816 static void
2817 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2818 {
2819         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2820         struct ice_vsi *vsi = pf->main_vsi;
2821         struct ice_rss_hash_cfg cfg;
2822         int ret;
2823
2824 #define ICE_RSS_HF_ALL ( \
2825         ETH_RSS_IPV4 | \
2826         ETH_RSS_IPV6 | \
2827         ETH_RSS_NONFRAG_IPV4_UDP | \
2828         ETH_RSS_NONFRAG_IPV6_UDP | \
2829         ETH_RSS_NONFRAG_IPV4_TCP | \
2830         ETH_RSS_NONFRAG_IPV6_TCP | \
2831         ETH_RSS_NONFRAG_IPV4_SCTP | \
2832         ETH_RSS_NONFRAG_IPV6_SCTP)
2833
2834         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2835         if (ret)
2836                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2837                             __func__, ret);
2838
2839         cfg.symm = 0;
2840         cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2841         /* Configure RSS for IPv4 with src/dst addr as input set */
2842         if (rss_hf & ETH_RSS_IPV4) {
2843                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2844                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2845                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2846                 if (ret)
2847                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2848                                     __func__, ret);
2849         }
2850
2851         /* Configure RSS for IPv6 with src/dst addr as input set */
2852         if (rss_hf & ETH_RSS_IPV6) {
2853                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2854                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2855                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2856                 if (ret)
2857                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2858                                     __func__, ret);
2859         }
2860
2861         /* Configure RSS for udp4 with src/dst addr and port as input set */
2862         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2863                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2864                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2865                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2866                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2867                 if (ret)
2868                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2869                                     __func__, ret);
2870         }
2871
2872         /* Configure RSS for udp6 with src/dst addr and port as input set */
2873         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2874                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2875                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2876                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2877                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2878                 if (ret)
2879                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2880                                     __func__, ret);
2881         }
2882
2883         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2884         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2885                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2886                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2887                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2888                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2889                 if (ret)
2890                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2891                                     __func__, ret);
2892         }
2893
2894         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2895         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2896                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2897                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2898                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2899                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2900                 if (ret)
2901                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2902                                     __func__, ret);
2903         }
2904
2905         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2906         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2907                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2908                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2909                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2910                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2911                 if (ret)
2912                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2913                                     __func__, ret);
2914         }
2915
2916         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2917         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2918                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2919                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2920                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2921                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2922                 if (ret)
2923                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2924                                     __func__, ret);
2925         }
2926
2927         if (rss_hf & ETH_RSS_IPV4) {
2928                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2929                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2930                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2931                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2932                 if (ret)
2933                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2934                                     __func__, ret);
2935
2936                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2937                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2938                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2939                 if (ret)
2940                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2941                                     __func__, ret);
2942
2943                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2944                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2945                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2946                 if (ret)
2947                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2948                                     __func__, ret);
2949         }
2950
2951         if (rss_hf & ETH_RSS_IPV6) {
2952                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2953                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2954                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2955                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2956                 if (ret)
2957                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2958                                     __func__, ret);
2959
2960                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2961                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2962                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2963                 if (ret)
2964                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2965                                     __func__, ret);
2966
2967                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2968                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2969                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2970                 if (ret)
2971                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2972                                     __func__, ret);
2973         }
2974
2975         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2976                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2977                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2978                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2979                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2980                 if (ret)
2981                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2982                                     __func__, ret);
2983
2984                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2985                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2986                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2987                 if (ret)
2988                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2989                                     __func__, ret);
2990
2991                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2992                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2993                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2994                 if (ret)
2995                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2996                                     __func__, ret);
2997         }
2998
2999         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3000                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
3001                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3002                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3003                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3004                 if (ret)
3005                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3006                                     __func__, ret);
3007
3008                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
3009                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3010                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3011                 if (ret)
3012                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3013                                     __func__, ret);
3014
3015                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3016                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3017                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3018                 if (ret)
3019                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3020                                     __func__, ret);
3021         }
3022
3023         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3024                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3025                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3026                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3027                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3028                 if (ret)
3029                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3030                                     __func__, ret);
3031
3032                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3033                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3034                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3035                 if (ret)
3036                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3037                                     __func__, ret);
3038
3039                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3040                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3041                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3042                 if (ret)
3043                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3044                                     __func__, ret);
3045         }
3046
3047         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3048                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3049                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3050                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3051                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3052                 if (ret)
3053                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3054                                     __func__, ret);
3055
3056                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3057                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3058                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3059                 if (ret)
3060                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3061                                     __func__, ret);
3062
3063                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3064                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3065                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3066                 if (ret)
3067                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3068                                     __func__, ret);
3069         }
3070
3071         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3072 }
3073
3074 static int ice_init_rss(struct ice_pf *pf)
3075 {
3076         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3077         struct ice_vsi *vsi = pf->main_vsi;
3078         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3079         struct ice_aq_get_set_rss_lut_params lut_params;
3080         struct rte_eth_rss_conf *rss_conf;
3081         struct ice_aqc_get_set_rss_keys key;
3082         uint16_t i, nb_q;
3083         int ret = 0;
3084         bool is_safe_mode = pf->adapter->is_safe_mode;
3085         uint32_t reg;
3086
3087         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3088         nb_q = dev->data->nb_rx_queues;
3089         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3090         vsi->rss_lut_size = pf->hash_lut_size;
3091
3092         if (nb_q == 0) {
3093                 PMD_DRV_LOG(WARNING,
3094                         "RSS is not supported as rx queues number is zero\n");
3095                 return 0;
3096         }
3097
3098         if (is_safe_mode) {
3099                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3100                 return 0;
3101         }
3102
3103         if (!vsi->rss_key) {
3104                 vsi->rss_key = rte_zmalloc(NULL,
3105                                            vsi->rss_key_size, 0);
3106                 if (vsi->rss_key == NULL) {
3107                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3108                         return -ENOMEM;
3109                 }
3110         }
3111         if (!vsi->rss_lut) {
3112                 vsi->rss_lut = rte_zmalloc(NULL,
3113                                            vsi->rss_lut_size, 0);
3114                 if (vsi->rss_lut == NULL) {
3115                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3116                         rte_free(vsi->rss_key);
3117                         vsi->rss_key = NULL;
3118                         return -ENOMEM;
3119                 }
3120         }
3121         /* configure RSS key */
3122         if (!rss_conf->rss_key) {
3123                 /* Calculate the default hash key */
3124                 for (i = 0; i <= vsi->rss_key_size; i++)
3125                         vsi->rss_key[i] = (uint8_t)rte_rand();
3126         } else {
3127                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3128                            RTE_MIN(rss_conf->rss_key_len,
3129                                    vsi->rss_key_size));
3130         }
3131         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3132         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3133         if (ret)
3134                 goto out;
3135
3136         /* init RSS LUT table */
3137         for (i = 0; i < vsi->rss_lut_size; i++)
3138                 vsi->rss_lut[i] = i % nb_q;
3139
3140         lut_params.vsi_handle = vsi->idx;
3141         lut_params.lut_size = vsi->rss_lut_size;
3142         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3143         lut_params.lut = vsi->rss_lut;
3144         lut_params.global_lut_id = 0;
3145         ret = ice_aq_set_rss_lut(hw, &lut_params);
3146         if (ret)
3147                 goto out;
3148
3149         /* Enable registers for symmetric_toeplitz function. */
3150         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3151         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3152                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3153         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3154
3155         /* RSS hash configuration */
3156         ice_rss_hash_set(pf, rss_conf->rss_hf);
3157
3158         return 0;
3159 out:
3160         rte_free(vsi->rss_key);
3161         vsi->rss_key = NULL;
3162         rte_free(vsi->rss_lut);
3163         vsi->rss_lut = NULL;
3164         return -EINVAL;
3165 }
3166
3167 static int
3168 ice_dev_configure(struct rte_eth_dev *dev)
3169 {
3170         struct ice_adapter *ad =
3171                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3172         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3173         int ret;
3174
3175         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3176          * bulk allocation or vector Rx preconditions we will reset it.
3177          */
3178         ad->rx_bulk_alloc_allowed = true;
3179         ad->tx_simple_allowed = true;
3180
3181         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3182                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3183
3184         if (dev->data->nb_rx_queues) {
3185                 ret = ice_init_rss(pf);
3186                 if (ret) {
3187                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3188                         return ret;
3189                 }
3190         }
3191
3192         return 0;
3193 }
3194
3195 static void
3196 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3197                        int base_queue, int nb_queue)
3198 {
3199         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3200         uint32_t val, val_tx;
3201         int i;
3202
3203         for (i = 0; i < nb_queue; i++) {
3204                 /*do actual bind*/
3205                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3206                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3207                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3208                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3209
3210                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3211                             base_queue + i, msix_vect);
3212                 /* set ITR0 value */
3213                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3214                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3215                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3216         }
3217 }
3218
3219 void
3220 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3221 {
3222         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3223         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3224         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3225         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3226         uint16_t msix_vect = vsi->msix_intr;
3227         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3228         uint16_t queue_idx = 0;
3229         int record = 0;
3230         int i;
3231
3232         /* clear Rx/Tx queue interrupt */
3233         for (i = 0; i < vsi->nb_used_qps; i++) {
3234                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3235                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3236         }
3237
3238         /* PF bind interrupt */
3239         if (rte_intr_dp_is_en(intr_handle)) {
3240                 queue_idx = 0;
3241                 record = 1;
3242         }
3243
3244         for (i = 0; i < vsi->nb_used_qps; i++) {
3245                 if (nb_msix <= 1) {
3246                         if (!rte_intr_allow_others(intr_handle))
3247                                 msix_vect = ICE_MISC_VEC_ID;
3248
3249                         /* uio mapping all queue to one msix_vect */
3250                         __vsi_queues_bind_intr(vsi, msix_vect,
3251                                                vsi->base_queue + i,
3252                                                vsi->nb_used_qps - i);
3253
3254                         for (; !!record && i < vsi->nb_used_qps; i++)
3255                                 intr_handle->intr_vec[queue_idx + i] =
3256                                         msix_vect;
3257                         break;
3258                 }
3259
3260                 /* vfio 1:1 queue/msix_vect mapping */
3261                 __vsi_queues_bind_intr(vsi, msix_vect,
3262                                        vsi->base_queue + i, 1);
3263
3264                 if (!!record)
3265                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3266
3267                 msix_vect++;
3268                 nb_msix--;
3269         }
3270 }
3271
3272 void
3273 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3274 {
3275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3276         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3277         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3278         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3279         uint16_t msix_intr, i;
3280
3281         if (rte_intr_allow_others(intr_handle))
3282                 for (i = 0; i < vsi->nb_used_qps; i++) {
3283                         msix_intr = vsi->msix_intr + i;
3284                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3285                                       GLINT_DYN_CTL_INTENA_M |
3286                                       GLINT_DYN_CTL_CLEARPBA_M |
3287                                       GLINT_DYN_CTL_ITR_INDX_M |
3288                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3289                 }
3290         else
3291                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3292                               GLINT_DYN_CTL_INTENA_M |
3293                               GLINT_DYN_CTL_CLEARPBA_M |
3294                               GLINT_DYN_CTL_ITR_INDX_M |
3295                               GLINT_DYN_CTL_WB_ON_ITR_M);
3296 }
3297
3298 static int
3299 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3300 {
3301         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3303         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3304         struct ice_vsi *vsi = pf->main_vsi;
3305         uint32_t intr_vector = 0;
3306
3307         rte_intr_disable(intr_handle);
3308
3309         /* check and configure queue intr-vector mapping */
3310         if ((rte_intr_cap_multiple(intr_handle) ||
3311              !RTE_ETH_DEV_SRIOV(dev).active) &&
3312             dev->data->dev_conf.intr_conf.rxq != 0) {
3313                 intr_vector = dev->data->nb_rx_queues;
3314                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3315                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3316                                     ICE_MAX_INTR_QUEUE_NUM);
3317                         return -ENOTSUP;
3318                 }
3319                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3320                         return -1;
3321         }
3322
3323         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3324                 intr_handle->intr_vec =
3325                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3326                             0);
3327                 if (!intr_handle->intr_vec) {
3328                         PMD_DRV_LOG(ERR,
3329                                     "Failed to allocate %d rx_queues intr_vec",
3330                                     dev->data->nb_rx_queues);
3331                         return -ENOMEM;
3332                 }
3333         }
3334
3335         /* Map queues with MSIX interrupt */
3336         vsi->nb_used_qps = dev->data->nb_rx_queues;
3337         ice_vsi_queues_bind_intr(vsi);
3338
3339         /* Enable interrupts for all the queues */
3340         ice_vsi_enable_queues_intr(vsi);
3341
3342         rte_intr_enable(intr_handle);
3343
3344         return 0;
3345 }
3346
3347 static void
3348 ice_get_init_link_status(struct rte_eth_dev *dev)
3349 {
3350         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3351         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3352         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3353         struct ice_link_status link_status;
3354         int ret;
3355
3356         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3357                                    &link_status, NULL);
3358         if (ret != ICE_SUCCESS) {
3359                 PMD_DRV_LOG(ERR, "Failed to get link info");
3360                 pf->init_link_up = false;
3361                 return;
3362         }
3363
3364         if (link_status.link_info & ICE_AQ_LINK_UP)
3365                 pf->init_link_up = true;
3366 }
3367
3368 static int
3369 ice_dev_start(struct rte_eth_dev *dev)
3370 {
3371         struct rte_eth_dev_data *data = dev->data;
3372         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3374         struct ice_vsi *vsi = pf->main_vsi;
3375         uint16_t nb_rxq = 0;
3376         uint16_t nb_txq, i;
3377         uint16_t max_frame_size;
3378         int mask, ret;
3379
3380         /* program Tx queues' context in hardware */
3381         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3382                 ret = ice_tx_queue_start(dev, nb_txq);
3383                 if (ret) {
3384                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3385                         goto tx_err;
3386                 }
3387         }
3388
3389         /* program Rx queues' context in hardware*/
3390         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3391                 ret = ice_rx_queue_start(dev, nb_rxq);
3392                 if (ret) {
3393                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3394                         goto rx_err;
3395                 }
3396         }
3397
3398         ice_set_rx_function(dev);
3399         ice_set_tx_function(dev);
3400
3401         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3402                         ETH_VLAN_EXTEND_MASK;
3403         ret = ice_vlan_offload_set(dev, mask);
3404         if (ret) {
3405                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3406                 goto rx_err;
3407         }
3408
3409         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3410         if (ice_rxq_intr_setup(dev))
3411                 return -EIO;
3412
3413         /* Enable receiving broadcast packets and transmitting packets */
3414         ret = ice_set_vsi_promisc(hw, vsi->idx,
3415                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3416                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3417                                   0);
3418         if (ret != ICE_SUCCESS)
3419                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3420
3421         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3422                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3423                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3424                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3425                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3426                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3427                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3428                                      NULL);
3429         if (ret != ICE_SUCCESS)
3430                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3431
3432         ice_get_init_link_status(dev);
3433
3434         ice_dev_set_link_up(dev);
3435
3436         /* Call get_link_info aq commond to enable/disable LSE */
3437         ice_link_update(dev, 0);
3438
3439         pf->adapter_stopped = false;
3440
3441         /* Set the max frame size to default value*/
3442         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3443                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3444                 ICE_FRAME_SIZE_MAX;
3445
3446         /* Set the max frame size to HW*/
3447         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3448
3449         return 0;
3450
3451         /* stop the started queues if failed to start all queues */
3452 rx_err:
3453         for (i = 0; i < nb_rxq; i++)
3454                 ice_rx_queue_stop(dev, i);
3455 tx_err:
3456         for (i = 0; i < nb_txq; i++)
3457                 ice_tx_queue_stop(dev, i);
3458
3459         return -EIO;
3460 }
3461
3462 static int
3463 ice_dev_reset(struct rte_eth_dev *dev)
3464 {
3465         int ret;
3466
3467         if (dev->data->sriov.active)
3468                 return -ENOTSUP;
3469
3470         ret = ice_dev_uninit(dev);
3471         if (ret) {
3472                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3473                 return -ENXIO;
3474         }
3475
3476         ret = ice_dev_init(dev);
3477         if (ret) {
3478                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3479                 return -ENXIO;
3480         }
3481
3482         return 0;
3483 }
3484
3485 static int
3486 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3487 {
3488         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3489         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490         struct ice_vsi *vsi = pf->main_vsi;
3491         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3492         bool is_safe_mode = pf->adapter->is_safe_mode;
3493         u64 phy_type_low;
3494         u64 phy_type_high;
3495
3496         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3497         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3498         dev_info->max_rx_queues = vsi->nb_qps;
3499         dev_info->max_tx_queues = vsi->nb_qps;
3500         dev_info->max_mac_addrs = vsi->max_macaddrs;
3501         dev_info->max_vfs = pci_dev->max_vfs;
3502         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3503         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3504
3505         dev_info->rx_offload_capa =
3506                 DEV_RX_OFFLOAD_VLAN_STRIP |
3507                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3508                 DEV_RX_OFFLOAD_KEEP_CRC |
3509                 DEV_RX_OFFLOAD_SCATTER |
3510                 DEV_RX_OFFLOAD_VLAN_FILTER;
3511         dev_info->tx_offload_capa =
3512                 DEV_TX_OFFLOAD_VLAN_INSERT |
3513                 DEV_TX_OFFLOAD_TCP_TSO |
3514                 DEV_TX_OFFLOAD_MULTI_SEGS |
3515                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3516         dev_info->flow_type_rss_offloads = 0;
3517
3518         if (!is_safe_mode) {
3519                 dev_info->rx_offload_capa |=
3520                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3521                         DEV_RX_OFFLOAD_UDP_CKSUM |
3522                         DEV_RX_OFFLOAD_TCP_CKSUM |
3523                         DEV_RX_OFFLOAD_QINQ_STRIP |
3524                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3525                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3526                         DEV_RX_OFFLOAD_RSS_HASH;
3527                 dev_info->tx_offload_capa |=
3528                         DEV_TX_OFFLOAD_QINQ_INSERT |
3529                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3530                         DEV_TX_OFFLOAD_UDP_CKSUM |
3531                         DEV_TX_OFFLOAD_TCP_CKSUM |
3532                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3533                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3534                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3535                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3536         }
3537
3538         dev_info->rx_queue_offload_capa = 0;
3539         dev_info->tx_queue_offload_capa = 0;
3540
3541         dev_info->reta_size = pf->hash_lut_size;
3542         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3543
3544         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3545                 .rx_thresh = {
3546                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3547                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3548                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3549                 },
3550                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3551                 .rx_drop_en = 0,
3552                 .offloads = 0,
3553         };
3554
3555         dev_info->default_txconf = (struct rte_eth_txconf) {
3556                 .tx_thresh = {
3557                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3558                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3559                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3560                 },
3561                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3562                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3563                 .offloads = 0,
3564         };
3565
3566         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3567                 .nb_max = ICE_MAX_RING_DESC,
3568                 .nb_min = ICE_MIN_RING_DESC,
3569                 .nb_align = ICE_ALIGN_RING_DESC,
3570         };
3571
3572         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3573                 .nb_max = ICE_MAX_RING_DESC,
3574                 .nb_min = ICE_MIN_RING_DESC,
3575                 .nb_align = ICE_ALIGN_RING_DESC,
3576         };
3577
3578         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3579                                ETH_LINK_SPEED_100M |
3580                                ETH_LINK_SPEED_1G |
3581                                ETH_LINK_SPEED_2_5G |
3582                                ETH_LINK_SPEED_5G |
3583                                ETH_LINK_SPEED_10G |
3584                                ETH_LINK_SPEED_20G |
3585                                ETH_LINK_SPEED_25G;
3586
3587         phy_type_low = hw->port_info->phy.phy_type_low;
3588         phy_type_high = hw->port_info->phy.phy_type_high;
3589
3590         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3591                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3592
3593         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3594                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3595                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3596
3597         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3598         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3599
3600         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3601         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3602         dev_info->default_rxportconf.nb_queues = 1;
3603         dev_info->default_txportconf.nb_queues = 1;
3604         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3605         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3606
3607         return 0;
3608 }
3609
3610 static inline int
3611 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3612                             struct rte_eth_link *link)
3613 {
3614         struct rte_eth_link *dst = link;
3615         struct rte_eth_link *src = &dev->data->dev_link;
3616
3617         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3618                                 *(uint64_t *)src) == 0)
3619                 return -1;
3620
3621         return 0;
3622 }
3623
3624 static inline int
3625 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3626                              struct rte_eth_link *link)
3627 {
3628         struct rte_eth_link *dst = &dev->data->dev_link;
3629         struct rte_eth_link *src = link;
3630
3631         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3632                                 *(uint64_t *)src) == 0)
3633                 return -1;
3634
3635         return 0;
3636 }
3637
3638 static int
3639 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3640 {
3641 #define CHECK_INTERVAL 100  /* 100ms */
3642 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3643         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644         struct ice_link_status link_status;
3645         struct rte_eth_link link, old;
3646         int status;
3647         unsigned int rep_cnt = MAX_REPEAT_TIME;
3648         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3649
3650         memset(&link, 0, sizeof(link));
3651         memset(&old, 0, sizeof(old));
3652         memset(&link_status, 0, sizeof(link_status));
3653         ice_atomic_read_link_status(dev, &old);
3654
3655         do {
3656                 /* Get link status information from hardware */
3657                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3658                                               &link_status, NULL);
3659                 if (status != ICE_SUCCESS) {
3660                         link.link_speed = ETH_SPEED_NUM_100M;
3661                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3662                         PMD_DRV_LOG(ERR, "Failed to get link info");
3663                         goto out;
3664                 }
3665
3666                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3667                 if (!wait_to_complete || link.link_status)
3668                         break;
3669
3670                 rte_delay_ms(CHECK_INTERVAL);
3671         } while (--rep_cnt);
3672
3673         if (!link.link_status)
3674                 goto out;
3675
3676         /* Full-duplex operation at all supported speeds */
3677         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3678
3679         /* Parse the link status */
3680         switch (link_status.link_speed) {
3681         case ICE_AQ_LINK_SPEED_10MB:
3682                 link.link_speed = ETH_SPEED_NUM_10M;
3683                 break;
3684         case ICE_AQ_LINK_SPEED_100MB:
3685                 link.link_speed = ETH_SPEED_NUM_100M;
3686                 break;
3687         case ICE_AQ_LINK_SPEED_1000MB:
3688                 link.link_speed = ETH_SPEED_NUM_1G;
3689                 break;
3690         case ICE_AQ_LINK_SPEED_2500MB:
3691                 link.link_speed = ETH_SPEED_NUM_2_5G;
3692                 break;
3693         case ICE_AQ_LINK_SPEED_5GB:
3694                 link.link_speed = ETH_SPEED_NUM_5G;
3695                 break;
3696         case ICE_AQ_LINK_SPEED_10GB:
3697                 link.link_speed = ETH_SPEED_NUM_10G;
3698                 break;
3699         case ICE_AQ_LINK_SPEED_20GB:
3700                 link.link_speed = ETH_SPEED_NUM_20G;
3701                 break;
3702         case ICE_AQ_LINK_SPEED_25GB:
3703                 link.link_speed = ETH_SPEED_NUM_25G;
3704                 break;
3705         case ICE_AQ_LINK_SPEED_40GB:
3706                 link.link_speed = ETH_SPEED_NUM_40G;
3707                 break;
3708         case ICE_AQ_LINK_SPEED_50GB:
3709                 link.link_speed = ETH_SPEED_NUM_50G;
3710                 break;
3711         case ICE_AQ_LINK_SPEED_100GB:
3712                 link.link_speed = ETH_SPEED_NUM_100G;
3713                 break;
3714         case ICE_AQ_LINK_SPEED_UNKNOWN:
3715                 PMD_DRV_LOG(ERR, "Unknown link speed");
3716                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3717                 break;
3718         default:
3719                 PMD_DRV_LOG(ERR, "None link speed");
3720                 link.link_speed = ETH_SPEED_NUM_NONE;
3721                 break;
3722         }
3723
3724         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3725                               ETH_LINK_SPEED_FIXED);
3726
3727 out:
3728         ice_atomic_write_link_status(dev, &link);
3729         if (link.link_status == old.link_status)
3730                 return -1;
3731
3732         return 0;
3733 }
3734
3735 /* Force the physical link state by getting the current PHY capabilities from
3736  * hardware and setting the PHY config based on the determined capabilities. If
3737  * link changes, link event will be triggered because both the Enable Automatic
3738  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3739  */
3740 static enum ice_status
3741 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3742 {
3743         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3744         struct ice_aqc_get_phy_caps_data *pcaps;
3745         struct ice_port_info *pi;
3746         enum ice_status status;
3747
3748         if (!hw || !hw->port_info)
3749                 return ICE_ERR_PARAM;
3750
3751         pi = hw->port_info;
3752
3753         pcaps = (struct ice_aqc_get_phy_caps_data *)
3754                 ice_malloc(hw, sizeof(*pcaps));
3755         if (!pcaps)
3756                 return ICE_ERR_NO_MEMORY;
3757
3758         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3759                                      pcaps, NULL);
3760         if (status)
3761                 goto out;
3762
3763         /* No change in link */
3764         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3765             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3766                 goto out;
3767
3768         cfg.phy_type_low = pcaps->phy_type_low;
3769         cfg.phy_type_high = pcaps->phy_type_high;
3770         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3771         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3772         cfg.eee_cap = pcaps->eee_cap;
3773         cfg.eeer_value = pcaps->eeer_value;
3774         cfg.link_fec_opt = pcaps->link_fec_options;
3775         if (link_up)
3776                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3777         else
3778                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3779
3780         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3781
3782 out:
3783         ice_free(hw, pcaps);
3784         return status;
3785 }
3786
3787 static int
3788 ice_dev_set_link_up(struct rte_eth_dev *dev)
3789 {
3790         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791
3792         return ice_force_phys_link_state(hw, true);
3793 }
3794
3795 static int
3796 ice_dev_set_link_down(struct rte_eth_dev *dev)
3797 {
3798         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799
3800         return ice_force_phys_link_state(hw, false);
3801 }
3802
3803 static int
3804 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3805 {
3806         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3807         struct rte_eth_dev_data *dev_data = pf->dev_data;
3808         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3809
3810         /* check if mtu is within the allowed range */
3811         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3812                 return -EINVAL;
3813
3814         /* mtu setting is forbidden if port is start */
3815         if (dev_data->dev_started) {
3816                 PMD_DRV_LOG(ERR,
3817                             "port %d must be stopped before configuration",
3818                             dev_data->port_id);
3819                 return -EBUSY;
3820         }
3821
3822         if (frame_size > ICE_ETH_MAX_LEN)
3823                 dev_data->dev_conf.rxmode.offloads |=
3824                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3825         else
3826                 dev_data->dev_conf.rxmode.offloads &=
3827                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3828
3829         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3830
3831         return 0;
3832 }
3833
3834 static int ice_macaddr_set(struct rte_eth_dev *dev,
3835                            struct rte_ether_addr *mac_addr)
3836 {
3837         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3839         struct ice_vsi *vsi = pf->main_vsi;
3840         struct ice_mac_filter *f;
3841         uint8_t flags = 0;
3842         int ret;
3843
3844         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3845                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3846                 return -EINVAL;
3847         }
3848
3849         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3850                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3851                         break;
3852         }
3853
3854         if (!f) {
3855                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3856                 return -EIO;
3857         }
3858
3859         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3860         if (ret != ICE_SUCCESS) {
3861                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3862                 return -EIO;
3863         }
3864         ret = ice_add_mac_filter(vsi, mac_addr);
3865         if (ret != ICE_SUCCESS) {
3866                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3867                 return -EIO;
3868         }
3869         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3870
3871         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3872         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3873         if (ret != ICE_SUCCESS)
3874                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3875
3876         return 0;
3877 }
3878
3879 /* Add a MAC address, and update filters */
3880 static int
3881 ice_macaddr_add(struct rte_eth_dev *dev,
3882                 struct rte_ether_addr *mac_addr,
3883                 __rte_unused uint32_t index,
3884                 __rte_unused uint32_t pool)
3885 {
3886         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3887         struct ice_vsi *vsi = pf->main_vsi;
3888         int ret;
3889
3890         ret = ice_add_mac_filter(vsi, mac_addr);
3891         if (ret != ICE_SUCCESS) {
3892                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3893                 return -EINVAL;
3894         }
3895
3896         return ICE_SUCCESS;
3897 }
3898
3899 /* Remove a MAC address, and update filters */
3900 static void
3901 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3902 {
3903         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3904         struct ice_vsi *vsi = pf->main_vsi;
3905         struct rte_eth_dev_data *data = dev->data;
3906         struct rte_ether_addr *macaddr;
3907         int ret;
3908
3909         macaddr = &data->mac_addrs[index];
3910         ret = ice_remove_mac_filter(vsi, macaddr);
3911         if (ret) {
3912                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3913                 return;
3914         }
3915 }
3916
3917 static int
3918 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3919 {
3920         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3921         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3922         struct ice_vsi *vsi = pf->main_vsi;
3923         int ret;
3924
3925         PMD_INIT_FUNC_TRACE();
3926
3927         /**
3928          * Vlan 0 is the generic filter for untagged packets
3929          * and can't be removed or added by user.
3930          */
3931         if (vlan_id == 0)
3932                 return 0;
3933
3934         if (on) {
3935                 ret = ice_add_vlan_filter(vsi, &vlan);
3936                 if (ret < 0) {
3937                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3938                         return -EINVAL;
3939                 }
3940         } else {
3941                 ret = ice_remove_vlan_filter(vsi, &vlan);
3942                 if (ret < 0) {
3943                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3944                         return -EINVAL;
3945                 }
3946         }
3947
3948         return 0;
3949 }
3950
3951 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3952  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3953  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3954  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3955  *
3956  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3957  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3958  * traffic in SVM, since the VLAN TPID isn't part of filtering.
3959  *
3960  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3961  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3962  * part of filtering.
3963  */
3964 static int
3965 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3966 {
3967         struct ice_vlan vlan;
3968         int err;
3969
3970         vlan = ICE_VLAN(0, 0);
3971         err = ice_add_vlan_filter(vsi, &vlan);
3972         if (err) {
3973                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3974                 return err;
3975         }
3976
3977         /* in SVM both VLAN 0 filters are identical */
3978         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3979                 return 0;
3980
3981         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3982         err = ice_add_vlan_filter(vsi, &vlan);
3983         if (err) {
3984                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3985                 return err;
3986         }
3987
3988         return 0;
3989 }
3990
3991 /*
3992  * Delete the VLAN 0 filters in the same manner that they were added in
3993  * ice_vsi_add_vlan_zero.
3994  */
3995 static int
3996 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3997 {
3998         struct ice_vlan vlan;
3999         int err;
4000
4001         vlan = ICE_VLAN(0, 0);
4002         err = ice_remove_vlan_filter(vsi, &vlan);
4003         if (err) {
4004                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4005                 return err;
4006         }
4007
4008         /* in SVM both VLAN 0 filters are identical */
4009         if (!ice_is_dvm_ena(&vsi->adapter->hw))
4010                 return 0;
4011
4012         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4013         err = ice_remove_vlan_filter(vsi, &vlan);
4014         if (err) {
4015                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4016                 return err;
4017         }
4018
4019         return 0;
4020 }
4021
4022 /* Configure vlan filter on or off */
4023 static int
4024 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4025 {
4026         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4027         struct ice_vsi_ctx ctxt;
4028         uint8_t sw_flags2;
4029         int ret = 0;
4030
4031         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4032
4033         if (on)
4034                 vsi->info.sw_flags2 |= sw_flags2;
4035         else
4036                 vsi->info.sw_flags2 &= ~sw_flags2;
4037
4038         vsi->info.sw_id = hw->port_info->sw_id;
4039         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4040         ctxt.info.valid_sections =
4041                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4042                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4043         ctxt.vsi_num = vsi->vsi_id;
4044
4045         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4046         if (ret) {
4047                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4048                             on ? "enable" : "disable");
4049                 return -EINVAL;
4050         } else {
4051                 vsi->info.valid_sections |=
4052                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4053                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4054         }
4055
4056         /* consist with other drivers, allow untagged packet when vlan filter on */
4057         if (on)
4058                 ret = ice_vsi_add_vlan_zero(vsi);
4059         else
4060                 ret = ice_vsi_del_vlan_zero(vsi);
4061
4062         return 0;
4063 }
4064
4065 /* Manage VLAN stripping for the VSI for Rx */
4066 static int
4067 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4068 {
4069         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4070         struct ice_vsi_ctx ctxt;
4071         enum ice_status status;
4072         int err = 0;
4073
4074         /* do not allow modifying VLAN stripping when a port VLAN is configured
4075          * on this VSI
4076          */
4077         if (vsi->info.port_based_inner_vlan)
4078                 return 0;
4079
4080         memset(&ctxt, 0, sizeof(ctxt));
4081
4082         if (ena)
4083                 /* Strip VLAN tag from Rx packet and put it in the desc */
4084                 ctxt.info.inner_vlan_flags =
4085                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4086         else
4087                 /* Disable stripping. Leave tag in packet */
4088                 ctxt.info.inner_vlan_flags =
4089                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4090
4091         /* Allow all packets untagged/tagged */
4092         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4093
4094         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4095
4096         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4097         if (status) {
4098                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4099                             ena ? "enable" : "disable");
4100                 err = -EIO;
4101         } else {
4102                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4103         }
4104
4105         return err;
4106 }
4107
4108 static int
4109 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4110 {
4111         return ice_vsi_manage_vlan_stripping(vsi, true);
4112 }
4113
4114 static int
4115 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4116 {
4117         return ice_vsi_manage_vlan_stripping(vsi, false);
4118 }
4119
4120 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4121 {
4122         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4123         struct ice_vsi_ctx ctxt;
4124         enum ice_status status;
4125         int err = 0;
4126
4127         /* do not allow modifying VLAN stripping when a port VLAN is configured
4128          * on this VSI
4129          */
4130         if (vsi->info.port_based_outer_vlan)
4131                 return 0;
4132
4133         memset(&ctxt, 0, sizeof(ctxt));
4134
4135         ctxt.info.valid_sections =
4136                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4137         /* clear current outer VLAN strip settings */
4138         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4139                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4140         ctxt.info.outer_vlan_flags |=
4141                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4142                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4143                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4144                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4145
4146         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4147         if (status) {
4148                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4149                 err = -EIO;
4150         } else {
4151                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4152         }
4153
4154         return err;
4155 }
4156
4157 static int
4158 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4159 {
4160         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4161         struct ice_vsi_ctx ctxt;
4162         enum ice_status status;
4163         int err = 0;
4164
4165         if (vsi->info.port_based_outer_vlan)
4166                 return 0;
4167
4168         memset(&ctxt, 0, sizeof(ctxt));
4169
4170         ctxt.info.valid_sections =
4171                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4172         /* clear current outer VLAN strip settings */
4173         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4174                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4175         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4176                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4177
4178         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4179         if (status) {
4180                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4181                 err = -EIO;
4182         } else {
4183                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4184         }
4185
4186         return err;
4187 }
4188
4189 static int
4190 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4191 {
4192         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4193         int ret;
4194
4195         if (ice_is_dvm_ena(hw)) {
4196                 if (ena)
4197                         ret = ice_vsi_ena_outer_stripping(vsi);
4198                 else
4199                         ret = ice_vsi_dis_outer_stripping(vsi);
4200         } else {
4201                 if (ena)
4202                         ret = ice_vsi_ena_inner_stripping(vsi);
4203                 else
4204                         ret = ice_vsi_dis_inner_stripping(vsi);
4205         }
4206
4207         return ret;
4208 }
4209
4210 static int
4211 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4212 {
4213         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4214         struct ice_vsi *vsi = pf->main_vsi;
4215         struct rte_eth_rxmode *rxmode;
4216
4217         rxmode = &dev->data->dev_conf.rxmode;
4218         if (mask & ETH_VLAN_FILTER_MASK) {
4219                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4220                         ice_vsi_config_vlan_filter(vsi, true);
4221                 else
4222                         ice_vsi_config_vlan_filter(vsi, false);
4223         }
4224
4225         if (mask & ETH_VLAN_STRIP_MASK) {
4226                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4227                         ice_vsi_config_vlan_stripping(vsi, true);
4228                 else
4229                         ice_vsi_config_vlan_stripping(vsi, false);
4230         }
4231
4232         return 0;
4233 }
4234
4235 static int
4236 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4237 {
4238         struct ice_aq_get_set_rss_lut_params lut_params;
4239         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4240         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4241         int ret;
4242
4243         if (!lut)
4244                 return -EINVAL;
4245
4246         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4247                 lut_params.vsi_handle = vsi->idx;
4248                 lut_params.lut_size = lut_size;
4249                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4250                 lut_params.lut = lut;
4251                 lut_params.global_lut_id = 0;
4252                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4253                 if (ret) {
4254                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4255                         return -EINVAL;
4256                 }
4257         } else {
4258                 uint64_t *lut_dw = (uint64_t *)lut;
4259                 uint16_t i, lut_size_dw = lut_size / 4;
4260
4261                 for (i = 0; i < lut_size_dw; i++)
4262                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4263         }
4264
4265         return 0;
4266 }
4267
4268 static int
4269 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4270 {
4271         struct ice_aq_get_set_rss_lut_params lut_params;
4272         struct ice_pf *pf;
4273         struct ice_hw *hw;
4274         int ret;
4275
4276         if (!vsi || !lut)
4277                 return -EINVAL;
4278
4279         pf = ICE_VSI_TO_PF(vsi);
4280         hw = ICE_VSI_TO_HW(vsi);
4281
4282         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4283                 lut_params.vsi_handle = vsi->idx;
4284                 lut_params.lut_size = lut_size;
4285                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4286                 lut_params.lut = lut;
4287                 lut_params.global_lut_id = 0;
4288                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4289                 if (ret) {
4290                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4291                         return -EINVAL;
4292                 }
4293         } else {
4294                 uint64_t *lut_dw = (uint64_t *)lut;
4295                 uint16_t i, lut_size_dw = lut_size / 4;
4296
4297                 for (i = 0; i < lut_size_dw; i++)
4298                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4299
4300                 ice_flush(hw);
4301         }
4302
4303         return 0;
4304 }
4305
4306 static int
4307 ice_rss_reta_update(struct rte_eth_dev *dev,
4308                     struct rte_eth_rss_reta_entry64 *reta_conf,
4309                     uint16_t reta_size)
4310 {
4311         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4312         uint16_t i, lut_size = pf->hash_lut_size;
4313         uint16_t idx, shift;
4314         uint8_t *lut;
4315         int ret;
4316
4317         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4318             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4319             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4320                 PMD_DRV_LOG(ERR,
4321                             "The size of hash lookup table configured (%d)"
4322                             "doesn't match the number hardware can "
4323                             "supported (128, 512, 2048)",
4324                             reta_size);
4325                 return -EINVAL;
4326         }
4327
4328         /* It MUST use the current LUT size to get the RSS lookup table,
4329          * otherwise if will fail with -100 error code.
4330          */
4331         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4332         if (!lut) {
4333                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4334                 return -ENOMEM;
4335         }
4336         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4337         if (ret)
4338                 goto out;
4339
4340         for (i = 0; i < reta_size; i++) {
4341                 idx = i / RTE_RETA_GROUP_SIZE;
4342                 shift = i % RTE_RETA_GROUP_SIZE;
4343                 if (reta_conf[idx].mask & (1ULL << shift))
4344                         lut[i] = reta_conf[idx].reta[shift];
4345         }
4346         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4347         if (ret == 0 && lut_size != reta_size) {
4348                 PMD_DRV_LOG(INFO,
4349                             "The size of hash lookup table is changed from (%d) to (%d)",
4350                             lut_size, reta_size);
4351                 pf->hash_lut_size = reta_size;
4352         }
4353
4354 out:
4355         rte_free(lut);
4356
4357         return ret;
4358 }
4359
4360 static int
4361 ice_rss_reta_query(struct rte_eth_dev *dev,
4362                    struct rte_eth_rss_reta_entry64 *reta_conf,
4363                    uint16_t reta_size)
4364 {
4365         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4366         uint16_t i, lut_size = pf->hash_lut_size;
4367         uint16_t idx, shift;
4368         uint8_t *lut;
4369         int ret;
4370
4371         if (reta_size != lut_size) {
4372                 PMD_DRV_LOG(ERR,
4373                             "The size of hash lookup table configured (%d)"
4374                             "doesn't match the number hardware can "
4375                             "supported (%d)",
4376                             reta_size, lut_size);
4377                 return -EINVAL;
4378         }
4379
4380         lut = rte_zmalloc(NULL, reta_size, 0);
4381         if (!lut) {
4382                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4383                 return -ENOMEM;
4384         }
4385
4386         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4387         if (ret)
4388                 goto out;
4389
4390         for (i = 0; i < reta_size; i++) {
4391                 idx = i / RTE_RETA_GROUP_SIZE;
4392                 shift = i % RTE_RETA_GROUP_SIZE;
4393                 if (reta_conf[idx].mask & (1ULL << shift))
4394                         reta_conf[idx].reta[shift] = lut[i];
4395         }
4396
4397 out:
4398         rte_free(lut);
4399
4400         return ret;
4401 }
4402
4403 static int
4404 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4405 {
4406         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4407         int ret = 0;
4408
4409         if (!key || key_len == 0) {
4410                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4411                 return 0;
4412         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4413                    sizeof(uint32_t)) {
4414                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4415                 return -EINVAL;
4416         }
4417
4418         struct ice_aqc_get_set_rss_keys *key_dw =
4419                 (struct ice_aqc_get_set_rss_keys *)key;
4420
4421         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4422         if (ret) {
4423                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4424                 ret = -EINVAL;
4425         }
4426
4427         return ret;
4428 }
4429
4430 static int
4431 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4432 {
4433         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4434         int ret;
4435
4436         if (!key || !key_len)
4437                 return -EINVAL;
4438
4439         ret = ice_aq_get_rss_key
4440                 (hw, vsi->idx,
4441                  (struct ice_aqc_get_set_rss_keys *)key);
4442         if (ret) {
4443                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4444                 return -EINVAL;
4445         }
4446         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4447
4448         return 0;
4449 }
4450
4451 static int
4452 ice_rss_hash_update(struct rte_eth_dev *dev,
4453                     struct rte_eth_rss_conf *rss_conf)
4454 {
4455         enum ice_status status = ICE_SUCCESS;
4456         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4457         struct ice_vsi *vsi = pf->main_vsi;
4458
4459         /* set hash key */
4460         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4461         if (status)
4462                 return status;
4463
4464         if (rss_conf->rss_hf == 0) {
4465                 pf->rss_hf = 0;
4466                 return 0;
4467         }
4468
4469         /* RSS hash configuration */
4470         ice_rss_hash_set(pf, rss_conf->rss_hf);
4471
4472         return 0;
4473 }
4474
4475 static int
4476 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4477                       struct rte_eth_rss_conf *rss_conf)
4478 {
4479         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4480         struct ice_vsi *vsi = pf->main_vsi;
4481
4482         ice_get_rss_key(vsi, rss_conf->rss_key,
4483                         &rss_conf->rss_key_len);
4484
4485         rss_conf->rss_hf = pf->rss_hf;
4486         return 0;
4487 }
4488
4489 static int
4490 ice_promisc_enable(struct rte_eth_dev *dev)
4491 {
4492         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4493         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4494         struct ice_vsi *vsi = pf->main_vsi;
4495         enum ice_status status;
4496         uint8_t pmask;
4497         int ret = 0;
4498
4499         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4500                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4501
4502         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4503         switch (status) {
4504         case ICE_ERR_ALREADY_EXISTS:
4505                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4506         case ICE_SUCCESS:
4507                 break;
4508         default:
4509                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4510                 ret = -EAGAIN;
4511         }
4512
4513         return ret;
4514 }
4515
4516 static int
4517 ice_promisc_disable(struct rte_eth_dev *dev)
4518 {
4519         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4520         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521         struct ice_vsi *vsi = pf->main_vsi;
4522         enum ice_status status;
4523         uint8_t pmask;
4524         int ret = 0;
4525
4526         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4527                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4528
4529         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4530         if (status != ICE_SUCCESS) {
4531                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4532                 ret = -EAGAIN;
4533         }
4534
4535         return ret;
4536 }
4537
4538 static int
4539 ice_allmulti_enable(struct rte_eth_dev *dev)
4540 {
4541         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4542         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543         struct ice_vsi *vsi = pf->main_vsi;
4544         enum ice_status status;
4545         uint8_t pmask;
4546         int ret = 0;
4547
4548         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4549
4550         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4551
4552         switch (status) {
4553         case ICE_ERR_ALREADY_EXISTS:
4554                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4555         case ICE_SUCCESS:
4556                 break;
4557         default:
4558                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4559                 ret = -EAGAIN;
4560         }
4561
4562         return ret;
4563 }
4564
4565 static int
4566 ice_allmulti_disable(struct rte_eth_dev *dev)
4567 {
4568         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4569         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570         struct ice_vsi *vsi = pf->main_vsi;
4571         enum ice_status status;
4572         uint8_t pmask;
4573         int ret = 0;
4574
4575         if (dev->data->promiscuous == 1)
4576                 return 0; /* must remain in all_multicast mode */
4577
4578         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4579
4580         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4581         if (status != ICE_SUCCESS) {
4582                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4583                 ret = -EAGAIN;
4584         }
4585
4586         return ret;
4587 }
4588
4589 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4590                                     uint16_t queue_id)
4591 {
4592         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4594         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4595         uint32_t val;
4596         uint16_t msix_intr;
4597
4598         msix_intr = intr_handle->intr_vec[queue_id];
4599
4600         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4601               GLINT_DYN_CTL_ITR_INDX_M;
4602         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4603
4604         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4605         rte_intr_ack(&pci_dev->intr_handle);
4606
4607         return 0;
4608 }
4609
4610 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4611                                      uint16_t queue_id)
4612 {
4613         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4614         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4615         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         uint16_t msix_intr;
4617
4618         msix_intr = intr_handle->intr_vec[queue_id];
4619
4620         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4621
4622         return 0;
4623 }
4624
4625 static int
4626 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4627 {
4628         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         u8 ver, patch;
4630         u16 build;
4631         int ret;
4632
4633         ver = hw->flash.orom.major;
4634         patch = hw->flash.orom.patch;
4635         build = hw->flash.orom.build;
4636
4637         ret = snprintf(fw_version, fw_size,
4638                         "%x.%02x 0x%08x %d.%d.%d",
4639                         hw->flash.nvm.major,
4640                         hw->flash.nvm.minor,
4641                         hw->flash.nvm.eetrack,
4642                         ver, build, patch);
4643
4644         /* add the size of '\0' */
4645         ret += 1;
4646         if (fw_size < (u32)ret)
4647                 return ret;
4648         else
4649                 return 0;
4650 }
4651
4652 static int
4653 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4654 {
4655         struct ice_hw *hw;
4656         struct ice_vsi_ctx ctxt;
4657         uint8_t vlan_flags = 0;
4658         int ret;
4659
4660         if (!vsi || !info) {
4661                 PMD_DRV_LOG(ERR, "invalid parameters");
4662                 return -EINVAL;
4663         }
4664
4665         if (info->on) {
4666                 vsi->info.port_based_inner_vlan = info->config.pvid;
4667                 /**
4668                  * If insert pvid is enabled, only tagged pkts are
4669                  * allowed to be sent out.
4670                  */
4671                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4672                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4673         } else {
4674                 vsi->info.port_based_inner_vlan = 0;
4675                 if (info->config.reject.tagged == 0)
4676                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4677
4678                 if (info->config.reject.untagged == 0)
4679                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4680         }
4681         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4682                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4683         vsi->info.inner_vlan_flags |= vlan_flags;
4684         memset(&ctxt, 0, sizeof(ctxt));
4685         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4686         ctxt.info.valid_sections =
4687                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4688         ctxt.vsi_num = vsi->vsi_id;
4689
4690         hw = ICE_VSI_TO_HW(vsi);
4691         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4692         if (ret != ICE_SUCCESS) {
4693                 PMD_DRV_LOG(ERR,
4694                             "update VSI for VLAN insert failed, err %d",
4695                             ret);
4696                 return -EINVAL;
4697         }
4698
4699         vsi->info.valid_sections |=
4700                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4701
4702         return ret;
4703 }
4704
4705 static int
4706 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4707 {
4708         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4709         struct ice_vsi *vsi = pf->main_vsi;
4710         struct rte_eth_dev_data *data = pf->dev_data;
4711         struct ice_vsi_vlan_pvid_info info;
4712         int ret;
4713
4714         memset(&info, 0, sizeof(info));
4715         info.on = on;
4716         if (info.on) {
4717                 info.config.pvid = pvid;
4718         } else {
4719                 info.config.reject.tagged =
4720                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4721                 info.config.reject.untagged =
4722                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4723         }
4724
4725         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4726         if (ret < 0) {
4727                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4728                 return -EINVAL;
4729         }
4730
4731         return 0;
4732 }
4733
4734 static int
4735 ice_get_eeprom_length(struct rte_eth_dev *dev)
4736 {
4737         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4738
4739         return hw->flash.flash_size;
4740 }
4741
4742 static int
4743 ice_get_eeprom(struct rte_eth_dev *dev,
4744                struct rte_dev_eeprom_info *eeprom)
4745 {
4746         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         enum ice_status status = ICE_SUCCESS;
4748         uint8_t *data = eeprom->data;
4749
4750         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4751
4752         status = ice_acquire_nvm(hw, ICE_RES_READ);
4753         if (status) {
4754                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4755                 return -EIO;
4756         }
4757
4758         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4759                                    data, false);
4760
4761         ice_release_nvm(hw);
4762
4763         if (status) {
4764                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4765                 return -EIO;
4766         }
4767
4768         return 0;
4769 }
4770
4771 static void
4772 ice_stat_update_32(struct ice_hw *hw,
4773                    uint32_t reg,
4774                    bool offset_loaded,
4775                    uint64_t *offset,
4776                    uint64_t *stat)
4777 {
4778         uint64_t new_data;
4779
4780         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4781         if (!offset_loaded)
4782                 *offset = new_data;
4783
4784         if (new_data >= *offset)
4785                 *stat = (uint64_t)(new_data - *offset);
4786         else
4787                 *stat = (uint64_t)((new_data +
4788                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4789                                    - *offset);
4790 }
4791
4792 static void
4793 ice_stat_update_40(struct ice_hw *hw,
4794                    uint32_t hireg,
4795                    uint32_t loreg,
4796                    bool offset_loaded,
4797                    uint64_t *offset,
4798                    uint64_t *stat)
4799 {
4800         uint64_t new_data;
4801
4802         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4803         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4804                     ICE_32_BIT_WIDTH;
4805
4806         if (!offset_loaded)
4807                 *offset = new_data;
4808
4809         if (new_data >= *offset)
4810                 *stat = new_data - *offset;
4811         else
4812                 *stat = (uint64_t)((new_data +
4813                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4814                                    *offset);
4815
4816         *stat &= ICE_40_BIT_MASK;
4817 }
4818
4819 /* Get all the statistics of a VSI */
4820 static void
4821 ice_update_vsi_stats(struct ice_vsi *vsi)
4822 {
4823         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4824         struct ice_eth_stats *nes = &vsi->eth_stats;
4825         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4826         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4827
4828         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4829                            vsi->offset_loaded, &oes->rx_bytes,
4830                            &nes->rx_bytes);
4831         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4832                            vsi->offset_loaded, &oes->rx_unicast,
4833                            &nes->rx_unicast);
4834         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4835                            vsi->offset_loaded, &oes->rx_multicast,
4836                            &nes->rx_multicast);
4837         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4838                            vsi->offset_loaded, &oes->rx_broadcast,
4839                            &nes->rx_broadcast);
4840         /* enlarge the limitation when rx_bytes overflowed */
4841         if (vsi->offset_loaded) {
4842                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4843                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4844                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4845         }
4846         vsi->old_rx_bytes = nes->rx_bytes;
4847         /* exclude CRC bytes */
4848         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4849                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4850
4851         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4852                            &oes->rx_discards, &nes->rx_discards);
4853         /* GLV_REPC not supported */
4854         /* GLV_RMPC not supported */
4855         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4856                            &oes->rx_unknown_protocol,
4857                            &nes->rx_unknown_protocol);
4858         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4859                            vsi->offset_loaded, &oes->tx_bytes,
4860                            &nes->tx_bytes);
4861         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4862                            vsi->offset_loaded, &oes->tx_unicast,
4863                            &nes->tx_unicast);
4864         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4865                            vsi->offset_loaded, &oes->tx_multicast,
4866                            &nes->tx_multicast);
4867         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4868                            vsi->offset_loaded,  &oes->tx_broadcast,
4869                            &nes->tx_broadcast);
4870         /* GLV_TDPC not supported */
4871         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4872                            &oes->tx_errors, &nes->tx_errors);
4873         /* enlarge the limitation when tx_bytes overflowed */
4874         if (vsi->offset_loaded) {
4875                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4876                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4877                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4878         }
4879         vsi->old_tx_bytes = nes->tx_bytes;
4880         vsi->offset_loaded = true;
4881
4882         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4883                     vsi->vsi_id);
4884         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4885         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4886         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4887         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4888         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4889         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4890                     nes->rx_unknown_protocol);
4891         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4892         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4893         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4894         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4895         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4896         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4897         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4898                     vsi->vsi_id);
4899 }
4900
4901 static void
4902 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4903 {
4904         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4905         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4906
4907         /* Get statistics of struct ice_eth_stats */
4908         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4909                            GLPRT_GORCL(hw->port_info->lport),
4910                            pf->offset_loaded, &os->eth.rx_bytes,
4911                            &ns->eth.rx_bytes);
4912         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4913                            GLPRT_UPRCL(hw->port_info->lport),
4914                            pf->offset_loaded, &os->eth.rx_unicast,
4915                            &ns->eth.rx_unicast);
4916         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4917                            GLPRT_MPRCL(hw->port_info->lport),
4918                            pf->offset_loaded, &os->eth.rx_multicast,
4919                            &ns->eth.rx_multicast);
4920         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4921                            GLPRT_BPRCL(hw->port_info->lport),
4922                            pf->offset_loaded, &os->eth.rx_broadcast,
4923                            &ns->eth.rx_broadcast);
4924         ice_stat_update_32(hw, PRTRPB_RDPC,
4925                            pf->offset_loaded, &os->eth.rx_discards,
4926                            &ns->eth.rx_discards);
4927         /* enlarge the limitation when rx_bytes overflowed */
4928         if (pf->offset_loaded) {
4929                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4930                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4931                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4932         }
4933         pf->old_rx_bytes = ns->eth.rx_bytes;
4934
4935         /* Workaround: CRC size should not be included in byte statistics,
4936          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4937          * packet.
4938          */
4939         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4940                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4941
4942         /* GLPRT_REPC not supported */
4943         /* GLPRT_RMPC not supported */
4944         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4945                            pf->offset_loaded,
4946                            &os->eth.rx_unknown_protocol,
4947                            &ns->eth.rx_unknown_protocol);
4948         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4949                            GLPRT_GOTCL(hw->port_info->lport),
4950                            pf->offset_loaded, &os->eth.tx_bytes,
4951                            &ns->eth.tx_bytes);
4952         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4953                            GLPRT_UPTCL(hw->port_info->lport),
4954                            pf->offset_loaded, &os->eth.tx_unicast,
4955                            &ns->eth.tx_unicast);
4956         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4957                            GLPRT_MPTCL(hw->port_info->lport),
4958                            pf->offset_loaded, &os->eth.tx_multicast,
4959                            &ns->eth.tx_multicast);
4960         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4961                            GLPRT_BPTCL(hw->port_info->lport),
4962                            pf->offset_loaded, &os->eth.tx_broadcast,
4963                            &ns->eth.tx_broadcast);
4964         /* enlarge the limitation when tx_bytes overflowed */
4965         if (pf->offset_loaded) {
4966                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4967                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4968                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4969         }
4970         pf->old_tx_bytes = ns->eth.tx_bytes;
4971         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4972                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4973
4974         /* GLPRT_TEPC not supported */
4975
4976         /* additional port specific stats */
4977         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4978                            pf->offset_loaded, &os->tx_dropped_link_down,
4979                            &ns->tx_dropped_link_down);
4980         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4981                            pf->offset_loaded, &os->crc_errors,
4982                            &ns->crc_errors);
4983         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4984                            pf->offset_loaded, &os->illegal_bytes,
4985                            &ns->illegal_bytes);
4986         /* GLPRT_ERRBC not supported */
4987         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4988                            pf->offset_loaded, &os->mac_local_faults,
4989                            &ns->mac_local_faults);
4990         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4991                            pf->offset_loaded, &os->mac_remote_faults,
4992                            &ns->mac_remote_faults);
4993
4994         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4995                            pf->offset_loaded, &os->rx_len_errors,
4996                            &ns->rx_len_errors);
4997
4998         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4999                            pf->offset_loaded, &os->link_xon_rx,
5000                            &ns->link_xon_rx);
5001         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
5002                            pf->offset_loaded, &os->link_xoff_rx,
5003                            &ns->link_xoff_rx);
5004         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
5005                            pf->offset_loaded, &os->link_xon_tx,
5006                            &ns->link_xon_tx);
5007         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5008                            pf->offset_loaded, &os->link_xoff_tx,
5009                            &ns->link_xoff_tx);
5010         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5011                            GLPRT_PRC64L(hw->port_info->lport),
5012                            pf->offset_loaded, &os->rx_size_64,
5013                            &ns->rx_size_64);
5014         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5015                            GLPRT_PRC127L(hw->port_info->lport),
5016                            pf->offset_loaded, &os->rx_size_127,
5017                            &ns->rx_size_127);
5018         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5019                            GLPRT_PRC255L(hw->port_info->lport),
5020                            pf->offset_loaded, &os->rx_size_255,
5021                            &ns->rx_size_255);
5022         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5023                            GLPRT_PRC511L(hw->port_info->lport),
5024                            pf->offset_loaded, &os->rx_size_511,
5025                            &ns->rx_size_511);
5026         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5027                            GLPRT_PRC1023L(hw->port_info->lport),
5028                            pf->offset_loaded, &os->rx_size_1023,
5029                            &ns->rx_size_1023);
5030         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5031                            GLPRT_PRC1522L(hw->port_info->lport),
5032                            pf->offset_loaded, &os->rx_size_1522,
5033                            &ns->rx_size_1522);
5034         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5035                            GLPRT_PRC9522L(hw->port_info->lport),
5036                            pf->offset_loaded, &os->rx_size_big,
5037                            &ns->rx_size_big);
5038         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5039                            pf->offset_loaded, &os->rx_undersize,
5040                            &ns->rx_undersize);
5041         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5042                            pf->offset_loaded, &os->rx_fragments,
5043                            &ns->rx_fragments);
5044         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5045                            pf->offset_loaded, &os->rx_oversize,
5046                            &ns->rx_oversize);
5047         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5048                            pf->offset_loaded, &os->rx_jabber,
5049                            &ns->rx_jabber);
5050         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5051                            GLPRT_PTC64L(hw->port_info->lport),
5052                            pf->offset_loaded, &os->tx_size_64,
5053                            &ns->tx_size_64);
5054         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5055                            GLPRT_PTC127L(hw->port_info->lport),
5056                            pf->offset_loaded, &os->tx_size_127,
5057                            &ns->tx_size_127);
5058         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5059                            GLPRT_PTC255L(hw->port_info->lport),
5060                            pf->offset_loaded, &os->tx_size_255,
5061                            &ns->tx_size_255);
5062         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5063                            GLPRT_PTC511L(hw->port_info->lport),
5064                            pf->offset_loaded, &os->tx_size_511,
5065                            &ns->tx_size_511);
5066         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5067                            GLPRT_PTC1023L(hw->port_info->lport),
5068                            pf->offset_loaded, &os->tx_size_1023,
5069                            &ns->tx_size_1023);
5070         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5071                            GLPRT_PTC1522L(hw->port_info->lport),
5072                            pf->offset_loaded, &os->tx_size_1522,
5073                            &ns->tx_size_1522);
5074         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5075                            GLPRT_PTC9522L(hw->port_info->lport),
5076                            pf->offset_loaded, &os->tx_size_big,
5077                            &ns->tx_size_big);
5078
5079         /* GLPRT_MSPDC not supported */
5080         /* GLPRT_XEC not supported */
5081
5082         pf->offset_loaded = true;
5083
5084         if (pf->main_vsi)
5085                 ice_update_vsi_stats(pf->main_vsi);
5086 }
5087
5088 /* Get all statistics of a port */
5089 static int
5090 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5091 {
5092         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5093         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5095
5096         /* call read registers - updates values, now write them to struct */
5097         ice_read_stats_registers(pf, hw);
5098
5099         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5100                           pf->main_vsi->eth_stats.rx_multicast +
5101                           pf->main_vsi->eth_stats.rx_broadcast -
5102                           pf->main_vsi->eth_stats.rx_discards;
5103         stats->opackets = ns->eth.tx_unicast +
5104                           ns->eth.tx_multicast +
5105                           ns->eth.tx_broadcast;
5106         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5107         stats->obytes   = ns->eth.tx_bytes;
5108         stats->oerrors  = ns->eth.tx_errors +
5109                           pf->main_vsi->eth_stats.tx_errors;
5110
5111         /* Rx Errors */
5112         stats->imissed  = ns->eth.rx_discards +
5113                           pf->main_vsi->eth_stats.rx_discards;
5114         stats->ierrors  = ns->crc_errors +
5115                           ns->rx_undersize +
5116                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5117
5118         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5119         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5120         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5121         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5122         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5123         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5124         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5125                     pf->main_vsi->eth_stats.rx_discards);
5126         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5127                     ns->eth.rx_unknown_protocol);
5128         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5129         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5130         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5131         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5132         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5133         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5134                     pf->main_vsi->eth_stats.tx_discards);
5135         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5136
5137         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5138                     ns->tx_dropped_link_down);
5139         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5140         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5141                     ns->illegal_bytes);
5142         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5143         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5144                     ns->mac_local_faults);
5145         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5146                     ns->mac_remote_faults);
5147         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5148         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5149         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5150         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5151         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5152         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5153         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5154         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5155         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5156         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5157         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5158         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5159         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5160         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5161         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5162         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5163         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5164         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5165         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5166         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5167         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5168         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5169         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5170         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5171         return 0;
5172 }
5173
5174 /* Reset the statistics */
5175 static int
5176 ice_stats_reset(struct rte_eth_dev *dev)
5177 {
5178         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5179         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180
5181         /* Mark PF and VSI stats to update the offset, aka "reset" */
5182         pf->offset_loaded = false;
5183         if (pf->main_vsi)
5184                 pf->main_vsi->offset_loaded = false;
5185
5186         /* read the stats, reading current register values into offset */
5187         ice_read_stats_registers(pf, hw);
5188
5189         return 0;
5190 }
5191
5192 static uint32_t
5193 ice_xstats_calc_num(void)
5194 {
5195         uint32_t num;
5196
5197         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5198
5199         return num;
5200 }
5201
5202 static int
5203 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5204                unsigned int n)
5205 {
5206         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5207         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5208         unsigned int i;
5209         unsigned int count;
5210         struct ice_hw_port_stats *hw_stats = &pf->stats;
5211
5212         count = ice_xstats_calc_num();
5213         if (n < count)
5214                 return count;
5215
5216         ice_read_stats_registers(pf, hw);
5217
5218         if (!xstats)
5219                 return 0;
5220
5221         count = 0;
5222
5223         /* Get stats from ice_eth_stats struct */
5224         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5225                 xstats[count].value =
5226                         *(uint64_t *)((char *)&hw_stats->eth +
5227                                       ice_stats_strings[i].offset);
5228                 xstats[count].id = count;
5229                 count++;
5230         }
5231
5232         /* Get individiual stats from ice_hw_port struct */
5233         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5234                 xstats[count].value =
5235                         *(uint64_t *)((char *)hw_stats +
5236                                       ice_hw_port_strings[i].offset);
5237                 xstats[count].id = count;
5238                 count++;
5239         }
5240
5241         return count;
5242 }
5243
5244 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5245                                 struct rte_eth_xstat_name *xstats_names,
5246                                 __rte_unused unsigned int limit)
5247 {
5248         unsigned int count = 0;
5249         unsigned int i;
5250
5251         if (!xstats_names)
5252                 return ice_xstats_calc_num();
5253
5254         /* Note: limit checked in rte_eth_xstats_names() */
5255
5256         /* Get stats from ice_eth_stats struct */
5257         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5258                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5259                         sizeof(xstats_names[count].name));
5260                 count++;
5261         }
5262
5263         /* Get individiual stats from ice_hw_port struct */
5264         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5265                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5266                         sizeof(xstats_names[count].name));
5267                 count++;
5268         }
5269
5270         return count;
5271 }
5272
5273 static int
5274 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5275                      const struct rte_flow_ops **ops)
5276 {
5277         if (!dev)
5278                 return -EINVAL;
5279
5280         *ops = &ice_flow_ops;
5281         return 0;
5282 }
5283
5284 /* Add UDP tunneling port */
5285 static int
5286 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5287                              struct rte_eth_udp_tunnel *udp_tunnel)
5288 {
5289         int ret = 0;
5290         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291
5292         if (udp_tunnel == NULL)
5293                 return -EINVAL;
5294
5295         switch (udp_tunnel->prot_type) {
5296         case RTE_TUNNEL_TYPE_VXLAN:
5297                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5298                 break;
5299         default:
5300                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5301                 ret = -EINVAL;
5302                 break;
5303         }
5304
5305         return ret;
5306 }
5307
5308 /* Delete UDP tunneling port */
5309 static int
5310 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5311                              struct rte_eth_udp_tunnel *udp_tunnel)
5312 {
5313         int ret = 0;
5314         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5315
5316         if (udp_tunnel == NULL)
5317                 return -EINVAL;
5318
5319         switch (udp_tunnel->prot_type) {
5320         case RTE_TUNNEL_TYPE_VXLAN:
5321                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5322                 break;
5323         default:
5324                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5325                 ret = -EINVAL;
5326                 break;
5327         }
5328
5329         return ret;
5330 }
5331
5332 static int
5333 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5334               struct rte_pci_device *pci_dev)
5335 {
5336         return rte_eth_dev_pci_generic_probe(pci_dev,
5337                                              sizeof(struct ice_adapter),
5338                                              ice_dev_init);
5339 }
5340
5341 static int
5342 ice_pci_remove(struct rte_pci_device *pci_dev)
5343 {
5344         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5345 }
5346
5347 static struct rte_pci_driver rte_ice_pmd = {
5348         .id_table = pci_id_ice_map,
5349         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5350         .probe = ice_pci_probe,
5351         .remove = ice_pci_remove,
5352 };
5353
5354 /**
5355  * Driver initialization routine.
5356  * Invoked once at EAL init time.
5357  * Register itself as the [Poll Mode] Driver of PCI devices.
5358  */
5359 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5360 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5361 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5362 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5363                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5364                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5365                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5366
5367 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5368 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5369 #ifdef RTE_ETHDEV_DEBUG_RX
5370 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5371 #endif
5372 #ifdef RTE_ETHDEV_DEBUG_TX
5373 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5374 #endif