1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support"
27 #define ICE_PROTO_XTR_ARG "proto_xtr"
29 static const char * const ice_valid_args[] = {
30 ICE_SAFE_MODE_SUPPORT_ARG,
31 ICE_PIPELINE_MODE_SUPPORT_ARG,
32 ICE_FLOW_MARK_SUPPORT_ARG,
37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
38 .name = "ice_dynfield_proto_xtr_metadata",
39 .size = sizeof(uint32_t),
40 .align = __alignof__(uint32_t),
44 struct proto_xtr_ol_flag {
45 const struct rte_mbuf_dynflag param;
50 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
52 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
54 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
55 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
57 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
58 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
60 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
61 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
62 [PROTO_XTR_IPV6_FLOW] = {
63 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
64 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
66 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
67 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
70 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
72 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
73 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
74 #define ICE_MAX_RES_DESC_NUM 1024
76 static int ice_dev_configure(struct rte_eth_dev *dev);
77 static int ice_dev_start(struct rte_eth_dev *dev);
78 static void ice_dev_stop(struct rte_eth_dev *dev);
79 static void ice_dev_close(struct rte_eth_dev *dev);
80 static int ice_dev_reset(struct rte_eth_dev *dev);
81 static int ice_dev_info_get(struct rte_eth_dev *dev,
82 struct rte_eth_dev_info *dev_info);
83 static int ice_link_update(struct rte_eth_dev *dev,
84 int wait_to_complete);
85 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
86 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
88 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
89 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
90 static int ice_rss_reta_update(struct rte_eth_dev *dev,
91 struct rte_eth_rss_reta_entry64 *reta_conf,
93 static int ice_rss_reta_query(struct rte_eth_dev *dev,
94 struct rte_eth_rss_reta_entry64 *reta_conf,
96 static int ice_rss_hash_update(struct rte_eth_dev *dev,
97 struct rte_eth_rss_conf *rss_conf);
98 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
99 struct rte_eth_rss_conf *rss_conf);
100 static int ice_promisc_enable(struct rte_eth_dev *dev);
101 static int ice_promisc_disable(struct rte_eth_dev *dev);
102 static int ice_allmulti_enable(struct rte_eth_dev *dev);
103 static int ice_allmulti_disable(struct rte_eth_dev *dev);
104 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
107 static int ice_macaddr_set(struct rte_eth_dev *dev,
108 struct rte_ether_addr *mac_addr);
109 static int ice_macaddr_add(struct rte_eth_dev *dev,
110 struct rte_ether_addr *mac_addr,
111 __rte_unused uint32_t index,
113 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
114 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
116 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
118 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
120 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
121 uint16_t pvid, int on);
122 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
123 static int ice_get_eeprom(struct rte_eth_dev *dev,
124 struct rte_dev_eeprom_info *eeprom);
125 static int ice_stats_get(struct rte_eth_dev *dev,
126 struct rte_eth_stats *stats);
127 static int ice_stats_reset(struct rte_eth_dev *dev);
128 static int ice_xstats_get(struct rte_eth_dev *dev,
129 struct rte_eth_xstat *xstats, unsigned int n);
130 static int ice_xstats_get_names(struct rte_eth_dev *dev,
131 struct rte_eth_xstat_name *xstats_names,
133 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
134 enum rte_filter_type filter_type,
135 enum rte_filter_op filter_op,
137 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
138 struct rte_eth_udp_tunnel *udp_tunnel);
139 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
140 struct rte_eth_udp_tunnel *udp_tunnel);
142 static const struct rte_pci_id pci_id_ice_map[] = {
143 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
144 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
145 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
146 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
147 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
148 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
149 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
150 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
151 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
152 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
153 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
154 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
155 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
156 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
157 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
158 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
159 { .vendor_id = 0, /* sentinel */ },
162 static const struct eth_dev_ops ice_eth_dev_ops = {
163 .dev_configure = ice_dev_configure,
164 .dev_start = ice_dev_start,
165 .dev_stop = ice_dev_stop,
166 .dev_close = ice_dev_close,
167 .dev_reset = ice_dev_reset,
168 .dev_set_link_up = ice_dev_set_link_up,
169 .dev_set_link_down = ice_dev_set_link_down,
170 .rx_queue_start = ice_rx_queue_start,
171 .rx_queue_stop = ice_rx_queue_stop,
172 .tx_queue_start = ice_tx_queue_start,
173 .tx_queue_stop = ice_tx_queue_stop,
174 .rx_queue_setup = ice_rx_queue_setup,
175 .rx_queue_release = ice_rx_queue_release,
176 .tx_queue_setup = ice_tx_queue_setup,
177 .tx_queue_release = ice_tx_queue_release,
178 .dev_infos_get = ice_dev_info_get,
179 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
180 .link_update = ice_link_update,
181 .mtu_set = ice_mtu_set,
182 .mac_addr_set = ice_macaddr_set,
183 .mac_addr_add = ice_macaddr_add,
184 .mac_addr_remove = ice_macaddr_remove,
185 .vlan_filter_set = ice_vlan_filter_set,
186 .vlan_offload_set = ice_vlan_offload_set,
187 .reta_update = ice_rss_reta_update,
188 .reta_query = ice_rss_reta_query,
189 .rss_hash_update = ice_rss_hash_update,
190 .rss_hash_conf_get = ice_rss_hash_conf_get,
191 .promiscuous_enable = ice_promisc_enable,
192 .promiscuous_disable = ice_promisc_disable,
193 .allmulticast_enable = ice_allmulti_enable,
194 .allmulticast_disable = ice_allmulti_disable,
195 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
196 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
197 .fw_version_get = ice_fw_version_get,
198 .vlan_pvid_set = ice_vlan_pvid_set,
199 .rxq_info_get = ice_rxq_info_get,
200 .txq_info_get = ice_txq_info_get,
201 .rx_burst_mode_get = ice_rx_burst_mode_get,
202 .tx_burst_mode_get = ice_tx_burst_mode_get,
203 .get_eeprom_length = ice_get_eeprom_length,
204 .get_eeprom = ice_get_eeprom,
205 .rx_queue_count = ice_rx_queue_count,
206 .rx_descriptor_status = ice_rx_descriptor_status,
207 .tx_descriptor_status = ice_tx_descriptor_status,
208 .stats_get = ice_stats_get,
209 .stats_reset = ice_stats_reset,
210 .xstats_get = ice_xstats_get,
211 .xstats_get_names = ice_xstats_get_names,
212 .xstats_reset = ice_stats_reset,
213 .filter_ctrl = ice_dev_filter_ctrl,
214 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
215 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
216 .tx_done_cleanup = ice_tx_done_cleanup,
219 /* store statistics names and its offset in stats structure */
220 struct ice_xstats_name_off {
221 char name[RTE_ETH_XSTATS_NAME_SIZE];
225 static const struct ice_xstats_name_off ice_stats_strings[] = {
226 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
227 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
228 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
229 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
230 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
231 rx_unknown_protocol)},
232 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
233 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
234 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
235 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
238 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
239 sizeof(ice_stats_strings[0]))
241 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
242 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
243 tx_dropped_link_down)},
244 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
245 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
247 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
248 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
250 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
252 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
254 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
255 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
256 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
257 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
258 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
259 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
261 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
263 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
265 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
267 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
273 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
275 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
276 mac_short_pkt_dropped)},
277 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
279 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
280 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
281 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
283 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
285 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
287 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
289 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
295 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
296 sizeof(ice_hw_port_strings[0]))
299 ice_init_controlq_parameter(struct ice_hw *hw)
301 /* fields for adminq */
302 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
303 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
304 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
305 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
307 /* fields for mailboxq, DPDK used as PF host */
308 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
309 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
310 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
311 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
315 lookup_proto_xtr_type(const char *xtr_name)
319 enum proto_xtr_type type;
321 { "vlan", PROTO_XTR_VLAN },
322 { "ipv4", PROTO_XTR_IPV4 },
323 { "ipv6", PROTO_XTR_IPV6 },
324 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
325 { "tcp", PROTO_XTR_TCP },
329 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
330 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
331 return xtr_type_map[i].type;
338 * Parse elem, the elem could be single number/range or '(' ')' group
339 * 1) A single number elem, it's just a simple digit. e.g. 9
340 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
341 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
342 * Within group elem, '-' used for a range separator;
343 * ',' used for a single number.
346 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
348 const char *str = input;
353 while (isblank(*str))
356 if (!isdigit(*str) && *str != '(')
359 /* process single number or single range of number */
362 idx = strtoul(str, &end, 10);
363 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
366 while (isblank(*end))
372 /* process single <number>-<number> */
375 while (isblank(*end))
381 idx = strtoul(end, &end, 10);
382 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
386 while (isblank(*end))
393 for (idx = RTE_MIN(min, max);
394 idx <= RTE_MAX(min, max); idx++)
395 devargs->proto_xtr[idx] = xtr_type;
400 /* process set within bracket */
402 while (isblank(*str))
407 min = ICE_MAX_QUEUE_NUM;
409 /* go ahead to the first digit */
410 while (isblank(*str))
415 /* get the digit value */
417 idx = strtoul(str, &end, 10);
418 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
421 /* go ahead to separator '-',',' and ')' */
422 while (isblank(*end))
425 if (min == ICE_MAX_QUEUE_NUM)
427 else /* avoid continuous '-' */
429 } else if (*end == ',' || *end == ')') {
431 if (min == ICE_MAX_QUEUE_NUM)
434 for (idx = RTE_MIN(min, max);
435 idx <= RTE_MAX(min, max); idx++)
436 devargs->proto_xtr[idx] = xtr_type;
438 min = ICE_MAX_QUEUE_NUM;
444 } while (*end != ')' && *end != '\0');
450 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
452 const char *queue_start;
457 while (isblank(*queues))
460 if (*queues != '[') {
461 xtr_type = lookup_proto_xtr_type(queues);
465 devargs->proto_xtr_dflt = xtr_type;
472 while (isblank(*queues))
477 queue_start = queues;
479 /* go across a complete bracket */
480 if (*queue_start == '(') {
481 queues += strcspn(queues, ")");
486 /* scan the separator ':' */
487 queues += strcspn(queues, ":");
488 if (*queues++ != ':')
490 while (isblank(*queues))
493 for (idx = 0; ; idx++) {
494 if (isblank(queues[idx]) ||
495 queues[idx] == ',' ||
496 queues[idx] == ']' ||
500 if (idx > sizeof(xtr_name) - 2)
503 xtr_name[idx] = queues[idx];
505 xtr_name[idx] = '\0';
506 xtr_type = lookup_proto_xtr_type(xtr_name);
512 while (isblank(*queues) || *queues == ',' || *queues == ']')
515 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
517 } while (*queues != '\0');
523 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
526 struct ice_devargs *devargs = extra_args;
528 if (value == NULL || extra_args == NULL)
531 if (parse_queue_proto_xtr(value, devargs) < 0) {
533 "The protocol extraction parameter is wrong : '%s'",
542 ice_check_proto_xtr_support(struct ice_hw *hw)
544 #define FLX_REG(val, fld, idx) \
545 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
546 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
553 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
555 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
556 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
558 ICE_PROT_IPV4_OF_OR_S,
559 ICE_PROT_IPV4_OF_OR_S },
560 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
562 ICE_PROT_IPV6_OF_OR_S,
563 ICE_PROT_IPV6_OF_OR_S },
564 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
566 ICE_PROT_IPV6_OF_OR_S,
567 ICE_PROT_IPV6_OF_OR_S },
568 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
570 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
574 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
575 uint32_t rxdid = xtr_sets[i].rxdid;
578 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
579 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
581 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
582 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
583 ice_proto_xtr_hw_support[i] = true;
586 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
587 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
589 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
590 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
591 ice_proto_xtr_hw_support[i] = true;
597 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
600 struct pool_entry *entry;
605 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
608 "Failed to allocate memory for resource pool");
612 /* queue heap initialize */
613 pool->num_free = num;
616 LIST_INIT(&pool->alloc_list);
617 LIST_INIT(&pool->free_list);
619 /* Initialize element */
623 LIST_INSERT_HEAD(&pool->free_list, entry, next);
628 ice_res_pool_alloc(struct ice_res_pool_info *pool,
631 struct pool_entry *entry, *valid_entry;
634 PMD_INIT_LOG(ERR, "Invalid parameter");
638 if (pool->num_free < num) {
639 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
640 num, pool->num_free);
645 /* Lookup in free list and find most fit one */
646 LIST_FOREACH(entry, &pool->free_list, next) {
647 if (entry->len >= num) {
649 if (entry->len == num) {
654 valid_entry->len > entry->len)
659 /* Not find one to satisfy the request, return */
661 PMD_INIT_LOG(ERR, "No valid entry found");
665 * The entry have equal queue number as requested,
666 * remove it from alloc_list.
668 if (valid_entry->len == num) {
669 LIST_REMOVE(valid_entry, next);
672 * The entry have more numbers than requested,
673 * create a new entry for alloc_list and minus its
674 * queue base and number in free_list.
676 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
679 "Failed to allocate memory for "
683 entry->base = valid_entry->base;
685 valid_entry->base += num;
686 valid_entry->len -= num;
690 /* Insert it into alloc list, not sorted */
691 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
693 pool->num_free -= valid_entry->len;
694 pool->num_alloc += valid_entry->len;
696 return valid_entry->base + pool->base;
700 ice_res_pool_destroy(struct ice_res_pool_info *pool)
702 struct pool_entry *entry, *next_entry;
707 for (entry = LIST_FIRST(&pool->alloc_list);
708 entry && (next_entry = LIST_NEXT(entry, next), 1);
709 entry = next_entry) {
710 LIST_REMOVE(entry, next);
714 for (entry = LIST_FIRST(&pool->free_list);
715 entry && (next_entry = LIST_NEXT(entry, next), 1);
716 entry = next_entry) {
717 LIST_REMOVE(entry, next);
724 LIST_INIT(&pool->alloc_list);
725 LIST_INIT(&pool->free_list);
729 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
731 /* Set VSI LUT selection */
732 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
733 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
734 /* Set Hash scheme */
735 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
736 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
738 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
741 static enum ice_status
742 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
743 struct ice_aqc_vsi_props *info,
744 uint8_t enabled_tcmap)
746 uint16_t bsf, qp_idx;
748 /* default tc 0 now. Multi-TC supporting need to be done later.
749 * Configure TC and queue mapping parameters, for enabled TC,
750 * allocate qpnum_per_tc queues to this traffic.
752 if (enabled_tcmap != 0x01) {
753 PMD_INIT_LOG(ERR, "only TC0 is supported");
757 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
758 bsf = rte_bsf32(vsi->nb_qps);
759 /* Adjust the queue number to actual queues that can be applied */
760 vsi->nb_qps = 0x1 << bsf;
763 /* Set tc and queue mapping with VSI */
764 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
765 ICE_AQ_VSI_TC_Q_OFFSET_S) |
766 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
768 /* Associate queue number with VSI */
769 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
770 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
771 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
772 info->valid_sections |=
773 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
774 /* Set the info.ingress_table and info.egress_table
775 * for UP translate table. Now just set it to 1:1 map by default
776 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
778 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
779 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
780 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
781 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
786 ice_init_mac_address(struct rte_eth_dev *dev)
788 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
790 if (!rte_is_unicast_ether_addr
791 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
792 PMD_INIT_LOG(ERR, "Invalid MAC address");
797 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
798 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
800 dev->data->mac_addrs =
801 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
802 if (!dev->data->mac_addrs) {
804 "Failed to allocate memory to store mac address");
807 /* store it to dev data */
809 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
810 &dev->data->mac_addrs[0]);
814 /* Find out specific MAC filter */
815 static struct ice_mac_filter *
816 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
818 struct ice_mac_filter *f;
820 TAILQ_FOREACH(f, &vsi->mac_list, next) {
821 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
829 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
831 struct ice_fltr_list_entry *m_list_itr = NULL;
832 struct ice_mac_filter *f;
833 struct LIST_HEAD_TYPE list_head;
834 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
837 /* If it's added and configured, return */
838 f = ice_find_mac_filter(vsi, mac_addr);
840 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
844 INIT_LIST_HEAD(&list_head);
846 m_list_itr = (struct ice_fltr_list_entry *)
847 ice_malloc(hw, sizeof(*m_list_itr));
852 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
853 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
854 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
855 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
856 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
857 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
858 m_list_itr->fltr_info.vsi_handle = vsi->idx;
860 LIST_ADD(&m_list_itr->list_entry, &list_head);
863 ret = ice_add_mac(hw, &list_head);
864 if (ret != ICE_SUCCESS) {
865 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
869 /* Add the mac addr into mac list */
870 f = rte_zmalloc(NULL, sizeof(*f), 0);
872 PMD_DRV_LOG(ERR, "failed to allocate memory");
876 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
877 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
883 rte_free(m_list_itr);
888 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
890 struct ice_fltr_list_entry *m_list_itr = NULL;
891 struct ice_mac_filter *f;
892 struct LIST_HEAD_TYPE list_head;
893 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
896 /* Can't find it, return an error */
897 f = ice_find_mac_filter(vsi, mac_addr);
901 INIT_LIST_HEAD(&list_head);
903 m_list_itr = (struct ice_fltr_list_entry *)
904 ice_malloc(hw, sizeof(*m_list_itr));
909 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
910 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
911 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
912 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
913 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
914 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
915 m_list_itr->fltr_info.vsi_handle = vsi->idx;
917 LIST_ADD(&m_list_itr->list_entry, &list_head);
919 /* remove the mac filter */
920 ret = ice_remove_mac(hw, &list_head);
921 if (ret != ICE_SUCCESS) {
922 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
927 /* Remove the mac addr from mac list */
928 TAILQ_REMOVE(&vsi->mac_list, f, next);
934 rte_free(m_list_itr);
938 /* Find out specific VLAN filter */
939 static struct ice_vlan_filter *
940 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
942 struct ice_vlan_filter *f;
944 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
945 if (vlan_id == f->vlan_info.vlan_id)
953 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
955 struct ice_fltr_list_entry *v_list_itr = NULL;
956 struct ice_vlan_filter *f;
957 struct LIST_HEAD_TYPE list_head;
961 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
964 hw = ICE_VSI_TO_HW(vsi);
966 /* If it's added and configured, return. */
967 f = ice_find_vlan_filter(vsi, vlan_id);
969 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
973 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
976 INIT_LIST_HEAD(&list_head);
978 v_list_itr = (struct ice_fltr_list_entry *)
979 ice_malloc(hw, sizeof(*v_list_itr));
984 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
985 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
986 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
987 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
988 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
989 v_list_itr->fltr_info.vsi_handle = vsi->idx;
991 LIST_ADD(&v_list_itr->list_entry, &list_head);
994 ret = ice_add_vlan(hw, &list_head);
995 if (ret != ICE_SUCCESS) {
996 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1001 /* Add vlan into vlan list */
1002 f = rte_zmalloc(NULL, sizeof(*f), 0);
1004 PMD_DRV_LOG(ERR, "failed to allocate memory");
1008 f->vlan_info.vlan_id = vlan_id;
1009 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1015 rte_free(v_list_itr);
1020 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1022 struct ice_fltr_list_entry *v_list_itr = NULL;
1023 struct ice_vlan_filter *f;
1024 struct LIST_HEAD_TYPE list_head;
1029 * Vlan 0 is the generic filter for untagged packets
1030 * and can't be removed.
1032 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1035 hw = ICE_VSI_TO_HW(vsi);
1037 /* Can't find it, return an error */
1038 f = ice_find_vlan_filter(vsi, vlan_id);
1042 INIT_LIST_HEAD(&list_head);
1044 v_list_itr = (struct ice_fltr_list_entry *)
1045 ice_malloc(hw, sizeof(*v_list_itr));
1051 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1052 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1053 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1054 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1055 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1056 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1058 LIST_ADD(&v_list_itr->list_entry, &list_head);
1060 /* remove the vlan filter */
1061 ret = ice_remove_vlan(hw, &list_head);
1062 if (ret != ICE_SUCCESS) {
1063 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1068 /* Remove the vlan id from vlan list */
1069 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1075 rte_free(v_list_itr);
1080 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1082 struct ice_mac_filter *m_f;
1083 struct ice_vlan_filter *v_f;
1086 if (!vsi || !vsi->mac_num)
1089 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1090 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1091 if (ret != ICE_SUCCESS) {
1097 if (vsi->vlan_num == 0)
1100 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1101 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1102 if (ret != ICE_SUCCESS) {
1113 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1115 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1116 struct ice_vsi_ctx ctxt;
1120 /* Check if it has been already on or off */
1121 if (vsi->info.valid_sections &
1122 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1124 if ((vsi->info.outer_tag_flags &
1125 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1126 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1127 return 0; /* already on */
1129 if (!(vsi->info.outer_tag_flags &
1130 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1131 return 0; /* already off */
1136 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1139 /* clear global insertion and use per packet insertion */
1140 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1141 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1142 vsi->info.outer_tag_flags |= qinq_flags;
1143 /* use default vlan type 0x8100 */
1144 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1145 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1146 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1147 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1148 ctxt.info.valid_sections =
1149 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1150 ctxt.vsi_num = vsi->vsi_id;
1151 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1154 "Update VSI failed to %s qinq stripping",
1155 on ? "enable" : "disable");
1159 vsi->info.valid_sections |=
1160 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1166 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1168 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1169 struct ice_vsi_ctx ctxt;
1173 /* Check if it has been already on or off */
1174 if (vsi->info.valid_sections &
1175 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1177 if ((vsi->info.outer_tag_flags &
1178 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1179 ICE_AQ_VSI_OUTER_TAG_COPY)
1180 return 0; /* already on */
1182 if ((vsi->info.outer_tag_flags &
1183 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1184 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1185 return 0; /* already off */
1190 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1192 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1193 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1194 vsi->info.outer_tag_flags |= qinq_flags;
1195 /* use default vlan type 0x8100 */
1196 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1197 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1198 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1199 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1200 ctxt.info.valid_sections =
1201 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1202 ctxt.vsi_num = vsi->vsi_id;
1203 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1206 "Update VSI failed to %s qinq stripping",
1207 on ? "enable" : "disable");
1211 vsi->info.valid_sections |=
1212 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1218 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1222 ret = ice_vsi_config_qinq_stripping(vsi, on);
1224 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1226 ret = ice_vsi_config_qinq_insertion(vsi, on);
1228 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1235 ice_pf_enable_irq0(struct ice_hw *hw)
1237 /* reset the registers */
1238 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1239 ICE_READ_REG(hw, PFINT_OICR);
1242 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1243 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1244 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1246 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1247 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1248 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1249 PFINT_OICR_CTL_ITR_INDX_M) |
1250 PFINT_OICR_CTL_CAUSE_ENA_M);
1252 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1253 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1254 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1255 PFINT_FW_CTL_ITR_INDX_M) |
1256 PFINT_FW_CTL_CAUSE_ENA_M);
1258 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1261 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1262 GLINT_DYN_CTL_INTENA_M |
1263 GLINT_DYN_CTL_CLEARPBA_M |
1264 GLINT_DYN_CTL_ITR_INDX_M);
1271 ice_pf_disable_irq0(struct ice_hw *hw)
1273 /* Disable all interrupt types */
1274 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1280 ice_handle_aq_msg(struct rte_eth_dev *dev)
1282 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283 struct ice_ctl_q_info *cq = &hw->adminq;
1284 struct ice_rq_event_info event;
1285 uint16_t pending, opcode;
1288 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1289 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1290 if (!event.msg_buf) {
1291 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1297 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1299 if (ret != ICE_SUCCESS) {
1301 "Failed to read msg from AdminQ, "
1303 hw->adminq.sq_last_status);
1306 opcode = rte_le_to_cpu_16(event.desc.opcode);
1309 case ice_aqc_opc_get_link_status:
1310 ret = ice_link_update(dev, 0);
1312 _rte_eth_dev_callback_process
1313 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1316 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1321 rte_free(event.msg_buf);
1326 * Interrupt handler triggered by NIC for handling
1327 * specific interrupt.
1330 * Pointer to interrupt handle.
1332 * The address of parameter (struct rte_eth_dev *) regsitered before.
1338 ice_interrupt_handler(void *param)
1340 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1341 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 uint32_t int_fw_ctl;
1352 /* Disable interrupt */
1353 ice_pf_disable_irq0(hw);
1355 /* read out interrupt causes */
1356 oicr = ICE_READ_REG(hw, PFINT_OICR);
1358 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1361 /* No interrupt event indicated */
1362 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1363 PMD_DRV_LOG(INFO, "No interrupt event");
1368 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1369 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1370 ice_handle_aq_msg(dev);
1373 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1374 PMD_DRV_LOG(INFO, "OICR: link state change event");
1375 ret = ice_link_update(dev, 0);
1377 _rte_eth_dev_callback_process
1378 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1382 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1383 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1384 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1385 if (reg & GL_MDET_TX_PQM_VALID_M) {
1386 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1387 GL_MDET_TX_PQM_PF_NUM_S;
1388 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1389 GL_MDET_TX_PQM_MAL_TYPE_S;
1390 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1391 GL_MDET_TX_PQM_QNUM_S;
1393 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1394 "%d by PQM on TX queue %d PF# %d",
1395 event, queue, pf_num);
1398 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1399 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1400 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1401 GL_MDET_TX_TCLAN_PF_NUM_S;
1402 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1403 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1404 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1405 GL_MDET_TX_TCLAN_QNUM_S;
1407 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1408 "%d by TCLAN on TX queue %d PF# %d",
1409 event, queue, pf_num);
1413 /* Enable interrupt */
1414 ice_pf_enable_irq0(hw);
1415 rte_intr_ack(dev->intr_handle);
1419 ice_init_proto_xtr(struct rte_eth_dev *dev)
1421 struct ice_adapter *ad =
1422 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1423 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1424 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1425 const struct proto_xtr_ol_flag *ol_flag;
1426 bool proto_xtr_enable = false;
1430 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1431 if (unlikely(pf->proto_xtr == NULL)) {
1432 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1436 for (i = 0; i < pf->lan_nb_qps; i++) {
1437 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1438 ad->devargs.proto_xtr[i] :
1439 ad->devargs.proto_xtr_dflt;
1441 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1442 uint8_t type = pf->proto_xtr[i];
1444 ice_proto_xtr_ol_flag_params[type].required = true;
1445 proto_xtr_enable = true;
1449 if (likely(!proto_xtr_enable))
1452 ice_check_proto_xtr_support(hw);
1454 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1455 if (unlikely(offset == -1)) {
1457 "Protocol extraction metadata is disabled in mbuf with error %d",
1463 "Protocol extraction metadata offset in mbuf is : %d",
1465 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1467 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1468 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1470 if (!ol_flag->required)
1473 if (!ice_proto_xtr_hw_support[i]) {
1475 "Protocol extraction type %u is not supported in hardware",
1477 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1481 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1482 if (unlikely(offset == -1)) {
1484 "Protocol extraction offload '%s' failed to register with error %d",
1485 ol_flag->param.name, -rte_errno);
1487 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1492 "Protocol extraction offload '%s' offset in mbuf is : %d",
1493 ol_flag->param.name, offset);
1494 *ol_flag->ol_flag = 1ULL << offset;
1498 /* Initialize SW parameters of PF */
1500 ice_pf_sw_init(struct rte_eth_dev *dev)
1502 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1503 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1506 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1507 hw->func_caps.common_cap.num_rxq);
1509 pf->lan_nb_qps = pf->lan_nb_qp_max;
1511 ice_init_proto_xtr(dev);
1513 if (hw->func_caps.fd_fltr_guar > 0 ||
1514 hw->func_caps.fd_fltr_best_effort > 0) {
1515 pf->flags |= ICE_FLAG_FDIR;
1516 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1517 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1519 pf->fdir_nb_qps = 0;
1521 pf->fdir_qp_offset = 0;
1527 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1529 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1530 struct ice_vsi *vsi = NULL;
1531 struct ice_vsi_ctx vsi_ctx;
1533 struct rte_ether_addr broadcast = {
1534 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1535 struct rte_ether_addr mac_addr;
1536 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1537 uint8_t tc_bitmap = 0x1;
1540 /* hw->num_lports = 1 in NIC mode */
1541 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1545 vsi->idx = pf->next_vsi_idx;
1548 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1549 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1550 vsi->vlan_anti_spoof_on = 0;
1551 vsi->vlan_filter_on = 1;
1552 TAILQ_INIT(&vsi->mac_list);
1553 TAILQ_INIT(&vsi->vlan_list);
1555 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1556 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1557 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1558 hw->func_caps.common_cap.rss_table_size;
1559 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1561 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1564 vsi->nb_qps = pf->lan_nb_qps;
1565 vsi->base_queue = 1;
1566 ice_vsi_config_default_rss(&vsi_ctx.info);
1567 vsi_ctx.alloc_from_pool = true;
1568 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1569 /* switch_id is queried by get_switch_config aq, which is done
1572 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1573 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1574 /* Allow all untagged or tagged packets */
1575 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1576 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1577 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1578 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1581 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1582 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1583 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1584 cfg = ICE_AQ_VSI_FD_ENABLE;
1585 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1586 vsi_ctx.info.max_fd_fltr_dedicated =
1587 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1588 vsi_ctx.info.max_fd_fltr_shared =
1589 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1591 /* Enable VLAN/UP trip */
1592 ret = ice_vsi_config_tc_queue_mapping(vsi,
1597 "tc queue mapping with vsi failed, "
1605 vsi->nb_qps = pf->fdir_nb_qps;
1606 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1607 vsi_ctx.alloc_from_pool = true;
1608 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1610 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1611 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1612 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1613 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1614 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1615 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1616 ret = ice_vsi_config_tc_queue_mapping(vsi,
1621 "tc queue mapping with vsi failed, "
1628 /* for other types of VSI */
1629 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1633 /* VF has MSIX interrupt in VF range, don't allocate here */
1634 if (type == ICE_VSI_PF) {
1635 ret = ice_res_pool_alloc(&pf->msix_pool,
1636 RTE_MIN(vsi->nb_qps,
1637 RTE_MAX_RXTX_INTR_VEC_ID));
1639 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1642 vsi->msix_intr = ret;
1643 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1644 } else if (type == ICE_VSI_CTRL) {
1645 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1647 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1650 vsi->msix_intr = ret;
1656 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1657 if (ret != ICE_SUCCESS) {
1658 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1661 /* store vsi information is SW structure */
1662 vsi->vsi_id = vsi_ctx.vsi_num;
1663 vsi->info = vsi_ctx.info;
1664 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1665 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1667 if (type == ICE_VSI_PF) {
1668 /* MAC configuration */
1669 rte_ether_addr_copy((struct rte_ether_addr *)
1670 hw->port_info->mac.perm_addr,
1673 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1674 ret = ice_add_mac_filter(vsi, &mac_addr);
1675 if (ret != ICE_SUCCESS)
1676 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1678 rte_ether_addr_copy(&broadcast, &mac_addr);
1679 ret = ice_add_mac_filter(vsi, &mac_addr);
1680 if (ret != ICE_SUCCESS)
1681 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1684 /* At the beginning, only TC0. */
1685 /* What we need here is the maximam number of the TX queues.
1686 * Currently vsi->nb_qps means it.
1687 * Correct it if any change.
1689 max_txqs[0] = vsi->nb_qps;
1690 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1691 tc_bitmap, max_txqs);
1692 if (ret != ICE_SUCCESS)
1693 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1703 ice_send_driver_ver(struct ice_hw *hw)
1705 struct ice_driver_ver dv;
1707 /* we don't have driver version use 0 for dummy */
1711 dv.subbuild_ver = 0;
1712 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1714 return ice_aq_send_driver_ver(hw, &dv, NULL);
1718 ice_pf_setup(struct ice_pf *pf)
1720 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1721 struct ice_vsi *vsi;
1724 /* Clear all stats counters */
1725 pf->offset_loaded = false;
1726 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1727 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1728 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1729 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1731 /* force guaranteed filter pool for PF */
1732 ice_alloc_fd_guar_item(hw, &unused,
1733 hw->func_caps.fd_fltr_guar);
1734 /* force shared filter pool for PF */
1735 ice_alloc_fd_shrd_item(hw, &unused,
1736 hw->func_caps.fd_fltr_best_effort);
1738 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1740 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1749 /* PCIe configuration space setting */
1750 #define PCI_CFG_SPACE_SIZE 256
1751 #define PCI_CFG_SPACE_EXP_SIZE 4096
1752 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1753 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1754 #define PCI_EXT_CAP_ID_DSN 0x03
1757 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1761 int pos = PCI_CFG_SPACE_SIZE;
1763 /* minimum 8 bytes per capability */
1764 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1766 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1767 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1772 * If we have no capabilities, this is indicated by cap ID,
1773 * cap version and next pointer all being 0.
1779 if (PCI_EXT_CAP_ID(header) == cap)
1782 pos = PCI_EXT_CAP_NEXT(header);
1784 if (pos < PCI_CFG_SPACE_SIZE)
1787 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1788 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1797 * Extract device serial number from PCIe Configuration Space and
1798 * determine the pkg file path according to the DSN.
1801 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1804 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1805 uint32_t dsn_low, dsn_high;
1806 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1808 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1811 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1812 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1813 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1814 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1816 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1820 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1821 ICE_MAX_PKG_FILENAME_SIZE);
1822 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1825 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1826 ICE_MAX_PKG_FILENAME_SIZE);
1827 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1831 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1832 if (!access(pkg_file, 0))
1834 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1839 ice_load_pkg_type(struct ice_hw *hw)
1841 enum ice_pkg_type package_type;
1843 /* store the activated package type (OS default or Comms) */
1844 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1846 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1847 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1849 package_type = ICE_PKG_TYPE_COMMS;
1851 package_type = ICE_PKG_TYPE_UNKNOWN;
1853 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1854 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1855 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1856 hw->active_pkg_name);
1858 return package_type;
1861 static int ice_load_pkg(struct rte_eth_dev *dev)
1863 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1870 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1871 struct ice_adapter *ad =
1872 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1874 ice_pkg_file_search_path(pci_dev, pkg_file);
1876 file = fopen(pkg_file, "rb");
1878 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1882 err = stat(pkg_file, &fstat);
1884 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1889 buf_len = fstat.st_size;
1890 buf = rte_malloc(NULL, buf_len, 0);
1893 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1899 err = fread(buf, buf_len, 1, file);
1901 PMD_INIT_LOG(ERR, "failed to read package data\n");
1909 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1911 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1915 /* store the loaded pkg type info */
1916 ad->active_pkg_type = ice_load_pkg_type(hw);
1918 err = ice_init_hw_tbls(hw);
1920 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1921 goto fail_init_tbls;
1927 rte_free(hw->pkg_copy);
1934 ice_base_queue_get(struct ice_pf *pf)
1937 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1939 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1940 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1941 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1943 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1949 parse_bool(const char *key, const char *value, void *args)
1951 int *i = (int *)args;
1955 num = strtoul(value, &end, 10);
1957 if (num != 0 && num != 1) {
1958 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1959 "value must be 0 or 1",
1968 static int ice_parse_devargs(struct rte_eth_dev *dev)
1970 struct ice_adapter *ad =
1971 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1972 struct rte_devargs *devargs = dev->device->devargs;
1973 struct rte_kvargs *kvlist;
1976 if (devargs == NULL)
1979 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1980 if (kvlist == NULL) {
1981 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1985 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1986 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1987 sizeof(ad->devargs.proto_xtr));
1989 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1990 &handle_proto_xtr_arg, &ad->devargs);
1994 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1995 &parse_bool, &ad->devargs.safe_mode_support);
1999 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
2000 &parse_bool, &ad->devargs.pipe_mode_support);
2004 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2005 &parse_bool, &ad->devargs.flow_mark_support);
2010 rte_kvargs_free(kvlist);
2014 /* Forward LLDP packets to default VSI by set switch rules */
2016 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2018 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2019 struct ice_fltr_list_entry *s_list_itr = NULL;
2020 struct LIST_HEAD_TYPE list_head;
2023 INIT_LIST_HEAD(&list_head);
2025 s_list_itr = (struct ice_fltr_list_entry *)
2026 ice_malloc(hw, sizeof(*s_list_itr));
2029 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2030 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2031 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2032 RTE_ETHER_TYPE_LLDP;
2033 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2034 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2035 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2036 LIST_ADD(&s_list_itr->list_entry, &list_head);
2038 ret = ice_add_eth_mac(hw, &list_head);
2040 ret = ice_remove_eth_mac(hw, &list_head);
2042 rte_free(s_list_itr);
2046 static enum ice_status
2047 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2048 uint16_t num, uint16_t desc_id,
2049 uint16_t *prof_buf, uint16_t *num_prof)
2051 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2054 bool res_shared = 1;
2055 struct ice_aq_desc aq_desc;
2056 struct ice_sq_cd *cd = NULL;
2057 struct ice_aqc_get_allocd_res_desc *cmd =
2058 &aq_desc.params.get_res_desc;
2060 buf_len = sizeof(resp_buf->elem) * num;
2061 resp_buf = ice_malloc(hw, buf_len);
2065 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2066 ice_aqc_opc_get_allocd_res_desc);
2068 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2069 ICE_AQC_RES_TYPE_M) | (res_shared ?
2070 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2071 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2073 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2075 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2079 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2080 (*num_prof), ICE_NONDMA_TO_NONDMA);
2087 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2091 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2092 uint16_t first_desc = 1;
2093 uint16_t num_prof = 0;
2095 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2096 first_desc, prof_buf, &num_prof);
2098 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2102 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2103 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2105 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2113 ice_reset_fxp_resource(struct ice_hw *hw)
2117 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2119 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2123 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2125 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2133 ice_rss_ctx_init(struct ice_pf *pf)
2135 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2136 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2138 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2139 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2141 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2142 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2146 ice_dev_init(struct rte_eth_dev *dev)
2148 struct rte_pci_device *pci_dev;
2149 struct rte_intr_handle *intr_handle;
2150 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152 struct ice_adapter *ad =
2153 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2154 struct ice_vsi *vsi;
2157 dev->dev_ops = &ice_eth_dev_ops;
2158 dev->rx_pkt_burst = ice_recv_pkts;
2159 dev->tx_pkt_burst = ice_xmit_pkts;
2160 dev->tx_pkt_prepare = ice_prep_pkts;
2162 /* for secondary processes, we don't initialise any further as primary
2163 * has already done this work.
2165 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2166 ice_set_rx_function(dev);
2167 ice_set_tx_function(dev);
2171 ice_set_default_ptype_table(dev);
2172 pci_dev = RTE_DEV_TO_PCI(dev->device);
2173 intr_handle = &pci_dev->intr_handle;
2175 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2176 pf->adapter->eth_dev = dev;
2177 pf->dev_data = dev->data;
2178 hw->back = pf->adapter;
2179 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2180 hw->vendor_id = pci_dev->id.vendor_id;
2181 hw->device_id = pci_dev->id.device_id;
2182 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2183 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2184 hw->bus.device = pci_dev->addr.devid;
2185 hw->bus.func = pci_dev->addr.function;
2187 ret = ice_parse_devargs(dev);
2189 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2193 ice_init_controlq_parameter(hw);
2195 ret = ice_init_hw(hw);
2197 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2201 ret = ice_load_pkg(dev);
2203 if (ad->devargs.safe_mode_support == 0) {
2204 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2205 "Use safe-mode-support=1 to enter Safe Mode");
2209 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2210 "Entering Safe Mode");
2211 ad->is_safe_mode = 1;
2214 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2215 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2216 hw->api_maj_ver, hw->api_min_ver);
2218 ice_pf_sw_init(dev);
2219 ret = ice_init_mac_address(dev);
2221 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2225 /* Pass the information to the rte_eth_dev_close() that it should also
2226 * release the private port resources.
2228 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2230 ret = ice_res_pool_init(&pf->msix_pool, 1,
2231 hw->func_caps.common_cap.num_msix_vectors - 1);
2233 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2234 goto err_msix_pool_init;
2237 ret = ice_pf_setup(pf);
2239 PMD_INIT_LOG(ERR, "Failed to setup PF");
2243 ret = ice_send_driver_ver(hw);
2245 PMD_INIT_LOG(ERR, "Failed to send driver version");
2251 /* Disable double vlan by default */
2252 ice_vsi_config_double_vlan(vsi, false);
2254 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2255 if (ret != ICE_SUCCESS)
2256 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2257 ret = ice_init_dcb(hw, true);
2258 if (ret != ICE_SUCCESS)
2259 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2260 /* Forward LLDP packets to default VSI */
2261 ret = ice_vsi_config_sw_lldp(vsi, true);
2262 if (ret != ICE_SUCCESS)
2263 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2264 /* register callback func to eal lib */
2265 rte_intr_callback_register(intr_handle,
2266 ice_interrupt_handler, dev);
2268 ice_pf_enable_irq0(hw);
2270 /* enable uio intr after callback register */
2271 rte_intr_enable(intr_handle);
2273 /* get base queue pairs index in the device */
2274 ice_base_queue_get(pf);
2276 /* Initialize RSS context for gtpu_eh */
2277 ice_rss_ctx_init(pf);
2279 if (!ad->is_safe_mode) {
2280 ret = ice_flow_init(ad);
2282 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2287 ret = ice_reset_fxp_resource(hw);
2289 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2296 ice_res_pool_destroy(&pf->msix_pool);
2298 rte_free(dev->data->mac_addrs);
2299 dev->data->mac_addrs = NULL;
2301 ice_sched_cleanup_all(hw);
2302 rte_free(hw->port_info);
2303 ice_shutdown_all_ctrlq(hw);
2304 rte_free(pf->proto_xtr);
2310 ice_release_vsi(struct ice_vsi *vsi)
2313 struct ice_vsi_ctx vsi_ctx;
2314 enum ice_status ret;
2320 hw = ICE_VSI_TO_HW(vsi);
2322 ice_remove_all_mac_vlan_filters(vsi);
2324 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2326 vsi_ctx.vsi_num = vsi->vsi_id;
2327 vsi_ctx.info = vsi->info;
2328 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2329 if (ret != ICE_SUCCESS) {
2330 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2334 rte_free(vsi->rss_lut);
2335 rte_free(vsi->rss_key);
2341 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2343 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2344 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2345 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2346 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2347 uint16_t msix_intr, i;
2349 /* disable interrupt and also clear all the exist config */
2350 for (i = 0; i < vsi->nb_qps; i++) {
2351 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2352 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2356 if (rte_intr_allow_others(intr_handle))
2358 for (i = 0; i < vsi->nb_msix; i++) {
2359 msix_intr = vsi->msix_intr + i;
2360 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2361 GLINT_DYN_CTL_WB_ON_ITR_M);
2365 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2369 ice_dev_stop(struct rte_eth_dev *dev)
2371 struct rte_eth_dev_data *data = dev->data;
2372 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2373 struct ice_vsi *main_vsi = pf->main_vsi;
2374 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2375 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2378 /* avoid stopping again */
2379 if (pf->adapter_stopped)
2382 /* stop and clear all Rx queues */
2383 for (i = 0; i < data->nb_rx_queues; i++)
2384 ice_rx_queue_stop(dev, i);
2386 /* stop and clear all Tx queues */
2387 for (i = 0; i < data->nb_tx_queues; i++)
2388 ice_tx_queue_stop(dev, i);
2390 /* disable all queue interrupts */
2391 ice_vsi_disable_queues_intr(main_vsi);
2393 if (pf->init_link_up)
2394 ice_dev_set_link_up(dev);
2396 ice_dev_set_link_down(dev);
2398 /* Clean datapath event and queue/vec mapping */
2399 rte_intr_efd_disable(intr_handle);
2400 if (intr_handle->intr_vec) {
2401 rte_free(intr_handle->intr_vec);
2402 intr_handle->intr_vec = NULL;
2405 pf->adapter_stopped = true;
2409 ice_dev_close(struct rte_eth_dev *dev)
2411 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2412 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2414 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2415 struct ice_adapter *ad =
2416 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2418 /* Since stop will make link down, then the link event will be
2419 * triggered, disable the irq firstly to avoid the port_infoe etc
2420 * resources deallocation causing the interrupt service thread
2423 ice_pf_disable_irq0(hw);
2427 if (!ad->is_safe_mode)
2428 ice_flow_uninit(ad);
2430 /* release all queue resource */
2431 ice_free_queues(dev);
2433 ice_res_pool_destroy(&pf->msix_pool);
2434 ice_release_vsi(pf->main_vsi);
2435 ice_sched_cleanup_all(hw);
2436 ice_free_hw_tbls(hw);
2437 rte_free(hw->port_info);
2438 hw->port_info = NULL;
2439 ice_shutdown_all_ctrlq(hw);
2440 rte_free(pf->proto_xtr);
2441 pf->proto_xtr = NULL;
2443 dev->dev_ops = NULL;
2444 dev->rx_pkt_burst = NULL;
2445 dev->tx_pkt_burst = NULL;
2447 rte_free(dev->data->mac_addrs);
2448 dev->data->mac_addrs = NULL;
2450 /* disable uio intr before callback unregister */
2451 rte_intr_disable(intr_handle);
2453 /* unregister callback func from eal lib */
2454 rte_intr_callback_unregister(intr_handle,
2455 ice_interrupt_handler, dev);
2459 ice_dev_uninit(struct rte_eth_dev *dev)
2467 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm)
2469 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2470 struct ice_vsi *vsi = pf->main_vsi;
2472 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2473 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2474 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2475 pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr = hdr;
2476 pf->gtpu_hash_ctx.ipv4_udp.hash_fld = fld;
2477 pf->gtpu_hash_ctx.ipv4_udp.symm = symm;
2478 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2479 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2480 pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr = hdr;
2481 pf->gtpu_hash_ctx.ipv6_udp.hash_fld = fld;
2482 pf->gtpu_hash_ctx.ipv6_udp.symm = symm;
2483 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2484 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2485 pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr = hdr;
2486 pf->gtpu_hash_ctx.ipv4_tcp.hash_fld = fld;
2487 pf->gtpu_hash_ctx.ipv4_tcp.symm = symm;
2488 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2489 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2490 pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr = hdr;
2491 pf->gtpu_hash_ctx.ipv6_tcp.hash_fld = fld;
2492 pf->gtpu_hash_ctx.ipv6_tcp.symm = symm;
2493 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2494 pf->gtpu_hash_ctx.ipv4.pkt_hdr = hdr;
2495 pf->gtpu_hash_ctx.ipv4.hash_fld = fld;
2496 pf->gtpu_hash_ctx.ipv4.symm = symm;
2497 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2498 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2499 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2500 pf->gtpu_hash_ctx.ipv6.pkt_hdr = hdr;
2501 pf->gtpu_hash_ctx.ipv6.hash_fld = fld;
2502 pf->gtpu_hash_ctx.ipv6.symm = symm;
2503 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2504 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2508 if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2509 ICE_FLOW_SEG_HDR_GTPU_UP)) {
2510 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2511 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2512 if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2513 ice_add_rss_cfg(hw, vsi->idx,
2514 pf->gtpu_hash_ctx.ipv4.hash_fld,
2515 pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2516 pf->gtpu_hash_ctx.ipv4.symm);
2517 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2519 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2520 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2521 if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2522 ice_add_rss_cfg(hw, vsi->idx,
2523 pf->gtpu_hash_ctx.ipv6.hash_fld,
2524 pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2525 pf->gtpu_hash_ctx.ipv6.symm);
2526 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2528 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2529 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2530 if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2531 ice_add_rss_cfg(hw, vsi->idx,
2532 pf->gtpu_hash_ctx.ipv4.hash_fld,
2533 pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2534 pf->gtpu_hash_ctx.ipv4.symm);
2535 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2537 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2538 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2539 if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2540 ice_add_rss_cfg(hw, vsi->idx,
2541 pf->gtpu_hash_ctx.ipv6.hash_fld,
2542 pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2543 pf->gtpu_hash_ctx.ipv6.symm);
2544 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2553 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2555 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2556 struct ice_vsi *vsi = pf->main_vsi;
2558 if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2559 ICE_FLOW_SEG_HDR_GTPU_UP)) {
2560 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2561 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2562 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2563 ice_rem_rss_cfg(hw, vsi->idx,
2564 pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2565 pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2566 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2569 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2570 ice_rem_rss_cfg(hw, vsi->idx,
2571 pf->gtpu_hash_ctx.ipv4.hash_fld,
2572 pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2573 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2575 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2576 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2577 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2578 ice_rem_rss_cfg(hw, vsi->idx,
2579 pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2580 pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2581 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2584 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2585 ice_rem_rss_cfg(hw, vsi->idx,
2586 pf->gtpu_hash_ctx.ipv6.hash_fld,
2587 pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2588 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2590 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2591 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2592 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2593 ice_rem_rss_cfg(hw, vsi->idx,
2594 pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2595 pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2596 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2599 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2600 ice_rem_rss_cfg(hw, vsi->idx,
2601 pf->gtpu_hash_ctx.ipv4.hash_fld,
2602 pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2603 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2605 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2606 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2607 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2608 ice_rem_rss_cfg(hw, vsi->idx,
2609 pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2610 pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2611 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2614 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2615 ice_rem_rss_cfg(hw, vsi->idx,
2616 pf->gtpu_hash_ctx.ipv6.hash_fld,
2617 pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2618 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2620 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2621 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2622 ice_rem_rss_cfg(hw, vsi->idx,
2623 pf->gtpu_hash_ctx.ipv4.hash_fld,
2624 pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2625 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2628 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2629 ice_rem_rss_cfg(hw, vsi->idx,
2630 pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2631 pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2632 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2635 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2636 ice_rem_rss_cfg(hw, vsi->idx,
2637 pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2638 pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2639 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2641 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2642 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2643 ice_rem_rss_cfg(hw, vsi->idx,
2644 pf->gtpu_hash_ctx.ipv6.hash_fld,
2645 pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2646 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2649 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2650 ice_rem_rss_cfg(hw, vsi->idx,
2651 pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2652 pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2653 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2656 if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2657 ice_rem_rss_cfg(hw, vsi->idx,
2658 pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2659 pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2660 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2669 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2671 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2672 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2673 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2674 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2675 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2676 (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2677 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2678 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2679 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2680 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2681 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2682 (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2683 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2684 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2685 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2686 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2687 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2695 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2696 uint64_t fld, uint32_t hdr)
2698 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2701 ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr);
2702 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2703 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2705 ret = ice_rem_rss_cfg_post(pf, hdr);
2707 PMD_DRV_LOG(ERR, "remove rss cfg post failed\n");
2713 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2714 uint64_t fld, uint32_t hdr, bool symm)
2716 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2719 ret = ice_add_rss_cfg_pre(pf, hdr);
2721 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2723 ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm);
2725 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2727 ret = ice_add_rss_cfg_post(pf, hdr, fld, symm);
2729 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2735 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2737 struct ice_vsi *vsi = pf->main_vsi;
2740 /* Configure RSS for IPv4 with src/dst addr as input set */
2741 if (rss_hf & ETH_RSS_IPV4) {
2742 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2743 ICE_FLOW_SEG_HDR_IPV4 |
2744 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2746 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2750 /* Configure RSS for IPv6 with src/dst addr as input set */
2751 if (rss_hf & ETH_RSS_IPV6) {
2752 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2753 ICE_FLOW_SEG_HDR_IPV6 |
2754 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2756 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2760 /* Configure RSS for udp4 with src/dst addr and port as input set */
2761 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2762 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2763 ICE_FLOW_SEG_HDR_UDP |
2764 ICE_FLOW_SEG_HDR_IPV4 |
2765 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2767 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2771 /* Configure RSS for udp6 with src/dst addr and port as input set */
2772 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2773 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2774 ICE_FLOW_SEG_HDR_UDP |
2775 ICE_FLOW_SEG_HDR_IPV6 |
2776 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2778 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2782 /* Configure RSS for tcp4 with src/dst addr and port as input set */
2783 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2784 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2785 ICE_FLOW_SEG_HDR_TCP |
2786 ICE_FLOW_SEG_HDR_IPV4 |
2787 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2789 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2793 /* Configure RSS for tcp6 with src/dst addr and port as input set */
2794 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2795 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2796 ICE_FLOW_SEG_HDR_TCP |
2797 ICE_FLOW_SEG_HDR_IPV6 |
2798 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2800 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2804 /* Configure RSS for sctp4 with src/dst addr and port as input set */
2805 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2806 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2807 ICE_FLOW_SEG_HDR_SCTP |
2808 ICE_FLOW_SEG_HDR_IPV4 |
2809 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2811 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2815 /* Configure RSS for sctp6 with src/dst addr and port as input set */
2816 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2817 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2818 ICE_FLOW_SEG_HDR_SCTP |
2819 ICE_FLOW_SEG_HDR_IPV6 |
2820 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2822 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2826 if (rss_hf & ETH_RSS_IPV4) {
2827 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2828 ICE_FLOW_SEG_HDR_GTPU_IP |
2829 ICE_FLOW_SEG_HDR_IPV4 |
2830 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2832 PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2835 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2836 ICE_FLOW_SEG_HDR_GTPU_EH |
2837 ICE_FLOW_SEG_HDR_IPV4 |
2838 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2840 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2843 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2844 ICE_FLOW_SEG_HDR_PPPOE |
2845 ICE_FLOW_SEG_HDR_IPV4 |
2846 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2848 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2852 if (rss_hf & ETH_RSS_IPV6) {
2853 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2854 ICE_FLOW_SEG_HDR_GTPU_IP |
2855 ICE_FLOW_SEG_HDR_IPV6 |
2856 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2858 PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2861 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2862 ICE_FLOW_SEG_HDR_GTPU_EH |
2863 ICE_FLOW_SEG_HDR_IPV6 |
2864 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2866 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2869 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2870 ICE_FLOW_SEG_HDR_PPPOE |
2871 ICE_FLOW_SEG_HDR_IPV6 |
2872 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2874 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2878 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2879 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2880 ICE_FLOW_SEG_HDR_GTPU_IP |
2881 ICE_FLOW_SEG_HDR_UDP |
2882 ICE_FLOW_SEG_HDR_IPV4 |
2883 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2885 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2888 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2889 ICE_FLOW_SEG_HDR_GTPU_EH |
2890 ICE_FLOW_SEG_HDR_UDP |
2891 ICE_FLOW_SEG_HDR_IPV4 |
2892 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2894 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2897 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2898 ICE_FLOW_SEG_HDR_PPPOE |
2899 ICE_FLOW_SEG_HDR_UDP |
2900 ICE_FLOW_SEG_HDR_IPV4 |
2901 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2903 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2907 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2908 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2909 ICE_FLOW_SEG_HDR_GTPU_IP |
2910 ICE_FLOW_SEG_HDR_UDP |
2911 ICE_FLOW_SEG_HDR_IPV6 |
2912 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2914 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2917 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2918 ICE_FLOW_SEG_HDR_GTPU_EH |
2919 ICE_FLOW_SEG_HDR_UDP |
2920 ICE_FLOW_SEG_HDR_IPV6 |
2921 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2923 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2926 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2927 ICE_FLOW_SEG_HDR_PPPOE |
2928 ICE_FLOW_SEG_HDR_UDP |
2929 ICE_FLOW_SEG_HDR_IPV6 |
2930 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2932 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2936 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2937 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2938 ICE_FLOW_SEG_HDR_GTPU_IP |
2939 ICE_FLOW_SEG_HDR_TCP |
2940 ICE_FLOW_SEG_HDR_IPV4 |
2941 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2943 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
2946 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2947 ICE_FLOW_SEG_HDR_GTPU_EH |
2948 ICE_FLOW_SEG_HDR_TCP |
2949 ICE_FLOW_SEG_HDR_IPV4 |
2950 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2952 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
2955 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2956 ICE_FLOW_SEG_HDR_PPPOE |
2957 ICE_FLOW_SEG_HDR_TCP |
2958 ICE_FLOW_SEG_HDR_IPV4 |
2959 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2961 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2965 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2966 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2967 ICE_FLOW_SEG_HDR_GTPU_IP |
2968 ICE_FLOW_SEG_HDR_TCP |
2969 ICE_FLOW_SEG_HDR_IPV6 |
2970 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2972 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
2975 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2976 ICE_FLOW_SEG_HDR_GTPU_EH |
2977 ICE_FLOW_SEG_HDR_TCP |
2978 ICE_FLOW_SEG_HDR_IPV6 |
2979 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2981 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
2984 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2985 ICE_FLOW_SEG_HDR_PPPOE |
2986 ICE_FLOW_SEG_HDR_TCP |
2987 ICE_FLOW_SEG_HDR_IPV6 |
2988 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2990 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2994 if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2995 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
2996 ICE_FLOW_SEG_HDR_GTPU_IP |
2997 ICE_FLOW_SEG_HDR_SCTP |
2998 ICE_FLOW_SEG_HDR_IPV4 |
2999 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3001 PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
3004 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3005 ICE_FLOW_SEG_HDR_GTPU_EH |
3006 ICE_FLOW_SEG_HDR_SCTP |
3007 ICE_FLOW_SEG_HDR_IPV4 |
3008 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3010 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
3014 if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3015 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3016 ICE_FLOW_SEG_HDR_GTPU_IP |
3017 ICE_FLOW_SEG_HDR_SCTP |
3018 ICE_FLOW_SEG_HDR_IPV6 |
3019 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3021 PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
3024 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3025 ICE_FLOW_SEG_HDR_GTPU_EH |
3026 ICE_FLOW_SEG_HDR_SCTP |
3027 ICE_FLOW_SEG_HDR_IPV6 |
3028 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3030 PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
3035 static int ice_init_rss(struct ice_pf *pf)
3037 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3038 struct ice_vsi *vsi = pf->main_vsi;
3039 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3040 struct rte_eth_rss_conf *rss_conf;
3041 struct ice_aqc_get_set_rss_keys key;
3044 bool is_safe_mode = pf->adapter->is_safe_mode;
3047 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3048 nb_q = dev->data->nb_rx_queues;
3049 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3050 vsi->rss_lut_size = pf->hash_lut_size;
3053 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3057 if (!vsi->rss_key) {
3058 vsi->rss_key = rte_zmalloc(NULL,
3059 vsi->rss_key_size, 0);
3060 if (vsi->rss_key == NULL) {
3061 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3065 if (!vsi->rss_lut) {
3066 vsi->rss_lut = rte_zmalloc(NULL,
3067 vsi->rss_lut_size, 0);
3068 if (vsi->rss_lut == NULL) {
3069 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3070 rte_free(vsi->rss_key);
3071 vsi->rss_key = NULL;
3075 /* configure RSS key */
3076 if (!rss_conf->rss_key) {
3077 /* Calculate the default hash key */
3078 for (i = 0; i <= vsi->rss_key_size; i++)
3079 vsi->rss_key[i] = (uint8_t)rte_rand();
3081 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3082 RTE_MIN(rss_conf->rss_key_len,
3083 vsi->rss_key_size));
3085 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3086 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3090 /* init RSS LUT table */
3091 for (i = 0; i < vsi->rss_lut_size; i++)
3092 vsi->rss_lut[i] = i % nb_q;
3094 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3095 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
3096 vsi->rss_lut, vsi->rss_lut_size);
3100 /* Enable registers for symmetric_toeplitz function. */
3101 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3102 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3103 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3104 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3106 /* RSS hash configuration */
3107 ice_rss_hash_set(pf, rss_conf->rss_hf);
3111 rte_free(vsi->rss_key);
3112 vsi->rss_key = NULL;
3113 rte_free(vsi->rss_lut);
3114 vsi->rss_lut = NULL;
3119 ice_dev_configure(struct rte_eth_dev *dev)
3121 struct ice_adapter *ad =
3122 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3123 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3127 * bulk allocation or vector Rx preconditions we will reset it.
3129 ad->rx_bulk_alloc_allowed = true;
3130 ad->tx_simple_allowed = true;
3132 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3133 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3135 ret = ice_init_rss(pf);
3137 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3145 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3146 int base_queue, int nb_queue)
3148 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3149 uint32_t val, val_tx;
3152 for (i = 0; i < nb_queue; i++) {
3154 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3155 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3156 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3157 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3159 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3160 base_queue + i, msix_vect);
3161 /* set ITR0 value */
3162 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
3163 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3164 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3169 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3171 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3172 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3173 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3174 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3175 uint16_t msix_vect = vsi->msix_intr;
3176 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3177 uint16_t queue_idx = 0;
3181 /* clear Rx/Tx queue interrupt */
3182 for (i = 0; i < vsi->nb_used_qps; i++) {
3183 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3184 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3187 /* PF bind interrupt */
3188 if (rte_intr_dp_is_en(intr_handle)) {
3193 for (i = 0; i < vsi->nb_used_qps; i++) {
3195 if (!rte_intr_allow_others(intr_handle))
3196 msix_vect = ICE_MISC_VEC_ID;
3198 /* uio mapping all queue to one msix_vect */
3199 __vsi_queues_bind_intr(vsi, msix_vect,
3200 vsi->base_queue + i,
3201 vsi->nb_used_qps - i);
3203 for (; !!record && i < vsi->nb_used_qps; i++)
3204 intr_handle->intr_vec[queue_idx + i] =
3209 /* vfio 1:1 queue/msix_vect mapping */
3210 __vsi_queues_bind_intr(vsi, msix_vect,
3211 vsi->base_queue + i, 1);
3214 intr_handle->intr_vec[queue_idx + i] = msix_vect;
3222 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3224 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3225 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3226 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3227 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3228 uint16_t msix_intr, i;
3230 if (rte_intr_allow_others(intr_handle))
3231 for (i = 0; i < vsi->nb_used_qps; i++) {
3232 msix_intr = vsi->msix_intr + i;
3233 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3234 GLINT_DYN_CTL_INTENA_M |
3235 GLINT_DYN_CTL_CLEARPBA_M |
3236 GLINT_DYN_CTL_ITR_INDX_M |
3237 GLINT_DYN_CTL_WB_ON_ITR_M);
3240 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3241 GLINT_DYN_CTL_INTENA_M |
3242 GLINT_DYN_CTL_CLEARPBA_M |
3243 GLINT_DYN_CTL_ITR_INDX_M |
3244 GLINT_DYN_CTL_WB_ON_ITR_M);
3248 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3250 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3251 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3252 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3253 struct ice_vsi *vsi = pf->main_vsi;
3254 uint32_t intr_vector = 0;
3256 rte_intr_disable(intr_handle);
3258 /* check and configure queue intr-vector mapping */
3259 if ((rte_intr_cap_multiple(intr_handle) ||
3260 !RTE_ETH_DEV_SRIOV(dev).active) &&
3261 dev->data->dev_conf.intr_conf.rxq != 0) {
3262 intr_vector = dev->data->nb_rx_queues;
3263 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3264 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3265 ICE_MAX_INTR_QUEUE_NUM);
3268 if (rte_intr_efd_enable(intr_handle, intr_vector))
3272 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3273 intr_handle->intr_vec =
3274 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3276 if (!intr_handle->intr_vec) {
3278 "Failed to allocate %d rx_queues intr_vec",
3279 dev->data->nb_rx_queues);
3284 /* Map queues with MSIX interrupt */
3285 vsi->nb_used_qps = dev->data->nb_rx_queues;
3286 ice_vsi_queues_bind_intr(vsi);
3288 /* Enable interrupts for all the queues */
3289 ice_vsi_enable_queues_intr(vsi);
3291 rte_intr_enable(intr_handle);
3297 ice_get_init_link_status(struct rte_eth_dev *dev)
3299 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3302 struct ice_link_status link_status;
3305 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3306 &link_status, NULL);
3307 if (ret != ICE_SUCCESS) {
3308 PMD_DRV_LOG(ERR, "Failed to get link info");
3309 pf->init_link_up = false;
3313 if (link_status.link_info & ICE_AQ_LINK_UP)
3314 pf->init_link_up = true;
3318 ice_dev_start(struct rte_eth_dev *dev)
3320 struct rte_eth_dev_data *data = dev->data;
3321 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323 struct ice_vsi *vsi = pf->main_vsi;
3324 uint16_t nb_rxq = 0;
3326 uint16_t max_frame_size;
3329 /* program Tx queues' context in hardware */
3330 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3331 ret = ice_tx_queue_start(dev, nb_txq);
3333 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3338 /* program Rx queues' context in hardware*/
3339 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3340 ret = ice_rx_queue_start(dev, nb_rxq);
3342 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3347 ice_set_rx_function(dev);
3348 ice_set_tx_function(dev);
3350 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3351 ETH_VLAN_EXTEND_MASK;
3352 ret = ice_vlan_offload_set(dev, mask);
3354 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3358 /* enable Rx interrput and mapping Rx queue to interrupt vector */
3359 if (ice_rxq_intr_setup(dev))
3362 /* Enable receiving broadcast packets and transmitting packets */
3363 ret = ice_set_vsi_promisc(hw, vsi->idx,
3364 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3365 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3367 if (ret != ICE_SUCCESS)
3368 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3370 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3371 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3372 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3373 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3374 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3375 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3376 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3378 if (ret != ICE_SUCCESS)
3379 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3381 ice_get_init_link_status(dev);
3383 ice_dev_set_link_up(dev);
3385 /* Call get_link_info aq commond to enable/disable LSE */
3386 ice_link_update(dev, 0);
3388 pf->adapter_stopped = false;
3390 /* Set the max frame size to default value*/
3391 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3392 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3395 /* Set the max frame size to HW*/
3396 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3400 /* stop the started queues if failed to start all queues */
3402 for (i = 0; i < nb_rxq; i++)
3403 ice_rx_queue_stop(dev, i);
3405 for (i = 0; i < nb_txq; i++)
3406 ice_tx_queue_stop(dev, i);
3412 ice_dev_reset(struct rte_eth_dev *dev)
3416 if (dev->data->sriov.active)
3419 ret = ice_dev_uninit(dev);
3421 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3425 ret = ice_dev_init(dev);
3427 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3435 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3437 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3438 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439 struct ice_vsi *vsi = pf->main_vsi;
3440 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3441 bool is_safe_mode = pf->adapter->is_safe_mode;
3445 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3446 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3447 dev_info->max_rx_queues = vsi->nb_qps;
3448 dev_info->max_tx_queues = vsi->nb_qps;
3449 dev_info->max_mac_addrs = vsi->max_macaddrs;
3450 dev_info->max_vfs = pci_dev->max_vfs;
3451 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3452 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3454 dev_info->rx_offload_capa =
3455 DEV_RX_OFFLOAD_VLAN_STRIP |
3456 DEV_RX_OFFLOAD_JUMBO_FRAME |
3457 DEV_RX_OFFLOAD_KEEP_CRC |
3458 DEV_RX_OFFLOAD_SCATTER |
3459 DEV_RX_OFFLOAD_VLAN_FILTER;
3460 dev_info->tx_offload_capa =
3461 DEV_TX_OFFLOAD_VLAN_INSERT |
3462 DEV_TX_OFFLOAD_TCP_TSO |
3463 DEV_TX_OFFLOAD_MULTI_SEGS |
3464 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3465 dev_info->flow_type_rss_offloads = 0;
3467 if (!is_safe_mode) {
3468 dev_info->rx_offload_capa |=
3469 DEV_RX_OFFLOAD_IPV4_CKSUM |
3470 DEV_RX_OFFLOAD_UDP_CKSUM |
3471 DEV_RX_OFFLOAD_TCP_CKSUM |
3472 DEV_RX_OFFLOAD_QINQ_STRIP |
3473 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3474 DEV_RX_OFFLOAD_VLAN_EXTEND |
3475 DEV_RX_OFFLOAD_RSS_HASH;
3476 dev_info->tx_offload_capa |=
3477 DEV_TX_OFFLOAD_QINQ_INSERT |
3478 DEV_TX_OFFLOAD_IPV4_CKSUM |
3479 DEV_TX_OFFLOAD_UDP_CKSUM |
3480 DEV_TX_OFFLOAD_TCP_CKSUM |
3481 DEV_TX_OFFLOAD_SCTP_CKSUM |
3482 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3483 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3484 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3487 dev_info->rx_queue_offload_capa = 0;
3488 dev_info->tx_queue_offload_capa = 0;
3490 dev_info->reta_size = pf->hash_lut_size;
3491 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3493 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3495 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3496 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3497 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3499 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3504 dev_info->default_txconf = (struct rte_eth_txconf) {
3506 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3507 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3508 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3510 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3511 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3515 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3516 .nb_max = ICE_MAX_RING_DESC,
3517 .nb_min = ICE_MIN_RING_DESC,
3518 .nb_align = ICE_ALIGN_RING_DESC,
3521 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3522 .nb_max = ICE_MAX_RING_DESC,
3523 .nb_min = ICE_MIN_RING_DESC,
3524 .nb_align = ICE_ALIGN_RING_DESC,
3527 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3528 ETH_LINK_SPEED_100M |
3530 ETH_LINK_SPEED_2_5G |
3532 ETH_LINK_SPEED_10G |
3533 ETH_LINK_SPEED_20G |
3536 phy_type_low = hw->port_info->phy.phy_type_low;
3537 phy_type_high = hw->port_info->phy.phy_type_high;
3539 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3540 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3542 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3543 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3544 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3546 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3547 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3549 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3550 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3551 dev_info->default_rxportconf.nb_queues = 1;
3552 dev_info->default_txportconf.nb_queues = 1;
3553 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3554 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3560 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3561 struct rte_eth_link *link)
3563 struct rte_eth_link *dst = link;
3564 struct rte_eth_link *src = &dev->data->dev_link;
3566 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3567 *(uint64_t *)src) == 0)
3574 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3575 struct rte_eth_link *link)
3577 struct rte_eth_link *dst = &dev->data->dev_link;
3578 struct rte_eth_link *src = link;
3580 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3581 *(uint64_t *)src) == 0)
3588 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3590 #define CHECK_INTERVAL 100 /* 100ms */
3591 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3592 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593 struct ice_link_status link_status;
3594 struct rte_eth_link link, old;
3596 unsigned int rep_cnt = MAX_REPEAT_TIME;
3597 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3599 memset(&link, 0, sizeof(link));
3600 memset(&old, 0, sizeof(old));
3601 memset(&link_status, 0, sizeof(link_status));
3602 ice_atomic_read_link_status(dev, &old);
3605 /* Get link status information from hardware */
3606 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3607 &link_status, NULL);
3608 if (status != ICE_SUCCESS) {
3609 link.link_speed = ETH_SPEED_NUM_100M;
3610 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3611 PMD_DRV_LOG(ERR, "Failed to get link info");
3615 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3616 if (!wait_to_complete || link.link_status)
3619 rte_delay_ms(CHECK_INTERVAL);
3620 } while (--rep_cnt);
3622 if (!link.link_status)
3625 /* Full-duplex operation at all supported speeds */
3626 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3628 /* Parse the link status */
3629 switch (link_status.link_speed) {
3630 case ICE_AQ_LINK_SPEED_10MB:
3631 link.link_speed = ETH_SPEED_NUM_10M;
3633 case ICE_AQ_LINK_SPEED_100MB:
3634 link.link_speed = ETH_SPEED_NUM_100M;
3636 case ICE_AQ_LINK_SPEED_1000MB:
3637 link.link_speed = ETH_SPEED_NUM_1G;
3639 case ICE_AQ_LINK_SPEED_2500MB:
3640 link.link_speed = ETH_SPEED_NUM_2_5G;
3642 case ICE_AQ_LINK_SPEED_5GB:
3643 link.link_speed = ETH_SPEED_NUM_5G;
3645 case ICE_AQ_LINK_SPEED_10GB:
3646 link.link_speed = ETH_SPEED_NUM_10G;
3648 case ICE_AQ_LINK_SPEED_20GB:
3649 link.link_speed = ETH_SPEED_NUM_20G;
3651 case ICE_AQ_LINK_SPEED_25GB:
3652 link.link_speed = ETH_SPEED_NUM_25G;
3654 case ICE_AQ_LINK_SPEED_40GB:
3655 link.link_speed = ETH_SPEED_NUM_40G;
3657 case ICE_AQ_LINK_SPEED_50GB:
3658 link.link_speed = ETH_SPEED_NUM_50G;
3660 case ICE_AQ_LINK_SPEED_100GB:
3661 link.link_speed = ETH_SPEED_NUM_100G;
3663 case ICE_AQ_LINK_SPEED_UNKNOWN:
3665 PMD_DRV_LOG(ERR, "Unknown link speed");
3666 link.link_speed = ETH_SPEED_NUM_NONE;
3670 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3671 ETH_LINK_SPEED_FIXED);
3674 ice_atomic_write_link_status(dev, &link);
3675 if (link.link_status == old.link_status)
3681 /* Force the physical link state by getting the current PHY capabilities from
3682 * hardware and setting the PHY config based on the determined capabilities. If
3683 * link changes, link event will be triggered because both the Enable Automatic
3684 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3686 static enum ice_status
3687 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3689 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3690 struct ice_aqc_get_phy_caps_data *pcaps;
3691 struct ice_port_info *pi;
3692 enum ice_status status;
3694 if (!hw || !hw->port_info)
3695 return ICE_ERR_PARAM;
3699 pcaps = (struct ice_aqc_get_phy_caps_data *)
3700 ice_malloc(hw, sizeof(*pcaps));
3702 return ICE_ERR_NO_MEMORY;
3704 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3709 /* No change in link */
3710 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3711 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3714 cfg.phy_type_low = pcaps->phy_type_low;
3715 cfg.phy_type_high = pcaps->phy_type_high;
3716 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3717 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3718 cfg.eee_cap = pcaps->eee_cap;
3719 cfg.eeer_value = pcaps->eeer_value;
3720 cfg.link_fec_opt = pcaps->link_fec_options;
3722 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3724 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3726 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3729 ice_free(hw, pcaps);
3734 ice_dev_set_link_up(struct rte_eth_dev *dev)
3736 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 return ice_force_phys_link_state(hw, true);
3742 ice_dev_set_link_down(struct rte_eth_dev *dev)
3744 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746 return ice_force_phys_link_state(hw, false);
3750 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3752 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3753 struct rte_eth_dev_data *dev_data = pf->dev_data;
3754 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3756 /* check if mtu is within the allowed range */
3757 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3760 /* mtu setting is forbidden if port is start */
3761 if (dev_data->dev_started) {
3763 "port %d must be stopped before configuration",
3768 if (frame_size > RTE_ETHER_MAX_LEN)
3769 dev_data->dev_conf.rxmode.offloads |=
3770 DEV_RX_OFFLOAD_JUMBO_FRAME;
3772 dev_data->dev_conf.rxmode.offloads &=
3773 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3775 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3780 static int ice_macaddr_set(struct rte_eth_dev *dev,
3781 struct rte_ether_addr *mac_addr)
3783 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3785 struct ice_vsi *vsi = pf->main_vsi;
3786 struct ice_mac_filter *f;
3790 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3791 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3795 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3796 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3801 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3805 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3806 if (ret != ICE_SUCCESS) {
3807 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3810 ret = ice_add_mac_filter(vsi, mac_addr);
3811 if (ret != ICE_SUCCESS) {
3812 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3815 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3817 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3818 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3819 if (ret != ICE_SUCCESS)
3820 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3825 /* Add a MAC address, and update filters */
3827 ice_macaddr_add(struct rte_eth_dev *dev,
3828 struct rte_ether_addr *mac_addr,
3829 __rte_unused uint32_t index,
3830 __rte_unused uint32_t pool)
3832 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3833 struct ice_vsi *vsi = pf->main_vsi;
3836 ret = ice_add_mac_filter(vsi, mac_addr);
3837 if (ret != ICE_SUCCESS) {
3838 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3845 /* Remove a MAC address, and update filters */
3847 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3849 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3850 struct ice_vsi *vsi = pf->main_vsi;
3851 struct rte_eth_dev_data *data = dev->data;
3852 struct rte_ether_addr *macaddr;
3855 macaddr = &data->mac_addrs[index];
3856 ret = ice_remove_mac_filter(vsi, macaddr);
3858 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3864 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3866 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3867 struct ice_vsi *vsi = pf->main_vsi;
3870 PMD_INIT_FUNC_TRACE();
3873 ret = ice_add_vlan_filter(vsi, vlan_id);
3875 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3879 ret = ice_remove_vlan_filter(vsi, vlan_id);
3881 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3889 /* Configure vlan filter on or off */
3891 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3893 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3894 struct ice_vsi_ctx ctxt;
3895 uint8_t sec_flags, sw_flags2;
3898 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3899 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3900 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3903 vsi->info.sec_flags |= sec_flags;
3904 vsi->info.sw_flags2 |= sw_flags2;
3906 vsi->info.sec_flags &= ~sec_flags;
3907 vsi->info.sw_flags2 &= ~sw_flags2;
3909 vsi->info.sw_id = hw->port_info->sw_id;
3910 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3911 ctxt.info.valid_sections =
3912 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3913 ICE_AQ_VSI_PROP_SECURITY_VALID);
3914 ctxt.vsi_num = vsi->vsi_id;
3916 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3918 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3919 on ? "enable" : "disable");
3922 vsi->info.valid_sections |=
3923 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3924 ICE_AQ_VSI_PROP_SECURITY_VALID);
3927 /* consist with other drivers, allow untagged packet when vlan filter on */
3929 ret = ice_add_vlan_filter(vsi, 0);
3931 ret = ice_remove_vlan_filter(vsi, 0);
3937 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3939 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3940 struct ice_vsi_ctx ctxt;
3944 /* Check if it has been already on or off */
3945 if (vsi->info.valid_sections &
3946 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3948 if ((vsi->info.vlan_flags &
3949 ICE_AQ_VSI_VLAN_EMOD_M) ==
3950 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3951 return 0; /* already on */
3953 if ((vsi->info.vlan_flags &
3954 ICE_AQ_VSI_VLAN_EMOD_M) ==
3955 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3956 return 0; /* already off */
3961 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3963 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3964 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3965 vsi->info.vlan_flags |= vlan_flags;
3966 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3967 ctxt.info.valid_sections =
3968 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3969 ctxt.vsi_num = vsi->vsi_id;
3970 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3972 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3973 on ? "enable" : "disable");
3977 vsi->info.valid_sections |=
3978 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3984 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3986 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3987 struct ice_vsi *vsi = pf->main_vsi;
3988 struct rte_eth_rxmode *rxmode;
3990 rxmode = &dev->data->dev_conf.rxmode;
3991 if (mask & ETH_VLAN_FILTER_MASK) {
3992 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3993 ice_vsi_config_vlan_filter(vsi, true);
3995 ice_vsi_config_vlan_filter(vsi, false);
3998 if (mask & ETH_VLAN_STRIP_MASK) {
3999 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4000 ice_vsi_config_vlan_stripping(vsi, true);
4002 ice_vsi_config_vlan_stripping(vsi, false);
4005 if (mask & ETH_VLAN_EXTEND_MASK) {
4006 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
4007 ice_vsi_config_double_vlan(vsi, true);
4009 ice_vsi_config_double_vlan(vsi, false);
4016 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4018 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4019 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4025 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4026 ret = ice_aq_get_rss_lut(hw, vsi->idx,
4027 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4029 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4033 uint64_t *lut_dw = (uint64_t *)lut;
4034 uint16_t i, lut_size_dw = lut_size / 4;
4036 for (i = 0; i < lut_size_dw; i++)
4037 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4044 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4053 pf = ICE_VSI_TO_PF(vsi);
4054 hw = ICE_VSI_TO_HW(vsi);
4056 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4057 ret = ice_aq_set_rss_lut(hw, vsi->idx,
4058 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4060 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4064 uint64_t *lut_dw = (uint64_t *)lut;
4065 uint16_t i, lut_size_dw = lut_size / 4;
4067 for (i = 0; i < lut_size_dw; i++)
4068 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4077 ice_rss_reta_update(struct rte_eth_dev *dev,
4078 struct rte_eth_rss_reta_entry64 *reta_conf,
4081 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4082 uint16_t i, lut_size = pf->hash_lut_size;
4083 uint16_t idx, shift;
4087 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4088 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4089 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4091 "The size of hash lookup table configured (%d)"
4092 "doesn't match the number hardware can "
4093 "supported (128, 512, 2048)",
4098 /* It MUST use the current LUT size to get the RSS lookup table,
4099 * otherwise if will fail with -100 error code.
4101 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4103 PMD_DRV_LOG(ERR, "No memory can be allocated");
4106 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4110 for (i = 0; i < reta_size; i++) {
4111 idx = i / RTE_RETA_GROUP_SIZE;
4112 shift = i % RTE_RETA_GROUP_SIZE;
4113 if (reta_conf[idx].mask & (1ULL << shift))
4114 lut[i] = reta_conf[idx].reta[shift];
4116 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4117 if (ret == 0 && lut_size != reta_size) {
4119 "The size of hash lookup table is changed from (%d) to (%d)",
4120 lut_size, reta_size);
4121 pf->hash_lut_size = reta_size;
4131 ice_rss_reta_query(struct rte_eth_dev *dev,
4132 struct rte_eth_rss_reta_entry64 *reta_conf,
4135 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4136 uint16_t i, lut_size = pf->hash_lut_size;
4137 uint16_t idx, shift;
4141 if (reta_size != lut_size) {
4143 "The size of hash lookup table configured (%d)"
4144 "doesn't match the number hardware can "
4146 reta_size, lut_size);
4150 lut = rte_zmalloc(NULL, reta_size, 0);
4152 PMD_DRV_LOG(ERR, "No memory can be allocated");
4156 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4160 for (i = 0; i < reta_size; i++) {
4161 idx = i / RTE_RETA_GROUP_SIZE;
4162 shift = i % RTE_RETA_GROUP_SIZE;
4163 if (reta_conf[idx].mask & (1ULL << shift))
4164 reta_conf[idx].reta[shift] = lut[i];
4174 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4176 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4179 if (!key || key_len == 0) {
4180 PMD_DRV_LOG(DEBUG, "No key to be configured");
4182 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4184 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4188 struct ice_aqc_get_set_rss_keys *key_dw =
4189 (struct ice_aqc_get_set_rss_keys *)key;
4191 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4193 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4201 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4203 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4206 if (!key || !key_len)
4209 ret = ice_aq_get_rss_key
4211 (struct ice_aqc_get_set_rss_keys *)key);
4213 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4216 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4222 ice_rss_hash_update(struct rte_eth_dev *dev,
4223 struct rte_eth_rss_conf *rss_conf)
4225 enum ice_status status = ICE_SUCCESS;
4226 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4227 struct ice_vsi *vsi = pf->main_vsi;
4230 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4234 if (rss_conf->rss_hf == 0)
4237 /* RSS hash configuration */
4238 ice_rss_hash_set(pf, rss_conf->rss_hf);
4244 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4245 struct rte_eth_rss_conf *rss_conf)
4247 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4248 struct ice_vsi *vsi = pf->main_vsi;
4250 ice_get_rss_key(vsi, rss_conf->rss_key,
4251 &rss_conf->rss_key_len);
4253 /* TODO: default set to 0 as hf config is not supported now */
4254 rss_conf->rss_hf = 0;
4259 ice_promisc_enable(struct rte_eth_dev *dev)
4261 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4262 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4263 struct ice_vsi *vsi = pf->main_vsi;
4264 enum ice_status status;
4268 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4269 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4271 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4273 case ICE_ERR_ALREADY_EXISTS:
4274 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4278 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4286 ice_promisc_disable(struct rte_eth_dev *dev)
4288 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4289 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4290 struct ice_vsi *vsi = pf->main_vsi;
4291 enum ice_status status;
4295 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4296 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4298 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4299 if (status != ICE_SUCCESS) {
4300 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4308 ice_allmulti_enable(struct rte_eth_dev *dev)
4310 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4311 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4312 struct ice_vsi *vsi = pf->main_vsi;
4313 enum ice_status status;
4317 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4319 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4322 case ICE_ERR_ALREADY_EXISTS:
4323 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4327 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4335 ice_allmulti_disable(struct rte_eth_dev *dev)
4337 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4338 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339 struct ice_vsi *vsi = pf->main_vsi;
4340 enum ice_status status;
4344 if (dev->data->promiscuous == 1)
4345 return 0; /* must remain in all_multicast mode */
4347 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4349 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4350 if (status != ICE_SUCCESS) {
4351 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4358 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4361 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4362 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4363 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367 msix_intr = intr_handle->intr_vec[queue_id];
4369 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4370 GLINT_DYN_CTL_ITR_INDX_M;
4371 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4373 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4374 rte_intr_ack(&pci_dev->intr_handle);
4379 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4382 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4383 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4384 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387 msix_intr = intr_handle->intr_vec[queue_id];
4389 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4395 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4397 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402 ver = hw->nvm.orom.major;
4403 patch = hw->nvm.orom.patch;
4404 build = hw->nvm.orom.build;
4406 ret = snprintf(fw_version, fw_size,
4407 "%d.%d 0x%08x %d.%d.%d",
4413 /* add the size of '\0' */
4415 if (fw_size < (u32)ret)
4422 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4425 struct ice_vsi_ctx ctxt;
4426 uint8_t vlan_flags = 0;
4429 if (!vsi || !info) {
4430 PMD_DRV_LOG(ERR, "invalid parameters");
4435 vsi->info.pvid = info->config.pvid;
4437 * If insert pvid is enabled, only tagged pkts are
4438 * allowed to be sent out.
4440 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
4441 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4444 if (info->config.reject.tagged == 0)
4445 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
4447 if (info->config.reject.untagged == 0)
4448 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4450 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
4451 ICE_AQ_VSI_VLAN_MODE_M);
4452 vsi->info.vlan_flags |= vlan_flags;
4453 memset(&ctxt, 0, sizeof(ctxt));
4454 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4455 ctxt.info.valid_sections =
4456 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4457 ctxt.vsi_num = vsi->vsi_id;
4459 hw = ICE_VSI_TO_HW(vsi);
4460 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4461 if (ret != ICE_SUCCESS) {
4463 "update VSI for VLAN insert failed, err %d",
4468 vsi->info.valid_sections |=
4469 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4475 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4477 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4478 struct ice_vsi *vsi = pf->main_vsi;
4479 struct rte_eth_dev_data *data = pf->dev_data;
4480 struct ice_vsi_vlan_pvid_info info;
4483 memset(&info, 0, sizeof(info));
4486 info.config.pvid = pvid;
4488 info.config.reject.tagged =
4489 data->dev_conf.txmode.hw_vlan_reject_tagged;
4490 info.config.reject.untagged =
4491 data->dev_conf.txmode.hw_vlan_reject_untagged;
4494 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4496 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4504 ice_get_eeprom_length(struct rte_eth_dev *dev)
4506 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508 return hw->nvm.flash_size;
4512 ice_get_eeprom(struct rte_eth_dev *dev,
4513 struct rte_dev_eeprom_info *eeprom)
4515 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516 enum ice_status status = ICE_SUCCESS;
4517 uint8_t *data = eeprom->data;
4519 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4521 status = ice_acquire_nvm(hw, ICE_RES_READ);
4523 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4527 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4530 ice_release_nvm(hw);
4533 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4541 ice_stat_update_32(struct ice_hw *hw,
4549 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4553 if (new_data >= *offset)
4554 *stat = (uint64_t)(new_data - *offset);
4556 *stat = (uint64_t)((new_data +
4557 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4562 ice_stat_update_40(struct ice_hw *hw,
4571 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4572 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4578 if (new_data >= *offset)
4579 *stat = new_data - *offset;
4581 *stat = (uint64_t)((new_data +
4582 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4585 *stat &= ICE_40_BIT_MASK;
4588 /* Get all the statistics of a VSI */
4590 ice_update_vsi_stats(struct ice_vsi *vsi)
4592 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4593 struct ice_eth_stats *nes = &vsi->eth_stats;
4594 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4595 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4597 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4598 vsi->offset_loaded, &oes->rx_bytes,
4600 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4601 vsi->offset_loaded, &oes->rx_unicast,
4603 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4604 vsi->offset_loaded, &oes->rx_multicast,
4605 &nes->rx_multicast);
4606 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4607 vsi->offset_loaded, &oes->rx_broadcast,
4608 &nes->rx_broadcast);
4609 /* enlarge the limitation when rx_bytes overflowed */
4610 if (vsi->offset_loaded) {
4611 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4612 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4613 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4615 vsi->old_rx_bytes = nes->rx_bytes;
4616 /* exclude CRC bytes */
4617 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4618 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4620 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4621 &oes->rx_discards, &nes->rx_discards);
4622 /* GLV_REPC not supported */
4623 /* GLV_RMPC not supported */
4624 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4625 &oes->rx_unknown_protocol,
4626 &nes->rx_unknown_protocol);
4627 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4628 vsi->offset_loaded, &oes->tx_bytes,
4630 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4631 vsi->offset_loaded, &oes->tx_unicast,
4633 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4634 vsi->offset_loaded, &oes->tx_multicast,
4635 &nes->tx_multicast);
4636 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4637 vsi->offset_loaded, &oes->tx_broadcast,
4638 &nes->tx_broadcast);
4639 /* GLV_TDPC not supported */
4640 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4641 &oes->tx_errors, &nes->tx_errors);
4642 /* enlarge the limitation when tx_bytes overflowed */
4643 if (vsi->offset_loaded) {
4644 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4645 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4646 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4648 vsi->old_tx_bytes = nes->tx_bytes;
4649 vsi->offset_loaded = true;
4651 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4653 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4654 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4655 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4656 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4657 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4658 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4659 nes->rx_unknown_protocol);
4660 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4661 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4662 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4663 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4664 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4665 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4666 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4671 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4673 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4674 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4676 /* Get statistics of struct ice_eth_stats */
4677 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4678 GLPRT_GORCL(hw->port_info->lport),
4679 pf->offset_loaded, &os->eth.rx_bytes,
4681 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4682 GLPRT_UPRCL(hw->port_info->lport),
4683 pf->offset_loaded, &os->eth.rx_unicast,
4684 &ns->eth.rx_unicast);
4685 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4686 GLPRT_MPRCL(hw->port_info->lport),
4687 pf->offset_loaded, &os->eth.rx_multicast,
4688 &ns->eth.rx_multicast);
4689 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4690 GLPRT_BPRCL(hw->port_info->lport),
4691 pf->offset_loaded, &os->eth.rx_broadcast,
4692 &ns->eth.rx_broadcast);
4693 ice_stat_update_32(hw, PRTRPB_RDPC,
4694 pf->offset_loaded, &os->eth.rx_discards,
4695 &ns->eth.rx_discards);
4696 /* enlarge the limitation when rx_bytes overflowed */
4697 if (pf->offset_loaded) {
4698 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4699 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4700 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4702 pf->old_rx_bytes = ns->eth.rx_bytes;
4704 /* Workaround: CRC size should not be included in byte statistics,
4705 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4708 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4709 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4711 /* GLPRT_REPC not supported */
4712 /* GLPRT_RMPC not supported */
4713 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4715 &os->eth.rx_unknown_protocol,
4716 &ns->eth.rx_unknown_protocol);
4717 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4718 GLPRT_GOTCL(hw->port_info->lport),
4719 pf->offset_loaded, &os->eth.tx_bytes,
4721 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4722 GLPRT_UPTCL(hw->port_info->lport),
4723 pf->offset_loaded, &os->eth.tx_unicast,
4724 &ns->eth.tx_unicast);
4725 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4726 GLPRT_MPTCL(hw->port_info->lport),
4727 pf->offset_loaded, &os->eth.tx_multicast,
4728 &ns->eth.tx_multicast);
4729 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4730 GLPRT_BPTCL(hw->port_info->lport),
4731 pf->offset_loaded, &os->eth.tx_broadcast,
4732 &ns->eth.tx_broadcast);
4733 /* enlarge the limitation when tx_bytes overflowed */
4734 if (pf->offset_loaded) {
4735 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4736 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4737 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4739 pf->old_tx_bytes = ns->eth.tx_bytes;
4740 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4741 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4743 /* GLPRT_TEPC not supported */
4745 /* additional port specific stats */
4746 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4747 pf->offset_loaded, &os->tx_dropped_link_down,
4748 &ns->tx_dropped_link_down);
4749 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4750 pf->offset_loaded, &os->crc_errors,
4752 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4753 pf->offset_loaded, &os->illegal_bytes,
4754 &ns->illegal_bytes);
4755 /* GLPRT_ERRBC not supported */
4756 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4757 pf->offset_loaded, &os->mac_local_faults,
4758 &ns->mac_local_faults);
4759 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4760 pf->offset_loaded, &os->mac_remote_faults,
4761 &ns->mac_remote_faults);
4763 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4764 pf->offset_loaded, &os->rx_len_errors,
4765 &ns->rx_len_errors);
4767 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4768 pf->offset_loaded, &os->link_xon_rx,
4770 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4771 pf->offset_loaded, &os->link_xoff_rx,
4773 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4774 pf->offset_loaded, &os->link_xon_tx,
4776 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4777 pf->offset_loaded, &os->link_xoff_tx,
4779 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4780 GLPRT_PRC64L(hw->port_info->lport),
4781 pf->offset_loaded, &os->rx_size_64,
4783 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4784 GLPRT_PRC127L(hw->port_info->lport),
4785 pf->offset_loaded, &os->rx_size_127,
4787 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4788 GLPRT_PRC255L(hw->port_info->lport),
4789 pf->offset_loaded, &os->rx_size_255,
4791 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4792 GLPRT_PRC511L(hw->port_info->lport),
4793 pf->offset_loaded, &os->rx_size_511,
4795 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4796 GLPRT_PRC1023L(hw->port_info->lport),
4797 pf->offset_loaded, &os->rx_size_1023,
4799 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4800 GLPRT_PRC1522L(hw->port_info->lport),
4801 pf->offset_loaded, &os->rx_size_1522,
4803 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4804 GLPRT_PRC9522L(hw->port_info->lport),
4805 pf->offset_loaded, &os->rx_size_big,
4807 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4808 pf->offset_loaded, &os->rx_undersize,
4810 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4811 pf->offset_loaded, &os->rx_fragments,
4813 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4814 pf->offset_loaded, &os->rx_oversize,
4816 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4817 pf->offset_loaded, &os->rx_jabber,
4819 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4820 GLPRT_PTC64L(hw->port_info->lport),
4821 pf->offset_loaded, &os->tx_size_64,
4823 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4824 GLPRT_PTC127L(hw->port_info->lport),
4825 pf->offset_loaded, &os->tx_size_127,
4827 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4828 GLPRT_PTC255L(hw->port_info->lport),
4829 pf->offset_loaded, &os->tx_size_255,
4831 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4832 GLPRT_PTC511L(hw->port_info->lport),
4833 pf->offset_loaded, &os->tx_size_511,
4835 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4836 GLPRT_PTC1023L(hw->port_info->lport),
4837 pf->offset_loaded, &os->tx_size_1023,
4839 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4840 GLPRT_PTC1522L(hw->port_info->lport),
4841 pf->offset_loaded, &os->tx_size_1522,
4843 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4844 GLPRT_PTC9522L(hw->port_info->lport),
4845 pf->offset_loaded, &os->tx_size_big,
4848 /* GLPRT_MSPDC not supported */
4849 /* GLPRT_XEC not supported */
4851 pf->offset_loaded = true;
4854 ice_update_vsi_stats(pf->main_vsi);
4857 /* Get all statistics of a port */
4859 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4861 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4862 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4863 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4865 /* call read registers - updates values, now write them to struct */
4866 ice_read_stats_registers(pf, hw);
4868 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4869 pf->main_vsi->eth_stats.rx_multicast +
4870 pf->main_vsi->eth_stats.rx_broadcast -
4871 pf->main_vsi->eth_stats.rx_discards;
4872 stats->opackets = ns->eth.tx_unicast +
4873 ns->eth.tx_multicast +
4874 ns->eth.tx_broadcast;
4875 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4876 stats->obytes = ns->eth.tx_bytes;
4877 stats->oerrors = ns->eth.tx_errors +
4878 pf->main_vsi->eth_stats.tx_errors;
4881 stats->imissed = ns->eth.rx_discards +
4882 pf->main_vsi->eth_stats.rx_discards;
4883 stats->ierrors = ns->crc_errors +
4885 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4887 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4888 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4889 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4890 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4891 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4892 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4893 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4894 pf->main_vsi->eth_stats.rx_discards);
4895 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4896 ns->eth.rx_unknown_protocol);
4897 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4898 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4899 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4900 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4901 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4902 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4903 pf->main_vsi->eth_stats.tx_discards);
4904 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4906 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4907 ns->tx_dropped_link_down);
4908 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4909 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4911 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4912 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4913 ns->mac_local_faults);
4914 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4915 ns->mac_remote_faults);
4916 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4917 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4918 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4919 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4920 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4921 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4922 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4923 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4924 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4925 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4926 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4927 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4928 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4929 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4930 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4931 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4932 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4933 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4934 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4935 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4936 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4937 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4938 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4939 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4943 /* Reset the statistics */
4945 ice_stats_reset(struct rte_eth_dev *dev)
4947 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4948 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4950 /* Mark PF and VSI stats to update the offset, aka "reset" */
4951 pf->offset_loaded = false;
4953 pf->main_vsi->offset_loaded = false;
4955 /* read the stats, reading current register values into offset */
4956 ice_read_stats_registers(pf, hw);
4962 ice_xstats_calc_num(void)
4966 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4972 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4975 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4976 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4979 struct ice_hw_port_stats *hw_stats = &pf->stats;
4981 count = ice_xstats_calc_num();
4985 ice_read_stats_registers(pf, hw);
4992 /* Get stats from ice_eth_stats struct */
4993 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4994 xstats[count].value =
4995 *(uint64_t *)((char *)&hw_stats->eth +
4996 ice_stats_strings[i].offset);
4997 xstats[count].id = count;
5001 /* Get individiual stats from ice_hw_port struct */
5002 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5003 xstats[count].value =
5004 *(uint64_t *)((char *)hw_stats +
5005 ice_hw_port_strings[i].offset);
5006 xstats[count].id = count;
5013 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5014 struct rte_eth_xstat_name *xstats_names,
5015 __rte_unused unsigned int limit)
5017 unsigned int count = 0;
5021 return ice_xstats_calc_num();
5023 /* Note: limit checked in rte_eth_xstats_names() */
5025 /* Get stats from ice_eth_stats struct */
5026 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5027 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5028 sizeof(xstats_names[count].name));
5032 /* Get individiual stats from ice_hw_port struct */
5033 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5034 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5035 sizeof(xstats_names[count].name));
5043 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5044 enum rte_filter_type filter_type,
5045 enum rte_filter_op filter_op,
5053 switch (filter_type) {
5054 case RTE_ETH_FILTER_GENERIC:
5055 if (filter_op != RTE_ETH_FILTER_GET)
5057 *(const void **)arg = &ice_flow_ops;
5060 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5069 /* Add UDP tunneling port */
5071 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5072 struct rte_eth_udp_tunnel *udp_tunnel)
5075 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077 if (udp_tunnel == NULL)
5080 switch (udp_tunnel->prot_type) {
5081 case RTE_TUNNEL_TYPE_VXLAN:
5082 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5085 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5093 /* Delete UDP tunneling port */
5095 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5096 struct rte_eth_udp_tunnel *udp_tunnel)
5099 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5101 if (udp_tunnel == NULL)
5104 switch (udp_tunnel->prot_type) {
5105 case RTE_TUNNEL_TYPE_VXLAN:
5106 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5109 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5118 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5119 struct rte_pci_device *pci_dev)
5121 return rte_eth_dev_pci_generic_probe(pci_dev,
5122 sizeof(struct ice_adapter),
5127 ice_pci_remove(struct rte_pci_device *pci_dev)
5129 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5132 static struct rte_pci_driver rte_ice_pmd = {
5133 .id_table = pci_id_ice_map,
5134 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5135 .probe = ice_pci_probe,
5136 .remove = ice_pci_remove,
5140 * Driver initialization routine.
5141 * Invoked once at EAL init time.
5142 * Register itself as the [Poll Mode] Driver of PCI devices.
5144 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5145 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5146 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5147 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5148 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
5149 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5150 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
5151 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
5153 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5154 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5155 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5156 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5158 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5159 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5161 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5162 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);