drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "ice_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  72
  73 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  74 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  75 #define ICE_MAX_RES_DESC_NUM        1024
  76
  77 static int ice_dev_configure(struct rte_eth_dev *dev);
  78 static int ice_dev_start(struct rte_eth_dev *dev);
  79 static void ice_dev_stop(struct rte_eth_dev *dev);
  80 static int ice_dev_close(struct rte_eth_dev *dev);
  81 static int ice_dev_reset(struct rte_eth_dev *dev);
  82 static int ice_dev_info_get(struct rte_eth_dev *dev,
  83                             struct rte_eth_dev_info *dev_info);
  84 static int ice_link_update(struct rte_eth_dev *dev,
  85                            int wait_to_complete);
  86 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  87 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  88
  89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  92                                struct rte_eth_rss_reta_entry64 *reta_conf,
  93                                uint16_t reta_size);
  94 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  95                               struct rte_eth_rss_reta_entry64 *reta_conf,
  96                               uint16_t reta_size);
  97 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  98                                struct rte_eth_rss_conf *rss_conf);
  99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 100                                  struct rte_eth_rss_conf *rss_conf);
 101 static int ice_promisc_enable(struct rte_eth_dev *dev);
 102 static int ice_promisc_disable(struct rte_eth_dev *dev);
 103 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 104 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 105 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 106                                uint16_t vlan_id,
 107                                int on);
 108 static int ice_macaddr_set(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr);
 110 static int ice_macaddr_add(struct rte_eth_dev *dev,
 111                            struct rte_ether_addr *mac_addr,
 112                            __rte_unused uint32_t index,
 113                            uint32_t pool);
 114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 116                                     uint16_t queue_id);
 117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 118                                      uint16_t queue_id);
 119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 120                               size_t fw_size);
 121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 122                              uint16_t pvid, int on);
 123 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 124 static int ice_get_eeprom(struct rte_eth_dev *dev,
 125                           struct rte_dev_eeprom_info *eeprom);
 126 static int ice_stats_get(struct rte_eth_dev *dev,
 127                          struct rte_eth_stats *stats);
 128 static int ice_stats_reset(struct rte_eth_dev *dev);
 129 static int ice_xstats_get(struct rte_eth_dev *dev,
 130                           struct rte_eth_xstat *xstats, unsigned int n);
 131 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 132                                 struct rte_eth_xstat_name *xstats_names,
 133                                 unsigned int limit);
 134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 135                         enum rte_filter_type filter_type,
 136                         enum rte_filter_op filter_op,
 137                         void *arg);
 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 139                         struct rte_eth_udp_tunnel *udp_tunnel);
 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142
 143 static const struct rte_pci_id pci_id_ice_map[] = {
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 164         { .vendor_id = 0, /* sentinel */ },
 165 };
 166
 167 static const struct eth_dev_ops ice_eth_dev_ops = {
 168         .dev_configure                = ice_dev_configure,
 169         .dev_start                    = ice_dev_start,
 170         .dev_stop                     = ice_dev_stop,
 171         .dev_close                    = ice_dev_close,
 172         .dev_reset                    = ice_dev_reset,
 173         .dev_set_link_up              = ice_dev_set_link_up,
 174         .dev_set_link_down            = ice_dev_set_link_down,
 175         .rx_queue_start               = ice_rx_queue_start,
 176         .rx_queue_stop                = ice_rx_queue_stop,
 177         .tx_queue_start               = ice_tx_queue_start,
 178         .tx_queue_stop                = ice_tx_queue_stop,
 179         .rx_queue_setup               = ice_rx_queue_setup,
 180         .rx_queue_release             = ice_rx_queue_release,
 181         .tx_queue_setup               = ice_tx_queue_setup,
 182         .tx_queue_release             = ice_tx_queue_release,
 183         .dev_infos_get                = ice_dev_info_get,
 184         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 185         .link_update                  = ice_link_update,
 186         .mtu_set                      = ice_mtu_set,
 187         .mac_addr_set                 = ice_macaddr_set,
 188         .mac_addr_add                 = ice_macaddr_add,
 189         .mac_addr_remove              = ice_macaddr_remove,
 190         .vlan_filter_set              = ice_vlan_filter_set,
 191         .vlan_offload_set             = ice_vlan_offload_set,
 192         .reta_update                  = ice_rss_reta_update,
 193         .reta_query                   = ice_rss_reta_query,
 194         .rss_hash_update              = ice_rss_hash_update,
 195         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 196         .promiscuous_enable           = ice_promisc_enable,
 197         .promiscuous_disable          = ice_promisc_disable,
 198         .allmulticast_enable          = ice_allmulti_enable,
 199         .allmulticast_disable         = ice_allmulti_disable,
 200         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 201         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 202         .fw_version_get               = ice_fw_version_get,
 203         .vlan_pvid_set                = ice_vlan_pvid_set,
 204         .rxq_info_get                 = ice_rxq_info_get,
 205         .txq_info_get                 = ice_txq_info_get,
 206         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 207         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 208         .get_eeprom_length            = ice_get_eeprom_length,
 209         .get_eeprom                   = ice_get_eeprom,
 210         .stats_get                    = ice_stats_get,
 211         .stats_reset                  = ice_stats_reset,
 212         .xstats_get                   = ice_xstats_get,
 213         .xstats_get_names             = ice_xstats_get_names,
 214         .xstats_reset                 = ice_stats_reset,
 215         .filter_ctrl                  = ice_dev_filter_ctrl,
 216         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 217         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 218         .tx_done_cleanup              = ice_tx_done_cleanup,
 219 };
 220
 221 /* store statistics names and its offset in stats structure */
 222 struct ice_xstats_name_off {
 223         char name[RTE_ETH_XSTATS_NAME_SIZE];
 224         unsigned int offset;
 225 };
 226
 227 static const struct ice_xstats_name_off ice_stats_strings[] = {
 228         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 229         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 230         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 231         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 232         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 233                 rx_unknown_protocol)},
 234         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 235         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 236         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 237         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 238 };
 239
 240 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 241                 sizeof(ice_stats_strings[0]))
 242
 243 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 244         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 245                 tx_dropped_link_down)},
 246         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 247         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 248                 illegal_bytes)},
 249         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 250         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 251                 mac_local_faults)},
 252         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 253                 mac_remote_faults)},
 254         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 255                 rx_len_errors)},
 256         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 257         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 258         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 259         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 260         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 261         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 262                 rx_size_127)},
 263         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_255)},
 265         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_511)},
 267         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_1023)},
 269         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_1522)},
 271         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_big)},
 273         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 274                 rx_undersize)},
 275         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 276                 rx_oversize)},
 277         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 278                 mac_short_pkt_dropped)},
 279         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_fragments)},
 281         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 282         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 283         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 284                 tx_size_127)},
 285         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_255)},
 287         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_511)},
 289         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_1023)},
 291         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_1522)},
 293         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_big)},
 295 };
 296
 297 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 298                 sizeof(ice_hw_port_strings[0]))
 299
 300 static void
 301 ice_init_controlq_parameter(struct ice_hw *hw)
 302 {
 303         /* fields for adminq */
 304         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 305         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 306         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 307         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 308
 309         /* fields for mailboxq, DPDK used as PF host */
 310         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 311         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 312         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 313         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 314 }
 315
 316 static int
 317 lookup_proto_xtr_type(const char *xtr_name)
 318 {
 319         static struct {
 320                 const char *name;
 321                 enum proto_xtr_type type;
 322         } xtr_type_map[] = {
 323                 { "vlan",      PROTO_XTR_VLAN      },
 324                 { "ipv4",      PROTO_XTR_IPV4      },
 325                 { "ipv6",      PROTO_XTR_IPV6      },
 326                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 327                 { "tcp",       PROTO_XTR_TCP       },
 328                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 329         };
 330         uint32_t i;
 331
 332         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 333                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 334                         return xtr_type_map[i].type;
 335         }
 336
 337         return -1;
 338 }
 339
 340 /*
 341  * Parse elem, the elem could be single number/range or '(' ')' group
 342  * 1) A single number elem, it's just a simple digit. e.g. 9
 343  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 344  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 345  *    Within group elem, '-' used for a range separator;
 346  *                       ',' used for a single number.
 347  */
 348 static int
 349 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 350 {
 351         const char *str = input;
 352         char *end = NULL;
 353         uint32_t min, max;
 354         uint32_t idx;
 355
 356         while (isblank(*str))
 357                 str++;
 358
 359         if (!isdigit(*str) && *str != '(')
 360                 return -1;
 361
 362         /* process single number or single range of number */
 363         if (*str != '(') {
 364                 errno = 0;
 365                 idx = strtoul(str, &end, 10);
 366                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 367                         return -1;
 368
 369                 while (isblank(*end))
 370                         end++;
 371
 372                 min = idx;
 373                 max = idx;
 374
 375                 /* process single <number>-<number> */
 376                 if (*end == '-') {
 377                         end++;
 378                         while (isblank(*end))
 379                                 end++;
 380                         if (!isdigit(*end))
 381                                 return -1;
 382
 383                         errno = 0;
 384                         idx = strtoul(end, &end, 10);
 385                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 386                                 return -1;
 387
 388                         max = idx;
 389                         while (isblank(*end))
 390                                 end++;
 391                 }
 392
 393                 if (*end != ':')
 394                         return -1;
 395
 396                 for (idx = RTE_MIN(min, max);
 397                      idx <= RTE_MAX(min, max); idx++)
 398                         devargs->proto_xtr[idx] = xtr_type;
 399
 400                 return 0;
 401         }
 402
 403         /* process set within bracket */
 404         str++;
 405         while (isblank(*str))
 406                 str++;
 407         if (*str == '\0')
 408                 return -1;
 409
 410         min = ICE_MAX_QUEUE_NUM;
 411         do {
 412                 /* go ahead to the first digit */
 413                 while (isblank(*str))
 414                         str++;
 415                 if (!isdigit(*str))
 416                         return -1;
 417
 418                 /* get the digit value */
 419                 errno = 0;
 420                 idx = strtoul(str, &end, 10);
 421                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 422                         return -1;
 423
 424                 /* go ahead to separator '-',',' and ')' */
 425                 while (isblank(*end))
 426                         end++;
 427                 if (*end == '-') {
 428                         if (min == ICE_MAX_QUEUE_NUM)
 429                                 min = idx;
 430                         else /* avoid continuous '-' */
 431                                 return -1;
 432                 } else if (*end == ',' || *end == ')') {
 433                         max = idx;
 434                         if (min == ICE_MAX_QUEUE_NUM)
 435                                 min = idx;
 436
 437                         for (idx = RTE_MIN(min, max);
 438                              idx <= RTE_MAX(min, max); idx++)
 439                                 devargs->proto_xtr[idx] = xtr_type;
 440
 441                         min = ICE_MAX_QUEUE_NUM;
 442                 } else {
 443                         return -1;
 444                 }
 445
 446                 str = end + 1;
 447         } while (*end != ')' && *end != '\0');
 448
 449         return 0;
 450 }
 451
 452 static int
 453 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 454 {
 455         const char *queue_start;
 456         uint32_t idx;
 457         int xtr_type;
 458         char xtr_name[32];
 459
 460         while (isblank(*queues))
 461                 queues++;
 462
 463         if (*queues != '[') {
 464                 xtr_type = lookup_proto_xtr_type(queues);
 465                 if (xtr_type < 0)
 466                         return -1;
 467
 468                 devargs->proto_xtr_dflt = xtr_type;
 469
 470                 return 0;
 471         }
 472
 473         queues++;
 474         do {
 475                 while (isblank(*queues))
 476                         queues++;
 477                 if (*queues == '\0')
 478                         return -1;
 479
 480                 queue_start = queues;
 481
 482                 /* go across a complete bracket */
 483                 if (*queue_start == '(') {
 484                         queues += strcspn(queues, ")");
 485                         if (*queues != ')')
 486                                 return -1;
 487                 }
 488
 489                 /* scan the separator ':' */
 490                 queues += strcspn(queues, ":");
 491                 if (*queues++ != ':')
 492                         return -1;
 493                 while (isblank(*queues))
 494                         queues++;
 495
 496                 for (idx = 0; ; idx++) {
 497                         if (isblank(queues[idx]) ||
 498                             queues[idx] == ',' ||
 499                             queues[idx] == ']' ||
 500                             queues[idx] == '\0')
 501                                 break;
 502
 503                         if (idx > sizeof(xtr_name) - 2)
 504                                 return -1;
 505
 506                         xtr_name[idx] = queues[idx];
 507                 }
 508                 xtr_name[idx] = '\0';
 509                 xtr_type = lookup_proto_xtr_type(xtr_name);
 510                 if (xtr_type < 0)
 511                         return -1;
 512
 513                 queues += idx;
 514
 515                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 516                         queues++;
 517
 518                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 519                         return -1;
 520         } while (*queues != '\0');
 521
 522         return 0;
 523 }
 524
 525 static int
 526 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 527                      void *extra_args)
 528 {
 529         struct ice_devargs *devargs = extra_args;
 530
 531         if (value == NULL || extra_args == NULL)
 532                 return -EINVAL;
 533
 534         if (parse_queue_proto_xtr(value, devargs) < 0) {
 535                 PMD_DRV_LOG(ERR,
 536                             "The protocol extraction parameter is wrong : '%s'",
 537                             value);
 538                 return -1;
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 ice_check_proto_xtr_support(struct ice_hw *hw)
 546 {
 547 #define FLX_REG(val, fld, idx) \
 548         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 549          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 550         static struct {
 551                 uint32_t rxdid;
 552                 uint8_t opcode;
 553                 uint8_t protid_0;
 554                 uint8_t protid_1;
 555         } xtr_sets[] = {
 556                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 557                                      ICE_RX_OPC_EXTRACT,
 558                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 559                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 560                                      ICE_RX_OPC_EXTRACT,
 561                                      ICE_PROT_IPV4_OF_OR_S,
 562                                      ICE_PROT_IPV4_OF_OR_S },
 563                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 564                                      ICE_RX_OPC_EXTRACT,
 565                                      ICE_PROT_IPV6_OF_OR_S,
 566                                      ICE_PROT_IPV6_OF_OR_S },
 567                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 568                                           ICE_RX_OPC_EXTRACT,
 569                                           ICE_PROT_IPV6_OF_OR_S,
 570                                           ICE_PROT_IPV6_OF_OR_S },
 571                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 572                                     ICE_RX_OPC_EXTRACT,
 573                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 574                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 575                                           ICE_RX_OPC_PROTID,
 576                                           ICE_PROT_IPV4_OF_OR_S,
 577                                           ICE_PROT_IPV6_OF_OR_S },
 578         };
 579         uint32_t i;
 580
 581         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 582                 uint32_t rxdid = xtr_sets[i].rxdid;
 583                 uint32_t v;
 584
 585                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 586                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 587
 588                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 589                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 590                                 ice_proto_xtr_hw_support[i] = true;
 591                 }
 592
 593                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 594                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 595
 596                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 597                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 598                                 ice_proto_xtr_hw_support[i] = true;
 599                 }
 600         }
 601 }
 602
 603 static int
 604 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 605                   uint32_t num)
 606 {
 607         struct pool_entry *entry;
 608
 609         if (!pool || !num)
 610                 return -EINVAL;
 611
 612         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 613         if (!entry) {
 614                 PMD_INIT_LOG(ERR,
 615                              "Failed to allocate memory for resource pool");
 616                 return -ENOMEM;
 617         }
 618
 619         /* queue heap initialize */
 620         pool->num_free = num;
 621         pool->num_alloc = 0;
 622         pool->base = base;
 623         LIST_INIT(&pool->alloc_list);
 624         LIST_INIT(&pool->free_list);
 625
 626         /* Initialize element  */
 627         entry->base = 0;
 628         entry->len = num;
 629
 630         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 631         return 0;
 632 }
 633
 634 static int
 635 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 636                    uint16_t num)
 637 {
 638         struct pool_entry *entry, *valid_entry;
 639
 640         if (!pool || !num) {
 641                 PMD_INIT_LOG(ERR, "Invalid parameter");
 642                 return -EINVAL;
 643         }
 644
 645         if (pool->num_free < num) {
 646                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 647                              num, pool->num_free);
 648                 return -ENOMEM;
 649         }
 650
 651         valid_entry = NULL;
 652         /* Lookup  in free list and find most fit one */
 653         LIST_FOREACH(entry, &pool->free_list, next) {
 654                 if (entry->len >= num) {
 655                         /* Find best one */
 656                         if (entry->len == num) {
 657                                 valid_entry = entry;
 658                                 break;
 659                         }
 660                         if (!valid_entry ||
 661                             valid_entry->len > entry->len)
 662                                 valid_entry = entry;
 663                 }
 664         }
 665
 666         /* Not find one to satisfy the request, return */
 667         if (!valid_entry) {
 668                 PMD_INIT_LOG(ERR, "No valid entry found");
 669                 return -ENOMEM;
 670         }
 671         /**
 672          * The entry have equal queue number as requested,
 673          * remove it from alloc_list.
 674          */
 675         if (valid_entry->len == num) {
 676                 LIST_REMOVE(valid_entry, next);
 677         } else {
 678                 /**
 679                  * The entry have more numbers than requested,
 680                  * create a new entry for alloc_list and minus its
 681                  * queue base and number in free_list.
 682                  */
 683                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 684                 if (!entry) {
 685                         PMD_INIT_LOG(ERR,
 686                                      "Failed to allocate memory for "
 687                                      "resource pool");
 688                         return -ENOMEM;
 689                 }
 690                 entry->base = valid_entry->base;
 691                 entry->len = num;
 692                 valid_entry->base += num;
 693                 valid_entry->len -= num;
 694                 valid_entry = entry;
 695         }
 696
 697         /* Insert it into alloc list, not sorted */
 698         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 699
 700         pool->num_free -= valid_entry->len;
 701         pool->num_alloc += valid_entry->len;
 702
 703         return valid_entry->base + pool->base;
 704 }
 705
 706 static void
 707 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 708 {
 709         struct pool_entry *entry, *next_entry;
 710
 711         if (!pool)
 712                 return;
 713
 714         for (entry = LIST_FIRST(&pool->alloc_list);
 715              entry && (next_entry = LIST_NEXT(entry, next), 1);
 716              entry = next_entry) {
 717                 LIST_REMOVE(entry, next);
 718                 rte_free(entry);
 719         }
 720
 721         for (entry = LIST_FIRST(&pool->free_list);
 722              entry && (next_entry = LIST_NEXT(entry, next), 1);
 723              entry = next_entry) {
 724                 LIST_REMOVE(entry, next);
 725                 rte_free(entry);
 726         }
 727
 728         pool->num_free = 0;
 729         pool->num_alloc = 0;
 730         pool->base = 0;
 731         LIST_INIT(&pool->alloc_list);
 732         LIST_INIT(&pool->free_list);
 733 }
 734
 735 static void
 736 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 737 {
 738         /* Set VSI LUT selection */
 739         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 740                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 741         /* Set Hash scheme */
 742         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 743                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 744         /* enable TC */
 745         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 746 }
 747
 748 static enum ice_status
 749 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 750                                 struct ice_aqc_vsi_props *info,
 751                                 uint8_t enabled_tcmap)
 752 {
 753         uint16_t bsf, qp_idx;
 754
 755         /* default tc 0 now. Multi-TC supporting need to be done later.
 756          * Configure TC and queue mapping parameters, for enabled TC,
 757          * allocate qpnum_per_tc queues to this traffic.
 758          */
 759         if (enabled_tcmap != 0x01) {
 760                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 761                 return -ENOTSUP;
 762         }
 763
 764         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 765         bsf = rte_bsf32(vsi->nb_qps);
 766         /* Adjust the queue number to actual queues that can be applied */
 767         vsi->nb_qps = 0x1 << bsf;
 768
 769         qp_idx = 0;
 770         /* Set tc and queue mapping with VSI */
 771         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 772                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 773                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 774
 775         /* Associate queue number with VSI */
 776         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 777         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 778         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 779         info->valid_sections |=
 780                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 781         /* Set the info.ingress_table and info.egress_table
 782          * for UP translate table. Now just set it to 1:1 map by default
 783          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 784          */
 785 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 786         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 787         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 788         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 789         return 0;
 790 }
 791
 792 static int
 793 ice_init_mac_address(struct rte_eth_dev *dev)
 794 {
 795         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 796
 797         if (!rte_is_unicast_ether_addr
 798                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 799                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 800                 return -EINVAL;
 801         }
 802
 803         rte_ether_addr_copy(
 804                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 805                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 806
 807         dev->data->mac_addrs =
 808                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 809         if (!dev->data->mac_addrs) {
 810                 PMD_INIT_LOG(ERR,
 811                              "Failed to allocate memory to store mac address");
 812                 return -ENOMEM;
 813         }
 814         /* store it to dev data */
 815         rte_ether_addr_copy(
 816                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 817                 &dev->data->mac_addrs[0]);
 818         return 0;
 819 }
 820
 821 /* Find out specific MAC filter */
 822 static struct ice_mac_filter *
 823 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 824 {
 825         struct ice_mac_filter *f;
 826
 827         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 828                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 829                         return f;
 830         }
 831
 832         return NULL;
 833 }
 834
 835 static int
 836 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 837 {
 838         struct ice_fltr_list_entry *m_list_itr = NULL;
 839         struct ice_mac_filter *f;
 840         struct LIST_HEAD_TYPE list_head;
 841         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 842         int ret = 0;
 843
 844         /* If it's added and configured, return */
 845         f = ice_find_mac_filter(vsi, mac_addr);
 846         if (f) {
 847                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 848                 return 0;
 849         }
 850
 851         INIT_LIST_HEAD(&list_head);
 852
 853         m_list_itr = (struct ice_fltr_list_entry *)
 854                 ice_malloc(hw, sizeof(*m_list_itr));
 855         if (!m_list_itr) {
 856                 ret = -ENOMEM;
 857                 goto DONE;
 858         }
 859         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 860                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 861         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 862         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 863         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 864         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 865         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 866
 867         LIST_ADD(&m_list_itr->list_entry, &list_head);
 868
 869         /* Add the mac */
 870         ret = ice_add_mac(hw, &list_head);
 871         if (ret != ICE_SUCCESS) {
 872                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 873                 ret = -EINVAL;
 874                 goto DONE;
 875         }
 876         /* Add the mac addr into mac list */
 877         f = rte_zmalloc(NULL, sizeof(*f), 0);
 878         if (!f) {
 879                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 880                 ret = -ENOMEM;
 881                 goto DONE;
 882         }
 883         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 884         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 885         vsi->mac_num++;
 886
 887         ret = 0;
 888
 889 DONE:
 890         rte_free(m_list_itr);
 891         return ret;
 892 }
 893
 894 static int
 895 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 896 {
 897         struct ice_fltr_list_entry *m_list_itr = NULL;
 898         struct ice_mac_filter *f;
 899         struct LIST_HEAD_TYPE list_head;
 900         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 901         int ret = 0;
 902
 903         /* Can't find it, return an error */
 904         f = ice_find_mac_filter(vsi, mac_addr);
 905         if (!f)
 906                 return -EINVAL;
 907
 908         INIT_LIST_HEAD(&list_head);
 909
 910         m_list_itr = (struct ice_fltr_list_entry *)
 911                 ice_malloc(hw, sizeof(*m_list_itr));
 912         if (!m_list_itr) {
 913                 ret = -ENOMEM;
 914                 goto DONE;
 915         }
 916         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 917                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 918         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 919         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 920         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 921         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 922         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 923
 924         LIST_ADD(&m_list_itr->list_entry, &list_head);
 925
 926         /* remove the mac filter */
 927         ret = ice_remove_mac(hw, &list_head);
 928         if (ret != ICE_SUCCESS) {
 929                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 930                 ret = -EINVAL;
 931                 goto DONE;
 932         }
 933
 934         /* Remove the mac addr from mac list */
 935         TAILQ_REMOVE(&vsi->mac_list, f, next);
 936         rte_free(f);
 937         vsi->mac_num--;
 938
 939         ret = 0;
 940 DONE:
 941         rte_free(m_list_itr);
 942         return ret;
 943 }
 944
 945 /* Find out specific VLAN filter */
 946 static struct ice_vlan_filter *
 947 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 948 {
 949         struct ice_vlan_filter *f;
 950
 951         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 952                 if (vlan_id == f->vlan_info.vlan_id)
 953                         return f;
 954         }
 955
 956         return NULL;
 957 }
 958
 959 static int
 960 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 961 {
 962         struct ice_fltr_list_entry *v_list_itr = NULL;
 963         struct ice_vlan_filter *f;
 964         struct LIST_HEAD_TYPE list_head;
 965         struct ice_hw *hw;
 966         int ret = 0;
 967
 968         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 969                 return -EINVAL;
 970
 971         hw = ICE_VSI_TO_HW(vsi);
 972
 973         /* If it's added and configured, return. */
 974         f = ice_find_vlan_filter(vsi, vlan_id);
 975         if (f) {
 976                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 977                 return 0;
 978         }
 979
 980         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 981                 return 0;
 982
 983         INIT_LIST_HEAD(&list_head);
 984
 985         v_list_itr = (struct ice_fltr_list_entry *)
 986                       ice_malloc(hw, sizeof(*v_list_itr));
 987         if (!v_list_itr) {
 988                 ret = -ENOMEM;
 989                 goto DONE;
 990         }
 991         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 992         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 993         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 994         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 995         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 996         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 997
 998         LIST_ADD(&v_list_itr->list_entry, &list_head);
 999
1000         /* Add the vlan */
1001         ret = ice_add_vlan(hw, &list_head);
1002         if (ret != ICE_SUCCESS) {
1003                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1004                 ret = -EINVAL;
1005                 goto DONE;
1006         }
1007
1008         /* Add vlan into vlan list */
1009         f = rte_zmalloc(NULL, sizeof(*f), 0);
1010         if (!f) {
1011                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1012                 ret = -ENOMEM;
1013                 goto DONE;
1014         }
1015         f->vlan_info.vlan_id = vlan_id;
1016         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1017         vsi->vlan_num++;
1018
1019         ret = 0;
1020
1021 DONE:
1022         rte_free(v_list_itr);
1023         return ret;
1024 }
1025
1026 static int
1027 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1028 {
1029         struct ice_fltr_list_entry *v_list_itr = NULL;
1030         struct ice_vlan_filter *f;
1031         struct LIST_HEAD_TYPE list_head;
1032         struct ice_hw *hw;
1033         int ret = 0;
1034
1035         /**
1036          * Vlan 0 is the generic filter for untagged packets
1037          * and can't be removed.
1038          */
1039         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1040                 return -EINVAL;
1041
1042         hw = ICE_VSI_TO_HW(vsi);
1043
1044         /* Can't find it, return an error */
1045         f = ice_find_vlan_filter(vsi, vlan_id);
1046         if (!f)
1047                 return -EINVAL;
1048
1049         INIT_LIST_HEAD(&list_head);
1050
1051         v_list_itr = (struct ice_fltr_list_entry *)
1052                       ice_malloc(hw, sizeof(*v_list_itr));
1053         if (!v_list_itr) {
1054                 ret = -ENOMEM;
1055                 goto DONE;
1056         }
1057
1058         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1059         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1060         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1061         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1062         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1063         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1064
1065         LIST_ADD(&v_list_itr->list_entry, &list_head);
1066
1067         /* remove the vlan filter */
1068         ret = ice_remove_vlan(hw, &list_head);
1069         if (ret != ICE_SUCCESS) {
1070                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1071                 ret = -EINVAL;
1072                 goto DONE;
1073         }
1074
1075         /* Remove the vlan id from vlan list */
1076         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1077         rte_free(f);
1078         vsi->vlan_num--;
1079
1080         ret = 0;
1081 DONE:
1082         rte_free(v_list_itr);
1083         return ret;
1084 }
1085
1086 static int
1087 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1088 {
1089         struct ice_mac_filter *m_f;
1090         struct ice_vlan_filter *v_f;
1091         int ret = 0;
1092
1093         if (!vsi || !vsi->mac_num)
1094                 return -EINVAL;
1095
1096         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1097                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1098                 if (ret != ICE_SUCCESS) {
1099                         ret = -EINVAL;
1100                         goto DONE;
1101                 }
1102         }
1103
1104         if (vsi->vlan_num == 0)
1105                 return 0;
1106
1107         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1108                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1109                 if (ret != ICE_SUCCESS) {
1110                         ret = -EINVAL;
1111                         goto DONE;
1112                 }
1113         }
1114
1115 DONE:
1116         return ret;
1117 }
1118
1119 static int
1120 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1121 {
1122         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1123         struct ice_vsi_ctx ctxt;
1124         uint8_t qinq_flags;
1125         int ret = 0;
1126
1127         /* Check if it has been already on or off */
1128         if (vsi->info.valid_sections &
1129                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1130                 if (on) {
1131                         if ((vsi->info.outer_tag_flags &
1132                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1133                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1134                                 return 0; /* already on */
1135                 } else {
1136                         if (!(vsi->info.outer_tag_flags &
1137                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1138                                 return 0; /* already off */
1139                 }
1140         }
1141
1142         if (on)
1143                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1144         else
1145                 qinq_flags = 0;
1146         /* clear global insertion and use per packet insertion */
1147         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1148         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1149         vsi->info.outer_tag_flags |= qinq_flags;
1150         /* use default vlan type 0x8100 */
1151         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1152         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1153                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1154         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1155         ctxt.info.valid_sections =
1156                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1157         ctxt.vsi_num = vsi->vsi_id;
1158         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1159         if (ret) {
1160                 PMD_DRV_LOG(INFO,
1161                             "Update VSI failed to %s qinq stripping",
1162                             on ? "enable" : "disable");
1163                 return -EINVAL;
1164         }
1165
1166         vsi->info.valid_sections |=
1167                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1168
1169         return ret;
1170 }
1171
1172 static int
1173 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1174 {
1175         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1176         struct ice_vsi_ctx ctxt;
1177         uint8_t qinq_flags;
1178         int ret = 0;
1179
1180         /* Check if it has been already on or off */
1181         if (vsi->info.valid_sections &
1182                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1183                 if (on) {
1184                         if ((vsi->info.outer_tag_flags &
1185                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1186                             ICE_AQ_VSI_OUTER_TAG_COPY)
1187                                 return 0; /* already on */
1188                 } else {
1189                         if ((vsi->info.outer_tag_flags &
1190                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1191                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1192                                 return 0; /* already off */
1193                 }
1194         }
1195
1196         if (on)
1197                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1198         else
1199                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1200         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1201         vsi->info.outer_tag_flags |= qinq_flags;
1202         /* use default vlan type 0x8100 */
1203         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1204         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1205                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1206         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1207         ctxt.info.valid_sections =
1208                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1209         ctxt.vsi_num = vsi->vsi_id;
1210         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1211         if (ret) {
1212                 PMD_DRV_LOG(INFO,
1213                             "Update VSI failed to %s qinq stripping",
1214                             on ? "enable" : "disable");
1215                 return -EINVAL;
1216         }
1217
1218         vsi->info.valid_sections |=
1219                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1220
1221         return ret;
1222 }
1223
1224 static int
1225 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1226 {
1227         int ret;
1228
1229         ret = ice_vsi_config_qinq_stripping(vsi, on);
1230         if (ret)
1231                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1232
1233         ret = ice_vsi_config_qinq_insertion(vsi, on);
1234         if (ret)
1235                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1236
1237         return ret;
1238 }
1239
1240 /* Enable IRQ0 */
1241 static void
1242 ice_pf_enable_irq0(struct ice_hw *hw)
1243 {
1244         /* reset the registers */
1245         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1246         ICE_READ_REG(hw, PFINT_OICR);
1247
1248 #ifdef ICE_LSE_SPT
1249         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1250                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1251                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1252
1253         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1254                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1255                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1256                        PFINT_OICR_CTL_ITR_INDX_M) |
1257                       PFINT_OICR_CTL_CAUSE_ENA_M);
1258
1259         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1260                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1261                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1262                        PFINT_FW_CTL_ITR_INDX_M) |
1263                       PFINT_FW_CTL_CAUSE_ENA_M);
1264 #else
1265         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1266 #endif
1267
1268         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1269                       GLINT_DYN_CTL_INTENA_M |
1270                       GLINT_DYN_CTL_CLEARPBA_M |
1271                       GLINT_DYN_CTL_ITR_INDX_M);
1272
1273         ice_flush(hw);
1274 }
1275
1276 /* Disable IRQ0 */
1277 static void
1278 ice_pf_disable_irq0(struct ice_hw *hw)
1279 {
1280         /* Disable all interrupt types */
1281         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1282         ice_flush(hw);
1283 }
1284
1285 #ifdef ICE_LSE_SPT
1286 static void
1287 ice_handle_aq_msg(struct rte_eth_dev *dev)
1288 {
1289         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         struct ice_ctl_q_info *cq = &hw->adminq;
1291         struct ice_rq_event_info event;
1292         uint16_t pending, opcode;
1293         int ret;
1294
1295         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1296         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1297         if (!event.msg_buf) {
1298                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1299                 return;
1300         }
1301
1302         pending = 1;
1303         while (pending) {
1304                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1305
1306                 if (ret != ICE_SUCCESS) {
1307                         PMD_DRV_LOG(INFO,
1308                                     "Failed to read msg from AdminQ, "
1309                                     "adminq_err: %u",
1310                                     hw->adminq.sq_last_status);
1311                         break;
1312                 }
1313                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1314
1315                 switch (opcode) {
1316                 case ice_aqc_opc_get_link_status:
1317                         ret = ice_link_update(dev, 0);
1318                         if (!ret)
1319                                 rte_eth_dev_callback_process
1320                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1321                         break;
1322                 default:
1323                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1324                                     opcode);
1325                         break;
1326                 }
1327         }
1328         rte_free(event.msg_buf);
1329 }
1330 #endif
1331
1332 /**
1333  * Interrupt handler triggered by NIC for handling
1334  * specific interrupt.
1335  *
1336  * @param handle
1337  *  Pointer to interrupt handle.
1338  * @param param
1339  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1340  *
1341  * @return
1342  *  void
1343  */
1344 static void
1345 ice_interrupt_handler(void *param)
1346 {
1347         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1348         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         uint32_t oicr;
1350         uint32_t reg;
1351         uint8_t pf_num;
1352         uint8_t event;
1353         uint16_t queue;
1354         int ret;
1355 #ifdef ICE_LSE_SPT
1356         uint32_t int_fw_ctl;
1357 #endif
1358
1359         /* Disable interrupt */
1360         ice_pf_disable_irq0(hw);
1361
1362         /* read out interrupt causes */
1363         oicr = ICE_READ_REG(hw, PFINT_OICR);
1364 #ifdef ICE_LSE_SPT
1365         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1366 #endif
1367
1368         /* No interrupt event indicated */
1369         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1370                 PMD_DRV_LOG(INFO, "No interrupt event");
1371                 goto done;
1372         }
1373
1374 #ifdef ICE_LSE_SPT
1375         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1376                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1377                 ice_handle_aq_msg(dev);
1378         }
1379 #else
1380         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1381                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1382                 ret = ice_link_update(dev, 0);
1383                 if (!ret)
1384                         rte_eth_dev_callback_process
1385                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1386         }
1387 #endif
1388
1389         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1390                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1391                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1392                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1393                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1394                                  GL_MDET_TX_PQM_PF_NUM_S;
1395                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1396                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1397                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1398                                 GL_MDET_TX_PQM_QNUM_S;
1399
1400                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1401                                     "%d by PQM on TX queue %d PF# %d",
1402                                     event, queue, pf_num);
1403                 }
1404
1405                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1406                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1407                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1408                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1409                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1410                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1411                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1412                                 GL_MDET_TX_TCLAN_QNUM_S;
1413
1414                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1415                                     "%d by TCLAN on TX queue %d PF# %d",
1416                                     event, queue, pf_num);
1417                 }
1418         }
1419 done:
1420         /* Enable interrupt */
1421         ice_pf_enable_irq0(hw);
1422         rte_intr_ack(dev->intr_handle);
1423 }
1424
1425 static void
1426 ice_init_proto_xtr(struct rte_eth_dev *dev)
1427 {
1428         struct ice_adapter *ad =
1429                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1430         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1432         const struct proto_xtr_ol_flag *ol_flag;
1433         bool proto_xtr_enable = false;
1434         int offset;
1435         uint16_t i;
1436
1437         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1438         if (unlikely(pf->proto_xtr == NULL)) {
1439                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1440                 return;
1441         }
1442
1443         for (i = 0; i < pf->lan_nb_qps; i++) {
1444                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1445                                    ad->devargs.proto_xtr[i] :
1446                                    ad->devargs.proto_xtr_dflt;
1447
1448                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1449                         uint8_t type = pf->proto_xtr[i];
1450
1451                         ice_proto_xtr_ol_flag_params[type].required = true;
1452                         proto_xtr_enable = true;
1453                 }
1454         }
1455
1456         if (likely(!proto_xtr_enable))
1457                 return;
1458
1459         ice_check_proto_xtr_support(hw);
1460
1461         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1462         if (unlikely(offset == -1)) {
1463                 PMD_DRV_LOG(ERR,
1464                             "Protocol extraction metadata is disabled in mbuf with error %d",
1465                             -rte_errno);
1466                 return;
1467         }
1468
1469         PMD_DRV_LOG(DEBUG,
1470                     "Protocol extraction metadata offset in mbuf is : %d",
1471                     offset);
1472         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1473
1474         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1475                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1476
1477                 if (!ol_flag->required)
1478                         continue;
1479
1480                 if (!ice_proto_xtr_hw_support[i]) {
1481                         PMD_DRV_LOG(ERR,
1482                                     "Protocol extraction type %u is not supported in hardware",
1483                                     i);
1484                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1485                         break;
1486                 }
1487
1488                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1489                 if (unlikely(offset == -1)) {
1490                         PMD_DRV_LOG(ERR,
1491                                     "Protocol extraction offload '%s' failed to register with error %d",
1492                                     ol_flag->param.name, -rte_errno);
1493
1494                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1495                         break;
1496                 }
1497
1498                 PMD_DRV_LOG(DEBUG,
1499                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1500                             ol_flag->param.name, offset);
1501                 *ol_flag->ol_flag = 1ULL << offset;
1502         }
1503 }
1504
1505 /*  Initialize SW parameters of PF */
1506 static int
1507 ice_pf_sw_init(struct rte_eth_dev *dev)
1508 {
1509         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1510         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1511
1512         pf->lan_nb_qp_max =
1513                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1514                                   hw->func_caps.common_cap.num_rxq);
1515
1516         pf->lan_nb_qps = pf->lan_nb_qp_max;
1517
1518         ice_init_proto_xtr(dev);
1519
1520         if (hw->func_caps.fd_fltr_guar > 0 ||
1521             hw->func_caps.fd_fltr_best_effort > 0) {
1522                 pf->flags |= ICE_FLAG_FDIR;
1523                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1524                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1525         } else {
1526                 pf->fdir_nb_qps = 0;
1527         }
1528         pf->fdir_qp_offset = 0;
1529
1530         return 0;
1531 }
1532
1533 struct ice_vsi *
1534 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1535 {
1536         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1537         struct ice_vsi *vsi = NULL;
1538         struct ice_vsi_ctx vsi_ctx;
1539         int ret;
1540         struct rte_ether_addr broadcast = {
1541                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1542         struct rte_ether_addr mac_addr;
1543         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1544         uint8_t tc_bitmap = 0x1;
1545         uint16_t cfg;
1546
1547         /* hw->num_lports = 1 in NIC mode */
1548         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1549         if (!vsi)
1550                 return NULL;
1551
1552         vsi->idx = pf->next_vsi_idx;
1553         pf->next_vsi_idx++;
1554         vsi->type = type;
1555         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1556         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1557         vsi->vlan_anti_spoof_on = 0;
1558         vsi->vlan_filter_on = 1;
1559         TAILQ_INIT(&vsi->mac_list);
1560         TAILQ_INIT(&vsi->vlan_list);
1561
1562         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1563         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1564                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1565                         hw->func_caps.common_cap.rss_table_size;
1566         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1567
1568         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1569         switch (type) {
1570         case ICE_VSI_PF:
1571                 vsi->nb_qps = pf->lan_nb_qps;
1572                 vsi->base_queue = 1;
1573                 ice_vsi_config_default_rss(&vsi_ctx.info);
1574                 vsi_ctx.alloc_from_pool = true;
1575                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1576                 /* switch_id is queried by get_switch_config aq, which is done
1577                  * by ice_init_hw
1578                  */
1579                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1580                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1581                 /* Allow all untagged or tagged packets */
1582                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1583                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1584                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1585                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1586
1587                 /* FDIR */
1588                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1589                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1590                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1591                 cfg = ICE_AQ_VSI_FD_ENABLE;
1592                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1593                 vsi_ctx.info.max_fd_fltr_dedicated =
1594                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1595                 vsi_ctx.info.max_fd_fltr_shared =
1596                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1597
1598                 /* Enable VLAN/UP trip */
1599                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1600                                                       &vsi_ctx.info,
1601                                                       ICE_DEFAULT_TCMAP);
1602                 if (ret) {
1603                         PMD_INIT_LOG(ERR,
1604                                      "tc queue mapping with vsi failed, "
1605                                      "err = %d",
1606                                      ret);
1607                         goto fail_mem;
1608                 }
1609
1610                 break;
1611         case ICE_VSI_CTRL:
1612                 vsi->nb_qps = pf->fdir_nb_qps;
1613                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1614                 vsi_ctx.alloc_from_pool = true;
1615                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1616
1617                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1618                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1619                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1620                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1621                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1622                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1623                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1624                                                       &vsi_ctx.info,
1625                                                       ICE_DEFAULT_TCMAP);
1626                 if (ret) {
1627                         PMD_INIT_LOG(ERR,
1628                                      "tc queue mapping with vsi failed, "
1629                                      "err = %d",
1630                                      ret);
1631                         goto fail_mem;
1632                 }
1633                 break;
1634         default:
1635                 /* for other types of VSI */
1636                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1637                 goto fail_mem;
1638         }
1639
1640         /* VF has MSIX interrupt in VF range, don't allocate here */
1641         if (type == ICE_VSI_PF) {
1642                 ret = ice_res_pool_alloc(&pf->msix_pool,
1643                                          RTE_MIN(vsi->nb_qps,
1644                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1645                 if (ret < 0) {
1646                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1647                                      vsi->vsi_id, ret);
1648                 }
1649                 vsi->msix_intr = ret;
1650                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1651         } else if (type == ICE_VSI_CTRL) {
1652                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1653                 if (ret < 0) {
1654                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1655                                     vsi->vsi_id, ret);
1656                 }
1657                 vsi->msix_intr = ret;
1658                 vsi->nb_msix = 1;
1659         } else {
1660                 vsi->msix_intr = 0;
1661                 vsi->nb_msix = 0;
1662         }
1663         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1664         if (ret != ICE_SUCCESS) {
1665                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1666                 goto fail_mem;
1667         }
1668         /* store vsi information is SW structure */
1669         vsi->vsi_id = vsi_ctx.vsi_num;
1670         vsi->info = vsi_ctx.info;
1671         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1672         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1673
1674         if (type == ICE_VSI_PF) {
1675                 /* MAC configuration */
1676                 rte_ether_addr_copy((struct rte_ether_addr *)
1677                                         hw->port_info->mac.perm_addr,
1678                                     &pf->dev_addr);
1679
1680                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1681                 ret = ice_add_mac_filter(vsi, &mac_addr);
1682                 if (ret != ICE_SUCCESS)
1683                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1684
1685                 rte_ether_addr_copy(&broadcast, &mac_addr);
1686                 ret = ice_add_mac_filter(vsi, &mac_addr);
1687                 if (ret != ICE_SUCCESS)
1688                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1689         }
1690
1691         /* At the beginning, only TC0. */
1692         /* What we need here is the maximam number of the TX queues.
1693          * Currently vsi->nb_qps means it.
1694          * Correct it if any change.
1695          */
1696         max_txqs[0] = vsi->nb_qps;
1697         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1698                               tc_bitmap, max_txqs);
1699         if (ret != ICE_SUCCESS)
1700                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1701
1702         return vsi;
1703 fail_mem:
1704         rte_free(vsi);
1705         pf->next_vsi_idx--;
1706         return NULL;
1707 }
1708
1709 static int
1710 ice_send_driver_ver(struct ice_hw *hw)
1711 {
1712         struct ice_driver_ver dv;
1713
1714         /* we don't have driver version use 0 for dummy */
1715         dv.major_ver = 0;
1716         dv.minor_ver = 0;
1717         dv.build_ver = 0;
1718         dv.subbuild_ver = 0;
1719         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1720
1721         return ice_aq_send_driver_ver(hw, &dv, NULL);
1722 }
1723
1724 static int
1725 ice_pf_setup(struct ice_pf *pf)
1726 {
1727         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1728         struct ice_vsi *vsi;
1729         uint16_t unused;
1730
1731         /* Clear all stats counters */
1732         pf->offset_loaded = false;
1733         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1734         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1735         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1736         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1737
1738         /* force guaranteed filter pool for PF */
1739         ice_alloc_fd_guar_item(hw, &unused,
1740                                hw->func_caps.fd_fltr_guar);
1741         /* force shared filter pool for PF */
1742         ice_alloc_fd_shrd_item(hw, &unused,
1743                                hw->func_caps.fd_fltr_best_effort);
1744
1745         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1746         if (!vsi) {
1747                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1748                 return -EINVAL;
1749         }
1750
1751         pf->main_vsi = vsi;
1752
1753         return 0;
1754 }
1755
1756 /*
1757  * Extract device serial number from PCIe Configuration Space and
1758  * determine the pkg file path according to the DSN.
1759  */
1760 static int
1761 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1762 {
1763         off_t pos;
1764         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1765         uint32_t dsn_low, dsn_high;
1766         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1767
1768         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1769
1770         if (pos) {
1771                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1772                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1773                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1774                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1775         } else {
1776                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1777                 goto fail_dsn;
1778         }
1779
1780         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1781                 ICE_MAX_PKG_FILENAME_SIZE);
1782         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1783                 return 0;
1784
1785         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1786                 ICE_MAX_PKG_FILENAME_SIZE);
1787         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1788                 return 0;
1789
1790 fail_dsn:
1791         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1792         if (!access(pkg_file, 0))
1793                 return 0;
1794         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1795         return 0;
1796 }
1797
1798 enum ice_pkg_type
1799 ice_load_pkg_type(struct ice_hw *hw)
1800 {
1801         enum ice_pkg_type package_type;
1802
1803         /* store the activated package type (OS default or Comms) */
1804         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1805                 ICE_PKG_NAME_SIZE))
1806                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1807         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1808                 ICE_PKG_NAME_SIZE))
1809                 package_type = ICE_PKG_TYPE_COMMS;
1810         else
1811                 package_type = ICE_PKG_TYPE_UNKNOWN;
1812
1813         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1814                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1815                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1816                 hw->active_pkg_name);
1817
1818         return package_type;
1819 }
1820
1821 static int ice_load_pkg(struct rte_eth_dev *dev)
1822 {
1823         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1825         int err;
1826         uint8_t *buf;
1827         int buf_len;
1828         FILE *file;
1829         struct stat fstat;
1830         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1831         struct ice_adapter *ad =
1832                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1833
1834         ice_pkg_file_search_path(pci_dev, pkg_file);
1835
1836         file = fopen(pkg_file, "rb");
1837         if (!file)  {
1838                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1839                 return -1;
1840         }
1841
1842         err = stat(pkg_file, &fstat);
1843         if (err) {
1844                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1845                 fclose(file);
1846                 return err;
1847         }
1848
1849         buf_len = fstat.st_size;
1850         buf = rte_malloc(NULL, buf_len, 0);
1851
1852         if (!buf) {
1853                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1854                                 buf_len);
1855                 fclose(file);
1856                 return -1;
1857         }
1858
1859         err = fread(buf, buf_len, 1, file);
1860         if (err != 1) {
1861                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1862                 fclose(file);
1863                 err = -1;
1864                 goto fail_exit;
1865         }
1866
1867         fclose(file);
1868
1869         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1870         if (err) {
1871                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1872                 goto fail_exit;
1873         }
1874
1875         /* store the loaded pkg type info */
1876         ad->active_pkg_type = ice_load_pkg_type(hw);
1877
1878         err = ice_init_hw_tbls(hw);
1879         if (err) {
1880                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1881                 goto fail_init_tbls;
1882         }
1883
1884         return 0;
1885
1886 fail_init_tbls:
1887         rte_free(hw->pkg_copy);
1888 fail_exit:
1889         rte_free(buf);
1890         return err;
1891 }
1892
1893 static void
1894 ice_base_queue_get(struct ice_pf *pf)
1895 {
1896         uint32_t reg;
1897         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1898
1899         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1900         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1901                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1902         } else {
1903                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1904                                         " index");
1905         }
1906 }
1907
1908 static int
1909 parse_bool(const char *key, const char *value, void *args)
1910 {
1911         int *i = (int *)args;
1912         char *end;
1913         int num;
1914
1915         num = strtoul(value, &end, 10);
1916
1917         if (num != 0 && num != 1) {
1918                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1919                         "value must be 0 or 1",
1920                         value, key);
1921                 return -1;
1922         }
1923
1924         *i = num;
1925         return 0;
1926 }
1927
1928 static int ice_parse_devargs(struct rte_eth_dev *dev)
1929 {
1930         struct ice_adapter *ad =
1931                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1932         struct rte_devargs *devargs = dev->device->devargs;
1933         struct rte_kvargs *kvlist;
1934         int ret;
1935
1936         if (devargs == NULL)
1937                 return 0;
1938
1939         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1940         if (kvlist == NULL) {
1941                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1942                 return -EINVAL;
1943         }
1944
1945         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1946         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1947                sizeof(ad->devargs.proto_xtr));
1948
1949         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1950                                  &handle_proto_xtr_arg, &ad->devargs);
1951         if (ret)
1952                 goto bail;
1953
1954         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1955                                  &parse_bool, &ad->devargs.safe_mode_support);
1956         if (ret)
1957                 goto bail;
1958
1959         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1960                                  &parse_bool, &ad->devargs.pipe_mode_support);
1961         if (ret)
1962                 goto bail;
1963
1964 bail:
1965         rte_kvargs_free(kvlist);
1966         return ret;
1967 }
1968
1969 /* Forward LLDP packets to default VSI by set switch rules */
1970 static int
1971 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1972 {
1973         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1974         struct ice_fltr_list_entry *s_list_itr = NULL;
1975         struct LIST_HEAD_TYPE list_head;
1976         int ret = 0;
1977
1978         INIT_LIST_HEAD(&list_head);
1979
1980         s_list_itr = (struct ice_fltr_list_entry *)
1981                         ice_malloc(hw, sizeof(*s_list_itr));
1982         if (!s_list_itr)
1983                 return -ENOMEM;
1984         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1985         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1986         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1987                         RTE_ETHER_TYPE_LLDP;
1988         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1989         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1990         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1991         LIST_ADD(&s_list_itr->list_entry, &list_head);
1992         if (on)
1993                 ret = ice_add_eth_mac(hw, &list_head);
1994         else
1995                 ret = ice_remove_eth_mac(hw, &list_head);
1996
1997         rte_free(s_list_itr);
1998         return ret;
1999 }
2000
2001 static enum ice_status
2002 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2003                 uint16_t num, uint16_t desc_id,
2004                 uint16_t *prof_buf, uint16_t *num_prof)
2005 {
2006         struct ice_aqc_res_elem *resp_buf;
2007         int ret;
2008         uint16_t buf_len;
2009         bool res_shared = 1;
2010         struct ice_aq_desc aq_desc;
2011         struct ice_sq_cd *cd = NULL;
2012         struct ice_aqc_get_allocd_res_desc *cmd =
2013                         &aq_desc.params.get_res_desc;
2014
2015         buf_len = sizeof(*resp_buf) * num;
2016         resp_buf = ice_malloc(hw, buf_len);
2017         if (!resp_buf)
2018                 return -ENOMEM;
2019
2020         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2021                         ice_aqc_opc_get_allocd_res_desc);
2022
2023         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2024                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2025                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2026         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2027
2028         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2029         if (!ret)
2030                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2031         else
2032                 goto exit;
2033
2034         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2035                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2036
2037 exit:
2038         rte_free(resp_buf);
2039         return ret;
2040 }
2041 static int
2042 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2043 {
2044         int ret;
2045         uint16_t prof_id;
2046         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2047         uint16_t first_desc = 1;
2048         uint16_t num_prof = 0;
2049
2050         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2051                         first_desc, prof_buf, &num_prof);
2052         if (ret) {
2053                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2054                 return ret;
2055         }
2056
2057         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2058                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2059                 if (ret) {
2060                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2061                         return ret;
2062                 }
2063         }
2064         return 0;
2065 }
2066
2067 static int
2068 ice_reset_fxp_resource(struct ice_hw *hw)
2069 {
2070         int ret;
2071
2072         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2073         if (ret) {
2074                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2075                 return ret;
2076         }
2077
2078         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2079         if (ret) {
2080                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2081                 return ret;
2082         }
2083
2084         return 0;
2085 }
2086
2087 static void
2088 ice_rss_ctx_init(struct ice_pf *pf)
2089 {
2090         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2091         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2092
2093         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2094         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2095
2096         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2097         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2098 }
2099
2100 static uint64_t
2101 ice_get_supported_rxdid(struct ice_hw *hw)
2102 {
2103         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2104         uint32_t regval;
2105         int i;
2106
2107         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2108
2109         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2110                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2111                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2112                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2113                         supported_rxdid |= BIT(i);
2114         }
2115         return supported_rxdid;
2116 }
2117
2118 static int
2119 ice_dev_init(struct rte_eth_dev *dev)
2120 {
2121         struct rte_pci_device *pci_dev;
2122         struct rte_intr_handle *intr_handle;
2123         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125         struct ice_adapter *ad =
2126                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2127         struct ice_vsi *vsi;
2128         int ret;
2129
2130         dev->dev_ops = &ice_eth_dev_ops;
2131         dev->rx_queue_count = ice_rx_queue_count;
2132         dev->rx_descriptor_status = ice_rx_descriptor_status;
2133         dev->tx_descriptor_status = ice_tx_descriptor_status;
2134         dev->rx_pkt_burst = ice_recv_pkts;
2135         dev->tx_pkt_burst = ice_xmit_pkts;
2136         dev->tx_pkt_prepare = ice_prep_pkts;
2137
2138         /* for secondary processes, we don't initialise any further as primary
2139          * has already done this work.
2140          */
2141         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2142                 ice_set_rx_function(dev);
2143                 ice_set_tx_function(dev);
2144                 return 0;
2145         }
2146
2147         ice_set_default_ptype_table(dev);
2148         pci_dev = RTE_DEV_TO_PCI(dev->device);
2149         intr_handle = &pci_dev->intr_handle;
2150
2151         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2152         pf->adapter->eth_dev = dev;
2153         pf->dev_data = dev->data;
2154         hw->back = pf->adapter;
2155         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2156         hw->vendor_id = pci_dev->id.vendor_id;
2157         hw->device_id = pci_dev->id.device_id;
2158         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2159         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2160         hw->bus.device = pci_dev->addr.devid;
2161         hw->bus.func = pci_dev->addr.function;
2162
2163         ret = ice_parse_devargs(dev);
2164         if (ret) {
2165                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2166                 return -EINVAL;
2167         }
2168
2169         ice_init_controlq_parameter(hw);
2170
2171         ret = ice_init_hw(hw);
2172         if (ret) {
2173                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2174                 return -EINVAL;
2175         }
2176
2177         ret = ice_load_pkg(dev);
2178         if (ret) {
2179                 if (ad->devargs.safe_mode_support == 0) {
2180                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2181                                         "Use safe-mode-support=1 to enter Safe Mode");
2182                         return ret;
2183                 }
2184
2185                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2186                                         "Entering Safe Mode");
2187                 ad->is_safe_mode = 1;
2188         }
2189
2190         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2191                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2192                      hw->api_maj_ver, hw->api_min_ver);
2193
2194         ice_pf_sw_init(dev);
2195         ret = ice_init_mac_address(dev);
2196         if (ret) {
2197                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2198                 goto err_init_mac;
2199         }
2200
2201         ret = ice_res_pool_init(&pf->msix_pool, 1,
2202                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2203         if (ret) {
2204                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2205                 goto err_msix_pool_init;
2206         }
2207
2208         ret = ice_pf_setup(pf);
2209         if (ret) {
2210                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2211                 goto err_pf_setup;
2212         }
2213
2214         ret = ice_send_driver_ver(hw);
2215         if (ret) {
2216                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2217                 goto err_pf_setup;
2218         }
2219
2220         vsi = pf->main_vsi;
2221
2222         /* Disable double vlan by default */
2223         ice_vsi_config_double_vlan(vsi, false);
2224
2225         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2226         if (ret != ICE_SUCCESS)
2227                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2228         ret = ice_init_dcb(hw, true);
2229         if (ret != ICE_SUCCESS)
2230                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2231         /* Forward LLDP packets to default VSI */
2232         ret = ice_vsi_config_sw_lldp(vsi, true);
2233         if (ret != ICE_SUCCESS)
2234                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2235         /* register callback func to eal lib */
2236         rte_intr_callback_register(intr_handle,
2237                                    ice_interrupt_handler, dev);
2238
2239         ice_pf_enable_irq0(hw);
2240
2241         /* enable uio intr after callback register */
2242         rte_intr_enable(intr_handle);
2243
2244         /* get base queue pairs index  in the device */
2245         ice_base_queue_get(pf);
2246
2247         /* Initialize RSS context for gtpu_eh */
2248         ice_rss_ctx_init(pf);
2249
2250         if (!ad->is_safe_mode) {
2251                 ret = ice_flow_init(ad);
2252                 if (ret) {
2253                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2254                         return ret;
2255                 }
2256         }
2257
2258         ret = ice_reset_fxp_resource(hw);
2259         if (ret) {
2260                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2261                 return ret;
2262         }
2263
2264         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2265
2266         return 0;
2267
2268 err_pf_setup:
2269         ice_res_pool_destroy(&pf->msix_pool);
2270 err_msix_pool_init:
2271         rte_free(dev->data->mac_addrs);
2272         dev->data->mac_addrs = NULL;
2273 err_init_mac:
2274         ice_sched_cleanup_all(hw);
2275         rte_free(hw->port_info);
2276         ice_shutdown_all_ctrlq(hw);
2277         rte_free(pf->proto_xtr);
2278
2279         return ret;
2280 }
2281
2282 int
2283 ice_release_vsi(struct ice_vsi *vsi)
2284 {
2285         struct ice_hw *hw;
2286         struct ice_vsi_ctx vsi_ctx;
2287         enum ice_status ret;
2288         int error = 0;
2289
2290         if (!vsi)
2291                 return error;
2292
2293         hw = ICE_VSI_TO_HW(vsi);
2294
2295         ice_remove_all_mac_vlan_filters(vsi);
2296
2297         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2298
2299         vsi_ctx.vsi_num = vsi->vsi_id;
2300         vsi_ctx.info = vsi->info;
2301         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2302         if (ret != ICE_SUCCESS) {
2303                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2304                 error = -1;
2305         }
2306
2307         rte_free(vsi->rss_lut);
2308         rte_free(vsi->rss_key);
2309         rte_free(vsi);
2310         return error;
2311 }
2312
2313 void
2314 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2315 {
2316         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2317         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2320         uint16_t msix_intr, i;
2321
2322         /* disable interrupt and also clear all the exist config */
2323         for (i = 0; i < vsi->nb_qps; i++) {
2324                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2325                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2326                 rte_wmb();
2327         }
2328
2329         if (rte_intr_allow_others(intr_handle))
2330                 /* vfio-pci */
2331                 for (i = 0; i < vsi->nb_msix; i++) {
2332                         msix_intr = vsi->msix_intr + i;
2333                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2334                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2335                 }
2336         else
2337                 /* igb_uio */
2338                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2339 }
2340
2341 static void
2342 ice_dev_stop(struct rte_eth_dev *dev)
2343 {
2344         struct rte_eth_dev_data *data = dev->data;
2345         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346         struct ice_vsi *main_vsi = pf->main_vsi;
2347         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2349         uint16_t i;
2350
2351         /* avoid stopping again */
2352         if (pf->adapter_stopped)
2353                 return;
2354
2355         /* stop and clear all Rx queues */
2356         for (i = 0; i < data->nb_rx_queues; i++)
2357                 ice_rx_queue_stop(dev, i);
2358
2359         /* stop and clear all Tx queues */
2360         for (i = 0; i < data->nb_tx_queues; i++)
2361                 ice_tx_queue_stop(dev, i);
2362
2363         /* disable all queue interrupts */
2364         ice_vsi_disable_queues_intr(main_vsi);
2365
2366         if (pf->init_link_up)
2367                 ice_dev_set_link_up(dev);
2368         else
2369                 ice_dev_set_link_down(dev);
2370
2371         /* Clean datapath event and queue/vec mapping */
2372         rte_intr_efd_disable(intr_handle);
2373         if (intr_handle->intr_vec) {
2374                 rte_free(intr_handle->intr_vec);
2375                 intr_handle->intr_vec = NULL;
2376         }
2377
2378         pf->adapter_stopped = true;
2379 }
2380
2381 static int
2382 ice_dev_close(struct rte_eth_dev *dev)
2383 {
2384         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2385         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2388         struct ice_adapter *ad =
2389                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2390
2391         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2392                 return 0;
2393
2394         /* Since stop will make link down, then the link event will be
2395          * triggered, disable the irq firstly to avoid the port_infoe etc
2396          * resources deallocation causing the interrupt service thread
2397          * crash.
2398          */
2399         ice_pf_disable_irq0(hw);
2400
2401         ice_dev_stop(dev);
2402
2403         if (!ad->is_safe_mode)
2404                 ice_flow_uninit(ad);
2405
2406         /* release all queue resource */
2407         ice_free_queues(dev);
2408
2409         ice_res_pool_destroy(&pf->msix_pool);
2410         ice_release_vsi(pf->main_vsi);
2411         ice_sched_cleanup_all(hw);
2412         ice_free_hw_tbls(hw);
2413         rte_free(hw->port_info);
2414         hw->port_info = NULL;
2415         ice_shutdown_all_ctrlq(hw);
2416         rte_free(pf->proto_xtr);
2417         pf->proto_xtr = NULL;
2418
2419         dev->dev_ops = NULL;
2420         dev->rx_pkt_burst = NULL;
2421         dev->tx_pkt_burst = NULL;
2422
2423         rte_free(dev->data->mac_addrs);
2424         dev->data->mac_addrs = NULL;
2425
2426         /* disable uio intr before callback unregister */
2427         rte_intr_disable(intr_handle);
2428
2429         /* unregister callback func from eal lib */
2430         rte_intr_callback_unregister(intr_handle,
2431                                      ice_interrupt_handler, dev);
2432
2433         return 0;
2434 }
2435
2436 static int
2437 ice_dev_uninit(struct rte_eth_dev *dev)
2438 {
2439         ice_dev_close(dev);
2440
2441         return 0;
2442 }
2443
2444 static int
2445 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm)
2446 {
2447         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2448         struct ice_vsi *vsi = pf->main_vsi;
2449
2450         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2451                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2452                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2453                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr = hdr;
2454                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld = fld;
2455                         pf->gtpu_hash_ctx.ipv4_udp.symm = symm;
2456                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2457                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2458                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr = hdr;
2459                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld = fld;
2460                         pf->gtpu_hash_ctx.ipv6_udp.symm = symm;
2461                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2462                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2463                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr = hdr;
2464                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld = fld;
2465                         pf->gtpu_hash_ctx.ipv4_tcp.symm = symm;
2466                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2467                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2468                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr = hdr;
2469                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld = fld;
2470                         pf->gtpu_hash_ctx.ipv6_tcp.symm = symm;
2471                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2472                         pf->gtpu_hash_ctx.ipv4.pkt_hdr = hdr;
2473                         pf->gtpu_hash_ctx.ipv4.hash_fld = fld;
2474                         pf->gtpu_hash_ctx.ipv4.symm = symm;
2475                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2476                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2477                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2478                         pf->gtpu_hash_ctx.ipv6.pkt_hdr = hdr;
2479                         pf->gtpu_hash_ctx.ipv6.hash_fld = fld;
2480                         pf->gtpu_hash_ctx.ipv6.symm = symm;
2481                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2482                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2483                 }
2484         }
2485
2486         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2487             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2488                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2489                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2490                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2491                                 ice_add_rss_cfg(hw, vsi->idx,
2492                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2493                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2494                                         pf->gtpu_hash_ctx.ipv4.symm);
2495                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2496                         }
2497                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2498                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2499                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2500                                 ice_add_rss_cfg(hw, vsi->idx,
2501                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2502                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2503                                         pf->gtpu_hash_ctx.ipv6.symm);
2504                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2505                         }
2506                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2507                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2508                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2509                                 ice_add_rss_cfg(hw, vsi->idx,
2510                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2511                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2512                                         pf->gtpu_hash_ctx.ipv4.symm);
2513                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2514                         }
2515                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2516                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2517                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2518                                 ice_add_rss_cfg(hw, vsi->idx,
2519                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2520                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2521                                         pf->gtpu_hash_ctx.ipv6.symm);
2522                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2523                         }
2524                 }
2525         }
2526
2527         return 0;
2528 }
2529
2530 static int
2531 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2532 {
2533         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2534         struct ice_vsi *vsi = pf->main_vsi;
2535
2536         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2537             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2538                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2539                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2540                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2541                                 ice_rem_rss_cfg(hw, vsi->idx,
2542                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2543                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2544                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2545                         }
2546
2547                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2548                                 ice_rem_rss_cfg(hw, vsi->idx,
2549                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2550                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2551                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2552                         }
2553                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2554                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2555                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2556                                 ice_rem_rss_cfg(hw, vsi->idx,
2557                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2558                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2559                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2560                         }
2561
2562                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2563                                 ice_rem_rss_cfg(hw, vsi->idx,
2564                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2565                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2566                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2567                         }
2568                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2569                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2570                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2571                                 ice_rem_rss_cfg(hw, vsi->idx,
2572                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2573                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2574                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2575                         }
2576
2577                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2578                                 ice_rem_rss_cfg(hw, vsi->idx,
2579                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2580                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2581                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2582                         }
2583                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2584                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2585                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2586                                 ice_rem_rss_cfg(hw, vsi->idx,
2587                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2588                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2589                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2590                         }
2591
2592                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2593                                 ice_rem_rss_cfg(hw, vsi->idx,
2594                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2595                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2596                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2597                         }
2598                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2599                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2600                                 ice_rem_rss_cfg(hw, vsi->idx,
2601                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2602                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2603                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2604                         }
2605
2606                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2607                                 ice_rem_rss_cfg(hw, vsi->idx,
2608                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2609                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2610                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2611                         }
2612
2613                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2614                                 ice_rem_rss_cfg(hw, vsi->idx,
2615                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2616                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2617                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2618                         }
2619                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2620                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2621                                 ice_rem_rss_cfg(hw, vsi->idx,
2622                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2623                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2624                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2625                         }
2626
2627                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2628                                 ice_rem_rss_cfg(hw, vsi->idx,
2629                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2630                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2631                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2632                         }
2633
2634                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2635                                 ice_rem_rss_cfg(hw, vsi->idx,
2636                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2637                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2638                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2639                         }
2640                 }
2641         }
2642
2643         return 0;
2644 }
2645
2646 static int
2647 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2648 {
2649         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2650                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2651                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2652                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2653                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2654                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2655                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2656                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2657                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2658                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2659                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2660                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2661                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2662                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2663                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2664                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2665                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2666                 }
2667         }
2668
2669         return 0;
2670 }
2671
2672 int
2673 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2674                 uint64_t fld, uint32_t hdr)
2675 {
2676         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2677         int ret;
2678
2679         ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr);
2680         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2681                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2682
2683         ret = ice_rem_rss_cfg_post(pf, hdr);
2684         if (ret)
2685                 PMD_DRV_LOG(ERR, "remove rss cfg post failed\n");
2686
2687         return 0;
2688 }
2689
2690 int
2691 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2692                 uint64_t fld, uint32_t hdr, bool symm)
2693 {
2694         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2695         int ret;
2696
2697         ret = ice_add_rss_cfg_pre(pf, hdr);
2698         if (ret)
2699                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2700
2701         ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm);
2702         if (ret)
2703                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2704
2705         ret = ice_add_rss_cfg_post(pf, hdr, fld, symm);
2706         if (ret)
2707                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2708
2709         return 0;
2710 }
2711
2712 static void
2713 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2714 {
2715         struct ice_vsi *vsi = pf->main_vsi;
2716         int ret;
2717
2718         /* Configure RSS for IPv4 with src/dst addr as input set */
2719         if (rss_hf & ETH_RSS_IPV4) {
2720                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2721                                       ICE_FLOW_SEG_HDR_IPV4 |
2722                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2723                 if (ret)
2724                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2725                                     __func__, ret);
2726         }
2727
2728         /* Configure RSS for IPv6 with src/dst addr as input set */
2729         if (rss_hf & ETH_RSS_IPV6) {
2730                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2731                                       ICE_FLOW_SEG_HDR_IPV6 |
2732                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2733                 if (ret)
2734                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2735                                     __func__, ret);
2736         }
2737
2738         /* Configure RSS for udp4 with src/dst addr and port as input set */
2739         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2740                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2741                                       ICE_FLOW_SEG_HDR_UDP |
2742                                       ICE_FLOW_SEG_HDR_IPV4 |
2743                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2744                 if (ret)
2745                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2746                                     __func__, ret);
2747         }
2748
2749         /* Configure RSS for udp6 with src/dst addr and port as input set */
2750         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2751                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2752                                       ICE_FLOW_SEG_HDR_UDP |
2753                                       ICE_FLOW_SEG_HDR_IPV6 |
2754                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2755                 if (ret)
2756                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2757                                     __func__, ret);
2758         }
2759
2760         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2761         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2762                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2763                                       ICE_FLOW_SEG_HDR_TCP |
2764                                       ICE_FLOW_SEG_HDR_IPV4 |
2765                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2766                 if (ret)
2767                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2768                                     __func__, ret);
2769         }
2770
2771         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2772         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2773                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2774                                       ICE_FLOW_SEG_HDR_TCP |
2775                                       ICE_FLOW_SEG_HDR_IPV6 |
2776                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2777                 if (ret)
2778                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2779                                     __func__, ret);
2780         }
2781
2782         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2783         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2784                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2785                                       ICE_FLOW_SEG_HDR_SCTP |
2786                                       ICE_FLOW_SEG_HDR_IPV4 |
2787                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2788                 if (ret)
2789                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2790                                     __func__, ret);
2791         }
2792
2793         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2794         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2795                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2796                                       ICE_FLOW_SEG_HDR_SCTP |
2797                                       ICE_FLOW_SEG_HDR_IPV6 |
2798                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2799                 if (ret)
2800                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2801                                     __func__, ret);
2802         }
2803
2804         if (rss_hf & ETH_RSS_IPV4) {
2805                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2806                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2807                                 ICE_FLOW_SEG_HDR_IPV4 |
2808                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2809                 if (ret)
2810                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2811                                     __func__, ret);
2812
2813                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2814                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2815                                 ICE_FLOW_SEG_HDR_IPV4 |
2816                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2817                 if (ret)
2818                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2819                                     __func__, ret);
2820
2821                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2822                                 ICE_FLOW_SEG_HDR_PPPOE |
2823                                 ICE_FLOW_SEG_HDR_IPV4 |
2824                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2825                 if (ret)
2826                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2827                                     __func__, ret);
2828         }
2829
2830         if (rss_hf & ETH_RSS_IPV6) {
2831                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2832                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2833                                 ICE_FLOW_SEG_HDR_IPV6 |
2834                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2835                 if (ret)
2836                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2837                                     __func__, ret);
2838
2839                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2840                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2841                                 ICE_FLOW_SEG_HDR_IPV6 |
2842                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2843                 if (ret)
2844                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2845                                     __func__, ret);
2846
2847                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2848                                 ICE_FLOW_SEG_HDR_PPPOE |
2849                                 ICE_FLOW_SEG_HDR_IPV6 |
2850                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2851                 if (ret)
2852                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2853                                     __func__, ret);
2854         }
2855
2856         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2857                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2858                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2859                                 ICE_FLOW_SEG_HDR_UDP |
2860                                 ICE_FLOW_SEG_HDR_IPV4 |
2861                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2862                 if (ret)
2863                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2864                                     __func__, ret);
2865
2866                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2867                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2868                                 ICE_FLOW_SEG_HDR_UDP |
2869                                 ICE_FLOW_SEG_HDR_IPV4 |
2870                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2871                 if (ret)
2872                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2873                                     __func__, ret);
2874
2875                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2876                                 ICE_FLOW_SEG_HDR_PPPOE |
2877                                 ICE_FLOW_SEG_HDR_UDP |
2878                                 ICE_FLOW_SEG_HDR_IPV4 |
2879                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2880                 if (ret)
2881                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2882                                     __func__, ret);
2883         }
2884
2885         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2886                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2887                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2888                                 ICE_FLOW_SEG_HDR_UDP |
2889                                 ICE_FLOW_SEG_HDR_IPV6 |
2890                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2891                 if (ret)
2892                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2893                                     __func__, ret);
2894
2895                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2896                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2897                                 ICE_FLOW_SEG_HDR_UDP |
2898                                 ICE_FLOW_SEG_HDR_IPV6 |
2899                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2900                 if (ret)
2901                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2902                                     __func__, ret);
2903
2904                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2905                                 ICE_FLOW_SEG_HDR_PPPOE |
2906                                 ICE_FLOW_SEG_HDR_UDP |
2907                                 ICE_FLOW_SEG_HDR_IPV6 |
2908                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2909                 if (ret)
2910                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2911                                     __func__, ret);
2912         }
2913
2914         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2915                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2916                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2917                                 ICE_FLOW_SEG_HDR_TCP |
2918                                 ICE_FLOW_SEG_HDR_IPV4 |
2919                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2920                 if (ret)
2921                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
2922                                     __func__, ret);
2923
2924                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2925                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2926                                 ICE_FLOW_SEG_HDR_TCP |
2927                                 ICE_FLOW_SEG_HDR_IPV4 |
2928                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2929                 if (ret)
2930                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
2931                                     __func__, ret);
2932
2933                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2934                                 ICE_FLOW_SEG_HDR_PPPOE |
2935                                 ICE_FLOW_SEG_HDR_TCP |
2936                                 ICE_FLOW_SEG_HDR_IPV4 |
2937                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2938                 if (ret)
2939                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2940                                     __func__, ret);
2941         }
2942
2943         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2944                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2945                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2946                                 ICE_FLOW_SEG_HDR_TCP |
2947                                 ICE_FLOW_SEG_HDR_IPV6 |
2948                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2949                 if (ret)
2950                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
2951                                     __func__, ret);
2952
2953                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2954                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2955                                 ICE_FLOW_SEG_HDR_TCP |
2956                                 ICE_FLOW_SEG_HDR_IPV6 |
2957                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2958                 if (ret)
2959                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
2960                                     __func__, ret);
2961
2962                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2963                                 ICE_FLOW_SEG_HDR_PPPOE |
2964                                 ICE_FLOW_SEG_HDR_TCP |
2965                                 ICE_FLOW_SEG_HDR_IPV6 |
2966                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2967                 if (ret)
2968                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2969                                     __func__, ret);
2970         }
2971
2972         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2973                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
2974                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2975                                 ICE_FLOW_SEG_HDR_SCTP |
2976                                 ICE_FLOW_SEG_HDR_IPV4 |
2977                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2978                 if (ret)
2979                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
2980                                     __func__, ret);
2981
2982                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
2983                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2984                                 ICE_FLOW_SEG_HDR_SCTP |
2985                                 ICE_FLOW_SEG_HDR_IPV4 |
2986                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2987                 if (ret)
2988                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
2989                                     __func__, ret);
2990         }
2991
2992         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2993                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
2994                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2995                                 ICE_FLOW_SEG_HDR_SCTP |
2996                                 ICE_FLOW_SEG_HDR_IPV6 |
2997                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2998                 if (ret)
2999                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
3000                                     __func__, ret);
3001
3002                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3003                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3004                                 ICE_FLOW_SEG_HDR_SCTP |
3005                                 ICE_FLOW_SEG_HDR_IPV6 |
3006                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3007                 if (ret)
3008                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
3009                                     __func__, ret);
3010         }
3011 }
3012
3013 static int ice_init_rss(struct ice_pf *pf)
3014 {
3015         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3016         struct ice_vsi *vsi = pf->main_vsi;
3017         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3018         struct rte_eth_rss_conf *rss_conf;
3019         struct ice_aqc_get_set_rss_keys key;
3020         uint16_t i, nb_q;
3021         int ret = 0;
3022         bool is_safe_mode = pf->adapter->is_safe_mode;
3023         uint32_t reg;
3024
3025         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3026         nb_q = dev->data->nb_rx_queues;
3027         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3028         vsi->rss_lut_size = pf->hash_lut_size;
3029
3030         if (is_safe_mode) {
3031                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3032                 return 0;
3033         }
3034
3035         if (!vsi->rss_key) {
3036                 vsi->rss_key = rte_zmalloc(NULL,
3037                                            vsi->rss_key_size, 0);
3038                 if (vsi->rss_key == NULL) {
3039                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3040                         return -ENOMEM;
3041                 }
3042         }
3043         if (!vsi->rss_lut) {
3044                 vsi->rss_lut = rte_zmalloc(NULL,
3045                                            vsi->rss_lut_size, 0);
3046                 if (vsi->rss_lut == NULL) {
3047                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3048                         rte_free(vsi->rss_key);
3049                         vsi->rss_key = NULL;
3050                         return -ENOMEM;
3051                 }
3052         }
3053         /* configure RSS key */
3054         if (!rss_conf->rss_key) {
3055                 /* Calculate the default hash key */
3056                 for (i = 0; i <= vsi->rss_key_size; i++)
3057                         vsi->rss_key[i] = (uint8_t)rte_rand();
3058         } else {
3059                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3060                            RTE_MIN(rss_conf->rss_key_len,
3061                                    vsi->rss_key_size));
3062         }
3063         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3064         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3065         if (ret)
3066                 goto out;
3067
3068         /* init RSS LUT table */
3069         for (i = 0; i < vsi->rss_lut_size; i++)
3070                 vsi->rss_lut[i] = i % nb_q;
3071
3072         ret = ice_aq_set_rss_lut(hw, vsi->idx,
3073                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
3074                                  vsi->rss_lut, vsi->rss_lut_size);
3075         if (ret)
3076                 goto out;
3077
3078         /* Enable registers for symmetric_toeplitz function. */
3079         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3080         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3081                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3082         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3083
3084         /* RSS hash configuration */
3085         ice_rss_hash_set(pf, rss_conf->rss_hf);
3086
3087         return 0;
3088 out:
3089         rte_free(vsi->rss_key);
3090         vsi->rss_key = NULL;
3091         rte_free(vsi->rss_lut);
3092         vsi->rss_lut = NULL;
3093         return -EINVAL;
3094 }
3095
3096 static int
3097 ice_dev_configure(struct rte_eth_dev *dev)
3098 {
3099         struct ice_adapter *ad =
3100                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3101         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3102         int ret;
3103
3104         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3105          * bulk allocation or vector Rx preconditions we will reset it.
3106          */
3107         ad->rx_bulk_alloc_allowed = true;
3108         ad->tx_simple_allowed = true;
3109
3110         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3111                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3112
3113         ret = ice_init_rss(pf);
3114         if (ret) {
3115                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3116                 return ret;
3117         }
3118
3119         return 0;
3120 }
3121
3122 static void
3123 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3124                        int base_queue, int nb_queue)
3125 {
3126         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3127         uint32_t val, val_tx;
3128         int i;
3129
3130         for (i = 0; i < nb_queue; i++) {
3131                 /*do actual bind*/
3132                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3133                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3134                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3135                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3136
3137                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3138                             base_queue + i, msix_vect);
3139                 /* set ITR0 value */
3140                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
3141                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3142                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3143         }
3144 }
3145
3146 void
3147 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3148 {
3149         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3150         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3151         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3152         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3153         uint16_t msix_vect = vsi->msix_intr;
3154         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3155         uint16_t queue_idx = 0;
3156         int record = 0;
3157         int i;
3158
3159         /* clear Rx/Tx queue interrupt */
3160         for (i = 0; i < vsi->nb_used_qps; i++) {
3161                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3162                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3163         }
3164
3165         /* PF bind interrupt */
3166         if (rte_intr_dp_is_en(intr_handle)) {
3167                 queue_idx = 0;
3168                 record = 1;
3169         }
3170
3171         for (i = 0; i < vsi->nb_used_qps; i++) {
3172                 if (nb_msix <= 1) {
3173                         if (!rte_intr_allow_others(intr_handle))
3174                                 msix_vect = ICE_MISC_VEC_ID;
3175
3176                         /* uio mapping all queue to one msix_vect */
3177                         __vsi_queues_bind_intr(vsi, msix_vect,
3178                                                vsi->base_queue + i,
3179                                                vsi->nb_used_qps - i);
3180
3181                         for (; !!record && i < vsi->nb_used_qps; i++)
3182                                 intr_handle->intr_vec[queue_idx + i] =
3183                                         msix_vect;
3184                         break;
3185                 }
3186
3187                 /* vfio 1:1 queue/msix_vect mapping */
3188                 __vsi_queues_bind_intr(vsi, msix_vect,
3189                                        vsi->base_queue + i, 1);
3190
3191                 if (!!record)
3192                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3193
3194                 msix_vect++;
3195                 nb_msix--;
3196         }
3197 }
3198
3199 void
3200 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3201 {
3202         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3203         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3204         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3205         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3206         uint16_t msix_intr, i;
3207
3208         if (rte_intr_allow_others(intr_handle))
3209                 for (i = 0; i < vsi->nb_used_qps; i++) {
3210                         msix_intr = vsi->msix_intr + i;
3211                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3212                                       GLINT_DYN_CTL_INTENA_M |
3213                                       GLINT_DYN_CTL_CLEARPBA_M |
3214                                       GLINT_DYN_CTL_ITR_INDX_M |
3215                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3216                 }
3217         else
3218                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3219                               GLINT_DYN_CTL_INTENA_M |
3220                               GLINT_DYN_CTL_CLEARPBA_M |
3221                               GLINT_DYN_CTL_ITR_INDX_M |
3222                               GLINT_DYN_CTL_WB_ON_ITR_M);
3223 }
3224
3225 static int
3226 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3227 {
3228         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3229         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3230         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3231         struct ice_vsi *vsi = pf->main_vsi;
3232         uint32_t intr_vector = 0;
3233
3234         rte_intr_disable(intr_handle);
3235
3236         /* check and configure queue intr-vector mapping */
3237         if ((rte_intr_cap_multiple(intr_handle) ||
3238              !RTE_ETH_DEV_SRIOV(dev).active) &&
3239             dev->data->dev_conf.intr_conf.rxq != 0) {
3240                 intr_vector = dev->data->nb_rx_queues;
3241                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3242                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3243                                     ICE_MAX_INTR_QUEUE_NUM);
3244                         return -ENOTSUP;
3245                 }
3246                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3247                         return -1;
3248         }
3249
3250         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3251                 intr_handle->intr_vec =
3252                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3253                             0);
3254                 if (!intr_handle->intr_vec) {
3255                         PMD_DRV_LOG(ERR,
3256                                     "Failed to allocate %d rx_queues intr_vec",
3257                                     dev->data->nb_rx_queues);
3258                         return -ENOMEM;
3259                 }
3260         }
3261
3262         /* Map queues with MSIX interrupt */
3263         vsi->nb_used_qps = dev->data->nb_rx_queues;
3264         ice_vsi_queues_bind_intr(vsi);
3265
3266         /* Enable interrupts for all the queues */
3267         ice_vsi_enable_queues_intr(vsi);
3268
3269         rte_intr_enable(intr_handle);
3270
3271         return 0;
3272 }
3273
3274 static void
3275 ice_get_init_link_status(struct rte_eth_dev *dev)
3276 {
3277         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3280         struct ice_link_status link_status;
3281         int ret;
3282
3283         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3284                                    &link_status, NULL);
3285         if (ret != ICE_SUCCESS) {
3286                 PMD_DRV_LOG(ERR, "Failed to get link info");
3287                 pf->init_link_up = false;
3288                 return;
3289         }
3290
3291         if (link_status.link_info & ICE_AQ_LINK_UP)
3292                 pf->init_link_up = true;
3293 }
3294
3295 static int
3296 ice_dev_start(struct rte_eth_dev *dev)
3297 {
3298         struct rte_eth_dev_data *data = dev->data;
3299         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301         struct ice_vsi *vsi = pf->main_vsi;
3302         uint16_t nb_rxq = 0;
3303         uint16_t nb_txq, i;
3304         uint16_t max_frame_size;
3305         int mask, ret;
3306
3307         /* program Tx queues' context in hardware */
3308         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3309                 ret = ice_tx_queue_start(dev, nb_txq);
3310                 if (ret) {
3311                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3312                         goto tx_err;
3313                 }
3314         }
3315
3316         /* program Rx queues' context in hardware*/
3317         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3318                 ret = ice_rx_queue_start(dev, nb_rxq);
3319                 if (ret) {
3320                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3321                         goto rx_err;
3322                 }
3323         }
3324
3325         ice_set_rx_function(dev);
3326         ice_set_tx_function(dev);
3327
3328         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3329                         ETH_VLAN_EXTEND_MASK;
3330         ret = ice_vlan_offload_set(dev, mask);
3331         if (ret) {
3332                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3333                 goto rx_err;
3334         }
3335
3336         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3337         if (ice_rxq_intr_setup(dev))
3338                 return -EIO;
3339
3340         /* Enable receiving broadcast packets and transmitting packets */
3341         ret = ice_set_vsi_promisc(hw, vsi->idx,
3342                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3343                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3344                                   0);
3345         if (ret != ICE_SUCCESS)
3346                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3347
3348         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3349                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3350                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3351                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3352                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3353                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3354                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3355                                      NULL);
3356         if (ret != ICE_SUCCESS)
3357                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3358
3359         ice_get_init_link_status(dev);
3360
3361         ice_dev_set_link_up(dev);
3362
3363         /* Call get_link_info aq commond to enable/disable LSE */
3364         ice_link_update(dev, 0);
3365
3366         pf->adapter_stopped = false;
3367
3368         /* Set the max frame size to default value*/
3369         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3370                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3371                 ICE_FRAME_SIZE_MAX;
3372
3373         /* Set the max frame size to HW*/
3374         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3375
3376         return 0;
3377
3378         /* stop the started queues if failed to start all queues */
3379 rx_err:
3380         for (i = 0; i < nb_rxq; i++)
3381                 ice_rx_queue_stop(dev, i);
3382 tx_err:
3383         for (i = 0; i < nb_txq; i++)
3384                 ice_tx_queue_stop(dev, i);
3385
3386         return -EIO;
3387 }
3388
3389 static int
3390 ice_dev_reset(struct rte_eth_dev *dev)
3391 {
3392         int ret;
3393
3394         if (dev->data->sriov.active)
3395                 return -ENOTSUP;
3396
3397         ret = ice_dev_uninit(dev);
3398         if (ret) {
3399                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3400                 return -ENXIO;
3401         }
3402
3403         ret = ice_dev_init(dev);
3404         if (ret) {
3405                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3406                 return -ENXIO;
3407         }
3408
3409         return 0;
3410 }
3411
3412 static int
3413 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3414 {
3415         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3416         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417         struct ice_vsi *vsi = pf->main_vsi;
3418         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3419         bool is_safe_mode = pf->adapter->is_safe_mode;
3420         u64 phy_type_low;
3421         u64 phy_type_high;
3422
3423         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3424         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3425         dev_info->max_rx_queues = vsi->nb_qps;
3426         dev_info->max_tx_queues = vsi->nb_qps;
3427         dev_info->max_mac_addrs = vsi->max_macaddrs;
3428         dev_info->max_vfs = pci_dev->max_vfs;
3429         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3430         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3431
3432         dev_info->rx_offload_capa =
3433                 DEV_RX_OFFLOAD_VLAN_STRIP |
3434                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3435                 DEV_RX_OFFLOAD_KEEP_CRC |
3436                 DEV_RX_OFFLOAD_SCATTER |
3437                 DEV_RX_OFFLOAD_VLAN_FILTER;
3438         dev_info->tx_offload_capa =
3439                 DEV_TX_OFFLOAD_VLAN_INSERT |
3440                 DEV_TX_OFFLOAD_TCP_TSO |
3441                 DEV_TX_OFFLOAD_MULTI_SEGS |
3442                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3443         dev_info->flow_type_rss_offloads = 0;
3444
3445         if (!is_safe_mode) {
3446                 dev_info->rx_offload_capa |=
3447                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3448                         DEV_RX_OFFLOAD_UDP_CKSUM |
3449                         DEV_RX_OFFLOAD_TCP_CKSUM |
3450                         DEV_RX_OFFLOAD_QINQ_STRIP |
3451                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3452                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3453                         DEV_RX_OFFLOAD_RSS_HASH;
3454                 dev_info->tx_offload_capa |=
3455                         DEV_TX_OFFLOAD_QINQ_INSERT |
3456                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3457                         DEV_TX_OFFLOAD_UDP_CKSUM |
3458                         DEV_TX_OFFLOAD_TCP_CKSUM |
3459                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3460                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3461                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3462                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3463         }
3464
3465         dev_info->rx_queue_offload_capa = 0;
3466         dev_info->tx_queue_offload_capa = 0;
3467
3468         dev_info->reta_size = pf->hash_lut_size;
3469         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3470
3471         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3472                 .rx_thresh = {
3473                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3474                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3475                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3476                 },
3477                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3478                 .rx_drop_en = 0,
3479                 .offloads = 0,
3480         };
3481
3482         dev_info->default_txconf = (struct rte_eth_txconf) {
3483                 .tx_thresh = {
3484                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3485                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3486                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3487                 },
3488                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3489                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3490                 .offloads = 0,
3491         };
3492
3493         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3494                 .nb_max = ICE_MAX_RING_DESC,
3495                 .nb_min = ICE_MIN_RING_DESC,
3496                 .nb_align = ICE_ALIGN_RING_DESC,
3497         };
3498
3499         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3500                 .nb_max = ICE_MAX_RING_DESC,
3501                 .nb_min = ICE_MIN_RING_DESC,
3502                 .nb_align = ICE_ALIGN_RING_DESC,
3503         };
3504
3505         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3506                                ETH_LINK_SPEED_100M |
3507                                ETH_LINK_SPEED_1G |
3508                                ETH_LINK_SPEED_2_5G |
3509                                ETH_LINK_SPEED_5G |
3510                                ETH_LINK_SPEED_10G |
3511                                ETH_LINK_SPEED_20G |
3512                                ETH_LINK_SPEED_25G;
3513
3514         phy_type_low = hw->port_info->phy.phy_type_low;
3515         phy_type_high = hw->port_info->phy.phy_type_high;
3516
3517         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3518                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3519
3520         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3521                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3522                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3523
3524         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3525         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3526
3527         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3528         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3529         dev_info->default_rxportconf.nb_queues = 1;
3530         dev_info->default_txportconf.nb_queues = 1;
3531         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3532         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3533
3534         return 0;
3535 }
3536
3537 static inline int
3538 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3539                             struct rte_eth_link *link)
3540 {
3541         struct rte_eth_link *dst = link;
3542         struct rte_eth_link *src = &dev->data->dev_link;
3543
3544         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3545                                 *(uint64_t *)src) == 0)
3546                 return -1;
3547
3548         return 0;
3549 }
3550
3551 static inline int
3552 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3553                              struct rte_eth_link *link)
3554 {
3555         struct rte_eth_link *dst = &dev->data->dev_link;
3556         struct rte_eth_link *src = link;
3557
3558         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3559                                 *(uint64_t *)src) == 0)
3560                 return -1;
3561
3562         return 0;
3563 }
3564
3565 static int
3566 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3567 {
3568 #define CHECK_INTERVAL 100  /* 100ms */
3569 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3570         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571         struct ice_link_status link_status;
3572         struct rte_eth_link link, old;
3573         int status;
3574         unsigned int rep_cnt = MAX_REPEAT_TIME;
3575         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3576
3577         memset(&link, 0, sizeof(link));
3578         memset(&old, 0, sizeof(old));
3579         memset(&link_status, 0, sizeof(link_status));
3580         ice_atomic_read_link_status(dev, &old);
3581
3582         do {
3583                 /* Get link status information from hardware */
3584                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3585                                               &link_status, NULL);
3586                 if (status != ICE_SUCCESS) {
3587                         link.link_speed = ETH_SPEED_NUM_100M;
3588                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3589                         PMD_DRV_LOG(ERR, "Failed to get link info");
3590                         goto out;
3591                 }
3592
3593                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3594                 if (!wait_to_complete || link.link_status)
3595                         break;
3596
3597                 rte_delay_ms(CHECK_INTERVAL);
3598         } while (--rep_cnt);
3599
3600         if (!link.link_status)
3601                 goto out;
3602
3603         /* Full-duplex operation at all supported speeds */
3604         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3605
3606         /* Parse the link status */
3607         switch (link_status.link_speed) {
3608         case ICE_AQ_LINK_SPEED_10MB:
3609                 link.link_speed = ETH_SPEED_NUM_10M;
3610                 break;
3611         case ICE_AQ_LINK_SPEED_100MB:
3612                 link.link_speed = ETH_SPEED_NUM_100M;
3613                 break;
3614         case ICE_AQ_LINK_SPEED_1000MB:
3615                 link.link_speed = ETH_SPEED_NUM_1G;
3616                 break;
3617         case ICE_AQ_LINK_SPEED_2500MB:
3618                 link.link_speed = ETH_SPEED_NUM_2_5G;
3619                 break;
3620         case ICE_AQ_LINK_SPEED_5GB:
3621                 link.link_speed = ETH_SPEED_NUM_5G;
3622                 break;
3623         case ICE_AQ_LINK_SPEED_10GB:
3624                 link.link_speed = ETH_SPEED_NUM_10G;
3625                 break;
3626         case ICE_AQ_LINK_SPEED_20GB:
3627                 link.link_speed = ETH_SPEED_NUM_20G;
3628                 break;
3629         case ICE_AQ_LINK_SPEED_25GB:
3630                 link.link_speed = ETH_SPEED_NUM_25G;
3631                 break;
3632         case ICE_AQ_LINK_SPEED_40GB:
3633                 link.link_speed = ETH_SPEED_NUM_40G;
3634                 break;
3635         case ICE_AQ_LINK_SPEED_50GB:
3636                 link.link_speed = ETH_SPEED_NUM_50G;
3637                 break;
3638         case ICE_AQ_LINK_SPEED_100GB:
3639                 link.link_speed = ETH_SPEED_NUM_100G;
3640                 break;
3641         case ICE_AQ_LINK_SPEED_UNKNOWN:
3642                 PMD_DRV_LOG(ERR, "Unknown link speed");
3643                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3644                 break;
3645         default:
3646                 PMD_DRV_LOG(ERR, "None link speed");
3647                 link.link_speed = ETH_SPEED_NUM_NONE;
3648                 break;
3649         }
3650
3651         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3652                               ETH_LINK_SPEED_FIXED);
3653
3654 out:
3655         ice_atomic_write_link_status(dev, &link);
3656         if (link.link_status == old.link_status)
3657                 return -1;
3658
3659         return 0;
3660 }
3661
3662 /* Force the physical link state by getting the current PHY capabilities from
3663  * hardware and setting the PHY config based on the determined capabilities. If
3664  * link changes, link event will be triggered because both the Enable Automatic
3665  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3666  */
3667 static enum ice_status
3668 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3669 {
3670         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3671         struct ice_aqc_get_phy_caps_data *pcaps;
3672         struct ice_port_info *pi;
3673         enum ice_status status;
3674
3675         if (!hw || !hw->port_info)
3676                 return ICE_ERR_PARAM;
3677
3678         pi = hw->port_info;
3679
3680         pcaps = (struct ice_aqc_get_phy_caps_data *)
3681                 ice_malloc(hw, sizeof(*pcaps));
3682         if (!pcaps)
3683                 return ICE_ERR_NO_MEMORY;
3684
3685         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3686                                      NULL);
3687         if (status)
3688                 goto out;
3689
3690         /* No change in link */
3691         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3692             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3693                 goto out;
3694
3695         cfg.phy_type_low = pcaps->phy_type_low;
3696         cfg.phy_type_high = pcaps->phy_type_high;
3697         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3698         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3699         cfg.eee_cap = pcaps->eee_cap;
3700         cfg.eeer_value = pcaps->eeer_value;
3701         cfg.link_fec_opt = pcaps->link_fec_options;
3702         if (link_up)
3703                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3704         else
3705                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3706
3707         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3708
3709 out:
3710         ice_free(hw, pcaps);
3711         return status;
3712 }
3713
3714 static int
3715 ice_dev_set_link_up(struct rte_eth_dev *dev)
3716 {
3717         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718
3719         return ice_force_phys_link_state(hw, true);
3720 }
3721
3722 static int
3723 ice_dev_set_link_down(struct rte_eth_dev *dev)
3724 {
3725         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726
3727         return ice_force_phys_link_state(hw, false);
3728 }
3729
3730 static int
3731 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3732 {
3733         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3734         struct rte_eth_dev_data *dev_data = pf->dev_data;
3735         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3736
3737         /* check if mtu is within the allowed range */
3738         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3739                 return -EINVAL;
3740
3741         /* mtu setting is forbidden if port is start */
3742         if (dev_data->dev_started) {
3743                 PMD_DRV_LOG(ERR,
3744                             "port %d must be stopped before configuration",
3745                             dev_data->port_id);
3746                 return -EBUSY;
3747         }
3748
3749         if (frame_size > RTE_ETHER_MAX_LEN)
3750                 dev_data->dev_conf.rxmode.offloads |=
3751                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3752         else
3753                 dev_data->dev_conf.rxmode.offloads &=
3754                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3755
3756         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3757
3758         return 0;
3759 }
3760
3761 static int ice_macaddr_set(struct rte_eth_dev *dev,
3762                            struct rte_ether_addr *mac_addr)
3763 {
3764         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3766         struct ice_vsi *vsi = pf->main_vsi;
3767         struct ice_mac_filter *f;
3768         uint8_t flags = 0;
3769         int ret;
3770
3771         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3772                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3773                 return -EINVAL;
3774         }
3775
3776         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3777                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3778                         break;
3779         }
3780
3781         if (!f) {
3782                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3783                 return -EIO;
3784         }
3785
3786         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3787         if (ret != ICE_SUCCESS) {
3788                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3789                 return -EIO;
3790         }
3791         ret = ice_add_mac_filter(vsi, mac_addr);
3792         if (ret != ICE_SUCCESS) {
3793                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3794                 return -EIO;
3795         }
3796         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3797
3798         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3799         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3800         if (ret != ICE_SUCCESS)
3801                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3802
3803         return 0;
3804 }
3805
3806 /* Add a MAC address, and update filters */
3807 static int
3808 ice_macaddr_add(struct rte_eth_dev *dev,
3809                 struct rte_ether_addr *mac_addr,
3810                 __rte_unused uint32_t index,
3811                 __rte_unused uint32_t pool)
3812 {
3813         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3814         struct ice_vsi *vsi = pf->main_vsi;
3815         int ret;
3816
3817         ret = ice_add_mac_filter(vsi, mac_addr);
3818         if (ret != ICE_SUCCESS) {
3819                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3820                 return -EINVAL;
3821         }
3822
3823         return ICE_SUCCESS;
3824 }
3825
3826 /* Remove a MAC address, and update filters */
3827 static void
3828 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3829 {
3830         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3831         struct ice_vsi *vsi = pf->main_vsi;
3832         struct rte_eth_dev_data *data = dev->data;
3833         struct rte_ether_addr *macaddr;
3834         int ret;
3835
3836         macaddr = &data->mac_addrs[index];
3837         ret = ice_remove_mac_filter(vsi, macaddr);
3838         if (ret) {
3839                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3840                 return;
3841         }
3842 }
3843
3844 static int
3845 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3846 {
3847         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3848         struct ice_vsi *vsi = pf->main_vsi;
3849         int ret;
3850
3851         PMD_INIT_FUNC_TRACE();
3852
3853         if (on) {
3854                 ret = ice_add_vlan_filter(vsi, vlan_id);
3855                 if (ret < 0) {
3856                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3857                         return -EINVAL;
3858                 }
3859         } else {
3860                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3861                 if (ret < 0) {
3862                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3863                         return -EINVAL;
3864                 }
3865         }
3866
3867         return 0;
3868 }
3869
3870 /* Configure vlan filter on or off */
3871 static int
3872 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3873 {
3874         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3875         struct ice_vsi_ctx ctxt;
3876         uint8_t sec_flags, sw_flags2;
3877         int ret = 0;
3878
3879         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3880                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3881         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3882
3883         if (on) {
3884                 vsi->info.sec_flags |= sec_flags;
3885                 vsi->info.sw_flags2 |= sw_flags2;
3886         } else {
3887                 vsi->info.sec_flags &= ~sec_flags;
3888                 vsi->info.sw_flags2 &= ~sw_flags2;
3889         }
3890         vsi->info.sw_id = hw->port_info->sw_id;
3891         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3892         ctxt.info.valid_sections =
3893                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3894                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3895         ctxt.vsi_num = vsi->vsi_id;
3896
3897         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3898         if (ret) {
3899                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3900                             on ? "enable" : "disable");
3901                 return -EINVAL;
3902         } else {
3903                 vsi->info.valid_sections |=
3904                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3905                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3906         }
3907
3908         /* consist with other drivers, allow untagged packet when vlan filter on */
3909         if (on)
3910                 ret = ice_add_vlan_filter(vsi, 0);
3911         else
3912                 ret = ice_remove_vlan_filter(vsi, 0);
3913
3914         return 0;
3915 }
3916
3917 static int
3918 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3919 {
3920         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3921         struct ice_vsi_ctx ctxt;
3922         uint8_t vlan_flags;
3923         int ret = 0;
3924
3925         /* Check if it has been already on or off */
3926         if (vsi->info.valid_sections &
3927                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3928                 if (on) {
3929                         if ((vsi->info.vlan_flags &
3930                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3931                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3932                                 return 0; /* already on */
3933                 } else {
3934                         if ((vsi->info.vlan_flags &
3935                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3936                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3937                                 return 0; /* already off */
3938                 }
3939         }
3940
3941         if (on)
3942                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3943         else
3944                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3945         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3946         vsi->info.vlan_flags |= vlan_flags;
3947         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3948         ctxt.info.valid_sections =
3949                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3950         ctxt.vsi_num = vsi->vsi_id;
3951         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3952         if (ret) {
3953                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3954                             on ? "enable" : "disable");
3955                 return -EINVAL;
3956         }
3957
3958         vsi->info.valid_sections |=
3959                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3960
3961         return ret;
3962 }
3963
3964 static int
3965 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3966 {
3967         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3968         struct ice_vsi *vsi = pf->main_vsi;
3969         struct rte_eth_rxmode *rxmode;
3970
3971         rxmode = &dev->data->dev_conf.rxmode;
3972         if (mask & ETH_VLAN_FILTER_MASK) {
3973                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3974                         ice_vsi_config_vlan_filter(vsi, true);
3975                 else
3976                         ice_vsi_config_vlan_filter(vsi, false);
3977         }
3978
3979         if (mask & ETH_VLAN_STRIP_MASK) {
3980                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3981                         ice_vsi_config_vlan_stripping(vsi, true);
3982                 else
3983                         ice_vsi_config_vlan_stripping(vsi, false);
3984         }
3985
3986         if (mask & ETH_VLAN_EXTEND_MASK) {
3987                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3988                         ice_vsi_config_double_vlan(vsi, true);
3989                 else
3990                         ice_vsi_config_double_vlan(vsi, false);
3991         }
3992
3993         return 0;
3994 }
3995
3996 static int
3997 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3998 {
3999         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4000         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4001         int ret;
4002
4003         if (!lut)
4004                 return -EINVAL;
4005
4006         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4007                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
4008                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4009                 if (ret) {
4010                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4011                         return -EINVAL;
4012                 }
4013         } else {
4014                 uint64_t *lut_dw = (uint64_t *)lut;
4015                 uint16_t i, lut_size_dw = lut_size / 4;
4016
4017                 for (i = 0; i < lut_size_dw; i++)
4018                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4019         }
4020
4021         return 0;
4022 }
4023
4024 static int
4025 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4026 {
4027         struct ice_pf *pf;
4028         struct ice_hw *hw;
4029         int ret;
4030
4031         if (!vsi || !lut)
4032                 return -EINVAL;
4033
4034         pf = ICE_VSI_TO_PF(vsi);
4035         hw = ICE_VSI_TO_HW(vsi);
4036
4037         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4038                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
4039                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4040                 if (ret) {
4041                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4042                         return -EINVAL;
4043                 }
4044         } else {
4045                 uint64_t *lut_dw = (uint64_t *)lut;
4046                 uint16_t i, lut_size_dw = lut_size / 4;
4047
4048                 for (i = 0; i < lut_size_dw; i++)
4049                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4050
4051                 ice_flush(hw);
4052         }
4053
4054         return 0;
4055 }
4056
4057 static int
4058 ice_rss_reta_update(struct rte_eth_dev *dev,
4059                     struct rte_eth_rss_reta_entry64 *reta_conf,
4060                     uint16_t reta_size)
4061 {
4062         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4063         uint16_t i, lut_size = pf->hash_lut_size;
4064         uint16_t idx, shift;
4065         uint8_t *lut;
4066         int ret;
4067
4068         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4069             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4070             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4071                 PMD_DRV_LOG(ERR,
4072                             "The size of hash lookup table configured (%d)"
4073                             "doesn't match the number hardware can "
4074                             "supported (128, 512, 2048)",
4075                             reta_size);
4076                 return -EINVAL;
4077         }
4078
4079         /* It MUST use the current LUT size to get the RSS lookup table,
4080          * otherwise if will fail with -100 error code.
4081          */
4082         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4083         if (!lut) {
4084                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4085                 return -ENOMEM;
4086         }
4087         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4088         if (ret)
4089                 goto out;
4090
4091         for (i = 0; i < reta_size; i++) {
4092                 idx = i / RTE_RETA_GROUP_SIZE;
4093                 shift = i % RTE_RETA_GROUP_SIZE;
4094                 if (reta_conf[idx].mask & (1ULL << shift))
4095                         lut[i] = reta_conf[idx].reta[shift];
4096         }
4097         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4098         if (ret == 0 && lut_size != reta_size) {
4099                 PMD_DRV_LOG(INFO,
4100                             "The size of hash lookup table is changed from (%d) to (%d)",
4101                             lut_size, reta_size);
4102                 pf->hash_lut_size = reta_size;
4103         }
4104
4105 out:
4106         rte_free(lut);
4107
4108         return ret;
4109 }
4110
4111 static int
4112 ice_rss_reta_query(struct rte_eth_dev *dev,
4113                    struct rte_eth_rss_reta_entry64 *reta_conf,
4114                    uint16_t reta_size)
4115 {
4116         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4117         uint16_t i, lut_size = pf->hash_lut_size;
4118         uint16_t idx, shift;
4119         uint8_t *lut;
4120         int ret;
4121
4122         if (reta_size != lut_size) {
4123                 PMD_DRV_LOG(ERR,
4124                             "The size of hash lookup table configured (%d)"
4125                             "doesn't match the number hardware can "
4126                             "supported (%d)",
4127                             reta_size, lut_size);
4128                 return -EINVAL;
4129         }
4130
4131         lut = rte_zmalloc(NULL, reta_size, 0);
4132         if (!lut) {
4133                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4134                 return -ENOMEM;
4135         }
4136
4137         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4138         if (ret)
4139                 goto out;
4140
4141         for (i = 0; i < reta_size; i++) {
4142                 idx = i / RTE_RETA_GROUP_SIZE;
4143                 shift = i % RTE_RETA_GROUP_SIZE;
4144                 if (reta_conf[idx].mask & (1ULL << shift))
4145                         reta_conf[idx].reta[shift] = lut[i];
4146         }
4147
4148 out:
4149         rte_free(lut);
4150
4151         return ret;
4152 }
4153
4154 static int
4155 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4156 {
4157         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4158         int ret = 0;
4159
4160         if (!key || key_len == 0) {
4161                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4162                 return 0;
4163         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4164                    sizeof(uint32_t)) {
4165                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4166                 return -EINVAL;
4167         }
4168
4169         struct ice_aqc_get_set_rss_keys *key_dw =
4170                 (struct ice_aqc_get_set_rss_keys *)key;
4171
4172         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4173         if (ret) {
4174                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4175                 ret = -EINVAL;
4176         }
4177
4178         return ret;
4179 }
4180
4181 static int
4182 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4183 {
4184         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4185         int ret;
4186
4187         if (!key || !key_len)
4188                 return -EINVAL;
4189
4190         ret = ice_aq_get_rss_key
4191                 (hw, vsi->idx,
4192                  (struct ice_aqc_get_set_rss_keys *)key);
4193         if (ret) {
4194                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4195                 return -EINVAL;
4196         }
4197         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4198
4199         return 0;
4200 }
4201
4202 static int
4203 ice_rss_hash_update(struct rte_eth_dev *dev,
4204                     struct rte_eth_rss_conf *rss_conf)
4205 {
4206         enum ice_status status = ICE_SUCCESS;
4207         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4208         struct ice_vsi *vsi = pf->main_vsi;
4209
4210         /* set hash key */
4211         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4212         if (status)
4213                 return status;
4214
4215         if (rss_conf->rss_hf == 0)
4216                 return 0;
4217
4218         /* RSS hash configuration */
4219         ice_rss_hash_set(pf, rss_conf->rss_hf);
4220
4221         return 0;
4222 }
4223
4224 static int
4225 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4226                       struct rte_eth_rss_conf *rss_conf)
4227 {
4228         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4229         struct ice_vsi *vsi = pf->main_vsi;
4230
4231         ice_get_rss_key(vsi, rss_conf->rss_key,
4232                         &rss_conf->rss_key_len);
4233
4234         /* TODO: default set to 0 as hf config is not supported now */
4235         rss_conf->rss_hf = 0;
4236         return 0;
4237 }
4238
4239 static int
4240 ice_promisc_enable(struct rte_eth_dev *dev)
4241 {
4242         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4243         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4244         struct ice_vsi *vsi = pf->main_vsi;
4245         enum ice_status status;
4246         uint8_t pmask;
4247         int ret = 0;
4248
4249         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4250                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4251
4252         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4253         switch (status) {
4254         case ICE_ERR_ALREADY_EXISTS:
4255                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4256         case ICE_SUCCESS:
4257                 break;
4258         default:
4259                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4260                 ret = -EAGAIN;
4261         }
4262
4263         return ret;
4264 }
4265
4266 static int
4267 ice_promisc_disable(struct rte_eth_dev *dev)
4268 {
4269         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4270         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         struct ice_vsi *vsi = pf->main_vsi;
4272         enum ice_status status;
4273         uint8_t pmask;
4274         int ret = 0;
4275
4276         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4277                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4278
4279         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4280         if (status != ICE_SUCCESS) {
4281                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4282                 ret = -EAGAIN;
4283         }
4284
4285         return ret;
4286 }
4287
4288 static int
4289 ice_allmulti_enable(struct rte_eth_dev *dev)
4290 {
4291         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4292         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         struct ice_vsi *vsi = pf->main_vsi;
4294         enum ice_status status;
4295         uint8_t pmask;
4296         int ret = 0;
4297
4298         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4299
4300         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4301
4302         switch (status) {
4303         case ICE_ERR_ALREADY_EXISTS:
4304                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4305         case ICE_SUCCESS:
4306                 break;
4307         default:
4308                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4309                 ret = -EAGAIN;
4310         }
4311
4312         return ret;
4313 }
4314
4315 static int
4316 ice_allmulti_disable(struct rte_eth_dev *dev)
4317 {
4318         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4319         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         struct ice_vsi *vsi = pf->main_vsi;
4321         enum ice_status status;
4322         uint8_t pmask;
4323         int ret = 0;
4324
4325         if (dev->data->promiscuous == 1)
4326                 return 0; /* must remain in all_multicast mode */
4327
4328         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4329
4330         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4331         if (status != ICE_SUCCESS) {
4332                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4333                 ret = -EAGAIN;
4334         }
4335
4336         return ret;
4337 }
4338
4339 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4340                                     uint16_t queue_id)
4341 {
4342         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4343         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4344         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345         uint32_t val;
4346         uint16_t msix_intr;
4347
4348         msix_intr = intr_handle->intr_vec[queue_id];
4349
4350         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4351               GLINT_DYN_CTL_ITR_INDX_M;
4352         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4353
4354         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4355         rte_intr_ack(&pci_dev->intr_handle);
4356
4357         return 0;
4358 }
4359
4360 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4361                                      uint16_t queue_id)
4362 {
4363         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4364         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4365         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366         uint16_t msix_intr;
4367
4368         msix_intr = intr_handle->intr_vec[queue_id];
4369
4370         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4371
4372         return 0;
4373 }
4374
4375 static int
4376 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4377 {
4378         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379         u8 ver, patch;
4380         u16 build;
4381         int ret;
4382
4383         ver = hw->flash.orom.major;
4384         patch = hw->flash.orom.patch;
4385         build = hw->flash.orom.build;
4386
4387         ret = snprintf(fw_version, fw_size,
4388                         "%x.%02x 0x%08x %d.%d.%d",
4389                         hw->flash.nvm.major,
4390                         hw->flash.nvm.minor,
4391                         hw->flash.nvm.eetrack,
4392                         ver, build, patch);
4393
4394         /* add the size of '\0' */
4395         ret += 1;
4396         if (fw_size < (u32)ret)
4397                 return ret;
4398         else
4399                 return 0;
4400 }
4401
4402 static int
4403 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4404 {
4405         struct ice_hw *hw;
4406         struct ice_vsi_ctx ctxt;
4407         uint8_t vlan_flags = 0;
4408         int ret;
4409
4410         if (!vsi || !info) {
4411                 PMD_DRV_LOG(ERR, "invalid parameters");
4412                 return -EINVAL;
4413         }
4414
4415         if (info->on) {
4416                 vsi->info.pvid = info->config.pvid;
4417                 /**
4418                  * If insert pvid is enabled, only tagged pkts are
4419                  * allowed to be sent out.
4420                  */
4421                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
4422                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4423         } else {
4424                 vsi->info.pvid = 0;
4425                 if (info->config.reject.tagged == 0)
4426                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
4427
4428                 if (info->config.reject.untagged == 0)
4429                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4430         }
4431         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
4432                                   ICE_AQ_VSI_VLAN_MODE_M);
4433         vsi->info.vlan_flags |= vlan_flags;
4434         memset(&ctxt, 0, sizeof(ctxt));
4435         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4436         ctxt.info.valid_sections =
4437                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4438         ctxt.vsi_num = vsi->vsi_id;
4439
4440         hw = ICE_VSI_TO_HW(vsi);
4441         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4442         if (ret != ICE_SUCCESS) {
4443                 PMD_DRV_LOG(ERR,
4444                             "update VSI for VLAN insert failed, err %d",
4445                             ret);
4446                 return -EINVAL;
4447         }
4448
4449         vsi->info.valid_sections |=
4450                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4451
4452         return ret;
4453 }
4454
4455 static int
4456 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4457 {
4458         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4459         struct ice_vsi *vsi = pf->main_vsi;
4460         struct rte_eth_dev_data *data = pf->dev_data;
4461         struct ice_vsi_vlan_pvid_info info;
4462         int ret;
4463
4464         memset(&info, 0, sizeof(info));
4465         info.on = on;
4466         if (info.on) {
4467                 info.config.pvid = pvid;
4468         } else {
4469                 info.config.reject.tagged =
4470                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4471                 info.config.reject.untagged =
4472                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4473         }
4474
4475         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4476         if (ret < 0) {
4477                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4478                 return -EINVAL;
4479         }
4480
4481         return 0;
4482 }
4483
4484 static int
4485 ice_get_eeprom_length(struct rte_eth_dev *dev)
4486 {
4487         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488
4489         return hw->flash.flash_size;
4490 }
4491
4492 static int
4493 ice_get_eeprom(struct rte_eth_dev *dev,
4494                struct rte_dev_eeprom_info *eeprom)
4495 {
4496         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497         enum ice_status status = ICE_SUCCESS;
4498         uint8_t *data = eeprom->data;
4499
4500         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4501
4502         status = ice_acquire_nvm(hw, ICE_RES_READ);
4503         if (status) {
4504                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4505                 return -EIO;
4506         }
4507
4508         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4509                                    data, false);
4510
4511         ice_release_nvm(hw);
4512
4513         if (status) {
4514                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4515                 return -EIO;
4516         }
4517
4518         return 0;
4519 }
4520
4521 static void
4522 ice_stat_update_32(struct ice_hw *hw,
4523                    uint32_t reg,
4524                    bool offset_loaded,
4525                    uint64_t *offset,
4526                    uint64_t *stat)
4527 {
4528         uint64_t new_data;
4529
4530         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4531         if (!offset_loaded)
4532                 *offset = new_data;
4533
4534         if (new_data >= *offset)
4535                 *stat = (uint64_t)(new_data - *offset);
4536         else
4537                 *stat = (uint64_t)((new_data +
4538                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4539                                    - *offset);
4540 }
4541
4542 static void
4543 ice_stat_update_40(struct ice_hw *hw,
4544                    uint32_t hireg,
4545                    uint32_t loreg,
4546                    bool offset_loaded,
4547                    uint64_t *offset,
4548                    uint64_t *stat)
4549 {
4550         uint64_t new_data;
4551
4552         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4553         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4554                     ICE_32_BIT_WIDTH;
4555
4556         if (!offset_loaded)
4557                 *offset = new_data;
4558
4559         if (new_data >= *offset)
4560                 *stat = new_data - *offset;
4561         else
4562                 *stat = (uint64_t)((new_data +
4563                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4564                                    *offset);
4565
4566         *stat &= ICE_40_BIT_MASK;
4567 }
4568
4569 /* Get all the statistics of a VSI */
4570 static void
4571 ice_update_vsi_stats(struct ice_vsi *vsi)
4572 {
4573         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4574         struct ice_eth_stats *nes = &vsi->eth_stats;
4575         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4576         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4577
4578         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4579                            vsi->offset_loaded, &oes->rx_bytes,
4580                            &nes->rx_bytes);
4581         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4582                            vsi->offset_loaded, &oes->rx_unicast,
4583                            &nes->rx_unicast);
4584         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4585                            vsi->offset_loaded, &oes->rx_multicast,
4586                            &nes->rx_multicast);
4587         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4588                            vsi->offset_loaded, &oes->rx_broadcast,
4589                            &nes->rx_broadcast);
4590         /* enlarge the limitation when rx_bytes overflowed */
4591         if (vsi->offset_loaded) {
4592                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4593                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4594                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4595         }
4596         vsi->old_rx_bytes = nes->rx_bytes;
4597         /* exclude CRC bytes */
4598         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4599                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4600
4601         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4602                            &oes->rx_discards, &nes->rx_discards);
4603         /* GLV_REPC not supported */
4604         /* GLV_RMPC not supported */
4605         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4606                            &oes->rx_unknown_protocol,
4607                            &nes->rx_unknown_protocol);
4608         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4609                            vsi->offset_loaded, &oes->tx_bytes,
4610                            &nes->tx_bytes);
4611         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4612                            vsi->offset_loaded, &oes->tx_unicast,
4613                            &nes->tx_unicast);
4614         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4615                            vsi->offset_loaded, &oes->tx_multicast,
4616                            &nes->tx_multicast);
4617         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4618                            vsi->offset_loaded,  &oes->tx_broadcast,
4619                            &nes->tx_broadcast);
4620         /* GLV_TDPC not supported */
4621         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4622                            &oes->tx_errors, &nes->tx_errors);
4623         /* enlarge the limitation when tx_bytes overflowed */
4624         if (vsi->offset_loaded) {
4625                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4626                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4627                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4628         }
4629         vsi->old_tx_bytes = nes->tx_bytes;
4630         vsi->offset_loaded = true;
4631
4632         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4633                     vsi->vsi_id);
4634         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4635         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4636         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4637         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4638         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4639         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4640                     nes->rx_unknown_protocol);
4641         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4642         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4643         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4644         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4645         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4646         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4647         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4648                     vsi->vsi_id);
4649 }
4650
4651 static void
4652 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4653 {
4654         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4655         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4656
4657         /* Get statistics of struct ice_eth_stats */
4658         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4659                            GLPRT_GORCL(hw->port_info->lport),
4660                            pf->offset_loaded, &os->eth.rx_bytes,
4661                            &ns->eth.rx_bytes);
4662         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4663                            GLPRT_UPRCL(hw->port_info->lport),
4664                            pf->offset_loaded, &os->eth.rx_unicast,
4665                            &ns->eth.rx_unicast);
4666         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4667                            GLPRT_MPRCL(hw->port_info->lport),
4668                            pf->offset_loaded, &os->eth.rx_multicast,
4669                            &ns->eth.rx_multicast);
4670         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4671                            GLPRT_BPRCL(hw->port_info->lport),
4672                            pf->offset_loaded, &os->eth.rx_broadcast,
4673                            &ns->eth.rx_broadcast);
4674         ice_stat_update_32(hw, PRTRPB_RDPC,
4675                            pf->offset_loaded, &os->eth.rx_discards,
4676                            &ns->eth.rx_discards);
4677         /* enlarge the limitation when rx_bytes overflowed */
4678         if (pf->offset_loaded) {
4679                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4680                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4681                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4682         }
4683         pf->old_rx_bytes = ns->eth.rx_bytes;
4684
4685         /* Workaround: CRC size should not be included in byte statistics,
4686          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4687          * packet.
4688          */
4689         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4690                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4691
4692         /* GLPRT_REPC not supported */
4693         /* GLPRT_RMPC not supported */
4694         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4695                            pf->offset_loaded,
4696                            &os->eth.rx_unknown_protocol,
4697                            &ns->eth.rx_unknown_protocol);
4698         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4699                            GLPRT_GOTCL(hw->port_info->lport),
4700                            pf->offset_loaded, &os->eth.tx_bytes,
4701                            &ns->eth.tx_bytes);
4702         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4703                            GLPRT_UPTCL(hw->port_info->lport),
4704                            pf->offset_loaded, &os->eth.tx_unicast,
4705                            &ns->eth.tx_unicast);
4706         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4707                            GLPRT_MPTCL(hw->port_info->lport),
4708                            pf->offset_loaded, &os->eth.tx_multicast,
4709                            &ns->eth.tx_multicast);
4710         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4711                            GLPRT_BPTCL(hw->port_info->lport),
4712                            pf->offset_loaded, &os->eth.tx_broadcast,
4713                            &ns->eth.tx_broadcast);
4714         /* enlarge the limitation when tx_bytes overflowed */
4715         if (pf->offset_loaded) {
4716                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4717                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4718                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4719         }
4720         pf->old_tx_bytes = ns->eth.tx_bytes;
4721         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4722                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4723
4724         /* GLPRT_TEPC not supported */
4725
4726         /* additional port specific stats */
4727         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4728                            pf->offset_loaded, &os->tx_dropped_link_down,
4729                            &ns->tx_dropped_link_down);
4730         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4731                            pf->offset_loaded, &os->crc_errors,
4732                            &ns->crc_errors);
4733         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4734                            pf->offset_loaded, &os->illegal_bytes,
4735                            &ns->illegal_bytes);
4736         /* GLPRT_ERRBC not supported */
4737         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4738                            pf->offset_loaded, &os->mac_local_faults,
4739                            &ns->mac_local_faults);
4740         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4741                            pf->offset_loaded, &os->mac_remote_faults,
4742                            &ns->mac_remote_faults);
4743
4744         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4745                            pf->offset_loaded, &os->rx_len_errors,
4746                            &ns->rx_len_errors);
4747
4748         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4749                            pf->offset_loaded, &os->link_xon_rx,
4750                            &ns->link_xon_rx);
4751         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4752                            pf->offset_loaded, &os->link_xoff_rx,
4753                            &ns->link_xoff_rx);
4754         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4755                            pf->offset_loaded, &os->link_xon_tx,
4756                            &ns->link_xon_tx);
4757         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4758                            pf->offset_loaded, &os->link_xoff_tx,
4759                            &ns->link_xoff_tx);
4760         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4761                            GLPRT_PRC64L(hw->port_info->lport),
4762                            pf->offset_loaded, &os->rx_size_64,
4763                            &ns->rx_size_64);
4764         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4765                            GLPRT_PRC127L(hw->port_info->lport),
4766                            pf->offset_loaded, &os->rx_size_127,
4767                            &ns->rx_size_127);
4768         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4769                            GLPRT_PRC255L(hw->port_info->lport),
4770                            pf->offset_loaded, &os->rx_size_255,
4771                            &ns->rx_size_255);
4772         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4773                            GLPRT_PRC511L(hw->port_info->lport),
4774                            pf->offset_loaded, &os->rx_size_511,
4775                            &ns->rx_size_511);
4776         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4777                            GLPRT_PRC1023L(hw->port_info->lport),
4778                            pf->offset_loaded, &os->rx_size_1023,
4779                            &ns->rx_size_1023);
4780         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4781                            GLPRT_PRC1522L(hw->port_info->lport),
4782                            pf->offset_loaded, &os->rx_size_1522,
4783                            &ns->rx_size_1522);
4784         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4785                            GLPRT_PRC9522L(hw->port_info->lport),
4786                            pf->offset_loaded, &os->rx_size_big,
4787                            &ns->rx_size_big);
4788         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4789                            pf->offset_loaded, &os->rx_undersize,
4790                            &ns->rx_undersize);
4791         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4792                            pf->offset_loaded, &os->rx_fragments,
4793                            &ns->rx_fragments);
4794         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4795                            pf->offset_loaded, &os->rx_oversize,
4796                            &ns->rx_oversize);
4797         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4798                            pf->offset_loaded, &os->rx_jabber,
4799                            &ns->rx_jabber);
4800         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4801                            GLPRT_PTC64L(hw->port_info->lport),
4802                            pf->offset_loaded, &os->tx_size_64,
4803                            &ns->tx_size_64);
4804         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4805                            GLPRT_PTC127L(hw->port_info->lport),
4806                            pf->offset_loaded, &os->tx_size_127,
4807                            &ns->tx_size_127);
4808         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4809                            GLPRT_PTC255L(hw->port_info->lport),
4810                            pf->offset_loaded, &os->tx_size_255,
4811                            &ns->tx_size_255);
4812         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4813                            GLPRT_PTC511L(hw->port_info->lport),
4814                            pf->offset_loaded, &os->tx_size_511,
4815                            &ns->tx_size_511);
4816         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4817                            GLPRT_PTC1023L(hw->port_info->lport),
4818                            pf->offset_loaded, &os->tx_size_1023,
4819                            &ns->tx_size_1023);
4820         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4821                            GLPRT_PTC1522L(hw->port_info->lport),
4822                            pf->offset_loaded, &os->tx_size_1522,
4823                            &ns->tx_size_1522);
4824         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4825                            GLPRT_PTC9522L(hw->port_info->lport),
4826                            pf->offset_loaded, &os->tx_size_big,
4827                            &ns->tx_size_big);
4828
4829         /* GLPRT_MSPDC not supported */
4830         /* GLPRT_XEC not supported */
4831
4832         pf->offset_loaded = true;
4833
4834         if (pf->main_vsi)
4835                 ice_update_vsi_stats(pf->main_vsi);
4836 }
4837
4838 /* Get all statistics of a port */
4839 static int
4840 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4841 {
4842         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4843         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4845
4846         /* call read registers - updates values, now write them to struct */
4847         ice_read_stats_registers(pf, hw);
4848
4849         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4850                           pf->main_vsi->eth_stats.rx_multicast +
4851                           pf->main_vsi->eth_stats.rx_broadcast -
4852                           pf->main_vsi->eth_stats.rx_discards;
4853         stats->opackets = ns->eth.tx_unicast +
4854                           ns->eth.tx_multicast +
4855                           ns->eth.tx_broadcast;
4856         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4857         stats->obytes   = ns->eth.tx_bytes;
4858         stats->oerrors  = ns->eth.tx_errors +
4859                           pf->main_vsi->eth_stats.tx_errors;
4860
4861         /* Rx Errors */
4862         stats->imissed  = ns->eth.rx_discards +
4863                           pf->main_vsi->eth_stats.rx_discards;
4864         stats->ierrors  = ns->crc_errors +
4865                           ns->rx_undersize +
4866                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4867
4868         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4869         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4870         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4871         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4872         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4873         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4874         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4875                     pf->main_vsi->eth_stats.rx_discards);
4876         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4877                     ns->eth.rx_unknown_protocol);
4878         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4879         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4880         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4881         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4882         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4883         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4884                     pf->main_vsi->eth_stats.tx_discards);
4885         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4886
4887         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4888                     ns->tx_dropped_link_down);
4889         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4890         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4891                     ns->illegal_bytes);
4892         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4893         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4894                     ns->mac_local_faults);
4895         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4896                     ns->mac_remote_faults);
4897         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4898         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4899         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4900         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4901         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4902         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4903         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4904         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4905         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4906         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4907         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4908         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4909         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4910         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4911         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4912         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4913         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4914         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4915         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4916         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4917         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4918         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4919         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4920         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4921         return 0;
4922 }
4923
4924 /* Reset the statistics */
4925 static int
4926 ice_stats_reset(struct rte_eth_dev *dev)
4927 {
4928         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4929         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4930
4931         /* Mark PF and VSI stats to update the offset, aka "reset" */
4932         pf->offset_loaded = false;
4933         if (pf->main_vsi)
4934                 pf->main_vsi->offset_loaded = false;
4935
4936         /* read the stats, reading current register values into offset */
4937         ice_read_stats_registers(pf, hw);
4938
4939         return 0;
4940 }
4941
4942 static uint32_t
4943 ice_xstats_calc_num(void)
4944 {
4945         uint32_t num;
4946
4947         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4948
4949         return num;
4950 }
4951
4952 static int
4953 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4954                unsigned int n)
4955 {
4956         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4957         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         unsigned int i;
4959         unsigned int count;
4960         struct ice_hw_port_stats *hw_stats = &pf->stats;
4961
4962         count = ice_xstats_calc_num();
4963         if (n < count)
4964                 return count;
4965
4966         ice_read_stats_registers(pf, hw);
4967
4968         if (!xstats)
4969                 return 0;
4970
4971         count = 0;
4972
4973         /* Get stats from ice_eth_stats struct */
4974         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4975                 xstats[count].value =
4976                         *(uint64_t *)((char *)&hw_stats->eth +
4977                                       ice_stats_strings[i].offset);
4978                 xstats[count].id = count;
4979                 count++;
4980         }
4981
4982         /* Get individiual stats from ice_hw_port struct */
4983         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4984                 xstats[count].value =
4985                         *(uint64_t *)((char *)hw_stats +
4986                                       ice_hw_port_strings[i].offset);
4987                 xstats[count].id = count;
4988                 count++;
4989         }
4990
4991         return count;
4992 }
4993
4994 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4995                                 struct rte_eth_xstat_name *xstats_names,
4996                                 __rte_unused unsigned int limit)
4997 {
4998         unsigned int count = 0;
4999         unsigned int i;
5000
5001         if (!xstats_names)
5002                 return ice_xstats_calc_num();
5003
5004         /* Note: limit checked in rte_eth_xstats_names() */
5005
5006         /* Get stats from ice_eth_stats struct */
5007         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5008                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5009                         sizeof(xstats_names[count].name));
5010                 count++;
5011         }
5012
5013         /* Get individiual stats from ice_hw_port struct */
5014         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5015                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5016                         sizeof(xstats_names[count].name));
5017                 count++;
5018         }
5019
5020         return count;
5021 }
5022
5023 static int
5024 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5025                      enum rte_filter_type filter_type,
5026                      enum rte_filter_op filter_op,
5027                      void *arg)
5028 {
5029         int ret = 0;
5030
5031         if (!dev)
5032                 return -EINVAL;
5033
5034         switch (filter_type) {
5035         case RTE_ETH_FILTER_GENERIC:
5036                 if (filter_op != RTE_ETH_FILTER_GET)
5037                         return -EINVAL;
5038                 *(const void **)arg = &ice_flow_ops;
5039                 break;
5040         default:
5041                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5042                                         filter_type);
5043                 ret = -EINVAL;
5044                 break;
5045         }
5046
5047         return ret;
5048 }
5049
5050 /* Add UDP tunneling port */
5051 static int
5052 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5053                              struct rte_eth_udp_tunnel *udp_tunnel)
5054 {
5055         int ret = 0;
5056         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057
5058         if (udp_tunnel == NULL)
5059                 return -EINVAL;
5060
5061         switch (udp_tunnel->prot_type) {
5062         case RTE_TUNNEL_TYPE_VXLAN:
5063                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5064                 break;
5065         default:
5066                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5067                 ret = -EINVAL;
5068                 break;
5069         }
5070
5071         return ret;
5072 }
5073
5074 /* Delete UDP tunneling port */
5075 static int
5076 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5077                              struct rte_eth_udp_tunnel *udp_tunnel)
5078 {
5079         int ret = 0;
5080         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081
5082         if (udp_tunnel == NULL)
5083                 return -EINVAL;
5084
5085         switch (udp_tunnel->prot_type) {
5086         case RTE_TUNNEL_TYPE_VXLAN:
5087                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5088                 break;
5089         default:
5090                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5091                 ret = -EINVAL;
5092                 break;
5093         }
5094
5095         return ret;
5096 }
5097
5098 static int
5099 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5100               struct rte_pci_device *pci_dev)
5101 {
5102         return rte_eth_dev_pci_generic_probe(pci_dev,
5103                                              sizeof(struct ice_adapter),
5104                                              ice_dev_init);
5105 }
5106
5107 static int
5108 ice_pci_remove(struct rte_pci_device *pci_dev)
5109 {
5110         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5111 }
5112
5113 static struct rte_pci_driver rte_ice_pmd = {
5114         .id_table = pci_id_ice_map,
5115         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5116         .probe = ice_pci_probe,
5117         .remove = ice_pci_remove,
5118 };
5119
5120 /**
5121  * Driver initialization routine.
5122  * Invoked once at EAL init time.
5123  * Register itself as the [Poll Mode] Driver of PCI devices.
5124  */
5125 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5126 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5127 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5128 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5129                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5130                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5131                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5132
5133 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5134 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5135 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5136 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5137 #endif
5138 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5139 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5140 #endif
5141 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5142 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5143 #endif