drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_FLOW_MARK_SUPPORT_ARG       "flow-mark-support"
  27 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  28
  29 static const char * const ice_valid_args[] = {
  30         ICE_SAFE_MODE_SUPPORT_ARG,
  31         ICE_PIPELINE_MODE_SUPPORT_ARG,
  32         ICE_FLOW_MARK_SUPPORT_ARG,
  33         ICE_PROTO_XTR_ARG,
  34         NULL
  35 };
  36
  37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  38         .name = "ice_dynfield_proto_xtr_metadata",
  39         .size = sizeof(uint32_t),
  40         .align = __alignof__(uint32_t),
  41         .flags = 0,
  42 };
  43
  44 struct proto_xtr_ol_flag {
  45         const struct rte_mbuf_dynflag param;
  46         uint64_t *ol_flag;
  47         bool required;
  48 };
  49
  50 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  51
  52 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  53         [PROTO_XTR_VLAN] = {
  54                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  55                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  56         [PROTO_XTR_IPV4] = {
  57                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  58                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  59         [PROTO_XTR_IPV6] = {
  60                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  61                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  62         [PROTO_XTR_IPV6_FLOW] = {
  63                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  64                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  65         [PROTO_XTR_TCP] = {
  66                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  67                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  68         [PROTO_XTR_IP_OFFSET] = {
  69                 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" },
  70                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  71 };
  72
  73 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  74
  75 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  76 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  77 #define ICE_MAX_RES_DESC_NUM        1024
  78
  79 static int ice_dev_configure(struct rte_eth_dev *dev);
  80 static int ice_dev_start(struct rte_eth_dev *dev);
  81 static void ice_dev_stop(struct rte_eth_dev *dev);
  82 static void ice_dev_close(struct rte_eth_dev *dev);
  83 static int ice_dev_reset(struct rte_eth_dev *dev);
  84 static int ice_dev_info_get(struct rte_eth_dev *dev,
  85                             struct rte_eth_dev_info *dev_info);
  86 static int ice_link_update(struct rte_eth_dev *dev,
  87                            int wait_to_complete);
  88 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  89 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  90
  91 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  92 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  93 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  94                                struct rte_eth_rss_reta_entry64 *reta_conf,
  95                                uint16_t reta_size);
  96 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  97                               struct rte_eth_rss_reta_entry64 *reta_conf,
  98                               uint16_t reta_size);
  99 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 100                                struct rte_eth_rss_conf *rss_conf);
 101 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 102                                  struct rte_eth_rss_conf *rss_conf);
 103 static int ice_promisc_enable(struct rte_eth_dev *dev);
 104 static int ice_promisc_disable(struct rte_eth_dev *dev);
 105 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 106 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 107 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 108                                uint16_t vlan_id,
 109                                int on);
 110 static int ice_macaddr_set(struct rte_eth_dev *dev,
 111                            struct rte_ether_addr *mac_addr);
 112 static int ice_macaddr_add(struct rte_eth_dev *dev,
 113                            struct rte_ether_addr *mac_addr,
 114                            __rte_unused uint32_t index,
 115                            uint32_t pool);
 116 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 117 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 118                                     uint16_t queue_id);
 119 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 120                                      uint16_t queue_id);
 121 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 122                               size_t fw_size);
 123 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 124                              uint16_t pvid, int on);
 125 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 126 static int ice_get_eeprom(struct rte_eth_dev *dev,
 127                           struct rte_dev_eeprom_info *eeprom);
 128 static int ice_stats_get(struct rte_eth_dev *dev,
 129                          struct rte_eth_stats *stats);
 130 static int ice_stats_reset(struct rte_eth_dev *dev);
 131 static int ice_xstats_get(struct rte_eth_dev *dev,
 132                           struct rte_eth_xstat *xstats, unsigned int n);
 133 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 134                                 struct rte_eth_xstat_name *xstats_names,
 135                                 unsigned int limit);
 136 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 137                         enum rte_filter_type filter_type,
 138                         enum rte_filter_op filter_op,
 139                         void *arg);
 140 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 143                         struct rte_eth_udp_tunnel *udp_tunnel);
 144
 145 static const struct rte_pci_id pci_id_ice_map[] = {
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 162         { .vendor_id = 0, /* sentinel */ },
 163 };
 164
 165 static const struct eth_dev_ops ice_eth_dev_ops = {
 166         .dev_configure                = ice_dev_configure,
 167         .dev_start                    = ice_dev_start,
 168         .dev_stop                     = ice_dev_stop,
 169         .dev_close                    = ice_dev_close,
 170         .dev_reset                    = ice_dev_reset,
 171         .dev_set_link_up              = ice_dev_set_link_up,
 172         .dev_set_link_down            = ice_dev_set_link_down,
 173         .rx_queue_start               = ice_rx_queue_start,
 174         .rx_queue_stop                = ice_rx_queue_stop,
 175         .tx_queue_start               = ice_tx_queue_start,
 176         .tx_queue_stop                = ice_tx_queue_stop,
 177         .rx_queue_setup               = ice_rx_queue_setup,
 178         .rx_queue_release             = ice_rx_queue_release,
 179         .tx_queue_setup               = ice_tx_queue_setup,
 180         .tx_queue_release             = ice_tx_queue_release,
 181         .dev_infos_get                = ice_dev_info_get,
 182         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 183         .link_update                  = ice_link_update,
 184         .mtu_set                      = ice_mtu_set,
 185         .mac_addr_set                 = ice_macaddr_set,
 186         .mac_addr_add                 = ice_macaddr_add,
 187         .mac_addr_remove              = ice_macaddr_remove,
 188         .vlan_filter_set              = ice_vlan_filter_set,
 189         .vlan_offload_set             = ice_vlan_offload_set,
 190         .reta_update                  = ice_rss_reta_update,
 191         .reta_query                   = ice_rss_reta_query,
 192         .rss_hash_update              = ice_rss_hash_update,
 193         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 194         .promiscuous_enable           = ice_promisc_enable,
 195         .promiscuous_disable          = ice_promisc_disable,
 196         .allmulticast_enable          = ice_allmulti_enable,
 197         .allmulticast_disable         = ice_allmulti_disable,
 198         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 199         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 200         .fw_version_get               = ice_fw_version_get,
 201         .vlan_pvid_set                = ice_vlan_pvid_set,
 202         .rxq_info_get                 = ice_rxq_info_get,
 203         .txq_info_get                 = ice_txq_info_get,
 204         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 205         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 206         .get_eeprom_length            = ice_get_eeprom_length,
 207         .get_eeprom                   = ice_get_eeprom,
 208         .stats_get                    = ice_stats_get,
 209         .stats_reset                  = ice_stats_reset,
 210         .xstats_get                   = ice_xstats_get,
 211         .xstats_get_names             = ice_xstats_get_names,
 212         .xstats_reset                 = ice_stats_reset,
 213         .filter_ctrl                  = ice_dev_filter_ctrl,
 214         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 215         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 216         .tx_done_cleanup              = ice_tx_done_cleanup,
 217 };
 218
 219 /* store statistics names and its offset in stats structure */
 220 struct ice_xstats_name_off {
 221         char name[RTE_ETH_XSTATS_NAME_SIZE];
 222         unsigned int offset;
 223 };
 224
 225 static const struct ice_xstats_name_off ice_stats_strings[] = {
 226         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 227         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 228         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 229         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 230         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 231                 rx_unknown_protocol)},
 232         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 233         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 234         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 235         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 236 };
 237
 238 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 239                 sizeof(ice_stats_strings[0]))
 240
 241 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 242         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 243                 tx_dropped_link_down)},
 244         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 245         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 246                 illegal_bytes)},
 247         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 248         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 249                 mac_local_faults)},
 250         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 251                 mac_remote_faults)},
 252         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 253                 rx_len_errors)},
 254         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 255         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 256         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 257         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 258         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 259         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 260                 rx_size_127)},
 261         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 262                 rx_size_255)},
 263         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_511)},
 265         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_1023)},
 267         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_1522)},
 269         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_big)},
 271         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 272                 rx_undersize)},
 273         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 274                 rx_oversize)},
 275         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 276                 mac_short_pkt_dropped)},
 277         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_fragments)},
 279         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 280         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 281         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 282                 tx_size_127)},
 283         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 284                 tx_size_255)},
 285         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_511)},
 287         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_1023)},
 289         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_1522)},
 291         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_big)},
 293 };
 294
 295 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 296                 sizeof(ice_hw_port_strings[0]))
 297
 298 static void
 299 ice_init_controlq_parameter(struct ice_hw *hw)
 300 {
 301         /* fields for adminq */
 302         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 303         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 304         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 305         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 306
 307         /* fields for mailboxq, DPDK used as PF host */
 308         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 309         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 310         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 311         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 312 }
 313
 314 static int
 315 lookup_proto_xtr_type(const char *xtr_name)
 316 {
 317         static struct {
 318                 const char *name;
 319                 enum proto_xtr_type type;
 320         } xtr_type_map[] = {
 321                 { "vlan",      PROTO_XTR_VLAN      },
 322                 { "ipv4",      PROTO_XTR_IPV4      },
 323                 { "ipv6",      PROTO_XTR_IPV6      },
 324                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 325                 { "tcp",       PROTO_XTR_TCP       },
 326                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 327         };
 328         uint32_t i;
 329
 330         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 331                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 332                         return xtr_type_map[i].type;
 333         }
 334
 335         return -1;
 336 }
 337
 338 /*
 339  * Parse elem, the elem could be single number/range or '(' ')' group
 340  * 1) A single number elem, it's just a simple digit. e.g. 9
 341  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 342  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 343  *    Within group elem, '-' used for a range separator;
 344  *                       ',' used for a single number.
 345  */
 346 static int
 347 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 348 {
 349         const char *str = input;
 350         char *end = NULL;
 351         uint32_t min, max;
 352         uint32_t idx;
 353
 354         while (isblank(*str))
 355                 str++;
 356
 357         if (!isdigit(*str) && *str != '(')
 358                 return -1;
 359
 360         /* process single number or single range of number */
 361         if (*str != '(') {
 362                 errno = 0;
 363                 idx = strtoul(str, &end, 10);
 364                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 365                         return -1;
 366
 367                 while (isblank(*end))
 368                         end++;
 369
 370                 min = idx;
 371                 max = idx;
 372
 373                 /* process single <number>-<number> */
 374                 if (*end == '-') {
 375                         end++;
 376                         while (isblank(*end))
 377                                 end++;
 378                         if (!isdigit(*end))
 379                                 return -1;
 380
 381                         errno = 0;
 382                         idx = strtoul(end, &end, 10);
 383                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 384                                 return -1;
 385
 386                         max = idx;
 387                         while (isblank(*end))
 388                                 end++;
 389                 }
 390
 391                 if (*end != ':')
 392                         return -1;
 393
 394                 for (idx = RTE_MIN(min, max);
 395                      idx <= RTE_MAX(min, max); idx++)
 396                         devargs->proto_xtr[idx] = xtr_type;
 397
 398                 return 0;
 399         }
 400
 401         /* process set within bracket */
 402         str++;
 403         while (isblank(*str))
 404                 str++;
 405         if (*str == '\0')
 406                 return -1;
 407
 408         min = ICE_MAX_QUEUE_NUM;
 409         do {
 410                 /* go ahead to the first digit */
 411                 while (isblank(*str))
 412                         str++;
 413                 if (!isdigit(*str))
 414                         return -1;
 415
 416                 /* get the digit value */
 417                 errno = 0;
 418                 idx = strtoul(str, &end, 10);
 419                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 420                         return -1;
 421
 422                 /* go ahead to separator '-',',' and ')' */
 423                 while (isblank(*end))
 424                         end++;
 425                 if (*end == '-') {
 426                         if (min == ICE_MAX_QUEUE_NUM)
 427                                 min = idx;
 428                         else /* avoid continuous '-' */
 429                                 return -1;
 430                 } else if (*end == ',' || *end == ')') {
 431                         max = idx;
 432                         if (min == ICE_MAX_QUEUE_NUM)
 433                                 min = idx;
 434
 435                         for (idx = RTE_MIN(min, max);
 436                              idx <= RTE_MAX(min, max); idx++)
 437                                 devargs->proto_xtr[idx] = xtr_type;
 438
 439                         min = ICE_MAX_QUEUE_NUM;
 440                 } else {
 441                         return -1;
 442                 }
 443
 444                 str = end + 1;
 445         } while (*end != ')' && *end != '\0');
 446
 447         return 0;
 448 }
 449
 450 static int
 451 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 452 {
 453         const char *queue_start;
 454         uint32_t idx;
 455         int xtr_type;
 456         char xtr_name[32];
 457
 458         while (isblank(*queues))
 459                 queues++;
 460
 461         if (*queues != '[') {
 462                 xtr_type = lookup_proto_xtr_type(queues);
 463                 if (xtr_type < 0)
 464                         return -1;
 465
 466                 devargs->proto_xtr_dflt = xtr_type;
 467
 468                 return 0;
 469         }
 470
 471         queues++;
 472         do {
 473                 while (isblank(*queues))
 474                         queues++;
 475                 if (*queues == '\0')
 476                         return -1;
 477
 478                 queue_start = queues;
 479
 480                 /* go across a complete bracket */
 481                 if (*queue_start == '(') {
 482                         queues += strcspn(queues, ")");
 483                         if (*queues != ')')
 484                                 return -1;
 485                 }
 486
 487                 /* scan the separator ':' */
 488                 queues += strcspn(queues, ":");
 489                 if (*queues++ != ':')
 490                         return -1;
 491                 while (isblank(*queues))
 492                         queues++;
 493
 494                 for (idx = 0; ; idx++) {
 495                         if (isblank(queues[idx]) ||
 496                             queues[idx] == ',' ||
 497                             queues[idx] == ']' ||
 498                             queues[idx] == '\0')
 499                                 break;
 500
 501                         if (idx > sizeof(xtr_name) - 2)
 502                                 return -1;
 503
 504                         xtr_name[idx] = queues[idx];
 505                 }
 506                 xtr_name[idx] = '\0';
 507                 xtr_type = lookup_proto_xtr_type(xtr_name);
 508                 if (xtr_type < 0)
 509                         return -1;
 510
 511                 queues += idx;
 512
 513                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 514                         queues++;
 515
 516                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 517                         return -1;
 518         } while (*queues != '\0');
 519
 520         return 0;
 521 }
 522
 523 static int
 524 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 525                      void *extra_args)
 526 {
 527         struct ice_devargs *devargs = extra_args;
 528
 529         if (value == NULL || extra_args == NULL)
 530                 return -EINVAL;
 531
 532         if (parse_queue_proto_xtr(value, devargs) < 0) {
 533                 PMD_DRV_LOG(ERR,
 534                             "The protocol extraction parameter is wrong : '%s'",
 535                             value);
 536                 return -1;
 537         }
 538
 539         return 0;
 540 }
 541
 542 static void
 543 ice_check_proto_xtr_support(struct ice_hw *hw)
 544 {
 545 #define FLX_REG(val, fld, idx) \
 546         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 547          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 548         static struct {
 549                 uint32_t rxdid;
 550                 uint8_t opcode;
 551                 uint8_t protid_0;
 552                 uint8_t protid_1;
 553         } xtr_sets[] = {
 554                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 555                                      ICE_RX_OPC_EXTRACT,
 556                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 557                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 558                                      ICE_RX_OPC_EXTRACT,
 559                                      ICE_PROT_IPV4_OF_OR_S,
 560                                      ICE_PROT_IPV4_OF_OR_S },
 561                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 562                                      ICE_RX_OPC_EXTRACT,
 563                                      ICE_PROT_IPV6_OF_OR_S,
 564                                      ICE_PROT_IPV6_OF_OR_S },
 565                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 566                                           ICE_RX_OPC_EXTRACT,
 567                                           ICE_PROT_IPV6_OF_OR_S,
 568                                           ICE_PROT_IPV6_OF_OR_S },
 569                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 570                                     ICE_RX_OPC_EXTRACT,
 571                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 572                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 573                                           ICE_RX_OPC_PROTID,
 574                                           ICE_PROT_IPV4_OF_OR_S,
 575                                           ICE_PROT_IPV6_OF_OR_S },
 576         };
 577         uint32_t i;
 578
 579         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 580                 uint32_t rxdid = xtr_sets[i].rxdid;
 581                 uint32_t v;
 582
 583                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 584                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 585
 586                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 587                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 588                                 ice_proto_xtr_hw_support[i] = true;
 589                 }
 590
 591                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 592                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 593
 594                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 595                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 596                                 ice_proto_xtr_hw_support[i] = true;
 597                 }
 598         }
 599 }
 600
 601 static int
 602 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 603                   uint32_t num)
 604 {
 605         struct pool_entry *entry;
 606
 607         if (!pool || !num)
 608                 return -EINVAL;
 609
 610         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 611         if (!entry) {
 612                 PMD_INIT_LOG(ERR,
 613                              "Failed to allocate memory for resource pool");
 614                 return -ENOMEM;
 615         }
 616
 617         /* queue heap initialize */
 618         pool->num_free = num;
 619         pool->num_alloc = 0;
 620         pool->base = base;
 621         LIST_INIT(&pool->alloc_list);
 622         LIST_INIT(&pool->free_list);
 623
 624         /* Initialize element  */
 625         entry->base = 0;
 626         entry->len = num;
 627
 628         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 629         return 0;
 630 }
 631
 632 static int
 633 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 634                    uint16_t num)
 635 {
 636         struct pool_entry *entry, *valid_entry;
 637
 638         if (!pool || !num) {
 639                 PMD_INIT_LOG(ERR, "Invalid parameter");
 640                 return -EINVAL;
 641         }
 642
 643         if (pool->num_free < num) {
 644                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 645                              num, pool->num_free);
 646                 return -ENOMEM;
 647         }
 648
 649         valid_entry = NULL;
 650         /* Lookup  in free list and find most fit one */
 651         LIST_FOREACH(entry, &pool->free_list, next) {
 652                 if (entry->len >= num) {
 653                         /* Find best one */
 654                         if (entry->len == num) {
 655                                 valid_entry = entry;
 656                                 break;
 657                         }
 658                         if (!valid_entry ||
 659                             valid_entry->len > entry->len)
 660                                 valid_entry = entry;
 661                 }
 662         }
 663
 664         /* Not find one to satisfy the request, return */
 665         if (!valid_entry) {
 666                 PMD_INIT_LOG(ERR, "No valid entry found");
 667                 return -ENOMEM;
 668         }
 669         /**
 670          * The entry have equal queue number as requested,
 671          * remove it from alloc_list.
 672          */
 673         if (valid_entry->len == num) {
 674                 LIST_REMOVE(valid_entry, next);
 675         } else {
 676                 /**
 677                  * The entry have more numbers than requested,
 678                  * create a new entry for alloc_list and minus its
 679                  * queue base and number in free_list.
 680                  */
 681                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 682                 if (!entry) {
 683                         PMD_INIT_LOG(ERR,
 684                                      "Failed to allocate memory for "
 685                                      "resource pool");
 686                         return -ENOMEM;
 687                 }
 688                 entry->base = valid_entry->base;
 689                 entry->len = num;
 690                 valid_entry->base += num;
 691                 valid_entry->len -= num;
 692                 valid_entry = entry;
 693         }
 694
 695         /* Insert it into alloc list, not sorted */
 696         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 697
 698         pool->num_free -= valid_entry->len;
 699         pool->num_alloc += valid_entry->len;
 700
 701         return valid_entry->base + pool->base;
 702 }
 703
 704 static void
 705 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 706 {
 707         struct pool_entry *entry, *next_entry;
 708
 709         if (!pool)
 710                 return;
 711
 712         for (entry = LIST_FIRST(&pool->alloc_list);
 713              entry && (next_entry = LIST_NEXT(entry, next), 1);
 714              entry = next_entry) {
 715                 LIST_REMOVE(entry, next);
 716                 rte_free(entry);
 717         }
 718
 719         for (entry = LIST_FIRST(&pool->free_list);
 720              entry && (next_entry = LIST_NEXT(entry, next), 1);
 721              entry = next_entry) {
 722                 LIST_REMOVE(entry, next);
 723                 rte_free(entry);
 724         }
 725
 726         pool->num_free = 0;
 727         pool->num_alloc = 0;
 728         pool->base = 0;
 729         LIST_INIT(&pool->alloc_list);
 730         LIST_INIT(&pool->free_list);
 731 }
 732
 733 static void
 734 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 735 {
 736         /* Set VSI LUT selection */
 737         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 738                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 739         /* Set Hash scheme */
 740         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 741                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 742         /* enable TC */
 743         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 744 }
 745
 746 static enum ice_status
 747 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 748                                 struct ice_aqc_vsi_props *info,
 749                                 uint8_t enabled_tcmap)
 750 {
 751         uint16_t bsf, qp_idx;
 752
 753         /* default tc 0 now. Multi-TC supporting need to be done later.
 754          * Configure TC and queue mapping parameters, for enabled TC,
 755          * allocate qpnum_per_tc queues to this traffic.
 756          */
 757         if (enabled_tcmap != 0x01) {
 758                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 759                 return -ENOTSUP;
 760         }
 761
 762         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 763         bsf = rte_bsf32(vsi->nb_qps);
 764         /* Adjust the queue number to actual queues that can be applied */
 765         vsi->nb_qps = 0x1 << bsf;
 766
 767         qp_idx = 0;
 768         /* Set tc and queue mapping with VSI */
 769         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 770                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 771                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 772
 773         /* Associate queue number with VSI */
 774         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 775         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 776         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 777         info->valid_sections |=
 778                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 779         /* Set the info.ingress_table and info.egress_table
 780          * for UP translate table. Now just set it to 1:1 map by default
 781          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 782          */
 783 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 784         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 785         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 786         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 787         return 0;
 788 }
 789
 790 static int
 791 ice_init_mac_address(struct rte_eth_dev *dev)
 792 {
 793         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 794
 795         if (!rte_is_unicast_ether_addr
 796                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 797                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 798                 return -EINVAL;
 799         }
 800
 801         rte_ether_addr_copy(
 802                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 803                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 804
 805         dev->data->mac_addrs =
 806                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 807         if (!dev->data->mac_addrs) {
 808                 PMD_INIT_LOG(ERR,
 809                              "Failed to allocate memory to store mac address");
 810                 return -ENOMEM;
 811         }
 812         /* store it to dev data */
 813         rte_ether_addr_copy(
 814                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 815                 &dev->data->mac_addrs[0]);
 816         return 0;
 817 }
 818
 819 /* Find out specific MAC filter */
 820 static struct ice_mac_filter *
 821 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 822 {
 823         struct ice_mac_filter *f;
 824
 825         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 826                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 827                         return f;
 828         }
 829
 830         return NULL;
 831 }
 832
 833 static int
 834 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 835 {
 836         struct ice_fltr_list_entry *m_list_itr = NULL;
 837         struct ice_mac_filter *f;
 838         struct LIST_HEAD_TYPE list_head;
 839         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 840         int ret = 0;
 841
 842         /* If it's added and configured, return */
 843         f = ice_find_mac_filter(vsi, mac_addr);
 844         if (f) {
 845                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 846                 return 0;
 847         }
 848
 849         INIT_LIST_HEAD(&list_head);
 850
 851         m_list_itr = (struct ice_fltr_list_entry *)
 852                 ice_malloc(hw, sizeof(*m_list_itr));
 853         if (!m_list_itr) {
 854                 ret = -ENOMEM;
 855                 goto DONE;
 856         }
 857         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 858                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 859         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 860         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 861         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 862         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 863         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 864
 865         LIST_ADD(&m_list_itr->list_entry, &list_head);
 866
 867         /* Add the mac */
 868         ret = ice_add_mac(hw, &list_head);
 869         if (ret != ICE_SUCCESS) {
 870                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 871                 ret = -EINVAL;
 872                 goto DONE;
 873         }
 874         /* Add the mac addr into mac list */
 875         f = rte_zmalloc(NULL, sizeof(*f), 0);
 876         if (!f) {
 877                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 878                 ret = -ENOMEM;
 879                 goto DONE;
 880         }
 881         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 882         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 883         vsi->mac_num++;
 884
 885         ret = 0;
 886
 887 DONE:
 888         rte_free(m_list_itr);
 889         return ret;
 890 }
 891
 892 static int
 893 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 894 {
 895         struct ice_fltr_list_entry *m_list_itr = NULL;
 896         struct ice_mac_filter *f;
 897         struct LIST_HEAD_TYPE list_head;
 898         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 899         int ret = 0;
 900
 901         /* Can't find it, return an error */
 902         f = ice_find_mac_filter(vsi, mac_addr);
 903         if (!f)
 904                 return -EINVAL;
 905
 906         INIT_LIST_HEAD(&list_head);
 907
 908         m_list_itr = (struct ice_fltr_list_entry *)
 909                 ice_malloc(hw, sizeof(*m_list_itr));
 910         if (!m_list_itr) {
 911                 ret = -ENOMEM;
 912                 goto DONE;
 913         }
 914         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 915                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 916         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 917         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 918         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 919         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 920         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 921
 922         LIST_ADD(&m_list_itr->list_entry, &list_head);
 923
 924         /* remove the mac filter */
 925         ret = ice_remove_mac(hw, &list_head);
 926         if (ret != ICE_SUCCESS) {
 927                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 928                 ret = -EINVAL;
 929                 goto DONE;
 930         }
 931
 932         /* Remove the mac addr from mac list */
 933         TAILQ_REMOVE(&vsi->mac_list, f, next);
 934         rte_free(f);
 935         vsi->mac_num--;
 936
 937         ret = 0;
 938 DONE:
 939         rte_free(m_list_itr);
 940         return ret;
 941 }
 942
 943 /* Find out specific VLAN filter */
 944 static struct ice_vlan_filter *
 945 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 946 {
 947         struct ice_vlan_filter *f;
 948
 949         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 950                 if (vlan_id == f->vlan_info.vlan_id)
 951                         return f;
 952         }
 953
 954         return NULL;
 955 }
 956
 957 static int
 958 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 959 {
 960         struct ice_fltr_list_entry *v_list_itr = NULL;
 961         struct ice_vlan_filter *f;
 962         struct LIST_HEAD_TYPE list_head;
 963         struct ice_hw *hw;
 964         int ret = 0;
 965
 966         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 967                 return -EINVAL;
 968
 969         hw = ICE_VSI_TO_HW(vsi);
 970
 971         /* If it's added and configured, return. */
 972         f = ice_find_vlan_filter(vsi, vlan_id);
 973         if (f) {
 974                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 975                 return 0;
 976         }
 977
 978         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 979                 return 0;
 980
 981         INIT_LIST_HEAD(&list_head);
 982
 983         v_list_itr = (struct ice_fltr_list_entry *)
 984                       ice_malloc(hw, sizeof(*v_list_itr));
 985         if (!v_list_itr) {
 986                 ret = -ENOMEM;
 987                 goto DONE;
 988         }
 989         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 990         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 991         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 992         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 993         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 994         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 995
 996         LIST_ADD(&v_list_itr->list_entry, &list_head);
 997
 998         /* Add the vlan */
 999         ret = ice_add_vlan(hw, &list_head);
1000         if (ret != ICE_SUCCESS) {
1001                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1002                 ret = -EINVAL;
1003                 goto DONE;
1004         }
1005
1006         /* Add vlan into vlan list */
1007         f = rte_zmalloc(NULL, sizeof(*f), 0);
1008         if (!f) {
1009                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1010                 ret = -ENOMEM;
1011                 goto DONE;
1012         }
1013         f->vlan_info.vlan_id = vlan_id;
1014         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1015         vsi->vlan_num++;
1016
1017         ret = 0;
1018
1019 DONE:
1020         rte_free(v_list_itr);
1021         return ret;
1022 }
1023
1024 static int
1025 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1026 {
1027         struct ice_fltr_list_entry *v_list_itr = NULL;
1028         struct ice_vlan_filter *f;
1029         struct LIST_HEAD_TYPE list_head;
1030         struct ice_hw *hw;
1031         int ret = 0;
1032
1033         /**
1034          * Vlan 0 is the generic filter for untagged packets
1035          * and can't be removed.
1036          */
1037         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1038                 return -EINVAL;
1039
1040         hw = ICE_VSI_TO_HW(vsi);
1041
1042         /* Can't find it, return an error */
1043         f = ice_find_vlan_filter(vsi, vlan_id);
1044         if (!f)
1045                 return -EINVAL;
1046
1047         INIT_LIST_HEAD(&list_head);
1048
1049         v_list_itr = (struct ice_fltr_list_entry *)
1050                       ice_malloc(hw, sizeof(*v_list_itr));
1051         if (!v_list_itr) {
1052                 ret = -ENOMEM;
1053                 goto DONE;
1054         }
1055
1056         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1057         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1058         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1059         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1060         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1061         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1062
1063         LIST_ADD(&v_list_itr->list_entry, &list_head);
1064
1065         /* remove the vlan filter */
1066         ret = ice_remove_vlan(hw, &list_head);
1067         if (ret != ICE_SUCCESS) {
1068                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1069                 ret = -EINVAL;
1070                 goto DONE;
1071         }
1072
1073         /* Remove the vlan id from vlan list */
1074         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1075         rte_free(f);
1076         vsi->vlan_num--;
1077
1078         ret = 0;
1079 DONE:
1080         rte_free(v_list_itr);
1081         return ret;
1082 }
1083
1084 static int
1085 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1086 {
1087         struct ice_mac_filter *m_f;
1088         struct ice_vlan_filter *v_f;
1089         int ret = 0;
1090
1091         if (!vsi || !vsi->mac_num)
1092                 return -EINVAL;
1093
1094         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1095                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1096                 if (ret != ICE_SUCCESS) {
1097                         ret = -EINVAL;
1098                         goto DONE;
1099                 }
1100         }
1101
1102         if (vsi->vlan_num == 0)
1103                 return 0;
1104
1105         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1106                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1107                 if (ret != ICE_SUCCESS) {
1108                         ret = -EINVAL;
1109                         goto DONE;
1110                 }
1111         }
1112
1113 DONE:
1114         return ret;
1115 }
1116
1117 static int
1118 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1119 {
1120         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1121         struct ice_vsi_ctx ctxt;
1122         uint8_t qinq_flags;
1123         int ret = 0;
1124
1125         /* Check if it has been already on or off */
1126         if (vsi->info.valid_sections &
1127                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1128                 if (on) {
1129                         if ((vsi->info.outer_tag_flags &
1130                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1131                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1132                                 return 0; /* already on */
1133                 } else {
1134                         if (!(vsi->info.outer_tag_flags &
1135                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1136                                 return 0; /* already off */
1137                 }
1138         }
1139
1140         if (on)
1141                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1142         else
1143                 qinq_flags = 0;
1144         /* clear global insertion and use per packet insertion */
1145         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1146         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1147         vsi->info.outer_tag_flags |= qinq_flags;
1148         /* use default vlan type 0x8100 */
1149         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1150         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1151                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1152         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1153         ctxt.info.valid_sections =
1154                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1155         ctxt.vsi_num = vsi->vsi_id;
1156         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1157         if (ret) {
1158                 PMD_DRV_LOG(INFO,
1159                             "Update VSI failed to %s qinq stripping",
1160                             on ? "enable" : "disable");
1161                 return -EINVAL;
1162         }
1163
1164         vsi->info.valid_sections |=
1165                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1166
1167         return ret;
1168 }
1169
1170 static int
1171 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1172 {
1173         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1174         struct ice_vsi_ctx ctxt;
1175         uint8_t qinq_flags;
1176         int ret = 0;
1177
1178         /* Check if it has been already on or off */
1179         if (vsi->info.valid_sections &
1180                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1181                 if (on) {
1182                         if ((vsi->info.outer_tag_flags &
1183                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1184                             ICE_AQ_VSI_OUTER_TAG_COPY)
1185                                 return 0; /* already on */
1186                 } else {
1187                         if ((vsi->info.outer_tag_flags &
1188                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1189                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1190                                 return 0; /* already off */
1191                 }
1192         }
1193
1194         if (on)
1195                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1196         else
1197                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1198         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1199         vsi->info.outer_tag_flags |= qinq_flags;
1200         /* use default vlan type 0x8100 */
1201         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1202         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1203                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1204         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1205         ctxt.info.valid_sections =
1206                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1207         ctxt.vsi_num = vsi->vsi_id;
1208         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1209         if (ret) {
1210                 PMD_DRV_LOG(INFO,
1211                             "Update VSI failed to %s qinq stripping",
1212                             on ? "enable" : "disable");
1213                 return -EINVAL;
1214         }
1215
1216         vsi->info.valid_sections |=
1217                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1218
1219         return ret;
1220 }
1221
1222 static int
1223 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1224 {
1225         int ret;
1226
1227         ret = ice_vsi_config_qinq_stripping(vsi, on);
1228         if (ret)
1229                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1230
1231         ret = ice_vsi_config_qinq_insertion(vsi, on);
1232         if (ret)
1233                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1234
1235         return ret;
1236 }
1237
1238 /* Enable IRQ0 */
1239 static void
1240 ice_pf_enable_irq0(struct ice_hw *hw)
1241 {
1242         /* reset the registers */
1243         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1244         ICE_READ_REG(hw, PFINT_OICR);
1245
1246 #ifdef ICE_LSE_SPT
1247         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1248                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1249                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1250
1251         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1252                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1253                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1254                        PFINT_OICR_CTL_ITR_INDX_M) |
1255                       PFINT_OICR_CTL_CAUSE_ENA_M);
1256
1257         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1258                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1259                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1260                        PFINT_FW_CTL_ITR_INDX_M) |
1261                       PFINT_FW_CTL_CAUSE_ENA_M);
1262 #else
1263         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1264 #endif
1265
1266         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1267                       GLINT_DYN_CTL_INTENA_M |
1268                       GLINT_DYN_CTL_CLEARPBA_M |
1269                       GLINT_DYN_CTL_ITR_INDX_M);
1270
1271         ice_flush(hw);
1272 }
1273
1274 /* Disable IRQ0 */
1275 static void
1276 ice_pf_disable_irq0(struct ice_hw *hw)
1277 {
1278         /* Disable all interrupt types */
1279         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1280         ice_flush(hw);
1281 }
1282
1283 #ifdef ICE_LSE_SPT
1284 static void
1285 ice_handle_aq_msg(struct rte_eth_dev *dev)
1286 {
1287         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288         struct ice_ctl_q_info *cq = &hw->adminq;
1289         struct ice_rq_event_info event;
1290         uint16_t pending, opcode;
1291         int ret;
1292
1293         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1294         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1295         if (!event.msg_buf) {
1296                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1297                 return;
1298         }
1299
1300         pending = 1;
1301         while (pending) {
1302                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1303
1304                 if (ret != ICE_SUCCESS) {
1305                         PMD_DRV_LOG(INFO,
1306                                     "Failed to read msg from AdminQ, "
1307                                     "adminq_err: %u",
1308                                     hw->adminq.sq_last_status);
1309                         break;
1310                 }
1311                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1312
1313                 switch (opcode) {
1314                 case ice_aqc_opc_get_link_status:
1315                         ret = ice_link_update(dev, 0);
1316                         if (!ret)
1317                                 rte_eth_dev_callback_process
1318                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1319                         break;
1320                 default:
1321                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1322                                     opcode);
1323                         break;
1324                 }
1325         }
1326         rte_free(event.msg_buf);
1327 }
1328 #endif
1329
1330 /**
1331  * Interrupt handler triggered by NIC for handling
1332  * specific interrupt.
1333  *
1334  * @param handle
1335  *  Pointer to interrupt handle.
1336  * @param param
1337  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1338  *
1339  * @return
1340  *  void
1341  */
1342 static void
1343 ice_interrupt_handler(void *param)
1344 {
1345         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1346         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t oicr;
1348         uint32_t reg;
1349         uint8_t pf_num;
1350         uint8_t event;
1351         uint16_t queue;
1352         int ret;
1353 #ifdef ICE_LSE_SPT
1354         uint32_t int_fw_ctl;
1355 #endif
1356
1357         /* Disable interrupt */
1358         ice_pf_disable_irq0(hw);
1359
1360         /* read out interrupt causes */
1361         oicr = ICE_READ_REG(hw, PFINT_OICR);
1362 #ifdef ICE_LSE_SPT
1363         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1364 #endif
1365
1366         /* No interrupt event indicated */
1367         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1368                 PMD_DRV_LOG(INFO, "No interrupt event");
1369                 goto done;
1370         }
1371
1372 #ifdef ICE_LSE_SPT
1373         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1374                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1375                 ice_handle_aq_msg(dev);
1376         }
1377 #else
1378         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1379                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1380                 ret = ice_link_update(dev, 0);
1381                 if (!ret)
1382                         rte_eth_dev_callback_process
1383                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1384         }
1385 #endif
1386
1387         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1388                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1389                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1390                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1391                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1392                                  GL_MDET_TX_PQM_PF_NUM_S;
1393                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1394                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1395                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1396                                 GL_MDET_TX_PQM_QNUM_S;
1397
1398                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1399                                     "%d by PQM on TX queue %d PF# %d",
1400                                     event, queue, pf_num);
1401                 }
1402
1403                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1404                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1405                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1406                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1407                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1408                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1409                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1410                                 GL_MDET_TX_TCLAN_QNUM_S;
1411
1412                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1413                                     "%d by TCLAN on TX queue %d PF# %d",
1414                                     event, queue, pf_num);
1415                 }
1416         }
1417 done:
1418         /* Enable interrupt */
1419         ice_pf_enable_irq0(hw);
1420         rte_intr_ack(dev->intr_handle);
1421 }
1422
1423 static void
1424 ice_init_proto_xtr(struct rte_eth_dev *dev)
1425 {
1426         struct ice_adapter *ad =
1427                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1428         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1429         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1430         const struct proto_xtr_ol_flag *ol_flag;
1431         bool proto_xtr_enable = false;
1432         int offset;
1433         uint16_t i;
1434
1435         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1436         if (unlikely(pf->proto_xtr == NULL)) {
1437                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1438                 return;
1439         }
1440
1441         for (i = 0; i < pf->lan_nb_qps; i++) {
1442                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1443                                    ad->devargs.proto_xtr[i] :
1444                                    ad->devargs.proto_xtr_dflt;
1445
1446                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1447                         uint8_t type = pf->proto_xtr[i];
1448
1449                         ice_proto_xtr_ol_flag_params[type].required = true;
1450                         proto_xtr_enable = true;
1451                 }
1452         }
1453
1454         if (likely(!proto_xtr_enable))
1455                 return;
1456
1457         ice_check_proto_xtr_support(hw);
1458
1459         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1460         if (unlikely(offset == -1)) {
1461                 PMD_DRV_LOG(ERR,
1462                             "Protocol extraction metadata is disabled in mbuf with error %d",
1463                             -rte_errno);
1464                 return;
1465         }
1466
1467         PMD_DRV_LOG(DEBUG,
1468                     "Protocol extraction metadata offset in mbuf is : %d",
1469                     offset);
1470         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1471
1472         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1473                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1474
1475                 if (!ol_flag->required)
1476                         continue;
1477
1478                 if (!ice_proto_xtr_hw_support[i]) {
1479                         PMD_DRV_LOG(ERR,
1480                                     "Protocol extraction type %u is not supported in hardware",
1481                                     i);
1482                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1483                         break;
1484                 }
1485
1486                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1487                 if (unlikely(offset == -1)) {
1488                         PMD_DRV_LOG(ERR,
1489                                     "Protocol extraction offload '%s' failed to register with error %d",
1490                                     ol_flag->param.name, -rte_errno);
1491
1492                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1493                         break;
1494                 }
1495
1496                 PMD_DRV_LOG(DEBUG,
1497                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1498                             ol_flag->param.name, offset);
1499                 *ol_flag->ol_flag = 1ULL << offset;
1500         }
1501 }
1502
1503 /*  Initialize SW parameters of PF */
1504 static int
1505 ice_pf_sw_init(struct rte_eth_dev *dev)
1506 {
1507         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1508         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1509
1510         pf->lan_nb_qp_max =
1511                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1512                                   hw->func_caps.common_cap.num_rxq);
1513
1514         pf->lan_nb_qps = pf->lan_nb_qp_max;
1515
1516         ice_init_proto_xtr(dev);
1517
1518         if (hw->func_caps.fd_fltr_guar > 0 ||
1519             hw->func_caps.fd_fltr_best_effort > 0) {
1520                 pf->flags |= ICE_FLAG_FDIR;
1521                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1522                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1523         } else {
1524                 pf->fdir_nb_qps = 0;
1525         }
1526         pf->fdir_qp_offset = 0;
1527
1528         return 0;
1529 }
1530
1531 struct ice_vsi *
1532 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1533 {
1534         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1535         struct ice_vsi *vsi = NULL;
1536         struct ice_vsi_ctx vsi_ctx;
1537         int ret;
1538         struct rte_ether_addr broadcast = {
1539                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1540         struct rte_ether_addr mac_addr;
1541         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1542         uint8_t tc_bitmap = 0x1;
1543         uint16_t cfg;
1544
1545         /* hw->num_lports = 1 in NIC mode */
1546         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1547         if (!vsi)
1548                 return NULL;
1549
1550         vsi->idx = pf->next_vsi_idx;
1551         pf->next_vsi_idx++;
1552         vsi->type = type;
1553         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1554         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1555         vsi->vlan_anti_spoof_on = 0;
1556         vsi->vlan_filter_on = 1;
1557         TAILQ_INIT(&vsi->mac_list);
1558         TAILQ_INIT(&vsi->vlan_list);
1559
1560         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1561         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1562                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1563                         hw->func_caps.common_cap.rss_table_size;
1564         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1565
1566         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1567         switch (type) {
1568         case ICE_VSI_PF:
1569                 vsi->nb_qps = pf->lan_nb_qps;
1570                 vsi->base_queue = 1;
1571                 ice_vsi_config_default_rss(&vsi_ctx.info);
1572                 vsi_ctx.alloc_from_pool = true;
1573                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1574                 /* switch_id is queried by get_switch_config aq, which is done
1575                  * by ice_init_hw
1576                  */
1577                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1578                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1579                 /* Allow all untagged or tagged packets */
1580                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1581                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1582                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1583                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1584
1585                 /* FDIR */
1586                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1587                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1588                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1589                 cfg = ICE_AQ_VSI_FD_ENABLE;
1590                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1591                 vsi_ctx.info.max_fd_fltr_dedicated =
1592                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1593                 vsi_ctx.info.max_fd_fltr_shared =
1594                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1595
1596                 /* Enable VLAN/UP trip */
1597                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1598                                                       &vsi_ctx.info,
1599                                                       ICE_DEFAULT_TCMAP);
1600                 if (ret) {
1601                         PMD_INIT_LOG(ERR,
1602                                      "tc queue mapping with vsi failed, "
1603                                      "err = %d",
1604                                      ret);
1605                         goto fail_mem;
1606                 }
1607
1608                 break;
1609         case ICE_VSI_CTRL:
1610                 vsi->nb_qps = pf->fdir_nb_qps;
1611                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1612                 vsi_ctx.alloc_from_pool = true;
1613                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1614
1615                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1616                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1617                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1618                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1619                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1620                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1621                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1622                                                       &vsi_ctx.info,
1623                                                       ICE_DEFAULT_TCMAP);
1624                 if (ret) {
1625                         PMD_INIT_LOG(ERR,
1626                                      "tc queue mapping with vsi failed, "
1627                                      "err = %d",
1628                                      ret);
1629                         goto fail_mem;
1630                 }
1631                 break;
1632         default:
1633                 /* for other types of VSI */
1634                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1635                 goto fail_mem;
1636         }
1637
1638         /* VF has MSIX interrupt in VF range, don't allocate here */
1639         if (type == ICE_VSI_PF) {
1640                 ret = ice_res_pool_alloc(&pf->msix_pool,
1641                                          RTE_MIN(vsi->nb_qps,
1642                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1643                 if (ret < 0) {
1644                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1645                                      vsi->vsi_id, ret);
1646                 }
1647                 vsi->msix_intr = ret;
1648                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1649         } else if (type == ICE_VSI_CTRL) {
1650                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1651                 if (ret < 0) {
1652                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1653                                     vsi->vsi_id, ret);
1654                 }
1655                 vsi->msix_intr = ret;
1656                 vsi->nb_msix = 1;
1657         } else {
1658                 vsi->msix_intr = 0;
1659                 vsi->nb_msix = 0;
1660         }
1661         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1662         if (ret != ICE_SUCCESS) {
1663                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1664                 goto fail_mem;
1665         }
1666         /* store vsi information is SW structure */
1667         vsi->vsi_id = vsi_ctx.vsi_num;
1668         vsi->info = vsi_ctx.info;
1669         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1670         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1671
1672         if (type == ICE_VSI_PF) {
1673                 /* MAC configuration */
1674                 rte_ether_addr_copy((struct rte_ether_addr *)
1675                                         hw->port_info->mac.perm_addr,
1676                                     &pf->dev_addr);
1677
1678                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1679                 ret = ice_add_mac_filter(vsi, &mac_addr);
1680                 if (ret != ICE_SUCCESS)
1681                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1682
1683                 rte_ether_addr_copy(&broadcast, &mac_addr);
1684                 ret = ice_add_mac_filter(vsi, &mac_addr);
1685                 if (ret != ICE_SUCCESS)
1686                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1687         }
1688
1689         /* At the beginning, only TC0. */
1690         /* What we need here is the maximam number of the TX queues.
1691          * Currently vsi->nb_qps means it.
1692          * Correct it if any change.
1693          */
1694         max_txqs[0] = vsi->nb_qps;
1695         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1696                               tc_bitmap, max_txqs);
1697         if (ret != ICE_SUCCESS)
1698                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1699
1700         return vsi;
1701 fail_mem:
1702         rte_free(vsi);
1703         pf->next_vsi_idx--;
1704         return NULL;
1705 }
1706
1707 static int
1708 ice_send_driver_ver(struct ice_hw *hw)
1709 {
1710         struct ice_driver_ver dv;
1711
1712         /* we don't have driver version use 0 for dummy */
1713         dv.major_ver = 0;
1714         dv.minor_ver = 0;
1715         dv.build_ver = 0;
1716         dv.subbuild_ver = 0;
1717         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1718
1719         return ice_aq_send_driver_ver(hw, &dv, NULL);
1720 }
1721
1722 static int
1723 ice_pf_setup(struct ice_pf *pf)
1724 {
1725         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1726         struct ice_vsi *vsi;
1727         uint16_t unused;
1728
1729         /* Clear all stats counters */
1730         pf->offset_loaded = false;
1731         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1732         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1733         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1734         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1735
1736         /* force guaranteed filter pool for PF */
1737         ice_alloc_fd_guar_item(hw, &unused,
1738                                hw->func_caps.fd_fltr_guar);
1739         /* force shared filter pool for PF */
1740         ice_alloc_fd_shrd_item(hw, &unused,
1741                                hw->func_caps.fd_fltr_best_effort);
1742
1743         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1744         if (!vsi) {
1745                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1746                 return -EINVAL;
1747         }
1748
1749         pf->main_vsi = vsi;
1750
1751         return 0;
1752 }
1753
1754 /* PCIe configuration space setting */
1755 #define PCI_CFG_SPACE_SIZE          256
1756 #define PCI_CFG_SPACE_EXP_SIZE      4096
1757 #define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
1758 #define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
1759 #define PCI_EXT_CAP_ID_DSN          0x03
1760
1761 static int
1762 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1763 {
1764         uint32_t header;
1765         int ttl;
1766         int pos = PCI_CFG_SPACE_SIZE;
1767
1768         /* minimum 8 bytes per capability */
1769         ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1770
1771         if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1772                 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1773                 return -1;
1774         }
1775
1776         /*
1777          * If we have no capabilities, this is indicated by cap ID,
1778          * cap version and next pointer all being 0.
1779          */
1780         if (header == 0)
1781                 return 0;
1782
1783         while (ttl-- > 0) {
1784                 if (PCI_EXT_CAP_ID(header) == cap)
1785                         return pos;
1786
1787                 pos = PCI_EXT_CAP_NEXT(header);
1788
1789                 if (pos < PCI_CFG_SPACE_SIZE)
1790                         break;
1791
1792                 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1793                         PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1794                         return -1;
1795                 }
1796         }
1797
1798         return 0;
1799 }
1800
1801 /*
1802  * Extract device serial number from PCIe Configuration Space and
1803  * determine the pkg file path according to the DSN.
1804  */
1805 static int
1806 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1807 {
1808         int pos;
1809         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1810         uint32_t dsn_low, dsn_high;
1811         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1812
1813         pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1814
1815         if (pos) {
1816                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1817                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1818                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1819                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1820         } else {
1821                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1822                 goto fail_dsn;
1823         }
1824
1825         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1826                 ICE_MAX_PKG_FILENAME_SIZE);
1827         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1828                 return 0;
1829
1830         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1831                 ICE_MAX_PKG_FILENAME_SIZE);
1832         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1833                 return 0;
1834
1835 fail_dsn:
1836         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1837         if (!access(pkg_file, 0))
1838                 return 0;
1839         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1840         return 0;
1841 }
1842
1843 enum ice_pkg_type
1844 ice_load_pkg_type(struct ice_hw *hw)
1845 {
1846         enum ice_pkg_type package_type;
1847
1848         /* store the activated package type (OS default or Comms) */
1849         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1850                 ICE_PKG_NAME_SIZE))
1851                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1852         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1853                 ICE_PKG_NAME_SIZE))
1854                 package_type = ICE_PKG_TYPE_COMMS;
1855         else
1856                 package_type = ICE_PKG_TYPE_UNKNOWN;
1857
1858         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1859                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1860                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1861                 hw->active_pkg_name);
1862
1863         return package_type;
1864 }
1865
1866 static int ice_load_pkg(struct rte_eth_dev *dev)
1867 {
1868         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1870         int err;
1871         uint8_t *buf;
1872         int buf_len;
1873         FILE *file;
1874         struct stat fstat;
1875         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1876         struct ice_adapter *ad =
1877                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1878
1879         ice_pkg_file_search_path(pci_dev, pkg_file);
1880
1881         file = fopen(pkg_file, "rb");
1882         if (!file)  {
1883                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1884                 return -1;
1885         }
1886
1887         err = stat(pkg_file, &fstat);
1888         if (err) {
1889                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1890                 fclose(file);
1891                 return err;
1892         }
1893
1894         buf_len = fstat.st_size;
1895         buf = rte_malloc(NULL, buf_len, 0);
1896
1897         if (!buf) {
1898                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1899                                 buf_len);
1900                 fclose(file);
1901                 return -1;
1902         }
1903
1904         err = fread(buf, buf_len, 1, file);
1905         if (err != 1) {
1906                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1907                 fclose(file);
1908                 err = -1;
1909                 goto fail_exit;
1910         }
1911
1912         fclose(file);
1913
1914         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1915         if (err) {
1916                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1917                 goto fail_exit;
1918         }
1919
1920         /* store the loaded pkg type info */
1921         ad->active_pkg_type = ice_load_pkg_type(hw);
1922
1923         err = ice_init_hw_tbls(hw);
1924         if (err) {
1925                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1926                 goto fail_init_tbls;
1927         }
1928
1929         return 0;
1930
1931 fail_init_tbls:
1932         rte_free(hw->pkg_copy);
1933 fail_exit:
1934         rte_free(buf);
1935         return err;
1936 }
1937
1938 static void
1939 ice_base_queue_get(struct ice_pf *pf)
1940 {
1941         uint32_t reg;
1942         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1943
1944         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1945         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1946                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1947         } else {
1948                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1949                                         " index");
1950         }
1951 }
1952
1953 static int
1954 parse_bool(const char *key, const char *value, void *args)
1955 {
1956         int *i = (int *)args;
1957         char *end;
1958         int num;
1959
1960         num = strtoul(value, &end, 10);
1961
1962         if (num != 0 && num != 1) {
1963                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1964                         "value must be 0 or 1",
1965                         value, key);
1966                 return -1;
1967         }
1968
1969         *i = num;
1970         return 0;
1971 }
1972
1973 static int ice_parse_devargs(struct rte_eth_dev *dev)
1974 {
1975         struct ice_adapter *ad =
1976                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1977         struct rte_devargs *devargs = dev->device->devargs;
1978         struct rte_kvargs *kvlist;
1979         int ret;
1980
1981         if (devargs == NULL)
1982                 return 0;
1983
1984         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1985         if (kvlist == NULL) {
1986                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1987                 return -EINVAL;
1988         }
1989
1990         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1991         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1992                sizeof(ad->devargs.proto_xtr));
1993
1994         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1995                                  &handle_proto_xtr_arg, &ad->devargs);
1996         if (ret)
1997                 goto bail;
1998
1999         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
2000                                  &parse_bool, &ad->devargs.safe_mode_support);
2001         if (ret)
2002                 goto bail;
2003
2004         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
2005                                  &parse_bool, &ad->devargs.pipe_mode_support);
2006         if (ret)
2007                 goto bail;
2008
2009         ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
2010                                  &parse_bool, &ad->devargs.flow_mark_support);
2011         if (ret)
2012                 goto bail;
2013
2014 bail:
2015         rte_kvargs_free(kvlist);
2016         return ret;
2017 }
2018
2019 /* Forward LLDP packets to default VSI by set switch rules */
2020 static int
2021 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
2022 {
2023         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2024         struct ice_fltr_list_entry *s_list_itr = NULL;
2025         struct LIST_HEAD_TYPE list_head;
2026         int ret = 0;
2027
2028         INIT_LIST_HEAD(&list_head);
2029
2030         s_list_itr = (struct ice_fltr_list_entry *)
2031                         ice_malloc(hw, sizeof(*s_list_itr));
2032         if (!s_list_itr)
2033                 return -ENOMEM;
2034         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2035         s_list_itr->fltr_info.vsi_handle = vsi->idx;
2036         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2037                         RTE_ETHER_TYPE_LLDP;
2038         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2039         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2040         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2041         LIST_ADD(&s_list_itr->list_entry, &list_head);
2042         if (on)
2043                 ret = ice_add_eth_mac(hw, &list_head);
2044         else
2045                 ret = ice_remove_eth_mac(hw, &list_head);
2046
2047         rte_free(s_list_itr);
2048         return ret;
2049 }
2050
2051 static enum ice_status
2052 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2053                 uint16_t num, uint16_t desc_id,
2054                 uint16_t *prof_buf, uint16_t *num_prof)
2055 {
2056         struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2057         int ret;
2058         uint16_t buf_len;
2059         bool res_shared = 1;
2060         struct ice_aq_desc aq_desc;
2061         struct ice_sq_cd *cd = NULL;
2062         struct ice_aqc_get_allocd_res_desc *cmd =
2063                         &aq_desc.params.get_res_desc;
2064
2065         buf_len = sizeof(resp_buf->elem) * num;
2066         resp_buf = ice_malloc(hw, buf_len);
2067         if (!resp_buf)
2068                 return -ENOMEM;
2069
2070         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2071                         ice_aqc_opc_get_allocd_res_desc);
2072
2073         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2074                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2075                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2076         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2077
2078         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2079         if (!ret)
2080                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2081         else
2082                 goto exit;
2083
2084         ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2085                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2086
2087 exit:
2088         rte_free(resp_buf);
2089         return ret;
2090 }
2091 static int
2092 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2093 {
2094         int ret;
2095         uint16_t prof_id;
2096         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2097         uint16_t first_desc = 1;
2098         uint16_t num_prof = 0;
2099
2100         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2101                         first_desc, prof_buf, &num_prof);
2102         if (ret) {
2103                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2104                 return ret;
2105         }
2106
2107         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2108                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2109                 if (ret) {
2110                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2111                         return ret;
2112                 }
2113         }
2114         return 0;
2115 }
2116
2117 static int
2118 ice_reset_fxp_resource(struct ice_hw *hw)
2119 {
2120         int ret;
2121
2122         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2123         if (ret) {
2124                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2125                 return ret;
2126         }
2127
2128         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2129         if (ret) {
2130                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2131                 return ret;
2132         }
2133
2134         return 0;
2135 }
2136
2137 static void
2138 ice_rss_ctx_init(struct ice_pf *pf)
2139 {
2140         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2141         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2142
2143         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2144         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2145
2146         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2147         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2148 }
2149
2150 static int
2151 ice_dev_init(struct rte_eth_dev *dev)
2152 {
2153         struct rte_pci_device *pci_dev;
2154         struct rte_intr_handle *intr_handle;
2155         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157         struct ice_adapter *ad =
2158                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2159         struct ice_vsi *vsi;
2160         int ret;
2161
2162         dev->dev_ops = &ice_eth_dev_ops;
2163         dev->rx_queue_count = ice_rx_queue_count;
2164         dev->rx_descriptor_status = ice_rx_descriptor_status;
2165         dev->tx_descriptor_status = ice_tx_descriptor_status;
2166         dev->rx_pkt_burst = ice_recv_pkts;
2167         dev->tx_pkt_burst = ice_xmit_pkts;
2168         dev->tx_pkt_prepare = ice_prep_pkts;
2169
2170         /* for secondary processes, we don't initialise any further as primary
2171          * has already done this work.
2172          */
2173         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2174                 ice_set_rx_function(dev);
2175                 ice_set_tx_function(dev);
2176                 return 0;
2177         }
2178
2179         ice_set_default_ptype_table(dev);
2180         pci_dev = RTE_DEV_TO_PCI(dev->device);
2181         intr_handle = &pci_dev->intr_handle;
2182
2183         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2184         pf->adapter->eth_dev = dev;
2185         pf->dev_data = dev->data;
2186         hw->back = pf->adapter;
2187         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2188         hw->vendor_id = pci_dev->id.vendor_id;
2189         hw->device_id = pci_dev->id.device_id;
2190         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2191         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2192         hw->bus.device = pci_dev->addr.devid;
2193         hw->bus.func = pci_dev->addr.function;
2194
2195         ret = ice_parse_devargs(dev);
2196         if (ret) {
2197                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2198                 return -EINVAL;
2199         }
2200
2201         ice_init_controlq_parameter(hw);
2202
2203         ret = ice_init_hw(hw);
2204         if (ret) {
2205                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2206                 return -EINVAL;
2207         }
2208
2209         ret = ice_load_pkg(dev);
2210         if (ret) {
2211                 if (ad->devargs.safe_mode_support == 0) {
2212                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2213                                         "Use safe-mode-support=1 to enter Safe Mode");
2214                         return ret;
2215                 }
2216
2217                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2218                                         "Entering Safe Mode");
2219                 ad->is_safe_mode = 1;
2220         }
2221
2222         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2223                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2224                      hw->api_maj_ver, hw->api_min_ver);
2225
2226         ice_pf_sw_init(dev);
2227         ret = ice_init_mac_address(dev);
2228         if (ret) {
2229                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2230                 goto err_init_mac;
2231         }
2232
2233         /* Pass the information to the rte_eth_dev_close() that it should also
2234          * release the private port resources.
2235          */
2236         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2237
2238         ret = ice_res_pool_init(&pf->msix_pool, 1,
2239                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2240         if (ret) {
2241                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2242                 goto err_msix_pool_init;
2243         }
2244
2245         ret = ice_pf_setup(pf);
2246         if (ret) {
2247                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2248                 goto err_pf_setup;
2249         }
2250
2251         ret = ice_send_driver_ver(hw);
2252         if (ret) {
2253                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2254                 goto err_pf_setup;
2255         }
2256
2257         vsi = pf->main_vsi;
2258
2259         /* Disable double vlan by default */
2260         ice_vsi_config_double_vlan(vsi, false);
2261
2262         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2263         if (ret != ICE_SUCCESS)
2264                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2265         ret = ice_init_dcb(hw, true);
2266         if (ret != ICE_SUCCESS)
2267                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2268         /* Forward LLDP packets to default VSI */
2269         ret = ice_vsi_config_sw_lldp(vsi, true);
2270         if (ret != ICE_SUCCESS)
2271                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2272         /* register callback func to eal lib */
2273         rte_intr_callback_register(intr_handle,
2274                                    ice_interrupt_handler, dev);
2275
2276         ice_pf_enable_irq0(hw);
2277
2278         /* enable uio intr after callback register */
2279         rte_intr_enable(intr_handle);
2280
2281         /* get base queue pairs index  in the device */
2282         ice_base_queue_get(pf);
2283
2284         /* Initialize RSS context for gtpu_eh */
2285         ice_rss_ctx_init(pf);
2286
2287         if (!ad->is_safe_mode) {
2288                 ret = ice_flow_init(ad);
2289                 if (ret) {
2290                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2291                         return ret;
2292                 }
2293         }
2294
2295         ret = ice_reset_fxp_resource(hw);
2296         if (ret) {
2297                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2298                 return ret;
2299         }
2300
2301         return 0;
2302
2303 err_pf_setup:
2304         ice_res_pool_destroy(&pf->msix_pool);
2305 err_msix_pool_init:
2306         rte_free(dev->data->mac_addrs);
2307         dev->data->mac_addrs = NULL;
2308 err_init_mac:
2309         ice_sched_cleanup_all(hw);
2310         rte_free(hw->port_info);
2311         ice_shutdown_all_ctrlq(hw);
2312         rte_free(pf->proto_xtr);
2313
2314         return ret;
2315 }
2316
2317 int
2318 ice_release_vsi(struct ice_vsi *vsi)
2319 {
2320         struct ice_hw *hw;
2321         struct ice_vsi_ctx vsi_ctx;
2322         enum ice_status ret;
2323         int error = 0;
2324
2325         if (!vsi)
2326                 return error;
2327
2328         hw = ICE_VSI_TO_HW(vsi);
2329
2330         ice_remove_all_mac_vlan_filters(vsi);
2331
2332         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2333
2334         vsi_ctx.vsi_num = vsi->vsi_id;
2335         vsi_ctx.info = vsi->info;
2336         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2337         if (ret != ICE_SUCCESS) {
2338                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2339                 error = -1;
2340         }
2341
2342         rte_free(vsi->rss_lut);
2343         rte_free(vsi->rss_key);
2344         rte_free(vsi);
2345         return error;
2346 }
2347
2348 void
2349 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2350 {
2351         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2352         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2354         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2355         uint16_t msix_intr, i;
2356
2357         /* disable interrupt and also clear all the exist config */
2358         for (i = 0; i < vsi->nb_qps; i++) {
2359                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2360                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2361                 rte_wmb();
2362         }
2363
2364         if (rte_intr_allow_others(intr_handle))
2365                 /* vfio-pci */
2366                 for (i = 0; i < vsi->nb_msix; i++) {
2367                         msix_intr = vsi->msix_intr + i;
2368                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2369                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2370                 }
2371         else
2372                 /* igb_uio */
2373                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2374 }
2375
2376 static void
2377 ice_dev_stop(struct rte_eth_dev *dev)
2378 {
2379         struct rte_eth_dev_data *data = dev->data;
2380         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2381         struct ice_vsi *main_vsi = pf->main_vsi;
2382         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2383         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2384         uint16_t i;
2385
2386         /* avoid stopping again */
2387         if (pf->adapter_stopped)
2388                 return;
2389
2390         /* stop and clear all Rx queues */
2391         for (i = 0; i < data->nb_rx_queues; i++)
2392                 ice_rx_queue_stop(dev, i);
2393
2394         /* stop and clear all Tx queues */
2395         for (i = 0; i < data->nb_tx_queues; i++)
2396                 ice_tx_queue_stop(dev, i);
2397
2398         /* disable all queue interrupts */
2399         ice_vsi_disable_queues_intr(main_vsi);
2400
2401         if (pf->init_link_up)
2402                 ice_dev_set_link_up(dev);
2403         else
2404                 ice_dev_set_link_down(dev);
2405
2406         /* Clean datapath event and queue/vec mapping */
2407         rte_intr_efd_disable(intr_handle);
2408         if (intr_handle->intr_vec) {
2409                 rte_free(intr_handle->intr_vec);
2410                 intr_handle->intr_vec = NULL;
2411         }
2412
2413         pf->adapter_stopped = true;
2414 }
2415
2416 static void
2417 ice_dev_close(struct rte_eth_dev *dev)
2418 {
2419         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2420         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2422         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2423         struct ice_adapter *ad =
2424                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2425
2426         /* Since stop will make link down, then the link event will be
2427          * triggered, disable the irq firstly to avoid the port_infoe etc
2428          * resources deallocation causing the interrupt service thread
2429          * crash.
2430          */
2431         ice_pf_disable_irq0(hw);
2432
2433         ice_dev_stop(dev);
2434
2435         if (!ad->is_safe_mode)
2436                 ice_flow_uninit(ad);
2437
2438         /* release all queue resource */
2439         ice_free_queues(dev);
2440
2441         ice_res_pool_destroy(&pf->msix_pool);
2442         ice_release_vsi(pf->main_vsi);
2443         ice_sched_cleanup_all(hw);
2444         ice_free_hw_tbls(hw);
2445         rte_free(hw->port_info);
2446         hw->port_info = NULL;
2447         ice_shutdown_all_ctrlq(hw);
2448         rte_free(pf->proto_xtr);
2449         pf->proto_xtr = NULL;
2450
2451         dev->dev_ops = NULL;
2452         dev->rx_pkt_burst = NULL;
2453         dev->tx_pkt_burst = NULL;
2454
2455         rte_free(dev->data->mac_addrs);
2456         dev->data->mac_addrs = NULL;
2457
2458         /* disable uio intr before callback unregister */
2459         rte_intr_disable(intr_handle);
2460
2461         /* unregister callback func from eal lib */
2462         rte_intr_callback_unregister(intr_handle,
2463                                      ice_interrupt_handler, dev);
2464 }
2465
2466 static int
2467 ice_dev_uninit(struct rte_eth_dev *dev)
2468 {
2469         ice_dev_close(dev);
2470
2471         return 0;
2472 }
2473
2474 static int
2475 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm)
2476 {
2477         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2478         struct ice_vsi *vsi = pf->main_vsi;
2479
2480         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2481                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2482                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2483                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr = hdr;
2484                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld = fld;
2485                         pf->gtpu_hash_ctx.ipv4_udp.symm = symm;
2486                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2487                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2488                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr = hdr;
2489                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld = fld;
2490                         pf->gtpu_hash_ctx.ipv6_udp.symm = symm;
2491                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2492                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2493                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr = hdr;
2494                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld = fld;
2495                         pf->gtpu_hash_ctx.ipv4_tcp.symm = symm;
2496                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2497                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2498                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr = hdr;
2499                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld = fld;
2500                         pf->gtpu_hash_ctx.ipv6_tcp.symm = symm;
2501                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2502                         pf->gtpu_hash_ctx.ipv4.pkt_hdr = hdr;
2503                         pf->gtpu_hash_ctx.ipv4.hash_fld = fld;
2504                         pf->gtpu_hash_ctx.ipv4.symm = symm;
2505                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2506                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2507                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2508                         pf->gtpu_hash_ctx.ipv6.pkt_hdr = hdr;
2509                         pf->gtpu_hash_ctx.ipv6.hash_fld = fld;
2510                         pf->gtpu_hash_ctx.ipv6.symm = symm;
2511                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2512                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2513                 }
2514         }
2515
2516         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2517             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2518                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2519                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2520                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2521                                 ice_add_rss_cfg(hw, vsi->idx,
2522                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2523                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2524                                         pf->gtpu_hash_ctx.ipv4.symm);
2525                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2526                         }
2527                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2528                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2529                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2530                                 ice_add_rss_cfg(hw, vsi->idx,
2531                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2532                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2533                                         pf->gtpu_hash_ctx.ipv6.symm);
2534                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2535                         }
2536                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2537                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2538                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2539                                 ice_add_rss_cfg(hw, vsi->idx,
2540                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2541                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2542                                         pf->gtpu_hash_ctx.ipv4.symm);
2543                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2544                         }
2545                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2546                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2547                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2548                                 ice_add_rss_cfg(hw, vsi->idx,
2549                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2550                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2551                                         pf->gtpu_hash_ctx.ipv6.symm);
2552                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2553                         }
2554                 }
2555         }
2556
2557         return 0;
2558 }
2559
2560 static int
2561 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2562 {
2563         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2564         struct ice_vsi *vsi = pf->main_vsi;
2565
2566         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2567             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2568                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2569                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2570                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2571                                 ice_rem_rss_cfg(hw, vsi->idx,
2572                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2573                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2574                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2575                         }
2576
2577                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2578                                 ice_rem_rss_cfg(hw, vsi->idx,
2579                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2580                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2581                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2582                         }
2583                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2584                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2585                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2586                                 ice_rem_rss_cfg(hw, vsi->idx,
2587                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2588                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2589                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2590                         }
2591
2592                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2593                                 ice_rem_rss_cfg(hw, vsi->idx,
2594                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2595                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2596                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2597                         }
2598                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2599                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2600                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2601                                 ice_rem_rss_cfg(hw, vsi->idx,
2602                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2603                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2604                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2605                         }
2606
2607                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2608                                 ice_rem_rss_cfg(hw, vsi->idx,
2609                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2610                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2611                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2612                         }
2613                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2614                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2615                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2616                                 ice_rem_rss_cfg(hw, vsi->idx,
2617                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2618                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2619                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2620                         }
2621
2622                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2623                                 ice_rem_rss_cfg(hw, vsi->idx,
2624                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2625                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2626                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2627                         }
2628                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2629                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2630                                 ice_rem_rss_cfg(hw, vsi->idx,
2631                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2632                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2633                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2634                         }
2635
2636                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2637                                 ice_rem_rss_cfg(hw, vsi->idx,
2638                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2639                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2640                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2641                         }
2642
2643                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2644                                 ice_rem_rss_cfg(hw, vsi->idx,
2645                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2646                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2647                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2648                         }
2649                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2650                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2651                                 ice_rem_rss_cfg(hw, vsi->idx,
2652                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2653                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2654                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2655                         }
2656
2657                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2658                                 ice_rem_rss_cfg(hw, vsi->idx,
2659                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2660                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2661                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2662                         }
2663
2664                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2665                                 ice_rem_rss_cfg(hw, vsi->idx,
2666                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2667                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2668                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2669                         }
2670                 }
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int
2677 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2678 {
2679         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2680                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2681                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2682                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2683                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2684                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2685                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2686                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2687                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2688                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2689                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2690                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2691                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2692                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2693                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2694                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2695                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2696                 }
2697         }
2698
2699         return 0;
2700 }
2701
2702 int
2703 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2704                 uint64_t fld, uint32_t hdr)
2705 {
2706         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2707         int ret;
2708
2709         ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr);
2710         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2711                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2712
2713         ret = ice_rem_rss_cfg_post(pf, hdr);
2714         if (ret)
2715                 PMD_DRV_LOG(ERR, "remove rss cfg post failed\n");
2716
2717         return 0;
2718 }
2719
2720 int
2721 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2722                 uint64_t fld, uint32_t hdr, bool symm)
2723 {
2724         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2725         int ret;
2726
2727         ret = ice_add_rss_cfg_pre(pf, hdr);
2728         if (ret)
2729                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2730
2731         ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm);
2732         if (ret)
2733                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2734
2735         ret = ice_add_rss_cfg_post(pf, hdr, fld, symm);
2736         if (ret)
2737                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2738
2739         return 0;
2740 }
2741
2742 static void
2743 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2744 {
2745         struct ice_vsi *vsi = pf->main_vsi;
2746         int ret;
2747
2748         /* Configure RSS for IPv4 with src/dst addr as input set */
2749         if (rss_hf & ETH_RSS_IPV4) {
2750                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2751                                       ICE_FLOW_SEG_HDR_IPV4 |
2752                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2753                 if (ret)
2754                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2755                                     __func__, ret);
2756         }
2757
2758         /* Configure RSS for IPv6 with src/dst addr as input set */
2759         if (rss_hf & ETH_RSS_IPV6) {
2760                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2761                                       ICE_FLOW_SEG_HDR_IPV6 |
2762                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2763                 if (ret)
2764                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2765                                     __func__, ret);
2766         }
2767
2768         /* Configure RSS for udp4 with src/dst addr and port as input set */
2769         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2770                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2771                                       ICE_FLOW_SEG_HDR_UDP |
2772                                       ICE_FLOW_SEG_HDR_IPV4 |
2773                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2774                 if (ret)
2775                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2776                                     __func__, ret);
2777         }
2778
2779         /* Configure RSS for udp6 with src/dst addr and port as input set */
2780         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2781                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2782                                       ICE_FLOW_SEG_HDR_UDP |
2783                                       ICE_FLOW_SEG_HDR_IPV6 |
2784                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2785                 if (ret)
2786                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2787                                     __func__, ret);
2788         }
2789
2790         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2791         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2792                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2793                                       ICE_FLOW_SEG_HDR_TCP |
2794                                       ICE_FLOW_SEG_HDR_IPV4 |
2795                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2796                 if (ret)
2797                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2798                                     __func__, ret);
2799         }
2800
2801         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2802         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2803                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2804                                       ICE_FLOW_SEG_HDR_TCP |
2805                                       ICE_FLOW_SEG_HDR_IPV6 |
2806                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2807                 if (ret)
2808                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2809                                     __func__, ret);
2810         }
2811
2812         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2813         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2814                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2815                                       ICE_FLOW_SEG_HDR_SCTP |
2816                                       ICE_FLOW_SEG_HDR_IPV4 |
2817                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2818                 if (ret)
2819                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2820                                     __func__, ret);
2821         }
2822
2823         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2824         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2825                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2826                                       ICE_FLOW_SEG_HDR_SCTP |
2827                                       ICE_FLOW_SEG_HDR_IPV6 |
2828                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2829                 if (ret)
2830                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2831                                     __func__, ret);
2832         }
2833
2834         if (rss_hf & ETH_RSS_IPV4) {
2835                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2836                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2837                                 ICE_FLOW_SEG_HDR_IPV4 |
2838                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2839                 if (ret)
2840                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2841                                     __func__, ret);
2842
2843                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2844                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2845                                 ICE_FLOW_SEG_HDR_IPV4 |
2846                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2847                 if (ret)
2848                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2849                                     __func__, ret);
2850
2851                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2852                                 ICE_FLOW_SEG_HDR_PPPOE |
2853                                 ICE_FLOW_SEG_HDR_IPV4 |
2854                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2855                 if (ret)
2856                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2857                                     __func__, ret);
2858         }
2859
2860         if (rss_hf & ETH_RSS_IPV6) {
2861                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2862                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2863                                 ICE_FLOW_SEG_HDR_IPV6 |
2864                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2865                 if (ret)
2866                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2867                                     __func__, ret);
2868
2869                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2870                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2871                                 ICE_FLOW_SEG_HDR_IPV6 |
2872                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2873                 if (ret)
2874                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2875                                     __func__, ret);
2876
2877                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2878                                 ICE_FLOW_SEG_HDR_PPPOE |
2879                                 ICE_FLOW_SEG_HDR_IPV6 |
2880                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2881                 if (ret)
2882                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2883                                     __func__, ret);
2884         }
2885
2886         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2887                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2888                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2889                                 ICE_FLOW_SEG_HDR_UDP |
2890                                 ICE_FLOW_SEG_HDR_IPV4 |
2891                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2892                 if (ret)
2893                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2894                                     __func__, ret);
2895
2896                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2897                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2898                                 ICE_FLOW_SEG_HDR_UDP |
2899                                 ICE_FLOW_SEG_HDR_IPV4 |
2900                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2901                 if (ret)
2902                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2903                                     __func__, ret);
2904
2905                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2906                                 ICE_FLOW_SEG_HDR_PPPOE |
2907                                 ICE_FLOW_SEG_HDR_UDP |
2908                                 ICE_FLOW_SEG_HDR_IPV4 |
2909                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2910                 if (ret)
2911                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2912                                     __func__, ret);
2913         }
2914
2915         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2916                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2917                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2918                                 ICE_FLOW_SEG_HDR_UDP |
2919                                 ICE_FLOW_SEG_HDR_IPV6 |
2920                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2921                 if (ret)
2922                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2923                                     __func__, ret);
2924
2925                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2926                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2927                                 ICE_FLOW_SEG_HDR_UDP |
2928                                 ICE_FLOW_SEG_HDR_IPV6 |
2929                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2930                 if (ret)
2931                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2932                                     __func__, ret);
2933
2934                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2935                                 ICE_FLOW_SEG_HDR_PPPOE |
2936                                 ICE_FLOW_SEG_HDR_UDP |
2937                                 ICE_FLOW_SEG_HDR_IPV6 |
2938                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2939                 if (ret)
2940                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2941                                     __func__, ret);
2942         }
2943
2944         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2945                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2946                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2947                                 ICE_FLOW_SEG_HDR_TCP |
2948                                 ICE_FLOW_SEG_HDR_IPV4 |
2949                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2950                 if (ret)
2951                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
2952                                     __func__, ret);
2953
2954                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2955                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2956                                 ICE_FLOW_SEG_HDR_TCP |
2957                                 ICE_FLOW_SEG_HDR_IPV4 |
2958                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2959                 if (ret)
2960                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
2961                                     __func__, ret);
2962
2963                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2964                                 ICE_FLOW_SEG_HDR_PPPOE |
2965                                 ICE_FLOW_SEG_HDR_TCP |
2966                                 ICE_FLOW_SEG_HDR_IPV4 |
2967                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2968                 if (ret)
2969                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2970                                     __func__, ret);
2971         }
2972
2973         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2974                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2975                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2976                                 ICE_FLOW_SEG_HDR_TCP |
2977                                 ICE_FLOW_SEG_HDR_IPV6 |
2978                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2979                 if (ret)
2980                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
2981                                     __func__, ret);
2982
2983                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2984                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2985                                 ICE_FLOW_SEG_HDR_TCP |
2986                                 ICE_FLOW_SEG_HDR_IPV6 |
2987                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2988                 if (ret)
2989                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
2990                                     __func__, ret);
2991
2992                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2993                                 ICE_FLOW_SEG_HDR_PPPOE |
2994                                 ICE_FLOW_SEG_HDR_TCP |
2995                                 ICE_FLOW_SEG_HDR_IPV6 |
2996                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2997                 if (ret)
2998                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2999                                     __func__, ret);
3000         }
3001
3002         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3003                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3004                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3005                                 ICE_FLOW_SEG_HDR_SCTP |
3006                                 ICE_FLOW_SEG_HDR_IPV4 |
3007                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3008                 if (ret)
3009                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
3010                                     __func__, ret);
3011
3012                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3013                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3014                                 ICE_FLOW_SEG_HDR_SCTP |
3015                                 ICE_FLOW_SEG_HDR_IPV4 |
3016                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3017                 if (ret)
3018                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
3019                                     __func__, ret);
3020         }
3021
3022         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3023                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3024                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3025                                 ICE_FLOW_SEG_HDR_SCTP |
3026                                 ICE_FLOW_SEG_HDR_IPV6 |
3027                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3028                 if (ret)
3029                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
3030                                     __func__, ret);
3031
3032                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3033                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3034                                 ICE_FLOW_SEG_HDR_SCTP |
3035                                 ICE_FLOW_SEG_HDR_IPV6 |
3036                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3037                 if (ret)
3038                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
3039                                     __func__, ret);
3040         }
3041 }
3042
3043 static int ice_init_rss(struct ice_pf *pf)
3044 {
3045         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3046         struct ice_vsi *vsi = pf->main_vsi;
3047         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3048         struct rte_eth_rss_conf *rss_conf;
3049         struct ice_aqc_get_set_rss_keys key;
3050         uint16_t i, nb_q;
3051         int ret = 0;
3052         bool is_safe_mode = pf->adapter->is_safe_mode;
3053         uint32_t reg;
3054
3055         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3056         nb_q = dev->data->nb_rx_queues;
3057         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3058         vsi->rss_lut_size = pf->hash_lut_size;
3059
3060         if (is_safe_mode) {
3061                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3062                 return 0;
3063         }
3064
3065         if (!vsi->rss_key) {
3066                 vsi->rss_key = rte_zmalloc(NULL,
3067                                            vsi->rss_key_size, 0);
3068                 if (vsi->rss_key == NULL) {
3069                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3070                         return -ENOMEM;
3071                 }
3072         }
3073         if (!vsi->rss_lut) {
3074                 vsi->rss_lut = rte_zmalloc(NULL,
3075                                            vsi->rss_lut_size, 0);
3076                 if (vsi->rss_lut == NULL) {
3077                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3078                         rte_free(vsi->rss_key);
3079                         vsi->rss_key = NULL;
3080                         return -ENOMEM;
3081                 }
3082         }
3083         /* configure RSS key */
3084         if (!rss_conf->rss_key) {
3085                 /* Calculate the default hash key */
3086                 for (i = 0; i <= vsi->rss_key_size; i++)
3087                         vsi->rss_key[i] = (uint8_t)rte_rand();
3088         } else {
3089                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3090                            RTE_MIN(rss_conf->rss_key_len,
3091                                    vsi->rss_key_size));
3092         }
3093         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3094         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3095         if (ret)
3096                 goto out;
3097
3098         /* init RSS LUT table */
3099         for (i = 0; i < vsi->rss_lut_size; i++)
3100                 vsi->rss_lut[i] = i % nb_q;
3101
3102         ret = ice_aq_set_rss_lut(hw, vsi->idx,
3103                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
3104                                  vsi->rss_lut, vsi->rss_lut_size);
3105         if (ret)
3106                 goto out;
3107
3108         /* Enable registers for symmetric_toeplitz function. */
3109         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3110         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3111                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3112         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3113
3114         /* RSS hash configuration */
3115         ice_rss_hash_set(pf, rss_conf->rss_hf);
3116
3117         return 0;
3118 out:
3119         rte_free(vsi->rss_key);
3120         vsi->rss_key = NULL;
3121         rte_free(vsi->rss_lut);
3122         vsi->rss_lut = NULL;
3123         return -EINVAL;
3124 }
3125
3126 static int
3127 ice_dev_configure(struct rte_eth_dev *dev)
3128 {
3129         struct ice_adapter *ad =
3130                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3131         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132         int ret;
3133
3134         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3135          * bulk allocation or vector Rx preconditions we will reset it.
3136          */
3137         ad->rx_bulk_alloc_allowed = true;
3138         ad->tx_simple_allowed = true;
3139
3140         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3141                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3142
3143         ret = ice_init_rss(pf);
3144         if (ret) {
3145                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3146                 return ret;
3147         }
3148
3149         return 0;
3150 }
3151
3152 static void
3153 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3154                        int base_queue, int nb_queue)
3155 {
3156         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3157         uint32_t val, val_tx;
3158         int i;
3159
3160         for (i = 0; i < nb_queue; i++) {
3161                 /*do actual bind*/
3162                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3163                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3164                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3165                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3166
3167                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3168                             base_queue + i, msix_vect);
3169                 /* set ITR0 value */
3170                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
3171                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3172                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3173         }
3174 }
3175
3176 void
3177 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3178 {
3179         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3180         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3181         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3182         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3183         uint16_t msix_vect = vsi->msix_intr;
3184         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3185         uint16_t queue_idx = 0;
3186         int record = 0;
3187         int i;
3188
3189         /* clear Rx/Tx queue interrupt */
3190         for (i = 0; i < vsi->nb_used_qps; i++) {
3191                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3192                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3193         }
3194
3195         /* PF bind interrupt */
3196         if (rte_intr_dp_is_en(intr_handle)) {
3197                 queue_idx = 0;
3198                 record = 1;
3199         }
3200
3201         for (i = 0; i < vsi->nb_used_qps; i++) {
3202                 if (nb_msix <= 1) {
3203                         if (!rte_intr_allow_others(intr_handle))
3204                                 msix_vect = ICE_MISC_VEC_ID;
3205
3206                         /* uio mapping all queue to one msix_vect */
3207                         __vsi_queues_bind_intr(vsi, msix_vect,
3208                                                vsi->base_queue + i,
3209                                                vsi->nb_used_qps - i);
3210
3211                         for (; !!record && i < vsi->nb_used_qps; i++)
3212                                 intr_handle->intr_vec[queue_idx + i] =
3213                                         msix_vect;
3214                         break;
3215                 }
3216
3217                 /* vfio 1:1 queue/msix_vect mapping */
3218                 __vsi_queues_bind_intr(vsi, msix_vect,
3219                                        vsi->base_queue + i, 1);
3220
3221                 if (!!record)
3222                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3223
3224                 msix_vect++;
3225                 nb_msix--;
3226         }
3227 }
3228
3229 void
3230 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3231 {
3232         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3233         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3235         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3236         uint16_t msix_intr, i;
3237
3238         if (rte_intr_allow_others(intr_handle))
3239                 for (i = 0; i < vsi->nb_used_qps; i++) {
3240                         msix_intr = vsi->msix_intr + i;
3241                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3242                                       GLINT_DYN_CTL_INTENA_M |
3243                                       GLINT_DYN_CTL_CLEARPBA_M |
3244                                       GLINT_DYN_CTL_ITR_INDX_M |
3245                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3246                 }
3247         else
3248                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3249                               GLINT_DYN_CTL_INTENA_M |
3250                               GLINT_DYN_CTL_CLEARPBA_M |
3251                               GLINT_DYN_CTL_ITR_INDX_M |
3252                               GLINT_DYN_CTL_WB_ON_ITR_M);
3253 }
3254
3255 static int
3256 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3257 {
3258         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3259         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3260         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3261         struct ice_vsi *vsi = pf->main_vsi;
3262         uint32_t intr_vector = 0;
3263
3264         rte_intr_disable(intr_handle);
3265
3266         /* check and configure queue intr-vector mapping */
3267         if ((rte_intr_cap_multiple(intr_handle) ||
3268              !RTE_ETH_DEV_SRIOV(dev).active) &&
3269             dev->data->dev_conf.intr_conf.rxq != 0) {
3270                 intr_vector = dev->data->nb_rx_queues;
3271                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3272                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3273                                     ICE_MAX_INTR_QUEUE_NUM);
3274                         return -ENOTSUP;
3275                 }
3276                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3277                         return -1;
3278         }
3279
3280         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3281                 intr_handle->intr_vec =
3282                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3283                             0);
3284                 if (!intr_handle->intr_vec) {
3285                         PMD_DRV_LOG(ERR,
3286                                     "Failed to allocate %d rx_queues intr_vec",
3287                                     dev->data->nb_rx_queues);
3288                         return -ENOMEM;
3289                 }
3290         }
3291
3292         /* Map queues with MSIX interrupt */
3293         vsi->nb_used_qps = dev->data->nb_rx_queues;
3294         ice_vsi_queues_bind_intr(vsi);
3295
3296         /* Enable interrupts for all the queues */
3297         ice_vsi_enable_queues_intr(vsi);
3298
3299         rte_intr_enable(intr_handle);
3300
3301         return 0;
3302 }
3303
3304 static void
3305 ice_get_init_link_status(struct rte_eth_dev *dev)
3306 {
3307         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3309         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3310         struct ice_link_status link_status;
3311         int ret;
3312
3313         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3314                                    &link_status, NULL);
3315         if (ret != ICE_SUCCESS) {
3316                 PMD_DRV_LOG(ERR, "Failed to get link info");
3317                 pf->init_link_up = false;
3318                 return;
3319         }
3320
3321         if (link_status.link_info & ICE_AQ_LINK_UP)
3322                 pf->init_link_up = true;
3323 }
3324
3325 static int
3326 ice_dev_start(struct rte_eth_dev *dev)
3327 {
3328         struct rte_eth_dev_data *data = dev->data;
3329         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3331         struct ice_vsi *vsi = pf->main_vsi;
3332         uint16_t nb_rxq = 0;
3333         uint16_t nb_txq, i;
3334         uint16_t max_frame_size;
3335         int mask, ret;
3336
3337         /* program Tx queues' context in hardware */
3338         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3339                 ret = ice_tx_queue_start(dev, nb_txq);
3340                 if (ret) {
3341                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3342                         goto tx_err;
3343                 }
3344         }
3345
3346         /* program Rx queues' context in hardware*/
3347         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3348                 ret = ice_rx_queue_start(dev, nb_rxq);
3349                 if (ret) {
3350                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3351                         goto rx_err;
3352                 }
3353         }
3354
3355         ice_set_rx_function(dev);
3356         ice_set_tx_function(dev);
3357
3358         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3359                         ETH_VLAN_EXTEND_MASK;
3360         ret = ice_vlan_offload_set(dev, mask);
3361         if (ret) {
3362                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3363                 goto rx_err;
3364         }
3365
3366         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3367         if (ice_rxq_intr_setup(dev))
3368                 return -EIO;
3369
3370         /* Enable receiving broadcast packets and transmitting packets */
3371         ret = ice_set_vsi_promisc(hw, vsi->idx,
3372                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3373                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3374                                   0);
3375         if (ret != ICE_SUCCESS)
3376                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3377
3378         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3379                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3380                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3381                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3382                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3383                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3384                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3385                                      NULL);
3386         if (ret != ICE_SUCCESS)
3387                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3388
3389         ice_get_init_link_status(dev);
3390
3391         ice_dev_set_link_up(dev);
3392
3393         /* Call get_link_info aq commond to enable/disable LSE */
3394         ice_link_update(dev, 0);
3395
3396         pf->adapter_stopped = false;
3397
3398         /* Set the max frame size to default value*/
3399         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3400                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3401                 ICE_FRAME_SIZE_MAX;
3402
3403         /* Set the max frame size to HW*/
3404         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3405
3406         return 0;
3407
3408         /* stop the started queues if failed to start all queues */
3409 rx_err:
3410         for (i = 0; i < nb_rxq; i++)
3411                 ice_rx_queue_stop(dev, i);
3412 tx_err:
3413         for (i = 0; i < nb_txq; i++)
3414                 ice_tx_queue_stop(dev, i);
3415
3416         return -EIO;
3417 }
3418
3419 static int
3420 ice_dev_reset(struct rte_eth_dev *dev)
3421 {
3422         int ret;
3423
3424         if (dev->data->sriov.active)
3425                 return -ENOTSUP;
3426
3427         ret = ice_dev_uninit(dev);
3428         if (ret) {
3429                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3430                 return -ENXIO;
3431         }
3432
3433         ret = ice_dev_init(dev);
3434         if (ret) {
3435                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3436                 return -ENXIO;
3437         }
3438
3439         return 0;
3440 }
3441
3442 static int
3443 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3444 {
3445         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447         struct ice_vsi *vsi = pf->main_vsi;
3448         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3449         bool is_safe_mode = pf->adapter->is_safe_mode;
3450         u64 phy_type_low;
3451         u64 phy_type_high;
3452
3453         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3454         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3455         dev_info->max_rx_queues = vsi->nb_qps;
3456         dev_info->max_tx_queues = vsi->nb_qps;
3457         dev_info->max_mac_addrs = vsi->max_macaddrs;
3458         dev_info->max_vfs = pci_dev->max_vfs;
3459         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3460         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3461
3462         dev_info->rx_offload_capa =
3463                 DEV_RX_OFFLOAD_VLAN_STRIP |
3464                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3465                 DEV_RX_OFFLOAD_KEEP_CRC |
3466                 DEV_RX_OFFLOAD_SCATTER |
3467                 DEV_RX_OFFLOAD_VLAN_FILTER;
3468         dev_info->tx_offload_capa =
3469                 DEV_TX_OFFLOAD_VLAN_INSERT |
3470                 DEV_TX_OFFLOAD_TCP_TSO |
3471                 DEV_TX_OFFLOAD_MULTI_SEGS |
3472                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3473         dev_info->flow_type_rss_offloads = 0;
3474
3475         if (!is_safe_mode) {
3476                 dev_info->rx_offload_capa |=
3477                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3478                         DEV_RX_OFFLOAD_UDP_CKSUM |
3479                         DEV_RX_OFFLOAD_TCP_CKSUM |
3480                         DEV_RX_OFFLOAD_QINQ_STRIP |
3481                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3482                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3483                         DEV_RX_OFFLOAD_RSS_HASH;
3484                 dev_info->tx_offload_capa |=
3485                         DEV_TX_OFFLOAD_QINQ_INSERT |
3486                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3487                         DEV_TX_OFFLOAD_UDP_CKSUM |
3488                         DEV_TX_OFFLOAD_TCP_CKSUM |
3489                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3490                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3491                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3492                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3493         }
3494
3495         dev_info->rx_queue_offload_capa = 0;
3496         dev_info->tx_queue_offload_capa = 0;
3497
3498         dev_info->reta_size = pf->hash_lut_size;
3499         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3500
3501         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3502                 .rx_thresh = {
3503                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3504                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3505                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3506                 },
3507                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3508                 .rx_drop_en = 0,
3509                 .offloads = 0,
3510         };
3511
3512         dev_info->default_txconf = (struct rte_eth_txconf) {
3513                 .tx_thresh = {
3514                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3515                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3516                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3517                 },
3518                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3519                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3520                 .offloads = 0,
3521         };
3522
3523         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3524                 .nb_max = ICE_MAX_RING_DESC,
3525                 .nb_min = ICE_MIN_RING_DESC,
3526                 .nb_align = ICE_ALIGN_RING_DESC,
3527         };
3528
3529         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3530                 .nb_max = ICE_MAX_RING_DESC,
3531                 .nb_min = ICE_MIN_RING_DESC,
3532                 .nb_align = ICE_ALIGN_RING_DESC,
3533         };
3534
3535         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3536                                ETH_LINK_SPEED_100M |
3537                                ETH_LINK_SPEED_1G |
3538                                ETH_LINK_SPEED_2_5G |
3539                                ETH_LINK_SPEED_5G |
3540                                ETH_LINK_SPEED_10G |
3541                                ETH_LINK_SPEED_20G |
3542                                ETH_LINK_SPEED_25G;
3543
3544         phy_type_low = hw->port_info->phy.phy_type_low;
3545         phy_type_high = hw->port_info->phy.phy_type_high;
3546
3547         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3548                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3549
3550         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3551                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3552                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3553
3554         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3555         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3556
3557         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3558         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3559         dev_info->default_rxportconf.nb_queues = 1;
3560         dev_info->default_txportconf.nb_queues = 1;
3561         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3562         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3563
3564         return 0;
3565 }
3566
3567 static inline int
3568 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3569                             struct rte_eth_link *link)
3570 {
3571         struct rte_eth_link *dst = link;
3572         struct rte_eth_link *src = &dev->data->dev_link;
3573
3574         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3575                                 *(uint64_t *)src) == 0)
3576                 return -1;
3577
3578         return 0;
3579 }
3580
3581 static inline int
3582 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3583                              struct rte_eth_link *link)
3584 {
3585         struct rte_eth_link *dst = &dev->data->dev_link;
3586         struct rte_eth_link *src = link;
3587
3588         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3589                                 *(uint64_t *)src) == 0)
3590                 return -1;
3591
3592         return 0;
3593 }
3594
3595 static int
3596 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3597 {
3598 #define CHECK_INTERVAL 100  /* 100ms */
3599 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3600         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         struct ice_link_status link_status;
3602         struct rte_eth_link link, old;
3603         int status;
3604         unsigned int rep_cnt = MAX_REPEAT_TIME;
3605         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3606
3607         memset(&link, 0, sizeof(link));
3608         memset(&old, 0, sizeof(old));
3609         memset(&link_status, 0, sizeof(link_status));
3610         ice_atomic_read_link_status(dev, &old);
3611
3612         do {
3613                 /* Get link status information from hardware */
3614                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3615                                               &link_status, NULL);
3616                 if (status != ICE_SUCCESS) {
3617                         link.link_speed = ETH_SPEED_NUM_100M;
3618                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3619                         PMD_DRV_LOG(ERR, "Failed to get link info");
3620                         goto out;
3621                 }
3622
3623                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3624                 if (!wait_to_complete || link.link_status)
3625                         break;
3626
3627                 rte_delay_ms(CHECK_INTERVAL);
3628         } while (--rep_cnt);
3629
3630         if (!link.link_status)
3631                 goto out;
3632
3633         /* Full-duplex operation at all supported speeds */
3634         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3635
3636         /* Parse the link status */
3637         switch (link_status.link_speed) {
3638         case ICE_AQ_LINK_SPEED_10MB:
3639                 link.link_speed = ETH_SPEED_NUM_10M;
3640                 break;
3641         case ICE_AQ_LINK_SPEED_100MB:
3642                 link.link_speed = ETH_SPEED_NUM_100M;
3643                 break;
3644         case ICE_AQ_LINK_SPEED_1000MB:
3645                 link.link_speed = ETH_SPEED_NUM_1G;
3646                 break;
3647         case ICE_AQ_LINK_SPEED_2500MB:
3648                 link.link_speed = ETH_SPEED_NUM_2_5G;
3649                 break;
3650         case ICE_AQ_LINK_SPEED_5GB:
3651                 link.link_speed = ETH_SPEED_NUM_5G;
3652                 break;
3653         case ICE_AQ_LINK_SPEED_10GB:
3654                 link.link_speed = ETH_SPEED_NUM_10G;
3655                 break;
3656         case ICE_AQ_LINK_SPEED_20GB:
3657                 link.link_speed = ETH_SPEED_NUM_20G;
3658                 break;
3659         case ICE_AQ_LINK_SPEED_25GB:
3660                 link.link_speed = ETH_SPEED_NUM_25G;
3661                 break;
3662         case ICE_AQ_LINK_SPEED_40GB:
3663                 link.link_speed = ETH_SPEED_NUM_40G;
3664                 break;
3665         case ICE_AQ_LINK_SPEED_50GB:
3666                 link.link_speed = ETH_SPEED_NUM_50G;
3667                 break;
3668         case ICE_AQ_LINK_SPEED_100GB:
3669                 link.link_speed = ETH_SPEED_NUM_100G;
3670                 break;
3671         case ICE_AQ_LINK_SPEED_UNKNOWN:
3672                 PMD_DRV_LOG(ERR, "Unknown link speed");
3673                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3674                 break;
3675         default:
3676                 PMD_DRV_LOG(ERR, "None link speed");
3677                 link.link_speed = ETH_SPEED_NUM_NONE;
3678                 break;
3679         }
3680
3681         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3682                               ETH_LINK_SPEED_FIXED);
3683
3684 out:
3685         ice_atomic_write_link_status(dev, &link);
3686         if (link.link_status == old.link_status)
3687                 return -1;
3688
3689         return 0;
3690 }
3691
3692 /* Force the physical link state by getting the current PHY capabilities from
3693  * hardware and setting the PHY config based on the determined capabilities. If
3694  * link changes, link event will be triggered because both the Enable Automatic
3695  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3696  */
3697 static enum ice_status
3698 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3699 {
3700         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3701         struct ice_aqc_get_phy_caps_data *pcaps;
3702         struct ice_port_info *pi;
3703         enum ice_status status;
3704
3705         if (!hw || !hw->port_info)
3706                 return ICE_ERR_PARAM;
3707
3708         pi = hw->port_info;
3709
3710         pcaps = (struct ice_aqc_get_phy_caps_data *)
3711                 ice_malloc(hw, sizeof(*pcaps));
3712         if (!pcaps)
3713                 return ICE_ERR_NO_MEMORY;
3714
3715         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3716                                      NULL);
3717         if (status)
3718                 goto out;
3719
3720         /* No change in link */
3721         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3722             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3723                 goto out;
3724
3725         cfg.phy_type_low = pcaps->phy_type_low;
3726         cfg.phy_type_high = pcaps->phy_type_high;
3727         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3728         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3729         cfg.eee_cap = pcaps->eee_cap;
3730         cfg.eeer_value = pcaps->eeer_value;
3731         cfg.link_fec_opt = pcaps->link_fec_options;
3732         if (link_up)
3733                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3734         else
3735                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3736
3737         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3738
3739 out:
3740         ice_free(hw, pcaps);
3741         return status;
3742 }
3743
3744 static int
3745 ice_dev_set_link_up(struct rte_eth_dev *dev)
3746 {
3747         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748
3749         return ice_force_phys_link_state(hw, true);
3750 }
3751
3752 static int
3753 ice_dev_set_link_down(struct rte_eth_dev *dev)
3754 {
3755         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756
3757         return ice_force_phys_link_state(hw, false);
3758 }
3759
3760 static int
3761 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3762 {
3763         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764         struct rte_eth_dev_data *dev_data = pf->dev_data;
3765         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3766
3767         /* check if mtu is within the allowed range */
3768         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3769                 return -EINVAL;
3770
3771         /* mtu setting is forbidden if port is start */
3772         if (dev_data->dev_started) {
3773                 PMD_DRV_LOG(ERR,
3774                             "port %d must be stopped before configuration",
3775                             dev_data->port_id);
3776                 return -EBUSY;
3777         }
3778
3779         if (frame_size > RTE_ETHER_MAX_LEN)
3780                 dev_data->dev_conf.rxmode.offloads |=
3781                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3782         else
3783                 dev_data->dev_conf.rxmode.offloads &=
3784                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3785
3786         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3787
3788         return 0;
3789 }
3790
3791 static int ice_macaddr_set(struct rte_eth_dev *dev,
3792                            struct rte_ether_addr *mac_addr)
3793 {
3794         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3796         struct ice_vsi *vsi = pf->main_vsi;
3797         struct ice_mac_filter *f;
3798         uint8_t flags = 0;
3799         int ret;
3800
3801         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3802                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3803                 return -EINVAL;
3804         }
3805
3806         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3807                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3808                         break;
3809         }
3810
3811         if (!f) {
3812                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3813                 return -EIO;
3814         }
3815
3816         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3817         if (ret != ICE_SUCCESS) {
3818                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3819                 return -EIO;
3820         }
3821         ret = ice_add_mac_filter(vsi, mac_addr);
3822         if (ret != ICE_SUCCESS) {
3823                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3824                 return -EIO;
3825         }
3826         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3827
3828         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3829         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3830         if (ret != ICE_SUCCESS)
3831                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3832
3833         return 0;
3834 }
3835
3836 /* Add a MAC address, and update filters */
3837 static int
3838 ice_macaddr_add(struct rte_eth_dev *dev,
3839                 struct rte_ether_addr *mac_addr,
3840                 __rte_unused uint32_t index,
3841                 __rte_unused uint32_t pool)
3842 {
3843         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3844         struct ice_vsi *vsi = pf->main_vsi;
3845         int ret;
3846
3847         ret = ice_add_mac_filter(vsi, mac_addr);
3848         if (ret != ICE_SUCCESS) {
3849                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3850                 return -EINVAL;
3851         }
3852
3853         return ICE_SUCCESS;
3854 }
3855
3856 /* Remove a MAC address, and update filters */
3857 static void
3858 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3859 {
3860         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3861         struct ice_vsi *vsi = pf->main_vsi;
3862         struct rte_eth_dev_data *data = dev->data;
3863         struct rte_ether_addr *macaddr;
3864         int ret;
3865
3866         macaddr = &data->mac_addrs[index];
3867         ret = ice_remove_mac_filter(vsi, macaddr);
3868         if (ret) {
3869                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3870                 return;
3871         }
3872 }
3873
3874 static int
3875 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3876 {
3877         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3878         struct ice_vsi *vsi = pf->main_vsi;
3879         int ret;
3880
3881         PMD_INIT_FUNC_TRACE();
3882
3883         if (on) {
3884                 ret = ice_add_vlan_filter(vsi, vlan_id);
3885                 if (ret < 0) {
3886                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3887                         return -EINVAL;
3888                 }
3889         } else {
3890                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3891                 if (ret < 0) {
3892                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3893                         return -EINVAL;
3894                 }
3895         }
3896
3897         return 0;
3898 }
3899
3900 /* Configure vlan filter on or off */
3901 static int
3902 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3903 {
3904         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3905         struct ice_vsi_ctx ctxt;
3906         uint8_t sec_flags, sw_flags2;
3907         int ret = 0;
3908
3909         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3910                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3911         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3912
3913         if (on) {
3914                 vsi->info.sec_flags |= sec_flags;
3915                 vsi->info.sw_flags2 |= sw_flags2;
3916         } else {
3917                 vsi->info.sec_flags &= ~sec_flags;
3918                 vsi->info.sw_flags2 &= ~sw_flags2;
3919         }
3920         vsi->info.sw_id = hw->port_info->sw_id;
3921         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3922         ctxt.info.valid_sections =
3923                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3924                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3925         ctxt.vsi_num = vsi->vsi_id;
3926
3927         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3928         if (ret) {
3929                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3930                             on ? "enable" : "disable");
3931                 return -EINVAL;
3932         } else {
3933                 vsi->info.valid_sections |=
3934                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3935                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3936         }
3937
3938         /* consist with other drivers, allow untagged packet when vlan filter on */
3939         if (on)
3940                 ret = ice_add_vlan_filter(vsi, 0);
3941         else
3942                 ret = ice_remove_vlan_filter(vsi, 0);
3943
3944         return 0;
3945 }
3946
3947 static int
3948 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3949 {
3950         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3951         struct ice_vsi_ctx ctxt;
3952         uint8_t vlan_flags;
3953         int ret = 0;
3954
3955         /* Check if it has been already on or off */
3956         if (vsi->info.valid_sections &
3957                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3958                 if (on) {
3959                         if ((vsi->info.vlan_flags &
3960                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3961                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3962                                 return 0; /* already on */
3963                 } else {
3964                         if ((vsi->info.vlan_flags &
3965                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3966                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3967                                 return 0; /* already off */
3968                 }
3969         }
3970
3971         if (on)
3972                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3973         else
3974                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3975         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3976         vsi->info.vlan_flags |= vlan_flags;
3977         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3978         ctxt.info.valid_sections =
3979                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3980         ctxt.vsi_num = vsi->vsi_id;
3981         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3982         if (ret) {
3983                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3984                             on ? "enable" : "disable");
3985                 return -EINVAL;
3986         }
3987
3988         vsi->info.valid_sections |=
3989                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3990
3991         return ret;
3992 }
3993
3994 static int
3995 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3996 {
3997         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3998         struct ice_vsi *vsi = pf->main_vsi;
3999         struct rte_eth_rxmode *rxmode;
4000
4001         rxmode = &dev->data->dev_conf.rxmode;
4002         if (mask & ETH_VLAN_FILTER_MASK) {
4003                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4004                         ice_vsi_config_vlan_filter(vsi, true);
4005                 else
4006                         ice_vsi_config_vlan_filter(vsi, false);
4007         }
4008
4009         if (mask & ETH_VLAN_STRIP_MASK) {
4010                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4011                         ice_vsi_config_vlan_stripping(vsi, true);
4012                 else
4013                         ice_vsi_config_vlan_stripping(vsi, false);
4014         }
4015
4016         if (mask & ETH_VLAN_EXTEND_MASK) {
4017                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
4018                         ice_vsi_config_double_vlan(vsi, true);
4019                 else
4020                         ice_vsi_config_double_vlan(vsi, false);
4021         }
4022
4023         return 0;
4024 }
4025
4026 static int
4027 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4028 {
4029         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4030         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4031         int ret;
4032
4033         if (!lut)
4034                 return -EINVAL;
4035
4036         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4037                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
4038                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4039                 if (ret) {
4040                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4041                         return -EINVAL;
4042                 }
4043         } else {
4044                 uint64_t *lut_dw = (uint64_t *)lut;
4045                 uint16_t i, lut_size_dw = lut_size / 4;
4046
4047                 for (i = 0; i < lut_size_dw; i++)
4048                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4049         }
4050
4051         return 0;
4052 }
4053
4054 static int
4055 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4056 {
4057         struct ice_pf *pf;
4058         struct ice_hw *hw;
4059         int ret;
4060
4061         if (!vsi || !lut)
4062                 return -EINVAL;
4063
4064         pf = ICE_VSI_TO_PF(vsi);
4065         hw = ICE_VSI_TO_HW(vsi);
4066
4067         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4068                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
4069                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4070                 if (ret) {
4071                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4072                         return -EINVAL;
4073                 }
4074         } else {
4075                 uint64_t *lut_dw = (uint64_t *)lut;
4076                 uint16_t i, lut_size_dw = lut_size / 4;
4077
4078                 for (i = 0; i < lut_size_dw; i++)
4079                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4080
4081                 ice_flush(hw);
4082         }
4083
4084         return 0;
4085 }
4086
4087 static int
4088 ice_rss_reta_update(struct rte_eth_dev *dev,
4089                     struct rte_eth_rss_reta_entry64 *reta_conf,
4090                     uint16_t reta_size)
4091 {
4092         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4093         uint16_t i, lut_size = pf->hash_lut_size;
4094         uint16_t idx, shift;
4095         uint8_t *lut;
4096         int ret;
4097
4098         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4099             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4100             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4101                 PMD_DRV_LOG(ERR,
4102                             "The size of hash lookup table configured (%d)"
4103                             "doesn't match the number hardware can "
4104                             "supported (128, 512, 2048)",
4105                             reta_size);
4106                 return -EINVAL;
4107         }
4108
4109         /* It MUST use the current LUT size to get the RSS lookup table,
4110          * otherwise if will fail with -100 error code.
4111          */
4112         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4113         if (!lut) {
4114                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4115                 return -ENOMEM;
4116         }
4117         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4118         if (ret)
4119                 goto out;
4120
4121         for (i = 0; i < reta_size; i++) {
4122                 idx = i / RTE_RETA_GROUP_SIZE;
4123                 shift = i % RTE_RETA_GROUP_SIZE;
4124                 if (reta_conf[idx].mask & (1ULL << shift))
4125                         lut[i] = reta_conf[idx].reta[shift];
4126         }
4127         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4128         if (ret == 0 && lut_size != reta_size) {
4129                 PMD_DRV_LOG(INFO,
4130                             "The size of hash lookup table is changed from (%d) to (%d)",
4131                             lut_size, reta_size);
4132                 pf->hash_lut_size = reta_size;
4133         }
4134
4135 out:
4136         rte_free(lut);
4137
4138         return ret;
4139 }
4140
4141 static int
4142 ice_rss_reta_query(struct rte_eth_dev *dev,
4143                    struct rte_eth_rss_reta_entry64 *reta_conf,
4144                    uint16_t reta_size)
4145 {
4146         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4147         uint16_t i, lut_size = pf->hash_lut_size;
4148         uint16_t idx, shift;
4149         uint8_t *lut;
4150         int ret;
4151
4152         if (reta_size != lut_size) {
4153                 PMD_DRV_LOG(ERR,
4154                             "The size of hash lookup table configured (%d)"
4155                             "doesn't match the number hardware can "
4156                             "supported (%d)",
4157                             reta_size, lut_size);
4158                 return -EINVAL;
4159         }
4160
4161         lut = rte_zmalloc(NULL, reta_size, 0);
4162         if (!lut) {
4163                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4164                 return -ENOMEM;
4165         }
4166
4167         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4168         if (ret)
4169                 goto out;
4170
4171         for (i = 0; i < reta_size; i++) {
4172                 idx = i / RTE_RETA_GROUP_SIZE;
4173                 shift = i % RTE_RETA_GROUP_SIZE;
4174                 if (reta_conf[idx].mask & (1ULL << shift))
4175                         reta_conf[idx].reta[shift] = lut[i];
4176         }
4177
4178 out:
4179         rte_free(lut);
4180
4181         return ret;
4182 }
4183
4184 static int
4185 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4186 {
4187         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4188         int ret = 0;
4189
4190         if (!key || key_len == 0) {
4191                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4192                 return 0;
4193         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4194                    sizeof(uint32_t)) {
4195                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4196                 return -EINVAL;
4197         }
4198
4199         struct ice_aqc_get_set_rss_keys *key_dw =
4200                 (struct ice_aqc_get_set_rss_keys *)key;
4201
4202         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4203         if (ret) {
4204                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4205                 ret = -EINVAL;
4206         }
4207
4208         return ret;
4209 }
4210
4211 static int
4212 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4213 {
4214         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4215         int ret;
4216
4217         if (!key || !key_len)
4218                 return -EINVAL;
4219
4220         ret = ice_aq_get_rss_key
4221                 (hw, vsi->idx,
4222                  (struct ice_aqc_get_set_rss_keys *)key);
4223         if (ret) {
4224                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4225                 return -EINVAL;
4226         }
4227         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4228
4229         return 0;
4230 }
4231
4232 static int
4233 ice_rss_hash_update(struct rte_eth_dev *dev,
4234                     struct rte_eth_rss_conf *rss_conf)
4235 {
4236         enum ice_status status = ICE_SUCCESS;
4237         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4238         struct ice_vsi *vsi = pf->main_vsi;
4239
4240         /* set hash key */
4241         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4242         if (status)
4243                 return status;
4244
4245         if (rss_conf->rss_hf == 0)
4246                 return 0;
4247
4248         /* RSS hash configuration */
4249         ice_rss_hash_set(pf, rss_conf->rss_hf);
4250
4251         return 0;
4252 }
4253
4254 static int
4255 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4256                       struct rte_eth_rss_conf *rss_conf)
4257 {
4258         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4259         struct ice_vsi *vsi = pf->main_vsi;
4260
4261         ice_get_rss_key(vsi, rss_conf->rss_key,
4262                         &rss_conf->rss_key_len);
4263
4264         /* TODO: default set to 0 as hf config is not supported now */
4265         rss_conf->rss_hf = 0;
4266         return 0;
4267 }
4268
4269 static int
4270 ice_promisc_enable(struct rte_eth_dev *dev)
4271 {
4272         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4273         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274         struct ice_vsi *vsi = pf->main_vsi;
4275         enum ice_status status;
4276         uint8_t pmask;
4277         int ret = 0;
4278
4279         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4280                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4281
4282         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4283         switch (status) {
4284         case ICE_ERR_ALREADY_EXISTS:
4285                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4286         case ICE_SUCCESS:
4287                 break;
4288         default:
4289                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4290                 ret = -EAGAIN;
4291         }
4292
4293         return ret;
4294 }
4295
4296 static int
4297 ice_promisc_disable(struct rte_eth_dev *dev)
4298 {
4299         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4300         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4301         struct ice_vsi *vsi = pf->main_vsi;
4302         enum ice_status status;
4303         uint8_t pmask;
4304         int ret = 0;
4305
4306         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4307                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4308
4309         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4310         if (status != ICE_SUCCESS) {
4311                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4312                 ret = -EAGAIN;
4313         }
4314
4315         return ret;
4316 }
4317
4318 static int
4319 ice_allmulti_enable(struct rte_eth_dev *dev)
4320 {
4321         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4322         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4323         struct ice_vsi *vsi = pf->main_vsi;
4324         enum ice_status status;
4325         uint8_t pmask;
4326         int ret = 0;
4327
4328         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4329
4330         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4331
4332         switch (status) {
4333         case ICE_ERR_ALREADY_EXISTS:
4334                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4335         case ICE_SUCCESS:
4336                 break;
4337         default:
4338                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4339                 ret = -EAGAIN;
4340         }
4341
4342         return ret;
4343 }
4344
4345 static int
4346 ice_allmulti_disable(struct rte_eth_dev *dev)
4347 {
4348         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4349         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350         struct ice_vsi *vsi = pf->main_vsi;
4351         enum ice_status status;
4352         uint8_t pmask;
4353         int ret = 0;
4354
4355         if (dev->data->promiscuous == 1)
4356                 return 0; /* must remain in all_multicast mode */
4357
4358         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4359
4360         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4361         if (status != ICE_SUCCESS) {
4362                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4363                 ret = -EAGAIN;
4364         }
4365
4366         return ret;
4367 }
4368
4369 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4370                                     uint16_t queue_id)
4371 {
4372         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4373         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4374         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375         uint32_t val;
4376         uint16_t msix_intr;
4377
4378         msix_intr = intr_handle->intr_vec[queue_id];
4379
4380         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4381               GLINT_DYN_CTL_ITR_INDX_M;
4382         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4383
4384         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4385         rte_intr_ack(&pci_dev->intr_handle);
4386
4387         return 0;
4388 }
4389
4390 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4391                                      uint16_t queue_id)
4392 {
4393         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4394         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4395         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4396         uint16_t msix_intr;
4397
4398         msix_intr = intr_handle->intr_vec[queue_id];
4399
4400         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4401
4402         return 0;
4403 }
4404
4405 static int
4406 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4407 {
4408         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409         u8 ver, patch;
4410         u16 build;
4411         int ret;
4412
4413         ver = hw->nvm.orom.major;
4414         patch = hw->nvm.orom.patch;
4415         build = hw->nvm.orom.build;
4416
4417         ret = snprintf(fw_version, fw_size,
4418                         "%d.%d 0x%08x %d.%d.%d",
4419                         hw->nvm.major_ver,
4420                         hw->nvm.minor_ver,
4421                         hw->nvm.eetrack,
4422                         ver, build, patch);
4423
4424         /* add the size of '\0' */
4425         ret += 1;
4426         if (fw_size < (u32)ret)
4427                 return ret;
4428         else
4429                 return 0;
4430 }
4431
4432 static int
4433 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4434 {
4435         struct ice_hw *hw;
4436         struct ice_vsi_ctx ctxt;
4437         uint8_t vlan_flags = 0;
4438         int ret;
4439
4440         if (!vsi || !info) {
4441                 PMD_DRV_LOG(ERR, "invalid parameters");
4442                 return -EINVAL;
4443         }
4444
4445         if (info->on) {
4446                 vsi->info.pvid = info->config.pvid;
4447                 /**
4448                  * If insert pvid is enabled, only tagged pkts are
4449                  * allowed to be sent out.
4450                  */
4451                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
4452                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4453         } else {
4454                 vsi->info.pvid = 0;
4455                 if (info->config.reject.tagged == 0)
4456                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
4457
4458                 if (info->config.reject.untagged == 0)
4459                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4460         }
4461         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
4462                                   ICE_AQ_VSI_VLAN_MODE_M);
4463         vsi->info.vlan_flags |= vlan_flags;
4464         memset(&ctxt, 0, sizeof(ctxt));
4465         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4466         ctxt.info.valid_sections =
4467                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4468         ctxt.vsi_num = vsi->vsi_id;
4469
4470         hw = ICE_VSI_TO_HW(vsi);
4471         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4472         if (ret != ICE_SUCCESS) {
4473                 PMD_DRV_LOG(ERR,
4474                             "update VSI for VLAN insert failed, err %d",
4475                             ret);
4476                 return -EINVAL;
4477         }
4478
4479         vsi->info.valid_sections |=
4480                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4481
4482         return ret;
4483 }
4484
4485 static int
4486 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4487 {
4488         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4489         struct ice_vsi *vsi = pf->main_vsi;
4490         struct rte_eth_dev_data *data = pf->dev_data;
4491         struct ice_vsi_vlan_pvid_info info;
4492         int ret;
4493
4494         memset(&info, 0, sizeof(info));
4495         info.on = on;
4496         if (info.on) {
4497                 info.config.pvid = pvid;
4498         } else {
4499                 info.config.reject.tagged =
4500                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4501                 info.config.reject.untagged =
4502                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4503         }
4504
4505         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4506         if (ret < 0) {
4507                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4508                 return -EINVAL;
4509         }
4510
4511         return 0;
4512 }
4513
4514 static int
4515 ice_get_eeprom_length(struct rte_eth_dev *dev)
4516 {
4517         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4518
4519         return hw->nvm.flash_size;
4520 }
4521
4522 static int
4523 ice_get_eeprom(struct rte_eth_dev *dev,
4524                struct rte_dev_eeprom_info *eeprom)
4525 {
4526         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         enum ice_status status = ICE_SUCCESS;
4528         uint8_t *data = eeprom->data;
4529
4530         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4531
4532         status = ice_acquire_nvm(hw, ICE_RES_READ);
4533         if (status) {
4534                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4535                 return -EIO;
4536         }
4537
4538         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4539                                    data, false);
4540
4541         ice_release_nvm(hw);
4542
4543         if (status) {
4544                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4545                 return -EIO;
4546         }
4547
4548         return 0;
4549 }
4550
4551 static void
4552 ice_stat_update_32(struct ice_hw *hw,
4553                    uint32_t reg,
4554                    bool offset_loaded,
4555                    uint64_t *offset,
4556                    uint64_t *stat)
4557 {
4558         uint64_t new_data;
4559
4560         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4561         if (!offset_loaded)
4562                 *offset = new_data;
4563
4564         if (new_data >= *offset)
4565                 *stat = (uint64_t)(new_data - *offset);
4566         else
4567                 *stat = (uint64_t)((new_data +
4568                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4569                                    - *offset);
4570 }
4571
4572 static void
4573 ice_stat_update_40(struct ice_hw *hw,
4574                    uint32_t hireg,
4575                    uint32_t loreg,
4576                    bool offset_loaded,
4577                    uint64_t *offset,
4578                    uint64_t *stat)
4579 {
4580         uint64_t new_data;
4581
4582         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4583         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4584                     ICE_32_BIT_WIDTH;
4585
4586         if (!offset_loaded)
4587                 *offset = new_data;
4588
4589         if (new_data >= *offset)
4590                 *stat = new_data - *offset;
4591         else
4592                 *stat = (uint64_t)((new_data +
4593                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4594                                    *offset);
4595
4596         *stat &= ICE_40_BIT_MASK;
4597 }
4598
4599 /* Get all the statistics of a VSI */
4600 static void
4601 ice_update_vsi_stats(struct ice_vsi *vsi)
4602 {
4603         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4604         struct ice_eth_stats *nes = &vsi->eth_stats;
4605         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4606         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4607
4608         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4609                            vsi->offset_loaded, &oes->rx_bytes,
4610                            &nes->rx_bytes);
4611         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4612                            vsi->offset_loaded, &oes->rx_unicast,
4613                            &nes->rx_unicast);
4614         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4615                            vsi->offset_loaded, &oes->rx_multicast,
4616                            &nes->rx_multicast);
4617         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4618                            vsi->offset_loaded, &oes->rx_broadcast,
4619                            &nes->rx_broadcast);
4620         /* enlarge the limitation when rx_bytes overflowed */
4621         if (vsi->offset_loaded) {
4622                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4623                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4624                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4625         }
4626         vsi->old_rx_bytes = nes->rx_bytes;
4627         /* exclude CRC bytes */
4628         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4629                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4630
4631         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4632                            &oes->rx_discards, &nes->rx_discards);
4633         /* GLV_REPC not supported */
4634         /* GLV_RMPC not supported */
4635         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4636                            &oes->rx_unknown_protocol,
4637                            &nes->rx_unknown_protocol);
4638         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4639                            vsi->offset_loaded, &oes->tx_bytes,
4640                            &nes->tx_bytes);
4641         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4642                            vsi->offset_loaded, &oes->tx_unicast,
4643                            &nes->tx_unicast);
4644         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4645                            vsi->offset_loaded, &oes->tx_multicast,
4646                            &nes->tx_multicast);
4647         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4648                            vsi->offset_loaded,  &oes->tx_broadcast,
4649                            &nes->tx_broadcast);
4650         /* GLV_TDPC not supported */
4651         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4652                            &oes->tx_errors, &nes->tx_errors);
4653         /* enlarge the limitation when tx_bytes overflowed */
4654         if (vsi->offset_loaded) {
4655                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4656                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4657                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4658         }
4659         vsi->old_tx_bytes = nes->tx_bytes;
4660         vsi->offset_loaded = true;
4661
4662         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4663                     vsi->vsi_id);
4664         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4665         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4666         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4667         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4668         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4669         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4670                     nes->rx_unknown_protocol);
4671         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4672         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4673         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4674         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4675         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4676         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4677         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4678                     vsi->vsi_id);
4679 }
4680
4681 static void
4682 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4683 {
4684         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4685         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4686
4687         /* Get statistics of struct ice_eth_stats */
4688         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4689                            GLPRT_GORCL(hw->port_info->lport),
4690                            pf->offset_loaded, &os->eth.rx_bytes,
4691                            &ns->eth.rx_bytes);
4692         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4693                            GLPRT_UPRCL(hw->port_info->lport),
4694                            pf->offset_loaded, &os->eth.rx_unicast,
4695                            &ns->eth.rx_unicast);
4696         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4697                            GLPRT_MPRCL(hw->port_info->lport),
4698                            pf->offset_loaded, &os->eth.rx_multicast,
4699                            &ns->eth.rx_multicast);
4700         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4701                            GLPRT_BPRCL(hw->port_info->lport),
4702                            pf->offset_loaded, &os->eth.rx_broadcast,
4703                            &ns->eth.rx_broadcast);
4704         ice_stat_update_32(hw, PRTRPB_RDPC,
4705                            pf->offset_loaded, &os->eth.rx_discards,
4706                            &ns->eth.rx_discards);
4707         /* enlarge the limitation when rx_bytes overflowed */
4708         if (pf->offset_loaded) {
4709                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4710                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4711                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4712         }
4713         pf->old_rx_bytes = ns->eth.rx_bytes;
4714
4715         /* Workaround: CRC size should not be included in byte statistics,
4716          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4717          * packet.
4718          */
4719         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4720                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4721
4722         /* GLPRT_REPC not supported */
4723         /* GLPRT_RMPC not supported */
4724         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4725                            pf->offset_loaded,
4726                            &os->eth.rx_unknown_protocol,
4727                            &ns->eth.rx_unknown_protocol);
4728         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4729                            GLPRT_GOTCL(hw->port_info->lport),
4730                            pf->offset_loaded, &os->eth.tx_bytes,
4731                            &ns->eth.tx_bytes);
4732         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4733                            GLPRT_UPTCL(hw->port_info->lport),
4734                            pf->offset_loaded, &os->eth.tx_unicast,
4735                            &ns->eth.tx_unicast);
4736         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4737                            GLPRT_MPTCL(hw->port_info->lport),
4738                            pf->offset_loaded, &os->eth.tx_multicast,
4739                            &ns->eth.tx_multicast);
4740         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4741                            GLPRT_BPTCL(hw->port_info->lport),
4742                            pf->offset_loaded, &os->eth.tx_broadcast,
4743                            &ns->eth.tx_broadcast);
4744         /* enlarge the limitation when tx_bytes overflowed */
4745         if (pf->offset_loaded) {
4746                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4747                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4748                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4749         }
4750         pf->old_tx_bytes = ns->eth.tx_bytes;
4751         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4752                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4753
4754         /* GLPRT_TEPC not supported */
4755
4756         /* additional port specific stats */
4757         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4758                            pf->offset_loaded, &os->tx_dropped_link_down,
4759                            &ns->tx_dropped_link_down);
4760         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4761                            pf->offset_loaded, &os->crc_errors,
4762                            &ns->crc_errors);
4763         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4764                            pf->offset_loaded, &os->illegal_bytes,
4765                            &ns->illegal_bytes);
4766         /* GLPRT_ERRBC not supported */
4767         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4768                            pf->offset_loaded, &os->mac_local_faults,
4769                            &ns->mac_local_faults);
4770         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4771                            pf->offset_loaded, &os->mac_remote_faults,
4772                            &ns->mac_remote_faults);
4773
4774         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4775                            pf->offset_loaded, &os->rx_len_errors,
4776                            &ns->rx_len_errors);
4777
4778         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4779                            pf->offset_loaded, &os->link_xon_rx,
4780                            &ns->link_xon_rx);
4781         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4782                            pf->offset_loaded, &os->link_xoff_rx,
4783                            &ns->link_xoff_rx);
4784         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4785                            pf->offset_loaded, &os->link_xon_tx,
4786                            &ns->link_xon_tx);
4787         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4788                            pf->offset_loaded, &os->link_xoff_tx,
4789                            &ns->link_xoff_tx);
4790         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4791                            GLPRT_PRC64L(hw->port_info->lport),
4792                            pf->offset_loaded, &os->rx_size_64,
4793                            &ns->rx_size_64);
4794         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4795                            GLPRT_PRC127L(hw->port_info->lport),
4796                            pf->offset_loaded, &os->rx_size_127,
4797                            &ns->rx_size_127);
4798         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4799                            GLPRT_PRC255L(hw->port_info->lport),
4800                            pf->offset_loaded, &os->rx_size_255,
4801                            &ns->rx_size_255);
4802         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4803                            GLPRT_PRC511L(hw->port_info->lport),
4804                            pf->offset_loaded, &os->rx_size_511,
4805                            &ns->rx_size_511);
4806         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4807                            GLPRT_PRC1023L(hw->port_info->lport),
4808                            pf->offset_loaded, &os->rx_size_1023,
4809                            &ns->rx_size_1023);
4810         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4811                            GLPRT_PRC1522L(hw->port_info->lport),
4812                            pf->offset_loaded, &os->rx_size_1522,
4813                            &ns->rx_size_1522);
4814         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4815                            GLPRT_PRC9522L(hw->port_info->lport),
4816                            pf->offset_loaded, &os->rx_size_big,
4817                            &ns->rx_size_big);
4818         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4819                            pf->offset_loaded, &os->rx_undersize,
4820                            &ns->rx_undersize);
4821         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4822                            pf->offset_loaded, &os->rx_fragments,
4823                            &ns->rx_fragments);
4824         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4825                            pf->offset_loaded, &os->rx_oversize,
4826                            &ns->rx_oversize);
4827         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4828                            pf->offset_loaded, &os->rx_jabber,
4829                            &ns->rx_jabber);
4830         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4831                            GLPRT_PTC64L(hw->port_info->lport),
4832                            pf->offset_loaded, &os->tx_size_64,
4833                            &ns->tx_size_64);
4834         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4835                            GLPRT_PTC127L(hw->port_info->lport),
4836                            pf->offset_loaded, &os->tx_size_127,
4837                            &ns->tx_size_127);
4838         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4839                            GLPRT_PTC255L(hw->port_info->lport),
4840                            pf->offset_loaded, &os->tx_size_255,
4841                            &ns->tx_size_255);
4842         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4843                            GLPRT_PTC511L(hw->port_info->lport),
4844                            pf->offset_loaded, &os->tx_size_511,
4845                            &ns->tx_size_511);
4846         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4847                            GLPRT_PTC1023L(hw->port_info->lport),
4848                            pf->offset_loaded, &os->tx_size_1023,
4849                            &ns->tx_size_1023);
4850         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4851                            GLPRT_PTC1522L(hw->port_info->lport),
4852                            pf->offset_loaded, &os->tx_size_1522,
4853                            &ns->tx_size_1522);
4854         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4855                            GLPRT_PTC9522L(hw->port_info->lport),
4856                            pf->offset_loaded, &os->tx_size_big,
4857                            &ns->tx_size_big);
4858
4859         /* GLPRT_MSPDC not supported */
4860         /* GLPRT_XEC not supported */
4861
4862         pf->offset_loaded = true;
4863
4864         if (pf->main_vsi)
4865                 ice_update_vsi_stats(pf->main_vsi);
4866 }
4867
4868 /* Get all statistics of a port */
4869 static int
4870 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4871 {
4872         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4873         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4874         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4875
4876         /* call read registers - updates values, now write them to struct */
4877         ice_read_stats_registers(pf, hw);
4878
4879         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4880                           pf->main_vsi->eth_stats.rx_multicast +
4881                           pf->main_vsi->eth_stats.rx_broadcast -
4882                           pf->main_vsi->eth_stats.rx_discards;
4883         stats->opackets = ns->eth.tx_unicast +
4884                           ns->eth.tx_multicast +
4885                           ns->eth.tx_broadcast;
4886         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4887         stats->obytes   = ns->eth.tx_bytes;
4888         stats->oerrors  = ns->eth.tx_errors +
4889                           pf->main_vsi->eth_stats.tx_errors;
4890
4891         /* Rx Errors */
4892         stats->imissed  = ns->eth.rx_discards +
4893                           pf->main_vsi->eth_stats.rx_discards;
4894         stats->ierrors  = ns->crc_errors +
4895                           ns->rx_undersize +
4896                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4897
4898         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4899         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4900         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4901         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4902         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4903         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4904         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4905                     pf->main_vsi->eth_stats.rx_discards);
4906         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4907                     ns->eth.rx_unknown_protocol);
4908         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4909         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4910         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4911         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4912         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4913         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4914                     pf->main_vsi->eth_stats.tx_discards);
4915         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4916
4917         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4918                     ns->tx_dropped_link_down);
4919         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4920         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4921                     ns->illegal_bytes);
4922         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4923         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4924                     ns->mac_local_faults);
4925         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4926                     ns->mac_remote_faults);
4927         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4928         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4929         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4930         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4931         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4932         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4933         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4934         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4935         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4936         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4937         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4938         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4939         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4940         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4941         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4942         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4943         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4944         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4945         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4946         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4947         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4948         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4949         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4950         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4951         return 0;
4952 }
4953
4954 /* Reset the statistics */
4955 static int
4956 ice_stats_reset(struct rte_eth_dev *dev)
4957 {
4958         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4959         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4960
4961         /* Mark PF and VSI stats to update the offset, aka "reset" */
4962         pf->offset_loaded = false;
4963         if (pf->main_vsi)
4964                 pf->main_vsi->offset_loaded = false;
4965
4966         /* read the stats, reading current register values into offset */
4967         ice_read_stats_registers(pf, hw);
4968
4969         return 0;
4970 }
4971
4972 static uint32_t
4973 ice_xstats_calc_num(void)
4974 {
4975         uint32_t num;
4976
4977         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4978
4979         return num;
4980 }
4981
4982 static int
4983 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4984                unsigned int n)
4985 {
4986         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4987         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4988         unsigned int i;
4989         unsigned int count;
4990         struct ice_hw_port_stats *hw_stats = &pf->stats;
4991
4992         count = ice_xstats_calc_num();
4993         if (n < count)
4994                 return count;
4995
4996         ice_read_stats_registers(pf, hw);
4997
4998         if (!xstats)
4999                 return 0;
5000
5001         count = 0;
5002
5003         /* Get stats from ice_eth_stats struct */
5004         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5005                 xstats[count].value =
5006                         *(uint64_t *)((char *)&hw_stats->eth +
5007                                       ice_stats_strings[i].offset);
5008                 xstats[count].id = count;
5009                 count++;
5010         }
5011
5012         /* Get individiual stats from ice_hw_port struct */
5013         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5014                 xstats[count].value =
5015                         *(uint64_t *)((char *)hw_stats +
5016                                       ice_hw_port_strings[i].offset);
5017                 xstats[count].id = count;
5018                 count++;
5019         }
5020
5021         return count;
5022 }
5023
5024 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5025                                 struct rte_eth_xstat_name *xstats_names,
5026                                 __rte_unused unsigned int limit)
5027 {
5028         unsigned int count = 0;
5029         unsigned int i;
5030
5031         if (!xstats_names)
5032                 return ice_xstats_calc_num();
5033
5034         /* Note: limit checked in rte_eth_xstats_names() */
5035
5036         /* Get stats from ice_eth_stats struct */
5037         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5038                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5039                         sizeof(xstats_names[count].name));
5040                 count++;
5041         }
5042
5043         /* Get individiual stats from ice_hw_port struct */
5044         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5045                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5046                         sizeof(xstats_names[count].name));
5047                 count++;
5048         }
5049
5050         return count;
5051 }
5052
5053 static int
5054 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5055                      enum rte_filter_type filter_type,
5056                      enum rte_filter_op filter_op,
5057                      void *arg)
5058 {
5059         int ret = 0;
5060
5061         if (!dev)
5062                 return -EINVAL;
5063
5064         switch (filter_type) {
5065         case RTE_ETH_FILTER_GENERIC:
5066                 if (filter_op != RTE_ETH_FILTER_GET)
5067                         return -EINVAL;
5068                 *(const void **)arg = &ice_flow_ops;
5069                 break;
5070         default:
5071                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5072                                         filter_type);
5073                 ret = -EINVAL;
5074                 break;
5075         }
5076
5077         return ret;
5078 }
5079
5080 /* Add UDP tunneling port */
5081 static int
5082 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5083                              struct rte_eth_udp_tunnel *udp_tunnel)
5084 {
5085         int ret = 0;
5086         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087
5088         if (udp_tunnel == NULL)
5089                 return -EINVAL;
5090
5091         switch (udp_tunnel->prot_type) {
5092         case RTE_TUNNEL_TYPE_VXLAN:
5093                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5094                 break;
5095         default:
5096                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5097                 ret = -EINVAL;
5098                 break;
5099         }
5100
5101         return ret;
5102 }
5103
5104 /* Delete UDP tunneling port */
5105 static int
5106 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5107                              struct rte_eth_udp_tunnel *udp_tunnel)
5108 {
5109         int ret = 0;
5110         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111
5112         if (udp_tunnel == NULL)
5113                 return -EINVAL;
5114
5115         switch (udp_tunnel->prot_type) {
5116         case RTE_TUNNEL_TYPE_VXLAN:
5117                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5118                 break;
5119         default:
5120                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5121                 ret = -EINVAL;
5122                 break;
5123         }
5124
5125         return ret;
5126 }
5127
5128 static int
5129 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5130               struct rte_pci_device *pci_dev)
5131 {
5132         return rte_eth_dev_pci_generic_probe(pci_dev,
5133                                              sizeof(struct ice_adapter),
5134                                              ice_dev_init);
5135 }
5136
5137 static int
5138 ice_pci_remove(struct rte_pci_device *pci_dev)
5139 {
5140         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5141 }
5142
5143 static struct rte_pci_driver rte_ice_pmd = {
5144         .id_table = pci_id_ice_map,
5145         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5146         .probe = ice_pci_probe,
5147         .remove = ice_pci_remove,
5148 };
5149
5150 /**
5151  * Driver initialization routine.
5152  * Invoked once at EAL init time.
5153  * Register itself as the [Poll Mode] Driver of PCI devices.
5154  */
5155 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5156 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5157 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5158 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5159                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5160                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5161                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
5162                               ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
5163
5164 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5165 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5166 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5167 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5168 #endif
5169 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5170 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5171 #endif
5172 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5173 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5174 #endif