drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include <rte_tailq.h>
  14
  15 #include "eal_firmware.h"
  16
  17 #include "base/ice_sched.h"
  18 #include "base/ice_flow.h"
  19 #include "base/ice_dcb.h"
  20 #include "base/ice_common.h"
  21
  22 #include "rte_pmd_ice.h"
  23 #include "ice_ethdev.h"
  24 #include "ice_rxtx.h"
  25 #include "ice_generic_flow.h"
  26
  27 /* devargs */
  28 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  29 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  30 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  31 #define ICE_HW_DEBUG_MASK_ARG     "hw_debug_mask"
  32 #define ICE_ONE_PPS_OUT_ARG       "pps_out"
  33 #define ICE_RX_LOW_LATENCY_ARG    "rx_low_latency"
  34
  35 uint64_t ice_timestamp_dynflag;
  36 int ice_timestamp_dynfield_offset = -1;
  37
  38 static const char * const ice_valid_args[] = {
  39         ICE_SAFE_MODE_SUPPORT_ARG,
  40         ICE_PIPELINE_MODE_SUPPORT_ARG,
  41         ICE_PROTO_XTR_ARG,
  42         ICE_HW_DEBUG_MASK_ARG,
  43         ICE_ONE_PPS_OUT_ARG,
  44         ICE_RX_LOW_LATENCY_ARG,
  45         NULL
  46 };
  47
  48 #define NSEC_PER_SEC      1000000000
  49 #define PPS_OUT_DELAY_NS  1
  50
  51 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  52         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  53         .size = sizeof(uint32_t),
  54         .align = __alignof__(uint32_t),
  55         .flags = 0,
  56 };
  57
  58 struct proto_xtr_ol_flag {
  59         const struct rte_mbuf_dynflag param;
  60         uint64_t *ol_flag;
  61         bool required;
  62 };
  63
  64 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  65
  66 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  67         [PROTO_XTR_VLAN] = {
  68                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  69                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  70         [PROTO_XTR_IPV4] = {
  71                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  72                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  73         [PROTO_XTR_IPV6] = {
  74                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  75                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  76         [PROTO_XTR_IPV6_FLOW] = {
  77                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  78                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  79         [PROTO_XTR_TCP] = {
  80                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  81                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  82         [PROTO_XTR_IP_OFFSET] = {
  83                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  84                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  85 };
  86
  87 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  88 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  89 #define ICE_MAX_RES_DESC_NUM        1024
  90
  91 static int ice_dev_configure(struct rte_eth_dev *dev);
  92 static int ice_dev_start(struct rte_eth_dev *dev);
  93 static int ice_dev_stop(struct rte_eth_dev *dev);
  94 static int ice_dev_close(struct rte_eth_dev *dev);
  95 static int ice_dev_reset(struct rte_eth_dev *dev);
  96 static int ice_dev_info_get(struct rte_eth_dev *dev,
  97                             struct rte_eth_dev_info *dev_info);
  98 static int ice_link_update(struct rte_eth_dev *dev,
  99                            int wait_to_complete);
 100 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
 101 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
 102
 103 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 104 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 105 static int ice_rss_reta_update(struct rte_eth_dev *dev,
 106                                struct rte_eth_rss_reta_entry64 *reta_conf,
 107                                uint16_t reta_size);
 108 static int ice_rss_reta_query(struct rte_eth_dev *dev,
 109                               struct rte_eth_rss_reta_entry64 *reta_conf,
 110                               uint16_t reta_size);
 111 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 112                                struct rte_eth_rss_conf *rss_conf);
 113 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_rss_conf *rss_conf);
 115 static int ice_promisc_enable(struct rte_eth_dev *dev);
 116 static int ice_promisc_disable(struct rte_eth_dev *dev);
 117 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 118 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 119 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 120                                uint16_t vlan_id,
 121                                int on);
 122 static int ice_macaddr_set(struct rte_eth_dev *dev,
 123                            struct rte_ether_addr *mac_addr);
 124 static int ice_macaddr_add(struct rte_eth_dev *dev,
 125                            struct rte_ether_addr *mac_addr,
 126                            __rte_unused uint32_t index,
 127                            uint32_t pool);
 128 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 129 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 130                                     uint16_t queue_id);
 131 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 132                                      uint16_t queue_id);
 133 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 134                               size_t fw_size);
 135 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 136                              uint16_t pvid, int on);
 137 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 138 static int ice_get_eeprom(struct rte_eth_dev *dev,
 139                           struct rte_dev_eeprom_info *eeprom);
 140 static int ice_stats_get(struct rte_eth_dev *dev,
 141                          struct rte_eth_stats *stats);
 142 static int ice_stats_reset(struct rte_eth_dev *dev);
 143 static int ice_xstats_get(struct rte_eth_dev *dev,
 144                           struct rte_eth_xstat *xstats, unsigned int n);
 145 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 146                                 struct rte_eth_xstat_name *xstats_names,
 147                                 unsigned int limit);
 148 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
 149                                 const struct rte_flow_ops **ops);
 150 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 151                         struct rte_eth_udp_tunnel *udp_tunnel);
 152 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 153                         struct rte_eth_udp_tunnel *udp_tunnel);
 154
 155 static const struct rte_pci_id pci_id_ice_map[] = {
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 169         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 170         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 171         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 172         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 173         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 174         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 175         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 176         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 177         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 178         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 179         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 180         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 181         { .vendor_id = 0, /* sentinel */ },
 182 };
 183
 184 static const struct eth_dev_ops ice_eth_dev_ops = {
 185         .dev_configure                = ice_dev_configure,
 186         .dev_start                    = ice_dev_start,
 187         .dev_stop                     = ice_dev_stop,
 188         .dev_close                    = ice_dev_close,
 189         .dev_reset                    = ice_dev_reset,
 190         .dev_set_link_up              = ice_dev_set_link_up,
 191         .dev_set_link_down            = ice_dev_set_link_down,
 192         .rx_queue_start               = ice_rx_queue_start,
 193         .rx_queue_stop                = ice_rx_queue_stop,
 194         .tx_queue_start               = ice_tx_queue_start,
 195         .tx_queue_stop                = ice_tx_queue_stop,
 196         .rx_queue_setup               = ice_rx_queue_setup,
 197         .rx_queue_release             = ice_rx_queue_release,
 198         .tx_queue_setup               = ice_tx_queue_setup,
 199         .tx_queue_release             = ice_tx_queue_release,
 200         .dev_infos_get                = ice_dev_info_get,
 201         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 202         .link_update                  = ice_link_update,
 203         .mtu_set                      = ice_mtu_set,
 204         .mac_addr_set                 = ice_macaddr_set,
 205         .mac_addr_add                 = ice_macaddr_add,
 206         .mac_addr_remove              = ice_macaddr_remove,
 207         .vlan_filter_set              = ice_vlan_filter_set,
 208         .vlan_offload_set             = ice_vlan_offload_set,
 209         .reta_update                  = ice_rss_reta_update,
 210         .reta_query                   = ice_rss_reta_query,
 211         .rss_hash_update              = ice_rss_hash_update,
 212         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 213         .promiscuous_enable           = ice_promisc_enable,
 214         .promiscuous_disable          = ice_promisc_disable,
 215         .allmulticast_enable          = ice_allmulti_enable,
 216         .allmulticast_disable         = ice_allmulti_disable,
 217         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 218         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 219         .fw_version_get               = ice_fw_version_get,
 220         .vlan_pvid_set                = ice_vlan_pvid_set,
 221         .rxq_info_get                 = ice_rxq_info_get,
 222         .txq_info_get                 = ice_txq_info_get,
 223         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 224         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 225         .get_eeprom_length            = ice_get_eeprom_length,
 226         .get_eeprom                   = ice_get_eeprom,
 227         .stats_get                    = ice_stats_get,
 228         .stats_reset                  = ice_stats_reset,
 229         .xstats_get                   = ice_xstats_get,
 230         .xstats_get_names             = ice_xstats_get_names,
 231         .xstats_reset                 = ice_stats_reset,
 232         .flow_ops_get                 = ice_dev_flow_ops_get,
 233         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 234         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 235         .tx_done_cleanup              = ice_tx_done_cleanup,
 236         .get_monitor_addr             = ice_get_monitor_addr,
 237 };
 238
 239 /* store statistics names and its offset in stats structure */
 240 struct ice_xstats_name_off {
 241         char name[RTE_ETH_XSTATS_NAME_SIZE];
 242         unsigned int offset;
 243 };
 244
 245 static const struct ice_xstats_name_off ice_stats_strings[] = {
 246         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 247         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 248         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 249         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 250         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 251                 rx_unknown_protocol)},
 252         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 253         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 254         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 255         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 256 };
 257
 258 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 259                 sizeof(ice_stats_strings[0]))
 260
 261 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 262         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 263                 tx_dropped_link_down)},
 264         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 265         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 266                 illegal_bytes)},
 267         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 268         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 269                 mac_local_faults)},
 270         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 271                 mac_remote_faults)},
 272         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 273                 rx_len_errors)},
 274         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 275         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 276         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 277         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 278         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 279         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 280                 rx_size_127)},
 281         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 282                 rx_size_255)},
 283         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 284                 rx_size_511)},
 285         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 286                 rx_size_1023)},
 287         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 288                 rx_size_1522)},
 289         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 290                 rx_size_big)},
 291         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 292                 rx_undersize)},
 293         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 294                 rx_oversize)},
 295         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 296                 mac_short_pkt_dropped)},
 297         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 298                 rx_fragments)},
 299         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 300         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 301         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 302                 tx_size_127)},
 303         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 304                 tx_size_255)},
 305         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 306                 tx_size_511)},
 307         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 308                 tx_size_1023)},
 309         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 310                 tx_size_1522)},
 311         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 312                 tx_size_big)},
 313 };
 314
 315 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 316                 sizeof(ice_hw_port_strings[0]))
 317
 318 static void
 319 ice_init_controlq_parameter(struct ice_hw *hw)
 320 {
 321         /* fields for adminq */
 322         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 323         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 324         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 325         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 326
 327         /* fields for mailboxq, DPDK used as PF host */
 328         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 329         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 330         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 331         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 332 }
 333
 334 static int
 335 lookup_proto_xtr_type(const char *xtr_name)
 336 {
 337         static struct {
 338                 const char *name;
 339                 enum proto_xtr_type type;
 340         } xtr_type_map[] = {
 341                 { "vlan",      PROTO_XTR_VLAN      },
 342                 { "ipv4",      PROTO_XTR_IPV4      },
 343                 { "ipv6",      PROTO_XTR_IPV6      },
 344                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 345                 { "tcp",       PROTO_XTR_TCP       },
 346                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 347         };
 348         uint32_t i;
 349
 350         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 351                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 352                         return xtr_type_map[i].type;
 353         }
 354
 355         return -1;
 356 }
 357
 358 /*
 359  * Parse elem, the elem could be single number/range or '(' ')' group
 360  * 1) A single number elem, it's just a simple digit. e.g. 9
 361  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 362  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 363  *    Within group elem, '-' used for a range separator;
 364  *                       ',' used for a single number.
 365  */
 366 static int
 367 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 368 {
 369         const char *str = input;
 370         char *end = NULL;
 371         uint32_t min, max;
 372         uint32_t idx;
 373
 374         while (isblank(*str))
 375                 str++;
 376
 377         if (!isdigit(*str) && *str != '(')
 378                 return -1;
 379
 380         /* process single number or single range of number */
 381         if (*str != '(') {
 382                 errno = 0;
 383                 idx = strtoul(str, &end, 10);
 384                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 385                         return -1;
 386
 387                 while (isblank(*end))
 388                         end++;
 389
 390                 min = idx;
 391                 max = idx;
 392
 393                 /* process single <number>-<number> */
 394                 if (*end == '-') {
 395                         end++;
 396                         while (isblank(*end))
 397                                 end++;
 398                         if (!isdigit(*end))
 399                                 return -1;
 400
 401                         errno = 0;
 402                         idx = strtoul(end, &end, 10);
 403                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 404                                 return -1;
 405
 406                         max = idx;
 407                         while (isblank(*end))
 408                                 end++;
 409                 }
 410
 411                 if (*end != ':')
 412                         return -1;
 413
 414                 for (idx = RTE_MIN(min, max);
 415                      idx <= RTE_MAX(min, max); idx++)
 416                         devargs->proto_xtr[idx] = xtr_type;
 417
 418                 return 0;
 419         }
 420
 421         /* process set within bracket */
 422         str++;
 423         while (isblank(*str))
 424                 str++;
 425         if (*str == '\0')
 426                 return -1;
 427
 428         min = ICE_MAX_QUEUE_NUM;
 429         do {
 430                 /* go ahead to the first digit */
 431                 while (isblank(*str))
 432                         str++;
 433                 if (!isdigit(*str))
 434                         return -1;
 435
 436                 /* get the digit value */
 437                 errno = 0;
 438                 idx = strtoul(str, &end, 10);
 439                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 440                         return -1;
 441
 442                 /* go ahead to separator '-',',' and ')' */
 443                 while (isblank(*end))
 444                         end++;
 445                 if (*end == '-') {
 446                         if (min == ICE_MAX_QUEUE_NUM)
 447                                 min = idx;
 448                         else /* avoid continuous '-' */
 449                                 return -1;
 450                 } else if (*end == ',' || *end == ')') {
 451                         max = idx;
 452                         if (min == ICE_MAX_QUEUE_NUM)
 453                                 min = idx;
 454
 455                         for (idx = RTE_MIN(min, max);
 456                              idx <= RTE_MAX(min, max); idx++)
 457                                 devargs->proto_xtr[idx] = xtr_type;
 458
 459                         min = ICE_MAX_QUEUE_NUM;
 460                 } else {
 461                         return -1;
 462                 }
 463
 464                 str = end + 1;
 465         } while (*end != ')' && *end != '\0');
 466
 467         return 0;
 468 }
 469
 470 static int
 471 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 472 {
 473         const char *queue_start;
 474         uint32_t idx;
 475         int xtr_type;
 476         char xtr_name[32];
 477
 478         while (isblank(*queues))
 479                 queues++;
 480
 481         if (*queues != '[') {
 482                 xtr_type = lookup_proto_xtr_type(queues);
 483                 if (xtr_type < 0)
 484                         return -1;
 485
 486                 devargs->proto_xtr_dflt = xtr_type;
 487
 488                 return 0;
 489         }
 490
 491         queues++;
 492         do {
 493                 while (isblank(*queues))
 494                         queues++;
 495                 if (*queues == '\0')
 496                         return -1;
 497
 498                 queue_start = queues;
 499
 500                 /* go across a complete bracket */
 501                 if (*queue_start == '(') {
 502                         queues += strcspn(queues, ")");
 503                         if (*queues != ')')
 504                                 return -1;
 505                 }
 506
 507                 /* scan the separator ':' */
 508                 queues += strcspn(queues, ":");
 509                 if (*queues++ != ':')
 510                         return -1;
 511                 while (isblank(*queues))
 512                         queues++;
 513
 514                 for (idx = 0; ; idx++) {
 515                         if (isblank(queues[idx]) ||
 516                             queues[idx] == ',' ||
 517                             queues[idx] == ']' ||
 518                             queues[idx] == '\0')
 519                                 break;
 520
 521                         if (idx > sizeof(xtr_name) - 2)
 522                                 return -1;
 523
 524                         xtr_name[idx] = queues[idx];
 525                 }
 526                 xtr_name[idx] = '\0';
 527                 xtr_type = lookup_proto_xtr_type(xtr_name);
 528                 if (xtr_type < 0)
 529                         return -1;
 530
 531                 queues += idx;
 532
 533                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 534                         queues++;
 535
 536                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 537                         return -1;
 538         } while (*queues != '\0');
 539
 540         return 0;
 541 }
 542
 543 static int
 544 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 545                      void *extra_args)
 546 {
 547         struct ice_devargs *devargs = extra_args;
 548
 549         if (value == NULL || extra_args == NULL)
 550                 return -EINVAL;
 551
 552         if (parse_queue_proto_xtr(value, devargs) < 0) {
 553                 PMD_DRV_LOG(ERR,
 554                             "The protocol extraction parameter is wrong : '%s'",
 555                             value);
 556                 return -1;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static void
 563 ice_check_proto_xtr_support(struct ice_hw *hw)
 564 {
 565 #define FLX_REG(val, fld, idx) \
 566         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 567          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 568         static struct {
 569                 uint32_t rxdid;
 570                 uint8_t opcode;
 571                 uint8_t protid_0;
 572                 uint8_t protid_1;
 573         } xtr_sets[] = {
 574                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 575                                      ICE_RX_OPC_EXTRACT,
 576                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 577                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 578                                      ICE_RX_OPC_EXTRACT,
 579                                      ICE_PROT_IPV4_OF_OR_S,
 580                                      ICE_PROT_IPV4_OF_OR_S },
 581                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 582                                      ICE_RX_OPC_EXTRACT,
 583                                      ICE_PROT_IPV6_OF_OR_S,
 584                                      ICE_PROT_IPV6_OF_OR_S },
 585                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 586                                           ICE_RX_OPC_EXTRACT,
 587                                           ICE_PROT_IPV6_OF_OR_S,
 588                                           ICE_PROT_IPV6_OF_OR_S },
 589                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 590                                     ICE_RX_OPC_EXTRACT,
 591                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 592                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 593                                           ICE_RX_OPC_PROTID,
 594                                           ICE_PROT_IPV4_OF_OR_S,
 595                                           ICE_PROT_IPV6_OF_OR_S },
 596         };
 597         uint32_t i;
 598
 599         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 600                 uint32_t rxdid = xtr_sets[i].rxdid;
 601                 uint32_t v;
 602
 603                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 604                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 605
 606                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 607                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 608                                 ice_proto_xtr_hw_support[i] = true;
 609                 }
 610
 611                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 612                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 613
 614                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 615                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 616                                 ice_proto_xtr_hw_support[i] = true;
 617                 }
 618         }
 619 }
 620
 621 static int
 622 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 623                   uint32_t num)
 624 {
 625         struct pool_entry *entry;
 626
 627         if (!pool || !num)
 628                 return -EINVAL;
 629
 630         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 631         if (!entry) {
 632                 PMD_INIT_LOG(ERR,
 633                              "Failed to allocate memory for resource pool");
 634                 return -ENOMEM;
 635         }
 636
 637         /* queue heap initialize */
 638         pool->num_free = num;
 639         pool->num_alloc = 0;
 640         pool->base = base;
 641         LIST_INIT(&pool->alloc_list);
 642         LIST_INIT(&pool->free_list);
 643
 644         /* Initialize element  */
 645         entry->base = 0;
 646         entry->len = num;
 647
 648         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 649         return 0;
 650 }
 651
 652 static int
 653 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 654                    uint16_t num)
 655 {
 656         struct pool_entry *entry, *valid_entry;
 657
 658         if (!pool || !num) {
 659                 PMD_INIT_LOG(ERR, "Invalid parameter");
 660                 return -EINVAL;
 661         }
 662
 663         if (pool->num_free < num) {
 664                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 665                              num, pool->num_free);
 666                 return -ENOMEM;
 667         }
 668
 669         valid_entry = NULL;
 670         /* Lookup  in free list and find most fit one */
 671         LIST_FOREACH(entry, &pool->free_list, next) {
 672                 if (entry->len >= num) {
 673                         /* Find best one */
 674                         if (entry->len == num) {
 675                                 valid_entry = entry;
 676                                 break;
 677                         }
 678                         if (!valid_entry ||
 679                             valid_entry->len > entry->len)
 680                                 valid_entry = entry;
 681                 }
 682         }
 683
 684         /* Not find one to satisfy the request, return */
 685         if (!valid_entry) {
 686                 PMD_INIT_LOG(ERR, "No valid entry found");
 687                 return -ENOMEM;
 688         }
 689         /**
 690          * The entry have equal queue number as requested,
 691          * remove it from alloc_list.
 692          */
 693         if (valid_entry->len == num) {
 694                 LIST_REMOVE(valid_entry, next);
 695         } else {
 696                 /**
 697                  * The entry have more numbers than requested,
 698                  * create a new entry for alloc_list and minus its
 699                  * queue base and number in free_list.
 700                  */
 701                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 702                 if (!entry) {
 703                         PMD_INIT_LOG(ERR,
 704                                      "Failed to allocate memory for "
 705                                      "resource pool");
 706                         return -ENOMEM;
 707                 }
 708                 entry->base = valid_entry->base;
 709                 entry->len = num;
 710                 valid_entry->base += num;
 711                 valid_entry->len -= num;
 712                 valid_entry = entry;
 713         }
 714
 715         /* Insert it into alloc list, not sorted */
 716         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 717
 718         pool->num_free -= valid_entry->len;
 719         pool->num_alloc += valid_entry->len;
 720
 721         return valid_entry->base + pool->base;
 722 }
 723
 724 static void
 725 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 726 {
 727         struct pool_entry *entry, *next_entry;
 728
 729         if (!pool)
 730                 return;
 731
 732         for (entry = LIST_FIRST(&pool->alloc_list);
 733              entry && (next_entry = LIST_NEXT(entry, next), 1);
 734              entry = next_entry) {
 735                 LIST_REMOVE(entry, next);
 736                 rte_free(entry);
 737         }
 738
 739         for (entry = LIST_FIRST(&pool->free_list);
 740              entry && (next_entry = LIST_NEXT(entry, next), 1);
 741              entry = next_entry) {
 742                 LIST_REMOVE(entry, next);
 743                 rte_free(entry);
 744         }
 745
 746         pool->num_free = 0;
 747         pool->num_alloc = 0;
 748         pool->base = 0;
 749         LIST_INIT(&pool->alloc_list);
 750         LIST_INIT(&pool->free_list);
 751 }
 752
 753 static void
 754 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 755 {
 756         /* Set VSI LUT selection */
 757         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 758                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 759         /* Set Hash scheme */
 760         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 761                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 762         /* enable TC */
 763         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 764 }
 765
 766 static enum ice_status
 767 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 768                                 struct ice_aqc_vsi_props *info,
 769                                 uint8_t enabled_tcmap)
 770 {
 771         uint16_t bsf, qp_idx;
 772
 773         /* default tc 0 now. Multi-TC supporting need to be done later.
 774          * Configure TC and queue mapping parameters, for enabled TC,
 775          * allocate qpnum_per_tc queues to this traffic.
 776          */
 777         if (enabled_tcmap != 0x01) {
 778                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 779                 return -ENOTSUP;
 780         }
 781
 782         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 783         bsf = rte_bsf32(vsi->nb_qps);
 784         /* Adjust the queue number to actual queues that can be applied */
 785         vsi->nb_qps = 0x1 << bsf;
 786
 787         qp_idx = 0;
 788         /* Set tc and queue mapping with VSI */
 789         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 790                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 791                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 792
 793         /* Associate queue number with VSI */
 794         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 795         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 796         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 797         info->valid_sections |=
 798                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 799         /* Set the info.ingress_table and info.egress_table
 800          * for UP translate table. Now just set it to 1:1 map by default
 801          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 802          */
 803 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 804         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 805         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 806         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 807         return 0;
 808 }
 809
 810 static int
 811 ice_init_mac_address(struct rte_eth_dev *dev)
 812 {
 813         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 814
 815         if (!rte_is_unicast_ether_addr
 816                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 817                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 818                 return -EINVAL;
 819         }
 820
 821         rte_ether_addr_copy(
 822                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 823                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 824
 825         dev->data->mac_addrs =
 826                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
 827         if (!dev->data->mac_addrs) {
 828                 PMD_INIT_LOG(ERR,
 829                              "Failed to allocate memory to store mac address");
 830                 return -ENOMEM;
 831         }
 832         /* store it to dev data */
 833         rte_ether_addr_copy(
 834                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 835                 &dev->data->mac_addrs[0]);
 836         return 0;
 837 }
 838
 839 /* Find out specific MAC filter */
 840 static struct ice_mac_filter *
 841 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 842 {
 843         struct ice_mac_filter *f;
 844
 845         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 846                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 847                         return f;
 848         }
 849
 850         return NULL;
 851 }
 852
 853 static int
 854 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 855 {
 856         struct ice_fltr_list_entry *m_list_itr = NULL;
 857         struct ice_mac_filter *f;
 858         struct LIST_HEAD_TYPE list_head;
 859         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 860         int ret = 0;
 861
 862         /* If it's added and configured, return */
 863         f = ice_find_mac_filter(vsi, mac_addr);
 864         if (f) {
 865                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 866                 return 0;
 867         }
 868
 869         INIT_LIST_HEAD(&list_head);
 870
 871         m_list_itr = (struct ice_fltr_list_entry *)
 872                 ice_malloc(hw, sizeof(*m_list_itr));
 873         if (!m_list_itr) {
 874                 ret = -ENOMEM;
 875                 goto DONE;
 876         }
 877         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 878                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 879         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 880         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 881         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 882         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 883         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 884
 885         LIST_ADD(&m_list_itr->list_entry, &list_head);
 886
 887         /* Add the mac */
 888         ret = ice_add_mac(hw, &list_head);
 889         if (ret != ICE_SUCCESS) {
 890                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 891                 ret = -EINVAL;
 892                 goto DONE;
 893         }
 894         /* Add the mac addr into mac list */
 895         f = rte_zmalloc(NULL, sizeof(*f), 0);
 896         if (!f) {
 897                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 898                 ret = -ENOMEM;
 899                 goto DONE;
 900         }
 901         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 902         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 903         vsi->mac_num++;
 904
 905         ret = 0;
 906
 907 DONE:
 908         rte_free(m_list_itr);
 909         return ret;
 910 }
 911
 912 static int
 913 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 914 {
 915         struct ice_fltr_list_entry *m_list_itr = NULL;
 916         struct ice_mac_filter *f;
 917         struct LIST_HEAD_TYPE list_head;
 918         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 919         int ret = 0;
 920
 921         /* Can't find it, return an error */
 922         f = ice_find_mac_filter(vsi, mac_addr);
 923         if (!f)
 924                 return -EINVAL;
 925
 926         INIT_LIST_HEAD(&list_head);
 927
 928         m_list_itr = (struct ice_fltr_list_entry *)
 929                 ice_malloc(hw, sizeof(*m_list_itr));
 930         if (!m_list_itr) {
 931                 ret = -ENOMEM;
 932                 goto DONE;
 933         }
 934         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 935                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 936         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 937         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 938         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 939         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 940         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 941
 942         LIST_ADD(&m_list_itr->list_entry, &list_head);
 943
 944         /* remove the mac filter */
 945         ret = ice_remove_mac(hw, &list_head);
 946         if (ret != ICE_SUCCESS) {
 947                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 948                 ret = -EINVAL;
 949                 goto DONE;
 950         }
 951
 952         /* Remove the mac addr from mac list */
 953         TAILQ_REMOVE(&vsi->mac_list, f, next);
 954         rte_free(f);
 955         vsi->mac_num--;
 956
 957         ret = 0;
 958 DONE:
 959         rte_free(m_list_itr);
 960         return ret;
 961 }
 962
 963 /* Find out specific VLAN filter */
 964 static struct ice_vlan_filter *
 965 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 966 {
 967         struct ice_vlan_filter *f;
 968
 969         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 970                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 971                     vlan->vid == f->vlan_info.vlan.vid)
 972                         return f;
 973         }
 974
 975         return NULL;
 976 }
 977
 978 static int
 979 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 980 {
 981         struct ice_fltr_list_entry *v_list_itr = NULL;
 982         struct ice_vlan_filter *f;
 983         struct LIST_HEAD_TYPE list_head;
 984         struct ice_hw *hw;
 985         int ret = 0;
 986
 987         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 988                 return -EINVAL;
 989
 990         hw = ICE_VSI_TO_HW(vsi);
 991
 992         /* If it's added and configured, return. */
 993         f = ice_find_vlan_filter(vsi, vlan);
 994         if (f) {
 995                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 996                 return 0;
 997         }
 998
 999         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
1000                 return 0;
1001
1002         INIT_LIST_HEAD(&list_head);
1003
1004         v_list_itr = (struct ice_fltr_list_entry *)
1005                       ice_malloc(hw, sizeof(*v_list_itr));
1006         if (!v_list_itr) {
1007                 ret = -ENOMEM;
1008                 goto DONE;
1009         }
1010         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1011         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1012         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1013         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1014         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1015         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1016         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1017         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1018
1019         LIST_ADD(&v_list_itr->list_entry, &list_head);
1020
1021         /* Add the vlan */
1022         ret = ice_add_vlan(hw, &list_head);
1023         if (ret != ICE_SUCCESS) {
1024                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1025                 ret = -EINVAL;
1026                 goto DONE;
1027         }
1028
1029         /* Add vlan into vlan list */
1030         f = rte_zmalloc(NULL, sizeof(*f), 0);
1031         if (!f) {
1032                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1033                 ret = -ENOMEM;
1034                 goto DONE;
1035         }
1036         f->vlan_info.vlan.tpid = vlan->tpid;
1037         f->vlan_info.vlan.vid = vlan->vid;
1038         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1039         vsi->vlan_num++;
1040
1041         ret = 0;
1042
1043 DONE:
1044         rte_free(v_list_itr);
1045         return ret;
1046 }
1047
1048 static int
1049 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1050 {
1051         struct ice_fltr_list_entry *v_list_itr = NULL;
1052         struct ice_vlan_filter *f;
1053         struct LIST_HEAD_TYPE list_head;
1054         struct ice_hw *hw;
1055         int ret = 0;
1056
1057         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1058                 return -EINVAL;
1059
1060         hw = ICE_VSI_TO_HW(vsi);
1061
1062         /* Can't find it, return an error */
1063         f = ice_find_vlan_filter(vsi, vlan);
1064         if (!f)
1065                 return -EINVAL;
1066
1067         INIT_LIST_HEAD(&list_head);
1068
1069         v_list_itr = (struct ice_fltr_list_entry *)
1070                       ice_malloc(hw, sizeof(*v_list_itr));
1071         if (!v_list_itr) {
1072                 ret = -ENOMEM;
1073                 goto DONE;
1074         }
1075
1076         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1077         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1078         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1079         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1080         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1081         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1082         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1083         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1084
1085         LIST_ADD(&v_list_itr->list_entry, &list_head);
1086
1087         /* remove the vlan filter */
1088         ret = ice_remove_vlan(hw, &list_head);
1089         if (ret != ICE_SUCCESS) {
1090                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1091                 ret = -EINVAL;
1092                 goto DONE;
1093         }
1094
1095         /* Remove the vlan id from vlan list */
1096         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1097         rte_free(f);
1098         vsi->vlan_num--;
1099
1100         ret = 0;
1101 DONE:
1102         rte_free(v_list_itr);
1103         return ret;
1104 }
1105
1106 static int
1107 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1108 {
1109         struct ice_mac_filter *m_f;
1110         struct ice_vlan_filter *v_f;
1111         void *temp;
1112         int ret = 0;
1113
1114         if (!vsi || !vsi->mac_num)
1115                 return -EINVAL;
1116
1117         RTE_TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1118                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1119                 if (ret != ICE_SUCCESS) {
1120                         ret = -EINVAL;
1121                         goto DONE;
1122                 }
1123         }
1124
1125         if (vsi->vlan_num == 0)
1126                 return 0;
1127
1128         RTE_TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1129                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1130                 if (ret != ICE_SUCCESS) {
1131                         ret = -EINVAL;
1132                         goto DONE;
1133                 }
1134         }
1135
1136 DONE:
1137         return ret;
1138 }
1139
1140 /* Enable IRQ0 */
1141 static void
1142 ice_pf_enable_irq0(struct ice_hw *hw)
1143 {
1144         /* reset the registers */
1145         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1146         ICE_READ_REG(hw, PFINT_OICR);
1147
1148 #ifdef ICE_LSE_SPT
1149         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1150                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1151                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1152
1153         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1154                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1155                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1156                        PFINT_OICR_CTL_ITR_INDX_M) |
1157                       PFINT_OICR_CTL_CAUSE_ENA_M);
1158
1159         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1160                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1161                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1162                        PFINT_FW_CTL_ITR_INDX_M) |
1163                       PFINT_FW_CTL_CAUSE_ENA_M);
1164 #else
1165         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1166 #endif
1167
1168         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1169                       GLINT_DYN_CTL_INTENA_M |
1170                       GLINT_DYN_CTL_CLEARPBA_M |
1171                       GLINT_DYN_CTL_ITR_INDX_M);
1172
1173         ice_flush(hw);
1174 }
1175
1176 /* Disable IRQ0 */
1177 static void
1178 ice_pf_disable_irq0(struct ice_hw *hw)
1179 {
1180         /* Disable all interrupt types */
1181         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1182         ice_flush(hw);
1183 }
1184
1185 #ifdef ICE_LSE_SPT
1186 static void
1187 ice_handle_aq_msg(struct rte_eth_dev *dev)
1188 {
1189         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1190         struct ice_ctl_q_info *cq = &hw->adminq;
1191         struct ice_rq_event_info event;
1192         uint16_t pending, opcode;
1193         int ret;
1194
1195         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1196         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1197         if (!event.msg_buf) {
1198                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1199                 return;
1200         }
1201
1202         pending = 1;
1203         while (pending) {
1204                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1205
1206                 if (ret != ICE_SUCCESS) {
1207                         PMD_DRV_LOG(INFO,
1208                                     "Failed to read msg from AdminQ, "
1209                                     "adminq_err: %u",
1210                                     hw->adminq.sq_last_status);
1211                         break;
1212                 }
1213                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1214
1215                 switch (opcode) {
1216                 case ice_aqc_opc_get_link_status:
1217                         ret = ice_link_update(dev, 0);
1218                         if (!ret)
1219                                 rte_eth_dev_callback_process
1220                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1221                         break;
1222                 default:
1223                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1224                                     opcode);
1225                         break;
1226                 }
1227         }
1228         rte_free(event.msg_buf);
1229 }
1230 #endif
1231
1232 /**
1233  * Interrupt handler triggered by NIC for handling
1234  * specific interrupt.
1235  *
1236  * @param handle
1237  *  Pointer to interrupt handle.
1238  * @param param
1239  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1240  *
1241  * @return
1242  *  void
1243  */
1244 static void
1245 ice_interrupt_handler(void *param)
1246 {
1247         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1248         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249         uint32_t oicr;
1250         uint32_t reg;
1251         uint8_t pf_num;
1252         uint8_t event;
1253         uint16_t queue;
1254         int ret;
1255 #ifdef ICE_LSE_SPT
1256         uint32_t int_fw_ctl;
1257 #endif
1258
1259         /* Disable interrupt */
1260         ice_pf_disable_irq0(hw);
1261
1262         /* read out interrupt causes */
1263         oicr = ICE_READ_REG(hw, PFINT_OICR);
1264 #ifdef ICE_LSE_SPT
1265         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1266 #endif
1267
1268         /* No interrupt event indicated */
1269         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1270                 PMD_DRV_LOG(INFO, "No interrupt event");
1271                 goto done;
1272         }
1273
1274 #ifdef ICE_LSE_SPT
1275         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1276                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1277                 ice_handle_aq_msg(dev);
1278         }
1279 #else
1280         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1281                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1282                 ret = ice_link_update(dev, 0);
1283                 if (!ret)
1284                         rte_eth_dev_callback_process
1285                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1286         }
1287 #endif
1288
1289         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1290                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1291                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1292                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1293                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1294                                  GL_MDET_TX_PQM_PF_NUM_S;
1295                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1296                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1297                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1298                                 GL_MDET_TX_PQM_QNUM_S;
1299
1300                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1301                                     "%d by PQM on TX queue %d PF# %d",
1302                                     event, queue, pf_num);
1303                 }
1304
1305                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1306                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1307                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1308                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1309                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1310                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1311                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1312                                 GL_MDET_TX_TCLAN_QNUM_S;
1313
1314                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1315                                     "%d by TCLAN on TX queue %d PF# %d",
1316                                     event, queue, pf_num);
1317                 }
1318         }
1319 done:
1320         /* Enable interrupt */
1321         ice_pf_enable_irq0(hw);
1322         rte_intr_ack(dev->intr_handle);
1323 }
1324
1325 static void
1326 ice_init_proto_xtr(struct rte_eth_dev *dev)
1327 {
1328         struct ice_adapter *ad =
1329                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1331         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1332         const struct proto_xtr_ol_flag *ol_flag;
1333         bool proto_xtr_enable = false;
1334         int offset;
1335         uint16_t i;
1336
1337         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1338         if (unlikely(pf->proto_xtr == NULL)) {
1339                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1340                 return;
1341         }
1342
1343         for (i = 0; i < pf->lan_nb_qps; i++) {
1344                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1345                                    ad->devargs.proto_xtr[i] :
1346                                    ad->devargs.proto_xtr_dflt;
1347
1348                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1349                         uint8_t type = pf->proto_xtr[i];
1350
1351                         ice_proto_xtr_ol_flag_params[type].required = true;
1352                         proto_xtr_enable = true;
1353                 }
1354         }
1355
1356         if (likely(!proto_xtr_enable))
1357                 return;
1358
1359         ice_check_proto_xtr_support(hw);
1360
1361         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1362         if (unlikely(offset == -1)) {
1363                 PMD_DRV_LOG(ERR,
1364                             "Protocol extraction metadata is disabled in mbuf with error %d",
1365                             -rte_errno);
1366                 return;
1367         }
1368
1369         PMD_DRV_LOG(DEBUG,
1370                     "Protocol extraction metadata offset in mbuf is : %d",
1371                     offset);
1372         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1373
1374         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1375                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1376
1377                 if (!ol_flag->required)
1378                         continue;
1379
1380                 if (!ice_proto_xtr_hw_support[i]) {
1381                         PMD_DRV_LOG(ERR,
1382                                     "Protocol extraction type %u is not supported in hardware",
1383                                     i);
1384                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1385                         break;
1386                 }
1387
1388                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1389                 if (unlikely(offset == -1)) {
1390                         PMD_DRV_LOG(ERR,
1391                                     "Protocol extraction offload '%s' failed to register with error %d",
1392                                     ol_flag->param.name, -rte_errno);
1393
1394                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1395                         break;
1396                 }
1397
1398                 PMD_DRV_LOG(DEBUG,
1399                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1400                             ol_flag->param.name, offset);
1401                 *ol_flag->ol_flag = 1ULL << offset;
1402         }
1403 }
1404
1405 /*  Initialize SW parameters of PF */
1406 static int
1407 ice_pf_sw_init(struct rte_eth_dev *dev)
1408 {
1409         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1410         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1411
1412         pf->lan_nb_qp_max =
1413                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1414                                   hw->func_caps.common_cap.num_rxq);
1415
1416         pf->lan_nb_qps = pf->lan_nb_qp_max;
1417
1418         ice_init_proto_xtr(dev);
1419
1420         if (hw->func_caps.fd_fltr_guar > 0 ||
1421             hw->func_caps.fd_fltr_best_effort > 0) {
1422                 pf->flags |= ICE_FLAG_FDIR;
1423                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1424                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1425         } else {
1426                 pf->fdir_nb_qps = 0;
1427         }
1428         pf->fdir_qp_offset = 0;
1429
1430         return 0;
1431 }
1432
1433 struct ice_vsi *
1434 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1435 {
1436         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1437         struct ice_vsi *vsi = NULL;
1438         struct ice_vsi_ctx vsi_ctx;
1439         int ret;
1440         struct rte_ether_addr broadcast = {
1441                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1442         struct rte_ether_addr mac_addr;
1443         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1444         uint8_t tc_bitmap = 0x1;
1445         uint16_t cfg;
1446
1447         /* hw->num_lports = 1 in NIC mode */
1448         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1449         if (!vsi)
1450                 return NULL;
1451
1452         vsi->idx = pf->next_vsi_idx;
1453         pf->next_vsi_idx++;
1454         vsi->type = type;
1455         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1456         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1457         vsi->vlan_anti_spoof_on = 0;
1458         vsi->vlan_filter_on = 1;
1459         TAILQ_INIT(&vsi->mac_list);
1460         TAILQ_INIT(&vsi->vlan_list);
1461
1462         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1463         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1464                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1465                         hw->func_caps.common_cap.rss_table_size;
1466         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1467
1468         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1469         switch (type) {
1470         case ICE_VSI_PF:
1471                 vsi->nb_qps = pf->lan_nb_qps;
1472                 vsi->base_queue = 1;
1473                 ice_vsi_config_default_rss(&vsi_ctx.info);
1474                 vsi_ctx.alloc_from_pool = true;
1475                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1476                 /* switch_id is queried by get_switch_config aq, which is done
1477                  * by ice_init_hw
1478                  */
1479                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1480                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1481                 /* Allow all untagged or tagged packets */
1482                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1483                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1484                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1485                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1486                 if (ice_is_dvm_ena(hw)) {
1487                         vsi_ctx.info.outer_vlan_flags =
1488                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1489                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1490                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1491                         vsi_ctx.info.outer_vlan_flags |=
1492                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1493                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1494                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1495                 }
1496
1497                 /* FDIR */
1498                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1499                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1500                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1501                 cfg = ICE_AQ_VSI_FD_ENABLE;
1502                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1503                 vsi_ctx.info.max_fd_fltr_dedicated =
1504                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1505                 vsi_ctx.info.max_fd_fltr_shared =
1506                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1507
1508                 /* Enable VLAN/UP trip */
1509                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1510                                                       &vsi_ctx.info,
1511                                                       ICE_DEFAULT_TCMAP);
1512                 if (ret) {
1513                         PMD_INIT_LOG(ERR,
1514                                      "tc queue mapping with vsi failed, "
1515                                      "err = %d",
1516                                      ret);
1517                         goto fail_mem;
1518                 }
1519
1520                 break;
1521         case ICE_VSI_CTRL:
1522                 vsi->nb_qps = pf->fdir_nb_qps;
1523                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1524                 vsi_ctx.alloc_from_pool = true;
1525                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1526
1527                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1528                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1529                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1530                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1531                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1532                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1533                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1534                                                       &vsi_ctx.info,
1535                                                       ICE_DEFAULT_TCMAP);
1536                 if (ret) {
1537                         PMD_INIT_LOG(ERR,
1538                                      "tc queue mapping with vsi failed, "
1539                                      "err = %d",
1540                                      ret);
1541                         goto fail_mem;
1542                 }
1543                 break;
1544         default:
1545                 /* for other types of VSI */
1546                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1547                 goto fail_mem;
1548         }
1549
1550         /* VF has MSIX interrupt in VF range, don't allocate here */
1551         if (type == ICE_VSI_PF) {
1552                 ret = ice_res_pool_alloc(&pf->msix_pool,
1553                                          RTE_MIN(vsi->nb_qps,
1554                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1555                 if (ret < 0) {
1556                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1557                                      vsi->vsi_id, ret);
1558                 }
1559                 vsi->msix_intr = ret;
1560                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1561         } else if (type == ICE_VSI_CTRL) {
1562                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1563                 if (ret < 0) {
1564                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1565                                     vsi->vsi_id, ret);
1566                 }
1567                 vsi->msix_intr = ret;
1568                 vsi->nb_msix = 1;
1569         } else {
1570                 vsi->msix_intr = 0;
1571                 vsi->nb_msix = 0;
1572         }
1573         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1574         if (ret != ICE_SUCCESS) {
1575                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1576                 goto fail_mem;
1577         }
1578         /* store vsi information is SW structure */
1579         vsi->vsi_id = vsi_ctx.vsi_num;
1580         vsi->info = vsi_ctx.info;
1581         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1582         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1583
1584         if (type == ICE_VSI_PF) {
1585                 /* MAC configuration */
1586                 rte_ether_addr_copy((struct rte_ether_addr *)
1587                                         hw->port_info->mac.perm_addr,
1588                                     &pf->dev_addr);
1589
1590                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1591                 ret = ice_add_mac_filter(vsi, &mac_addr);
1592                 if (ret != ICE_SUCCESS)
1593                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1594
1595                 rte_ether_addr_copy(&broadcast, &mac_addr);
1596                 ret = ice_add_mac_filter(vsi, &mac_addr);
1597                 if (ret != ICE_SUCCESS)
1598                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1599         }
1600
1601         /* At the beginning, only TC0. */
1602         /* What we need here is the maximam number of the TX queues.
1603          * Currently vsi->nb_qps means it.
1604          * Correct it if any change.
1605          */
1606         max_txqs[0] = vsi->nb_qps;
1607         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1608                               tc_bitmap, max_txqs);
1609         if (ret != ICE_SUCCESS)
1610                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1611
1612         return vsi;
1613 fail_mem:
1614         rte_free(vsi);
1615         pf->next_vsi_idx--;
1616         return NULL;
1617 }
1618
1619 static int
1620 ice_send_driver_ver(struct ice_hw *hw)
1621 {
1622         struct ice_driver_ver dv;
1623
1624         /* we don't have driver version use 0 for dummy */
1625         dv.major_ver = 0;
1626         dv.minor_ver = 0;
1627         dv.build_ver = 0;
1628         dv.subbuild_ver = 0;
1629         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1630
1631         return ice_aq_send_driver_ver(hw, &dv, NULL);
1632 }
1633
1634 static int
1635 ice_pf_setup(struct ice_pf *pf)
1636 {
1637         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1638         struct ice_vsi *vsi;
1639         uint16_t unused;
1640
1641         /* Clear all stats counters */
1642         pf->offset_loaded = false;
1643         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1644         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1645         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1646         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1647
1648         /* force guaranteed filter pool for PF */
1649         ice_alloc_fd_guar_item(hw, &unused,
1650                                hw->func_caps.fd_fltr_guar);
1651         /* force shared filter pool for PF */
1652         ice_alloc_fd_shrd_item(hw, &unused,
1653                                hw->func_caps.fd_fltr_best_effort);
1654
1655         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1656         if (!vsi) {
1657                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1658                 return -EINVAL;
1659         }
1660
1661         pf->main_vsi = vsi;
1662
1663         return 0;
1664 }
1665
1666 static enum ice_pkg_type
1667 ice_load_pkg_type(struct ice_hw *hw)
1668 {
1669         enum ice_pkg_type package_type;
1670
1671         /* store the activated package type (OS default or Comms) */
1672         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1673                 ICE_PKG_NAME_SIZE))
1674                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1675         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1676                 ICE_PKG_NAME_SIZE))
1677                 package_type = ICE_PKG_TYPE_COMMS;
1678         else
1679                 package_type = ICE_PKG_TYPE_UNKNOWN;
1680
1681         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1682                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1683                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1684                 hw->active_pkg_name,
1685                 ice_is_dvm_ena(hw) ? "double" : "single");
1686
1687         return package_type;
1688 }
1689
1690 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1691 {
1692         struct ice_hw *hw = &adapter->hw;
1693         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1694         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1695         void *buf;
1696         size_t bufsz;
1697         int err;
1698
1699         if (!use_dsn)
1700                 goto no_dsn;
1701
1702         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1703         snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1704                 "ice-%016" PRIx64 ".pkg", dsn);
1705         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1706                 ICE_MAX_PKG_FILENAME_SIZE);
1707         strcat(pkg_file, opt_ddp_filename);
1708         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1709                 goto load_fw;
1710
1711         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1712                 ICE_MAX_PKG_FILENAME_SIZE);
1713         strcat(pkg_file, opt_ddp_filename);
1714         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1715                 goto load_fw;
1716
1717 no_dsn:
1718         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1719         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1720                 goto load_fw;
1721
1722         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1723         if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1724                 PMD_INIT_LOG(ERR, "failed to search file path\n");
1725                 return -1;
1726         }
1727
1728 load_fw:
1729         PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1730
1731         err = ice_copy_and_init_pkg(hw, buf, bufsz);
1732         if (err) {
1733                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1734                 goto out;
1735         }
1736
1737         /* store the loaded pkg type info */
1738         adapter->active_pkg_type = ice_load_pkg_type(hw);
1739
1740 out:
1741         free(buf);
1742         return err;
1743 }
1744
1745 static void
1746 ice_base_queue_get(struct ice_pf *pf)
1747 {
1748         uint32_t reg;
1749         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1750
1751         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1752         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1753                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1754         } else {
1755                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1756                                         " index");
1757         }
1758 }
1759
1760 static int
1761 parse_bool(const char *key, const char *value, void *args)
1762 {
1763         int *i = (int *)args;
1764         char *end;
1765         int num;
1766
1767         num = strtoul(value, &end, 10);
1768
1769         if (num != 0 && num != 1) {
1770                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1771                         "value must be 0 or 1",
1772                         value, key);
1773                 return -1;
1774         }
1775
1776         *i = num;
1777         return 0;
1778 }
1779
1780 static int
1781 parse_u64(const char *key, const char *value, void *args)
1782 {
1783         u64 *num = (u64 *)args;
1784         u64 tmp;
1785
1786         errno = 0;
1787         tmp = strtoull(value, NULL, 16);
1788         if (errno) {
1789                 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1790                             key, value);
1791                 return -1;
1792         }
1793
1794         *num = tmp;
1795
1796         return 0;
1797 }
1798
1799 static int
1800 lookup_pps_type(const char *pps_name)
1801 {
1802         static struct {
1803                 const char *name;
1804                 enum pps_type type;
1805         } pps_type_map[] = {
1806                 { "pin",  PPS_PIN  },
1807         };
1808
1809         uint32_t i;
1810
1811         for (i = 0; i < RTE_DIM(pps_type_map); i++) {
1812                 if (strcmp(pps_name, pps_type_map[i].name) == 0)
1813                         return pps_type_map[i].type;
1814         }
1815
1816         return -1;
1817 }
1818
1819 static int
1820 parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs)
1821 {
1822         const char *str = input;
1823         char *end = NULL;
1824         uint32_t idx;
1825
1826         while (isblank(*str))
1827                 str++;
1828
1829         if (!isdigit(*str))
1830                 return -1;
1831
1832         if (pps_type == PPS_PIN) {
1833                 idx = strtoul(str, &end, 10);
1834                 if (end == NULL || idx >= ICE_MAX_PIN_NUM)
1835                         return -1;
1836
1837                 devargs->pin_idx = idx;
1838                 devargs->pps_out_ena = 1;
1839         }
1840
1841         while (isblank(*end))
1842                 end++;
1843
1844         if (*end != ']')
1845                 return -1;
1846
1847         return 0;
1848 }
1849
1850 static int
1851 parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs)
1852 {
1853         const char *pin_start;
1854         uint32_t idx;
1855         int pps_type;
1856         char pps_name[32];
1857
1858         while (isblank(*pins))
1859                 pins++;
1860
1861         pins++;
1862         while (isblank(*pins))
1863                 pins++;
1864         if (*pins == '\0')
1865                 return -1;
1866
1867         for (idx = 0; ; idx++) {
1868                 if (isblank(pins[idx]) ||
1869                     pins[idx] == ':' ||
1870                     pins[idx] == '\0')
1871                         break;
1872
1873                 pps_name[idx] = pins[idx];
1874         }
1875         pps_name[idx] = '\0';
1876         pps_type = lookup_pps_type(pps_name);
1877         if (pps_type < 0)
1878                 return -1;
1879
1880         pins += idx;
1881
1882         pins += strcspn(pins, ":");
1883         if (*pins++ != ':')
1884                 return -1;
1885         while (isblank(*pins))
1886                 pins++;
1887
1888         pin_start = pins;
1889
1890         while (isblank(*pins))
1891                 pins++;
1892
1893         if (parse_pin_set(pin_start, pps_type, devargs) < 0)
1894                 return -1;
1895
1896         return 0;
1897 }
1898
1899 static int
1900 handle_pps_out_arg(__rte_unused const char *key, const char *value,
1901                    void *extra_args)
1902 {
1903         struct ice_devargs *devargs = extra_args;
1904
1905         if (value == NULL || extra_args == NULL)
1906                 return -EINVAL;
1907
1908         if (parse_pps_out_parameter(value, devargs) < 0) {
1909                 PMD_DRV_LOG(ERR,
1910                             "The GPIO pin parameter is wrong : '%s'",
1911                             value);
1912                 return -1;
1913         }
1914
1915         return 0;
1916 }
1917
1918 static int ice_parse_devargs(struct rte_eth_dev *dev)
1919 {
1920         struct ice_adapter *ad =
1921                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1922         struct rte_devargs *devargs = dev->device->devargs;
1923         struct rte_kvargs *kvlist;
1924         int ret;
1925
1926         if (devargs == NULL)
1927                 return 0;
1928
1929         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1930         if (kvlist == NULL) {
1931                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1932                 return -EINVAL;
1933         }
1934
1935         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1936         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1937                sizeof(ad->devargs.proto_xtr));
1938
1939         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1940                                  &handle_proto_xtr_arg, &ad->devargs);
1941         if (ret)
1942                 goto bail;
1943
1944         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1945                                  &parse_bool, &ad->devargs.safe_mode_support);
1946         if (ret)
1947                 goto bail;
1948
1949         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1950                                  &parse_bool, &ad->devargs.pipe_mode_support);
1951         if (ret)
1952                 goto bail;
1953
1954         ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1955                                  &parse_u64, &ad->hw.debug_mask);
1956         if (ret)
1957                 goto bail;
1958
1959         ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG,
1960                                  &handle_pps_out_arg, &ad->devargs);
1961         if (ret)
1962                 goto bail;
1963
1964         ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG,
1965                                  &parse_bool, &ad->devargs.rx_low_latency);
1966
1967 bail:
1968         rte_kvargs_free(kvlist);
1969         return ret;
1970 }
1971
1972 /* Forward LLDP packets to default VSI by set switch rules */
1973 static int
1974 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1975 {
1976         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1977         struct ice_fltr_list_entry *s_list_itr = NULL;
1978         struct LIST_HEAD_TYPE list_head;
1979         int ret = 0;
1980
1981         INIT_LIST_HEAD(&list_head);
1982
1983         s_list_itr = (struct ice_fltr_list_entry *)
1984                         ice_malloc(hw, sizeof(*s_list_itr));
1985         if (!s_list_itr)
1986                 return -ENOMEM;
1987         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1988         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1989         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1990                         RTE_ETHER_TYPE_LLDP;
1991         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1992         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1993         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1994         LIST_ADD(&s_list_itr->list_entry, &list_head);
1995         if (on)
1996                 ret = ice_add_eth_mac(hw, &list_head);
1997         else
1998                 ret = ice_remove_eth_mac(hw, &list_head);
1999
2000         rte_free(s_list_itr);
2001         return ret;
2002 }
2003
2004 static enum ice_status
2005 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2006                 uint16_t num, uint16_t desc_id,
2007                 uint16_t *prof_buf, uint16_t *num_prof)
2008 {
2009         struct ice_aqc_res_elem *resp_buf;
2010         int ret;
2011         uint16_t buf_len;
2012         bool res_shared = 1;
2013         struct ice_aq_desc aq_desc;
2014         struct ice_sq_cd *cd = NULL;
2015         struct ice_aqc_get_allocd_res_desc *cmd =
2016                         &aq_desc.params.get_res_desc;
2017
2018         buf_len = sizeof(*resp_buf) * num;
2019         resp_buf = ice_malloc(hw, buf_len);
2020         if (!resp_buf)
2021                 return -ENOMEM;
2022
2023         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2024                         ice_aqc_opc_get_allocd_res_desc);
2025
2026         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2027                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2028                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2029         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2030
2031         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2032         if (!ret)
2033                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2034         else
2035                 goto exit;
2036
2037         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2038                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2039
2040 exit:
2041         rte_free(resp_buf);
2042         return ret;
2043 }
2044 static int
2045 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2046 {
2047         int ret;
2048         uint16_t prof_id;
2049         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2050         uint16_t first_desc = 1;
2051         uint16_t num_prof = 0;
2052
2053         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2054                         first_desc, prof_buf, &num_prof);
2055         if (ret) {
2056                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2057                 return ret;
2058         }
2059
2060         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2061                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2062                 if (ret) {
2063                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2064                         return ret;
2065                 }
2066         }
2067         return 0;
2068 }
2069
2070 static int
2071 ice_reset_fxp_resource(struct ice_hw *hw)
2072 {
2073         int ret;
2074
2075         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2076         if (ret) {
2077                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2078                 return ret;
2079         }
2080
2081         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2082         if (ret) {
2083                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2084                 return ret;
2085         }
2086
2087         return 0;
2088 }
2089
2090 static void
2091 ice_rss_ctx_init(struct ice_pf *pf)
2092 {
2093         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2094 }
2095
2096 static uint64_t
2097 ice_get_supported_rxdid(struct ice_hw *hw)
2098 {
2099         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2100         uint32_t regval;
2101         int i;
2102
2103         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2104
2105         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2106                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2107                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2108                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2109                         supported_rxdid |= BIT(i);
2110         }
2111         return supported_rxdid;
2112 }
2113
2114 static int
2115 ice_dev_init(struct rte_eth_dev *dev)
2116 {
2117         struct rte_pci_device *pci_dev;
2118         struct rte_intr_handle *intr_handle;
2119         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2121         struct ice_adapter *ad =
2122                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2123         struct ice_vsi *vsi;
2124         int ret;
2125 #ifndef RTE_EXEC_ENV_WINDOWS
2126         off_t pos;
2127         uint32_t dsn_low, dsn_high;
2128         uint64_t dsn;
2129         bool use_dsn;
2130 #endif
2131
2132         dev->dev_ops = &ice_eth_dev_ops;
2133         dev->rx_queue_count = ice_rx_queue_count;
2134         dev->rx_descriptor_status = ice_rx_descriptor_status;
2135         dev->tx_descriptor_status = ice_tx_descriptor_status;
2136         dev->rx_pkt_burst = ice_recv_pkts;
2137         dev->tx_pkt_burst = ice_xmit_pkts;
2138         dev->tx_pkt_prepare = ice_prep_pkts;
2139
2140         /* for secondary processes, we don't initialise any further as primary
2141          * has already done this work.
2142          */
2143         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2144                 ice_set_rx_function(dev);
2145                 ice_set_tx_function(dev);
2146                 return 0;
2147         }
2148
2149         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2150
2151         ice_set_default_ptype_table(dev);
2152         pci_dev = RTE_DEV_TO_PCI(dev->device);
2153         intr_handle = &pci_dev->intr_handle;
2154
2155         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2156         pf->dev_data = dev->data;
2157         hw->back = pf->adapter;
2158         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2159         hw->vendor_id = pci_dev->id.vendor_id;
2160         hw->device_id = pci_dev->id.device_id;
2161         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2162         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2163         hw->bus.device = pci_dev->addr.devid;
2164         hw->bus.func = pci_dev->addr.function;
2165
2166         ret = ice_parse_devargs(dev);
2167         if (ret) {
2168                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2169                 return -EINVAL;
2170         }
2171
2172         ice_init_controlq_parameter(hw);
2173
2174         ret = ice_init_hw(hw);
2175         if (ret) {
2176                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2177                 return -EINVAL;
2178         }
2179
2180 #ifndef RTE_EXEC_ENV_WINDOWS
2181         use_dsn = false;
2182         dsn = 0;
2183         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2184         if (pos) {
2185                 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2186                                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2187                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2188                 } else {
2189                         use_dsn = true;
2190                         dsn = (uint64_t)dsn_high << 32 | dsn_low;
2191                 }
2192         } else {
2193                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2194         }
2195
2196         ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2197         if (ret == 0) {
2198                 ret = ice_init_hw_tbls(hw);
2199                 if (ret) {
2200                         PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2201                         rte_free(hw->pkg_copy);
2202                 }
2203         }
2204
2205         if (ret) {
2206                 if (ad->devargs.safe_mode_support == 0) {
2207                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2208                                         "Use safe-mode-support=1 to enter Safe Mode");
2209                         goto err_init_fw;
2210                 }
2211
2212                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2213                                         "Entering Safe Mode");
2214                 ad->is_safe_mode = 1;
2215         }
2216 #endif
2217
2218         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2219                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2220                      hw->api_maj_ver, hw->api_min_ver);
2221
2222         ice_pf_sw_init(dev);
2223         ret = ice_init_mac_address(dev);
2224         if (ret) {
2225                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2226                 goto err_init_mac;
2227         }
2228
2229         ret = ice_res_pool_init(&pf->msix_pool, 1,
2230                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2231         if (ret) {
2232                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2233                 goto err_msix_pool_init;
2234         }
2235
2236         ret = ice_pf_setup(pf);
2237         if (ret) {
2238                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2239                 goto err_pf_setup;
2240         }
2241
2242         ret = ice_send_driver_ver(hw);
2243         if (ret) {
2244                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2245                 goto err_pf_setup;
2246         }
2247
2248         vsi = pf->main_vsi;
2249
2250         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2251         if (ret != ICE_SUCCESS)
2252                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2253         ret = ice_init_dcb(hw, true);
2254         if (ret != ICE_SUCCESS)
2255                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2256         /* Forward LLDP packets to default VSI */
2257         ret = ice_vsi_config_sw_lldp(vsi, true);
2258         if (ret != ICE_SUCCESS)
2259                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2260         /* register callback func to eal lib */
2261         rte_intr_callback_register(intr_handle,
2262                                    ice_interrupt_handler, dev);
2263
2264         ice_pf_enable_irq0(hw);
2265
2266         /* enable uio intr after callback register */
2267         rte_intr_enable(intr_handle);
2268
2269         /* get base queue pairs index  in the device */
2270         ice_base_queue_get(pf);
2271
2272         /* Initialize RSS context for gtpu_eh */
2273         ice_rss_ctx_init(pf);
2274
2275         if (!ad->is_safe_mode) {
2276                 ret = ice_flow_init(ad);
2277                 if (ret) {
2278                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2279                         goto err_flow_init;
2280                 }
2281         }
2282
2283         ret = ice_reset_fxp_resource(hw);
2284         if (ret) {
2285                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2286                 goto err_flow_init;
2287         }
2288
2289         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2290
2291         return 0;
2292
2293 err_flow_init:
2294         ice_flow_uninit(ad);
2295         rte_intr_disable(intr_handle);
2296         ice_pf_disable_irq0(hw);
2297         rte_intr_callback_unregister(intr_handle,
2298                                      ice_interrupt_handler, dev);
2299 err_pf_setup:
2300         ice_res_pool_destroy(&pf->msix_pool);
2301 err_msix_pool_init:
2302         rte_free(dev->data->mac_addrs);
2303         dev->data->mac_addrs = NULL;
2304 err_init_mac:
2305         rte_free(pf->proto_xtr);
2306 #ifndef RTE_EXEC_ENV_WINDOWS
2307 err_init_fw:
2308 #endif
2309         ice_deinit_hw(hw);
2310
2311         return ret;
2312 }
2313
2314 int
2315 ice_release_vsi(struct ice_vsi *vsi)
2316 {
2317         struct ice_hw *hw;
2318         struct ice_vsi_ctx vsi_ctx;
2319         enum ice_status ret;
2320         int error = 0;
2321
2322         if (!vsi)
2323                 return error;
2324
2325         hw = ICE_VSI_TO_HW(vsi);
2326
2327         ice_remove_all_mac_vlan_filters(vsi);
2328
2329         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2330
2331         vsi_ctx.vsi_num = vsi->vsi_id;
2332         vsi_ctx.info = vsi->info;
2333         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2334         if (ret != ICE_SUCCESS) {
2335                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2336                 error = -1;
2337         }
2338
2339         rte_free(vsi->rss_lut);
2340         rte_free(vsi->rss_key);
2341         rte_free(vsi);
2342         return error;
2343 }
2344
2345 void
2346 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2347 {
2348         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2349         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2350         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2351         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2352         uint16_t msix_intr, i;
2353
2354         /* disable interrupt and also clear all the exist config */
2355         for (i = 0; i < vsi->nb_qps; i++) {
2356                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2357                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2358                 rte_wmb();
2359         }
2360
2361         if (rte_intr_allow_others(intr_handle))
2362                 /* vfio-pci */
2363                 for (i = 0; i < vsi->nb_msix; i++) {
2364                         msix_intr = vsi->msix_intr + i;
2365                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2366                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2367                 }
2368         else
2369                 /* igb_uio */
2370                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2371 }
2372
2373 static int
2374 ice_dev_stop(struct rte_eth_dev *dev)
2375 {
2376         struct rte_eth_dev_data *data = dev->data;
2377         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2378         struct ice_vsi *main_vsi = pf->main_vsi;
2379         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2380         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2381         uint16_t i;
2382
2383         /* avoid stopping again */
2384         if (pf->adapter_stopped)
2385                 return 0;
2386
2387         /* stop and clear all Rx queues */
2388         for (i = 0; i < data->nb_rx_queues; i++)
2389                 ice_rx_queue_stop(dev, i);
2390
2391         /* stop and clear all Tx queues */
2392         for (i = 0; i < data->nb_tx_queues; i++)
2393                 ice_tx_queue_stop(dev, i);
2394
2395         /* disable all queue interrupts */
2396         ice_vsi_disable_queues_intr(main_vsi);
2397
2398         if (pf->init_link_up)
2399                 ice_dev_set_link_up(dev);
2400         else
2401                 ice_dev_set_link_down(dev);
2402
2403         /* Clean datapath event and queue/vec mapping */
2404         rte_intr_efd_disable(intr_handle);
2405         if (intr_handle->intr_vec) {
2406                 rte_free(intr_handle->intr_vec);
2407                 intr_handle->intr_vec = NULL;
2408         }
2409
2410         pf->adapter_stopped = true;
2411         dev->data->dev_started = 0;
2412
2413         return 0;
2414 }
2415
2416 static int
2417 ice_dev_close(struct rte_eth_dev *dev)
2418 {
2419         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2420         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2422         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2423         struct ice_adapter *ad =
2424                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2425         int ret;
2426         uint32_t val;
2427         uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
2428         uint32_t pin_idx = ad->devargs.pin_idx;
2429
2430         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2431                 return 0;
2432
2433         /* Since stop will make link down, then the link event will be
2434          * triggered, disable the irq firstly to avoid the port_infoe etc
2435          * resources deallocation causing the interrupt service thread
2436          * crash.
2437          */
2438         ice_pf_disable_irq0(hw);
2439
2440         ret = ice_dev_stop(dev);
2441
2442         if (!ad->is_safe_mode)
2443                 ice_flow_uninit(ad);
2444
2445         /* release all queue resource */
2446         ice_free_queues(dev);
2447
2448         ice_res_pool_destroy(&pf->msix_pool);
2449         ice_release_vsi(pf->main_vsi);
2450         ice_sched_cleanup_all(hw);
2451         ice_free_hw_tbls(hw);
2452         rte_free(hw->port_info);
2453         hw->port_info = NULL;
2454         ice_shutdown_all_ctrlq(hw);
2455         rte_free(pf->proto_xtr);
2456         pf->proto_xtr = NULL;
2457
2458         if (ad->devargs.pps_out_ena) {
2459                 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0);
2460                 ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0);
2461                 ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0);
2462                 ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0);
2463
2464                 val = GLGEN_GPIO_CTL_PIN_DIR_M;
2465                 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val);
2466         }
2467
2468         /* disable uio intr before callback unregister */
2469         rte_intr_disable(intr_handle);
2470
2471         /* unregister callback func from eal lib */
2472         rte_intr_callback_unregister(intr_handle,
2473                                      ice_interrupt_handler, dev);
2474
2475         return ret;
2476 }
2477
2478 static int
2479 ice_dev_uninit(struct rte_eth_dev *dev)
2480 {
2481         ice_dev_close(dev);
2482
2483         return 0;
2484 }
2485
2486 static bool
2487 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2488 {
2489         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2490 }
2491
2492 static void
2493 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2494 {
2495         cfg->hash_flds = 0;
2496         cfg->addl_hdrs = 0;
2497         cfg->symm = 0;
2498         cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2499 }
2500
2501 static int
2502 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2503 {
2504         enum ice_status status = ICE_SUCCESS;
2505         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2506         struct ice_vsi *vsi = pf->main_vsi;
2507
2508         if (!is_hash_cfg_valid(cfg))
2509                 return -ENOENT;
2510
2511         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2512         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2513                 PMD_DRV_LOG(ERR,
2514                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2515                             vsi->idx, status);
2516                 return -EBUSY;
2517         }
2518
2519         return 0;
2520 }
2521
2522 static int
2523 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2524 {
2525         enum ice_status status = ICE_SUCCESS;
2526         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2527         struct ice_vsi *vsi = pf->main_vsi;
2528
2529         if (!is_hash_cfg_valid(cfg))
2530                 return -ENOENT;
2531
2532         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2533         if (status) {
2534                 PMD_DRV_LOG(ERR,
2535                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2536                             vsi->idx, status);
2537                 return -EBUSY;
2538         }
2539
2540         return 0;
2541 }
2542
2543 static int
2544 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2545 {
2546         int ret;
2547
2548         ret = ice_hash_moveout(pf, cfg);
2549         if (ret && (ret != -ENOENT))
2550                 return ret;
2551
2552         hash_cfg_reset(cfg);
2553
2554         return 0;
2555 }
2556
2557 static int
2558 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2559                          u8 ctx_idx)
2560 {
2561         int ret;
2562
2563         switch (ctx_idx) {
2564         case ICE_HASH_GTPU_CTX_EH_IP:
2565                 ret = ice_hash_remove(pf,
2566                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2567                 if (ret && (ret != -ENOENT))
2568                         return ret;
2569
2570                 ret = ice_hash_remove(pf,
2571                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2572                 if (ret && (ret != -ENOENT))
2573                         return ret;
2574
2575                 ret = ice_hash_remove(pf,
2576                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2577                 if (ret && (ret != -ENOENT))
2578                         return ret;
2579
2580                 ret = ice_hash_remove(pf,
2581                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2582                 if (ret && (ret != -ENOENT))
2583                         return ret;
2584
2585                 ret = ice_hash_remove(pf,
2586                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2587                 if (ret && (ret != -ENOENT))
2588                         return ret;
2589
2590                 ret = ice_hash_remove(pf,
2591                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2592                 if (ret && (ret != -ENOENT))
2593                         return ret;
2594
2595                 ret = ice_hash_remove(pf,
2596                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2597                 if (ret && (ret != -ENOENT))
2598                         return ret;
2599
2600                 ret = ice_hash_remove(pf,
2601                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2602                 if (ret && (ret != -ENOENT))
2603                         return ret;
2604
2605                 break;
2606         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2607                 ret = ice_hash_remove(pf,
2608                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2609                 if (ret && (ret != -ENOENT))
2610                         return ret;
2611
2612                 ret = ice_hash_remove(pf,
2613                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2614                 if (ret && (ret != -ENOENT))
2615                         return ret;
2616
2617                 ret = ice_hash_moveout(pf,
2618                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2619                 if (ret && (ret != -ENOENT))
2620                         return ret;
2621
2622                 ret = ice_hash_moveout(pf,
2623                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2624                 if (ret && (ret != -ENOENT))
2625                         return ret;
2626
2627                 ret = ice_hash_moveout(pf,
2628                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2629                 if (ret && (ret != -ENOENT))
2630                         return ret;
2631
2632                 ret = ice_hash_moveout(pf,
2633                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2634                 if (ret && (ret != -ENOENT))
2635                         return ret;
2636
2637                 break;
2638         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2639                 ret = ice_hash_remove(pf,
2640                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2641                 if (ret && (ret != -ENOENT))
2642                         return ret;
2643
2644                 ret = ice_hash_remove(pf,
2645                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2646                 if (ret && (ret != -ENOENT))
2647                         return ret;
2648
2649                 ret = ice_hash_moveout(pf,
2650                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2651                 if (ret && (ret != -ENOENT))
2652                         return ret;
2653
2654                 ret = ice_hash_moveout(pf,
2655                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2656                 if (ret && (ret != -ENOENT))
2657                         return ret;
2658
2659                 ret = ice_hash_moveout(pf,
2660                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2661                 if (ret && (ret != -ENOENT))
2662                         return ret;
2663
2664                 ret = ice_hash_moveout(pf,
2665                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2666                 if (ret && (ret != -ENOENT))
2667                         return ret;
2668
2669                 break;
2670         case ICE_HASH_GTPU_CTX_UP_IP:
2671                 ret = ice_hash_remove(pf,
2672                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2673                 if (ret && (ret != -ENOENT))
2674                         return ret;
2675
2676                 ret = ice_hash_remove(pf,
2677                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2678                 if (ret && (ret != -ENOENT))
2679                         return ret;
2680
2681                 ret = ice_hash_moveout(pf,
2682                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2683                 if (ret && (ret != -ENOENT))
2684                         return ret;
2685
2686                 ret = ice_hash_moveout(pf,
2687                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2688                 if (ret && (ret != -ENOENT))
2689                         return ret;
2690
2691                 ret = ice_hash_moveout(pf,
2692                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2693                 if (ret && (ret != -ENOENT))
2694                         return ret;
2695
2696                 break;
2697         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2698         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2699                 ret = ice_hash_moveout(pf,
2700                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2701                 if (ret && (ret != -ENOENT))
2702                         return ret;
2703
2704                 ret = ice_hash_moveout(pf,
2705                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2706                 if (ret && (ret != -ENOENT))
2707                         return ret;
2708
2709                 ret = ice_hash_moveout(pf,
2710                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2711                 if (ret && (ret != -ENOENT))
2712                         return ret;
2713
2714                 break;
2715         case ICE_HASH_GTPU_CTX_DW_IP:
2716                 ret = ice_hash_remove(pf,
2717                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2718                 if (ret && (ret != -ENOENT))
2719                         return ret;
2720
2721                 ret = ice_hash_remove(pf,
2722                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2723                 if (ret && (ret != -ENOENT))
2724                         return ret;
2725
2726                 ret = ice_hash_moveout(pf,
2727                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2728                 if (ret && (ret != -ENOENT))
2729                         return ret;
2730
2731                 ret = ice_hash_moveout(pf,
2732                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2733                 if (ret && (ret != -ENOENT))
2734                         return ret;
2735
2736                 ret = ice_hash_moveout(pf,
2737                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2738                 if (ret && (ret != -ENOENT))
2739                         return ret;
2740
2741                 break;
2742         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2743         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2744                 ret = ice_hash_moveout(pf,
2745                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2746                 if (ret && (ret != -ENOENT))
2747                         return ret;
2748
2749                 ret = ice_hash_moveout(pf,
2750                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2751                 if (ret && (ret != -ENOENT))
2752                         return ret;
2753
2754                 ret = ice_hash_moveout(pf,
2755                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2756                 if (ret && (ret != -ENOENT))
2757                         return ret;
2758
2759                 break;
2760         default:
2761                 break;
2762         }
2763
2764         return 0;
2765 }
2766
2767 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2768 {
2769         u8 eh_idx, ip_idx;
2770
2771         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2772                 eh_idx = 0;
2773         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2774                 eh_idx = 1;
2775         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2776                 eh_idx = 2;
2777         else
2778                 return ICE_HASH_GTPU_CTX_MAX;
2779
2780         ip_idx = 0;
2781         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2782                 ip_idx = 1;
2783         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2784                 ip_idx = 2;
2785
2786         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2787                 return eh_idx * 3 + ip_idx;
2788         else
2789                 return ICE_HASH_GTPU_CTX_MAX;
2790 }
2791
2792 static int
2793 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2794 {
2795         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2796
2797         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2798                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2799                                                 gtpu_ctx_idx);
2800         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2801                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2802                                                 gtpu_ctx_idx);
2803
2804         return 0;
2805 }
2806
2807 static int
2808 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2809                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2810 {
2811         int ret;
2812
2813         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2814                 ctx->ctx[ctx_idx] = *cfg;
2815
2816         switch (ctx_idx) {
2817         case ICE_HASH_GTPU_CTX_EH_IP:
2818                 break;
2819         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2820                 ret = ice_hash_moveback(pf,
2821                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2822                 if (ret && (ret != -ENOENT))
2823                         return ret;
2824
2825                 ret = ice_hash_moveback(pf,
2826                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2827                 if (ret && (ret != -ENOENT))
2828                         return ret;
2829
2830                 ret = ice_hash_moveback(pf,
2831                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2832                 if (ret && (ret != -ENOENT))
2833                         return ret;
2834
2835                 ret = ice_hash_moveback(pf,
2836                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2837                 if (ret && (ret != -ENOENT))
2838                         return ret;
2839
2840                 break;
2841         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2842                 ret = ice_hash_moveback(pf,
2843                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2844                 if (ret && (ret != -ENOENT))
2845                         return ret;
2846
2847                 ret = ice_hash_moveback(pf,
2848                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2849                 if (ret && (ret != -ENOENT))
2850                         return ret;
2851
2852                 ret = ice_hash_moveback(pf,
2853                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2854                 if (ret && (ret != -ENOENT))
2855                         return ret;
2856
2857                 ret = ice_hash_moveback(pf,
2858                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2859                 if (ret && (ret != -ENOENT))
2860                         return ret;
2861
2862                 break;
2863         case ICE_HASH_GTPU_CTX_UP_IP:
2864         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2865         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2866         case ICE_HASH_GTPU_CTX_DW_IP:
2867         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2868         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2869                 ret = ice_hash_moveback(pf,
2870                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2871                 if (ret && (ret != -ENOENT))
2872                         return ret;
2873
2874                 ret = ice_hash_moveback(pf,
2875                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2876                 if (ret && (ret != -ENOENT))
2877                         return ret;
2878
2879                 ret = ice_hash_moveback(pf,
2880                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2881                 if (ret && (ret != -ENOENT))
2882                         return ret;
2883
2884                 break;
2885         default:
2886                 break;
2887         }
2888
2889         return 0;
2890 }
2891
2892 static int
2893 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2894 {
2895         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2896
2897         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2898                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2899                                                  gtpu_ctx_idx, cfg);
2900         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2901                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2902                                                  gtpu_ctx_idx, cfg);
2903
2904         return 0;
2905 }
2906
2907 static void
2908 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2909 {
2910         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2911
2912         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2913                 return;
2914
2915         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2916                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2917         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2918                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2919 }
2920
2921 int
2922 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2923                      struct ice_rss_hash_cfg *cfg)
2924 {
2925         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2926         int ret;
2927
2928         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2929         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2930                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2931
2932         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2933
2934         return 0;
2935 }
2936
2937 int
2938 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2939                      struct ice_rss_hash_cfg *cfg)
2940 {
2941         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2942         int ret;
2943
2944         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2945         if (ret)
2946                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2947
2948         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2949         if (ret)
2950                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2951
2952         ret = ice_add_rss_cfg_post(pf, cfg);
2953         if (ret)
2954                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2955
2956         return 0;
2957 }
2958
2959 static void
2960 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2961 {
2962         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2963         struct ice_vsi *vsi = pf->main_vsi;
2964         struct ice_rss_hash_cfg cfg;
2965         int ret;
2966
2967 #define ICE_RSS_HF_ALL ( \
2968         ETH_RSS_IPV4 | \
2969         ETH_RSS_IPV6 | \
2970         ETH_RSS_NONFRAG_IPV4_UDP | \
2971         ETH_RSS_NONFRAG_IPV6_UDP | \
2972         ETH_RSS_NONFRAG_IPV4_TCP | \
2973         ETH_RSS_NONFRAG_IPV6_TCP | \
2974         ETH_RSS_NONFRAG_IPV4_SCTP | \
2975         ETH_RSS_NONFRAG_IPV6_SCTP)
2976
2977         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2978         if (ret)
2979                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2980                             __func__, ret);
2981
2982         cfg.symm = 0;
2983         cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2984         /* Configure RSS for IPv4 with src/dst addr as input set */
2985         if (rss_hf & ETH_RSS_IPV4) {
2986                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2987                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2988                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2989                 if (ret)
2990                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2991                                     __func__, ret);
2992         }
2993
2994         /* Configure RSS for IPv6 with src/dst addr as input set */
2995         if (rss_hf & ETH_RSS_IPV6) {
2996                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2997                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2998                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2999                 if (ret)
3000                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
3001                                     __func__, ret);
3002         }
3003
3004         /* Configure RSS for udp4 with src/dst addr and port as input set */
3005         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3006                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
3007                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3008                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3009                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3010                 if (ret)
3011                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
3012                                     __func__, ret);
3013         }
3014
3015         /* Configure RSS for udp6 with src/dst addr and port as input set */
3016         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3017                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
3018                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3019                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3020                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3021                 if (ret)
3022                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
3023                                     __func__, ret);
3024         }
3025
3026         /* Configure RSS for tcp4 with src/dst addr and port as input set */
3027         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3028                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
3029                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3030                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3031                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3032                 if (ret)
3033                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
3034                                     __func__, ret);
3035         }
3036
3037         /* Configure RSS for tcp6 with src/dst addr and port as input set */
3038         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3039                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
3040                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3041                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3042                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3043                 if (ret)
3044                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
3045                                     __func__, ret);
3046         }
3047
3048         /* Configure RSS for sctp4 with src/dst addr and port as input set */
3049         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3050                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3051                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3052                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3053                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3054                 if (ret)
3055                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3056                                     __func__, ret);
3057         }
3058
3059         /* Configure RSS for sctp6 with src/dst addr and port as input set */
3060         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3061                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3062                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3063                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3064                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3065                 if (ret)
3066                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3067                                     __func__, ret);
3068         }
3069
3070         if (rss_hf & ETH_RSS_IPV4) {
3071                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3072                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3073                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3074                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3075                 if (ret)
3076                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3077                                     __func__, ret);
3078         }
3079
3080         if (rss_hf & ETH_RSS_IPV6) {
3081                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3082                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
3083                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3084                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3085                 if (ret)
3086                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3087                                     __func__, ret);
3088         }
3089
3090         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3091                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3092                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3093                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3094                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3095                 if (ret)
3096                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3097                                     __func__, ret);
3098         }
3099
3100         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3101                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3102                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3103                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3104                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3105                 if (ret)
3106                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3107                                     __func__, ret);
3108         }
3109
3110         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3111                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3112                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3113                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3114                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3115                 if (ret)
3116                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3117                                     __func__, ret);
3118         }
3119
3120         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3121                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3122                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3123                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3124                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3125                 if (ret)
3126                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3127                                     __func__, ret);
3128         }
3129
3130         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3131 }
3132
3133 static void
3134 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3135 {
3136         static struct ice_aqc_get_set_rss_keys default_key;
3137         static bool default_key_done;
3138         uint8_t *key = (uint8_t *)&default_key;
3139         size_t i;
3140
3141         if (rss_key_size > sizeof(default_key)) {
3142                 PMD_DRV_LOG(WARNING,
3143                             "requested size %u is larger than default %zu, "
3144                             "only %zu bytes are gotten for key\n",
3145                             rss_key_size, sizeof(default_key),
3146                             sizeof(default_key));
3147         }
3148
3149         if (!default_key_done) {
3150                 /* Calculate the default hash key */
3151                 for (i = 0; i < sizeof(default_key); i++)
3152                         key[i] = (uint8_t)rte_rand();
3153                 default_key_done = true;
3154         }
3155         rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3156 }
3157
3158 static int ice_init_rss(struct ice_pf *pf)
3159 {
3160         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3161         struct ice_vsi *vsi = pf->main_vsi;
3162         struct rte_eth_dev_data *dev_data = pf->dev_data;
3163         struct ice_aq_get_set_rss_lut_params lut_params;
3164         struct rte_eth_rss_conf *rss_conf;
3165         struct ice_aqc_get_set_rss_keys key;
3166         uint16_t i, nb_q;
3167         int ret = 0;
3168         bool is_safe_mode = pf->adapter->is_safe_mode;
3169         uint32_t reg;
3170
3171         rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3172         nb_q = dev_data->nb_rx_queues;
3173         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3174         vsi->rss_lut_size = pf->hash_lut_size;
3175
3176         if (nb_q == 0) {
3177                 PMD_DRV_LOG(WARNING,
3178                         "RSS is not supported as rx queues number is zero\n");
3179                 return 0;
3180         }
3181
3182         if (is_safe_mode) {
3183                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3184                 return 0;
3185         }
3186
3187         if (!vsi->rss_key) {
3188                 vsi->rss_key = rte_zmalloc(NULL,
3189                                            vsi->rss_key_size, 0);
3190                 if (vsi->rss_key == NULL) {
3191                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3192                         return -ENOMEM;
3193                 }
3194         }
3195         if (!vsi->rss_lut) {
3196                 vsi->rss_lut = rte_zmalloc(NULL,
3197                                            vsi->rss_lut_size, 0);
3198                 if (vsi->rss_lut == NULL) {
3199                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3200                         rte_free(vsi->rss_key);
3201                         vsi->rss_key = NULL;
3202                         return -ENOMEM;
3203                 }
3204         }
3205         /* configure RSS key */
3206         if (!rss_conf->rss_key)
3207                 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3208         else
3209                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3210                            RTE_MIN(rss_conf->rss_key_len,
3211                                    vsi->rss_key_size));
3212
3213         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3214         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3215         if (ret)
3216                 goto out;
3217
3218         /* init RSS LUT table */
3219         for (i = 0; i < vsi->rss_lut_size; i++)
3220                 vsi->rss_lut[i] = i % nb_q;
3221
3222         lut_params.vsi_handle = vsi->idx;
3223         lut_params.lut_size = vsi->rss_lut_size;
3224         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3225         lut_params.lut = vsi->rss_lut;
3226         lut_params.global_lut_id = 0;
3227         ret = ice_aq_set_rss_lut(hw, &lut_params);
3228         if (ret)
3229                 goto out;
3230
3231         /* Enable registers for symmetric_toeplitz function. */
3232         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3233         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3234                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3235         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3236
3237         /* RSS hash configuration */
3238         ice_rss_hash_set(pf, rss_conf->rss_hf);
3239
3240         return 0;
3241 out:
3242         rte_free(vsi->rss_key);
3243         vsi->rss_key = NULL;
3244         rte_free(vsi->rss_lut);
3245         vsi->rss_lut = NULL;
3246         return -EINVAL;
3247 }
3248
3249 static int
3250 ice_dev_configure(struct rte_eth_dev *dev)
3251 {
3252         struct ice_adapter *ad =
3253                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3254         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3255         int ret;
3256
3257         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3258          * bulk allocation or vector Rx preconditions we will reset it.
3259          */
3260         ad->rx_bulk_alloc_allowed = true;
3261         ad->tx_simple_allowed = true;
3262
3263         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3264                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3265
3266         if (dev->data->nb_rx_queues) {
3267                 ret = ice_init_rss(pf);
3268                 if (ret) {
3269                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3270                         return ret;
3271                 }
3272         }
3273
3274         return 0;
3275 }
3276
3277 static void
3278 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3279                        int base_queue, int nb_queue)
3280 {
3281         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3282         uint32_t val, val_tx;
3283         int rx_low_latency, i;
3284
3285         rx_low_latency = vsi->adapter->devargs.rx_low_latency;
3286         for (i = 0; i < nb_queue; i++) {
3287                 /*do actual bind*/
3288                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3289                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3290                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3291                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3292
3293                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3294                             base_queue + i, msix_vect);
3295
3296                 /* set ITR0 value */
3297                 if (rx_low_latency) {
3298                         /**
3299                          * Empirical configuration for optimal real time
3300                          * latency reduced interrupt throttling to 2us
3301                          */
3302                         ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
3303                         ICE_WRITE_REG(hw, QRX_ITR(base_queue + i),
3304                                       QRX_ITR_NO_EXPR_M);
3305                 } else {
3306                         ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3307                         ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0);
3308                 }
3309
3310                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3311                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3312         }
3313 }
3314
3315 void
3316 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3317 {
3318         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3319         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3321         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3322         uint16_t msix_vect = vsi->msix_intr;
3323         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3324         uint16_t queue_idx = 0;
3325         int record = 0;
3326         int i;
3327
3328         /* clear Rx/Tx queue interrupt */
3329         for (i = 0; i < vsi->nb_used_qps; i++) {
3330                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3331                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3332         }
3333
3334         /* PF bind interrupt */
3335         if (rte_intr_dp_is_en(intr_handle)) {
3336                 queue_idx = 0;
3337                 record = 1;
3338         }
3339
3340         for (i = 0; i < vsi->nb_used_qps; i++) {
3341                 if (nb_msix <= 1) {
3342                         if (!rte_intr_allow_others(intr_handle))
3343                                 msix_vect = ICE_MISC_VEC_ID;
3344
3345                         /* uio mapping all queue to one msix_vect */
3346                         __vsi_queues_bind_intr(vsi, msix_vect,
3347                                                vsi->base_queue + i,
3348                                                vsi->nb_used_qps - i);
3349
3350                         for (; !!record && i < vsi->nb_used_qps; i++)
3351                                 intr_handle->intr_vec[queue_idx + i] =
3352                                         msix_vect;
3353                         break;
3354                 }
3355
3356                 /* vfio 1:1 queue/msix_vect mapping */
3357                 __vsi_queues_bind_intr(vsi, msix_vect,
3358                                        vsi->base_queue + i, 1);
3359
3360                 if (!!record)
3361                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3362
3363                 msix_vect++;
3364                 nb_msix--;
3365         }
3366 }
3367
3368 void
3369 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3370 {
3371         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3372         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3373         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3374         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3375         uint16_t msix_intr, i;
3376
3377         if (rte_intr_allow_others(intr_handle))
3378                 for (i = 0; i < vsi->nb_used_qps; i++) {
3379                         msix_intr = vsi->msix_intr + i;
3380                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3381                                       GLINT_DYN_CTL_INTENA_M |
3382                                       GLINT_DYN_CTL_CLEARPBA_M |
3383                                       GLINT_DYN_CTL_ITR_INDX_M |
3384                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3385                 }
3386         else
3387                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3388                               GLINT_DYN_CTL_INTENA_M |
3389                               GLINT_DYN_CTL_CLEARPBA_M |
3390                               GLINT_DYN_CTL_ITR_INDX_M |
3391                               GLINT_DYN_CTL_WB_ON_ITR_M);
3392 }
3393
3394 static int
3395 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3396 {
3397         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3398         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3399         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3400         struct ice_vsi *vsi = pf->main_vsi;
3401         uint32_t intr_vector = 0;
3402
3403         rte_intr_disable(intr_handle);
3404
3405         /* check and configure queue intr-vector mapping */
3406         if ((rte_intr_cap_multiple(intr_handle) ||
3407              !RTE_ETH_DEV_SRIOV(dev).active) &&
3408             dev->data->dev_conf.intr_conf.rxq != 0) {
3409                 intr_vector = dev->data->nb_rx_queues;
3410                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3411                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3412                                     ICE_MAX_INTR_QUEUE_NUM);
3413                         return -ENOTSUP;
3414                 }
3415                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3416                         return -1;
3417         }
3418
3419         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3420                 intr_handle->intr_vec =
3421                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3422                             0);
3423                 if (!intr_handle->intr_vec) {
3424                         PMD_DRV_LOG(ERR,
3425                                     "Failed to allocate %d rx_queues intr_vec",
3426                                     dev->data->nb_rx_queues);
3427                         return -ENOMEM;
3428                 }
3429         }
3430
3431         /* Map queues with MSIX interrupt */
3432         vsi->nb_used_qps = dev->data->nb_rx_queues;
3433         ice_vsi_queues_bind_intr(vsi);
3434
3435         /* Enable interrupts for all the queues */
3436         ice_vsi_enable_queues_intr(vsi);
3437
3438         rte_intr_enable(intr_handle);
3439
3440         return 0;
3441 }
3442
3443 static void
3444 ice_get_init_link_status(struct rte_eth_dev *dev)
3445 {
3446         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3448         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3449         struct ice_link_status link_status;
3450         int ret;
3451
3452         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3453                                    &link_status, NULL);
3454         if (ret != ICE_SUCCESS) {
3455                 PMD_DRV_LOG(ERR, "Failed to get link info");
3456                 pf->init_link_up = false;
3457                 return;
3458         }
3459
3460         if (link_status.link_info & ICE_AQ_LINK_UP)
3461                 pf->init_link_up = true;
3462 }
3463
3464 static int
3465 ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer)
3466 {
3467         uint64_t current_time, start_time;
3468         uint32_t hi, lo, lo2, func, val;
3469
3470         lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3471         hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3472         lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3473
3474         if (lo2 < lo) {
3475                 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3476                 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3477         }
3478
3479         current_time = ((uint64_t)hi << 32) | lo;
3480
3481         start_time = (current_time + NSEC_PER_SEC) /
3482                         NSEC_PER_SEC * NSEC_PER_SEC;
3483         start_time = start_time - PPS_OUT_DELAY_NS;
3484
3485         func = 8 + idx + timer * 4;
3486         val = GLGEN_GPIO_CTL_PIN_DIR_M |
3487                 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
3488                 GLGEN_GPIO_CTL_PIN_FUNC_M);
3489
3490         /* Write clkout with half of period value */
3491         ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2);
3492
3493         /* Write TARGET time register */
3494         ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff);
3495         ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32);
3496
3497         /* Write AUX_OUT register */
3498         ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer),
3499                       GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M);
3500
3501         /* Write GPIO CTL register */
3502         ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val);
3503
3504         return 0;
3505 }
3506
3507 static int
3508 ice_dev_start(struct rte_eth_dev *dev)
3509 {
3510         struct rte_eth_dev_data *data = dev->data;
3511         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3513         struct ice_vsi *vsi = pf->main_vsi;
3514         struct ice_adapter *ad =
3515                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3516         uint16_t nb_rxq = 0;
3517         uint16_t nb_txq, i;
3518         uint16_t max_frame_size;
3519         int mask, ret;
3520         uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
3521         uint32_t pin_idx = ad->devargs.pin_idx;
3522
3523         /* program Tx queues' context in hardware */
3524         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3525                 ret = ice_tx_queue_start(dev, nb_txq);
3526                 if (ret) {
3527                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3528                         goto tx_err;
3529                 }
3530         }
3531
3532         /* program Rx queues' context in hardware*/
3533         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3534                 ret = ice_rx_queue_start(dev, nb_rxq);
3535                 if (ret) {
3536                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3537                         goto rx_err;
3538                 }
3539         }
3540
3541         ice_set_rx_function(dev);
3542         ice_set_tx_function(dev);
3543
3544         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3545                         ETH_VLAN_EXTEND_MASK;
3546         ret = ice_vlan_offload_set(dev, mask);
3547         if (ret) {
3548                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3549                 goto rx_err;
3550         }
3551
3552         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3553         if (ice_rxq_intr_setup(dev))
3554                 return -EIO;
3555
3556         /* Enable receiving broadcast packets and transmitting packets */
3557         ret = ice_set_vsi_promisc(hw, vsi->idx,
3558                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3559                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3560                                   0);
3561         if (ret != ICE_SUCCESS)
3562                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3563
3564         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3565                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3566                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3567                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3568                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3569                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3570                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3571                                      NULL);
3572         if (ret != ICE_SUCCESS)
3573                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3574
3575         ice_get_init_link_status(dev);
3576
3577         ice_dev_set_link_up(dev);
3578
3579         /* Call get_link_info aq commond to enable/disable LSE */
3580         ice_link_update(dev, 0);
3581
3582         pf->adapter_stopped = false;
3583
3584         /* Set the max frame size to default value*/
3585         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3586                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3587                 ICE_FRAME_SIZE_MAX;
3588
3589         /* Set the max frame size to HW*/
3590         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3591
3592         if (ad->devargs.pps_out_ena) {
3593                 ret = ice_pps_out_cfg(hw, pin_idx, timer);
3594                 if (ret) {
3595                         PMD_DRV_LOG(ERR, "Fail to configure 1pps out");
3596                         goto rx_err;
3597                 }
3598         }
3599
3600         return 0;
3601
3602         /* stop the started queues if failed to start all queues */
3603 rx_err:
3604         for (i = 0; i < nb_rxq; i++)
3605                 ice_rx_queue_stop(dev, i);
3606 tx_err:
3607         for (i = 0; i < nb_txq; i++)
3608                 ice_tx_queue_stop(dev, i);
3609
3610         return -EIO;
3611 }
3612
3613 static int
3614 ice_dev_reset(struct rte_eth_dev *dev)
3615 {
3616         int ret;
3617
3618         if (dev->data->sriov.active)
3619                 return -ENOTSUP;
3620
3621         ret = ice_dev_uninit(dev);
3622         if (ret) {
3623                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3624                 return -ENXIO;
3625         }
3626
3627         ret = ice_dev_init(dev);
3628         if (ret) {
3629                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3630                 return -ENXIO;
3631         }
3632
3633         return 0;
3634 }
3635
3636 static int
3637 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3638 {
3639         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3640         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         struct ice_vsi *vsi = pf->main_vsi;
3642         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3643         bool is_safe_mode = pf->adapter->is_safe_mode;
3644         u64 phy_type_low;
3645         u64 phy_type_high;
3646
3647         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3648         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3649         dev_info->max_rx_queues = vsi->nb_qps;
3650         dev_info->max_tx_queues = vsi->nb_qps;
3651         dev_info->max_mac_addrs = vsi->max_macaddrs;
3652         dev_info->max_vfs = pci_dev->max_vfs;
3653         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3654         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3655
3656         dev_info->rx_offload_capa =
3657                 DEV_RX_OFFLOAD_VLAN_STRIP |
3658                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3659                 DEV_RX_OFFLOAD_KEEP_CRC |
3660                 DEV_RX_OFFLOAD_SCATTER |
3661                 DEV_RX_OFFLOAD_VLAN_FILTER;
3662         dev_info->tx_offload_capa =
3663                 DEV_TX_OFFLOAD_VLAN_INSERT |
3664                 DEV_TX_OFFLOAD_TCP_TSO |
3665                 DEV_TX_OFFLOAD_MULTI_SEGS |
3666                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3667         dev_info->flow_type_rss_offloads = 0;
3668
3669         if (!is_safe_mode) {
3670                 dev_info->rx_offload_capa |=
3671                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3672                         DEV_RX_OFFLOAD_UDP_CKSUM |
3673                         DEV_RX_OFFLOAD_TCP_CKSUM |
3674                         DEV_RX_OFFLOAD_QINQ_STRIP |
3675                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3676                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3677                         DEV_RX_OFFLOAD_RSS_HASH |
3678                         DEV_RX_OFFLOAD_TIMESTAMP;
3679                 dev_info->tx_offload_capa |=
3680                         DEV_TX_OFFLOAD_QINQ_INSERT |
3681                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3682                         DEV_TX_OFFLOAD_UDP_CKSUM |
3683                         DEV_TX_OFFLOAD_TCP_CKSUM |
3684                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3685                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3686                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3687                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3688         }
3689
3690         dev_info->rx_queue_offload_capa = 0;
3691         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3692
3693         dev_info->reta_size = pf->hash_lut_size;
3694         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3695
3696         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3697                 .rx_thresh = {
3698                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3699                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3700                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3701                 },
3702                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3703                 .rx_drop_en = 0,
3704                 .offloads = 0,
3705         };
3706
3707         dev_info->default_txconf = (struct rte_eth_txconf) {
3708                 .tx_thresh = {
3709                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3710                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3711                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3712                 },
3713                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3714                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3715                 .offloads = 0,
3716         };
3717
3718         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3719                 .nb_max = ICE_MAX_RING_DESC,
3720                 .nb_min = ICE_MIN_RING_DESC,
3721                 .nb_align = ICE_ALIGN_RING_DESC,
3722         };
3723
3724         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3725                 .nb_max = ICE_MAX_RING_DESC,
3726                 .nb_min = ICE_MIN_RING_DESC,
3727                 .nb_align = ICE_ALIGN_RING_DESC,
3728         };
3729
3730         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3731                                ETH_LINK_SPEED_100M |
3732                                ETH_LINK_SPEED_1G |
3733                                ETH_LINK_SPEED_2_5G |
3734                                ETH_LINK_SPEED_5G |
3735                                ETH_LINK_SPEED_10G |
3736                                ETH_LINK_SPEED_20G |
3737                                ETH_LINK_SPEED_25G;
3738
3739         phy_type_low = hw->port_info->phy.phy_type_low;
3740         phy_type_high = hw->port_info->phy.phy_type_high;
3741
3742         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3743                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3744
3745         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3746                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3747                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3748
3749         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3750         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3751
3752         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3753         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3754         dev_info->default_rxportconf.nb_queues = 1;
3755         dev_info->default_txportconf.nb_queues = 1;
3756         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3757         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3758
3759         return 0;
3760 }
3761
3762 static inline int
3763 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3764                             struct rte_eth_link *link)
3765 {
3766         struct rte_eth_link *dst = link;
3767         struct rte_eth_link *src = &dev->data->dev_link;
3768
3769         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3770                                 *(uint64_t *)src) == 0)
3771                 return -1;
3772
3773         return 0;
3774 }
3775
3776 static inline int
3777 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3778                              struct rte_eth_link *link)
3779 {
3780         struct rte_eth_link *dst = &dev->data->dev_link;
3781         struct rte_eth_link *src = link;
3782
3783         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3784                                 *(uint64_t *)src) == 0)
3785                 return -1;
3786
3787         return 0;
3788 }
3789
3790 static int
3791 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3792 {
3793 #define CHECK_INTERVAL 100  /* 100ms */
3794 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3795         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796         struct ice_link_status link_status;
3797         struct rte_eth_link link, old;
3798         int status;
3799         unsigned int rep_cnt = MAX_REPEAT_TIME;
3800         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3801
3802         memset(&link, 0, sizeof(link));
3803         memset(&old, 0, sizeof(old));
3804         memset(&link_status, 0, sizeof(link_status));
3805         ice_atomic_read_link_status(dev, &old);
3806
3807         do {
3808                 /* Get link status information from hardware */
3809                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3810                                               &link_status, NULL);
3811                 if (status != ICE_SUCCESS) {
3812                         link.link_speed = ETH_SPEED_NUM_100M;
3813                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3814                         PMD_DRV_LOG(ERR, "Failed to get link info");
3815                         goto out;
3816                 }
3817
3818                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3819                 if (!wait_to_complete || link.link_status)
3820                         break;
3821
3822                 rte_delay_ms(CHECK_INTERVAL);
3823         } while (--rep_cnt);
3824
3825         if (!link.link_status)
3826                 goto out;
3827
3828         /* Full-duplex operation at all supported speeds */
3829         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3830
3831         /* Parse the link status */
3832         switch (link_status.link_speed) {
3833         case ICE_AQ_LINK_SPEED_10MB:
3834                 link.link_speed = ETH_SPEED_NUM_10M;
3835                 break;
3836         case ICE_AQ_LINK_SPEED_100MB:
3837                 link.link_speed = ETH_SPEED_NUM_100M;
3838                 break;
3839         case ICE_AQ_LINK_SPEED_1000MB:
3840                 link.link_speed = ETH_SPEED_NUM_1G;
3841                 break;
3842         case ICE_AQ_LINK_SPEED_2500MB:
3843                 link.link_speed = ETH_SPEED_NUM_2_5G;
3844                 break;
3845         case ICE_AQ_LINK_SPEED_5GB:
3846                 link.link_speed = ETH_SPEED_NUM_5G;
3847                 break;
3848         case ICE_AQ_LINK_SPEED_10GB:
3849                 link.link_speed = ETH_SPEED_NUM_10G;
3850                 break;
3851         case ICE_AQ_LINK_SPEED_20GB:
3852                 link.link_speed = ETH_SPEED_NUM_20G;
3853                 break;
3854         case ICE_AQ_LINK_SPEED_25GB:
3855                 link.link_speed = ETH_SPEED_NUM_25G;
3856                 break;
3857         case ICE_AQ_LINK_SPEED_40GB:
3858                 link.link_speed = ETH_SPEED_NUM_40G;
3859                 break;
3860         case ICE_AQ_LINK_SPEED_50GB:
3861                 link.link_speed = ETH_SPEED_NUM_50G;
3862                 break;
3863         case ICE_AQ_LINK_SPEED_100GB:
3864                 link.link_speed = ETH_SPEED_NUM_100G;
3865                 break;
3866         case ICE_AQ_LINK_SPEED_UNKNOWN:
3867                 PMD_DRV_LOG(ERR, "Unknown link speed");
3868                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3869                 break;
3870         default:
3871                 PMD_DRV_LOG(ERR, "None link speed");
3872                 link.link_speed = ETH_SPEED_NUM_NONE;
3873                 break;
3874         }
3875
3876         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3877                               ETH_LINK_SPEED_FIXED);
3878
3879 out:
3880         ice_atomic_write_link_status(dev, &link);
3881         if (link.link_status == old.link_status)
3882                 return -1;
3883
3884         return 0;
3885 }
3886
3887 /* Force the physical link state by getting the current PHY capabilities from
3888  * hardware and setting the PHY config based on the determined capabilities. If
3889  * link changes, link event will be triggered because both the Enable Automatic
3890  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3891  */
3892 static enum ice_status
3893 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3894 {
3895         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3896         struct ice_aqc_get_phy_caps_data *pcaps;
3897         struct ice_port_info *pi;
3898         enum ice_status status;
3899
3900         if (!hw || !hw->port_info)
3901                 return ICE_ERR_PARAM;
3902
3903         pi = hw->port_info;
3904
3905         pcaps = (struct ice_aqc_get_phy_caps_data *)
3906                 ice_malloc(hw, sizeof(*pcaps));
3907         if (!pcaps)
3908                 return ICE_ERR_NO_MEMORY;
3909
3910         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3911                                      pcaps, NULL);
3912         if (status)
3913                 goto out;
3914
3915         /* No change in link */
3916         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3917             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3918                 goto out;
3919
3920         cfg.phy_type_low = pcaps->phy_type_low;
3921         cfg.phy_type_high = pcaps->phy_type_high;
3922         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3923         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3924         cfg.eee_cap = pcaps->eee_cap;
3925         cfg.eeer_value = pcaps->eeer_value;
3926         cfg.link_fec_opt = pcaps->link_fec_options;
3927         if (link_up)
3928                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3929         else
3930                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3931
3932         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3933
3934 out:
3935         ice_free(hw, pcaps);
3936         return status;
3937 }
3938
3939 static int
3940 ice_dev_set_link_up(struct rte_eth_dev *dev)
3941 {
3942         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943
3944         return ice_force_phys_link_state(hw, true);
3945 }
3946
3947 static int
3948 ice_dev_set_link_down(struct rte_eth_dev *dev)
3949 {
3950         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951
3952         return ice_force_phys_link_state(hw, false);
3953 }
3954
3955 static int
3956 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3957 {
3958         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3959         struct rte_eth_dev_data *dev_data = pf->dev_data;
3960         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3961
3962         /* check if mtu is within the allowed range */
3963         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3964                 return -EINVAL;
3965
3966         /* mtu setting is forbidden if port is start */
3967         if (dev_data->dev_started) {
3968                 PMD_DRV_LOG(ERR,
3969                             "port %d must be stopped before configuration",
3970                             dev_data->port_id);
3971                 return -EBUSY;
3972         }
3973
3974         if (frame_size > ICE_ETH_MAX_LEN)
3975                 dev_data->dev_conf.rxmode.offloads |=
3976                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3977         else
3978                 dev_data->dev_conf.rxmode.offloads &=
3979                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3980
3981         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3982
3983         return 0;
3984 }
3985
3986 static int ice_macaddr_set(struct rte_eth_dev *dev,
3987                            struct rte_ether_addr *mac_addr)
3988 {
3989         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3991         struct ice_vsi *vsi = pf->main_vsi;
3992         struct ice_mac_filter *f;
3993         uint8_t flags = 0;
3994         int ret;
3995
3996         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3997                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3998                 return -EINVAL;
3999         }
4000
4001         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4002                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
4003                         break;
4004         }
4005
4006         if (!f) {
4007                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
4008                 return -EIO;
4009         }
4010
4011         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
4012         if (ret != ICE_SUCCESS) {
4013                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
4014                 return -EIO;
4015         }
4016         ret = ice_add_mac_filter(vsi, mac_addr);
4017         if (ret != ICE_SUCCESS) {
4018                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
4019                 return -EIO;
4020         }
4021         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
4022
4023         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
4024         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
4025         if (ret != ICE_SUCCESS)
4026                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
4027
4028         return 0;
4029 }
4030
4031 /* Add a MAC address, and update filters */
4032 static int
4033 ice_macaddr_add(struct rte_eth_dev *dev,
4034                 struct rte_ether_addr *mac_addr,
4035                 __rte_unused uint32_t index,
4036                 __rte_unused uint32_t pool)
4037 {
4038         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4039         struct ice_vsi *vsi = pf->main_vsi;
4040         int ret;
4041
4042         ret = ice_add_mac_filter(vsi, mac_addr);
4043         if (ret != ICE_SUCCESS) {
4044                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
4045                 return -EINVAL;
4046         }
4047
4048         return ICE_SUCCESS;
4049 }
4050
4051 /* Remove a MAC address, and update filters */
4052 static void
4053 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4054 {
4055         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4056         struct ice_vsi *vsi = pf->main_vsi;
4057         struct rte_eth_dev_data *data = dev->data;
4058         struct rte_ether_addr *macaddr;
4059         int ret;
4060
4061         macaddr = &data->mac_addrs[index];
4062         ret = ice_remove_mac_filter(vsi, macaddr);
4063         if (ret) {
4064                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4065                 return;
4066         }
4067 }
4068
4069 static int
4070 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4071 {
4072         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4073         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
4074         struct ice_vsi *vsi = pf->main_vsi;
4075         int ret;
4076
4077         PMD_INIT_FUNC_TRACE();
4078
4079         /**
4080          * Vlan 0 is the generic filter for untagged packets
4081          * and can't be removed or added by user.
4082          */
4083         if (vlan_id == 0)
4084                 return 0;
4085
4086         if (on) {
4087                 ret = ice_add_vlan_filter(vsi, &vlan);
4088                 if (ret < 0) {
4089                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4090                         return -EINVAL;
4091                 }
4092         } else {
4093                 ret = ice_remove_vlan_filter(vsi, &vlan);
4094                 if (ret < 0) {
4095                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4096                         return -EINVAL;
4097                 }
4098         }
4099
4100         return 0;
4101 }
4102
4103 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
4104  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
4105  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
4106  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
4107  *
4108  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
4109  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
4110  * traffic in SVM, since the VLAN TPID isn't part of filtering.
4111  *
4112  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
4113  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
4114  * part of filtering.
4115  */
4116 static int
4117 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
4118 {
4119         struct ice_vlan vlan;
4120         int err;
4121
4122         vlan = ICE_VLAN(0, 0);
4123         err = ice_add_vlan_filter(vsi, &vlan);
4124         if (err) {
4125                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
4126                 return err;
4127         }
4128
4129         /* in SVM both VLAN 0 filters are identical */
4130         if (!ice_is_dvm_ena(&vsi->adapter->hw))
4131                 return 0;
4132
4133         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4134         err = ice_add_vlan_filter(vsi, &vlan);
4135         if (err) {
4136                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
4137                 return err;
4138         }
4139
4140         return 0;
4141 }
4142
4143 /*
4144  * Delete the VLAN 0 filters in the same manner that they were added in
4145  * ice_vsi_add_vlan_zero.
4146  */
4147 static int
4148 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
4149 {
4150         struct ice_vlan vlan;
4151         int err;
4152
4153         vlan = ICE_VLAN(0, 0);
4154         err = ice_remove_vlan_filter(vsi, &vlan);
4155         if (err) {
4156                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4157                 return err;
4158         }
4159
4160         /* in SVM both VLAN 0 filters are identical */
4161         if (!ice_is_dvm_ena(&vsi->adapter->hw))
4162                 return 0;
4163
4164         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4165         err = ice_remove_vlan_filter(vsi, &vlan);
4166         if (err) {
4167                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4168                 return err;
4169         }
4170
4171         return 0;
4172 }
4173
4174 /* Configure vlan filter on or off */
4175 static int
4176 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4177 {
4178         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4179         struct ice_vsi_ctx ctxt;
4180         uint8_t sw_flags2;
4181         int ret = 0;
4182
4183         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4184
4185         if (on)
4186                 vsi->info.sw_flags2 |= sw_flags2;
4187         else
4188                 vsi->info.sw_flags2 &= ~sw_flags2;
4189
4190         vsi->info.sw_id = hw->port_info->sw_id;
4191         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4192         ctxt.info.valid_sections =
4193                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4194                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4195         ctxt.vsi_num = vsi->vsi_id;
4196
4197         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4198         if (ret) {
4199                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4200                             on ? "enable" : "disable");
4201                 return -EINVAL;
4202         } else {
4203                 vsi->info.valid_sections |=
4204                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4205                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4206         }
4207
4208         /* consist with other drivers, allow untagged packet when vlan filter on */
4209         if (on)
4210                 ret = ice_vsi_add_vlan_zero(vsi);
4211         else
4212                 ret = ice_vsi_del_vlan_zero(vsi);
4213
4214         return 0;
4215 }
4216
4217 /* Manage VLAN stripping for the VSI for Rx */
4218 static int
4219 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4220 {
4221         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4222         struct ice_vsi_ctx ctxt;
4223         enum ice_status status;
4224         int err = 0;
4225
4226         /* do not allow modifying VLAN stripping when a port VLAN is configured
4227          * on this VSI
4228          */
4229         if (vsi->info.port_based_inner_vlan)
4230                 return 0;
4231
4232         memset(&ctxt, 0, sizeof(ctxt));
4233
4234         if (ena)
4235                 /* Strip VLAN tag from Rx packet and put it in the desc */
4236                 ctxt.info.inner_vlan_flags =
4237                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4238         else
4239                 /* Disable stripping. Leave tag in packet */
4240                 ctxt.info.inner_vlan_flags =
4241                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4242
4243         /* Allow all packets untagged/tagged */
4244         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4245
4246         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4247
4248         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4249         if (status) {
4250                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4251                             ena ? "enable" : "disable");
4252                 err = -EIO;
4253         } else {
4254                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4255         }
4256
4257         return err;
4258 }
4259
4260 static int
4261 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4262 {
4263         return ice_vsi_manage_vlan_stripping(vsi, true);
4264 }
4265
4266 static int
4267 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4268 {
4269         return ice_vsi_manage_vlan_stripping(vsi, false);
4270 }
4271
4272 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4273 {
4274         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4275         struct ice_vsi_ctx ctxt;
4276         enum ice_status status;
4277         int err = 0;
4278
4279         /* do not allow modifying VLAN stripping when a port VLAN is configured
4280          * on this VSI
4281          */
4282         if (vsi->info.port_based_outer_vlan)
4283                 return 0;
4284
4285         memset(&ctxt, 0, sizeof(ctxt));
4286
4287         ctxt.info.valid_sections =
4288                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4289         /* clear current outer VLAN strip settings */
4290         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4291                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4292         ctxt.info.outer_vlan_flags |=
4293                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4294                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4295                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4296                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4297
4298         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4299         if (status) {
4300                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4301                 err = -EIO;
4302         } else {
4303                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4304         }
4305
4306         return err;
4307 }
4308
4309 static int
4310 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4311 {
4312         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4313         struct ice_vsi_ctx ctxt;
4314         enum ice_status status;
4315         int err = 0;
4316
4317         if (vsi->info.port_based_outer_vlan)
4318                 return 0;
4319
4320         memset(&ctxt, 0, sizeof(ctxt));
4321
4322         ctxt.info.valid_sections =
4323                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4324         /* clear current outer VLAN strip settings */
4325         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4326                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4327         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4328                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4329
4330         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4331         if (status) {
4332                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4333                 err = -EIO;
4334         } else {
4335                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4336         }
4337
4338         return err;
4339 }
4340
4341 static int
4342 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4343 {
4344         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4345         int ret;
4346
4347         if (ice_is_dvm_ena(hw)) {
4348                 if (ena)
4349                         ret = ice_vsi_ena_outer_stripping(vsi);
4350                 else
4351                         ret = ice_vsi_dis_outer_stripping(vsi);
4352         } else {
4353                 if (ena)
4354                         ret = ice_vsi_ena_inner_stripping(vsi);
4355                 else
4356                         ret = ice_vsi_dis_inner_stripping(vsi);
4357         }
4358
4359         return ret;
4360 }
4361
4362 static int
4363 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4364 {
4365         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4366         struct ice_vsi *vsi = pf->main_vsi;
4367         struct rte_eth_rxmode *rxmode;
4368
4369         rxmode = &dev->data->dev_conf.rxmode;
4370         if (mask & ETH_VLAN_FILTER_MASK) {
4371                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4372                         ice_vsi_config_vlan_filter(vsi, true);
4373                 else
4374                         ice_vsi_config_vlan_filter(vsi, false);
4375         }
4376
4377         if (mask & ETH_VLAN_STRIP_MASK) {
4378                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4379                         ice_vsi_config_vlan_stripping(vsi, true);
4380                 else
4381                         ice_vsi_config_vlan_stripping(vsi, false);
4382         }
4383
4384         return 0;
4385 }
4386
4387 static int
4388 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4389 {
4390         struct ice_aq_get_set_rss_lut_params lut_params;
4391         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4392         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4393         int ret;
4394
4395         if (!lut)
4396                 return -EINVAL;
4397
4398         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4399                 lut_params.vsi_handle = vsi->idx;
4400                 lut_params.lut_size = lut_size;
4401                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4402                 lut_params.lut = lut;
4403                 lut_params.global_lut_id = 0;
4404                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4405                 if (ret) {
4406                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4407                         return -EINVAL;
4408                 }
4409         } else {
4410                 uint64_t *lut_dw = (uint64_t *)lut;
4411                 uint16_t i, lut_size_dw = lut_size / 4;
4412
4413                 for (i = 0; i < lut_size_dw; i++)
4414                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4415         }
4416
4417         return 0;
4418 }
4419
4420 static int
4421 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4422 {
4423         struct ice_aq_get_set_rss_lut_params lut_params;
4424         struct ice_pf *pf;
4425         struct ice_hw *hw;
4426         int ret;
4427
4428         if (!vsi || !lut)
4429                 return -EINVAL;
4430
4431         pf = ICE_VSI_TO_PF(vsi);
4432         hw = ICE_VSI_TO_HW(vsi);
4433
4434         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4435                 lut_params.vsi_handle = vsi->idx;
4436                 lut_params.lut_size = lut_size;
4437                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4438                 lut_params.lut = lut;
4439                 lut_params.global_lut_id = 0;
4440                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4441                 if (ret) {
4442                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4443                         return -EINVAL;
4444                 }
4445         } else {
4446                 uint64_t *lut_dw = (uint64_t *)lut;
4447                 uint16_t i, lut_size_dw = lut_size / 4;
4448
4449                 for (i = 0; i < lut_size_dw; i++)
4450                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4451
4452                 ice_flush(hw);
4453         }
4454
4455         return 0;
4456 }
4457
4458 static int
4459 ice_rss_reta_update(struct rte_eth_dev *dev,
4460                     struct rte_eth_rss_reta_entry64 *reta_conf,
4461                     uint16_t reta_size)
4462 {
4463         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4464         uint16_t i, lut_size = pf->hash_lut_size;
4465         uint16_t idx, shift;
4466         uint8_t *lut;
4467         int ret;
4468
4469         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4470             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4471             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4472                 PMD_DRV_LOG(ERR,
4473                             "The size of hash lookup table configured (%d)"
4474                             "doesn't match the number hardware can "
4475                             "supported (128, 512, 2048)",
4476                             reta_size);
4477                 return -EINVAL;
4478         }
4479
4480         /* It MUST use the current LUT size to get the RSS lookup table,
4481          * otherwise if will fail with -100 error code.
4482          */
4483         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4484         if (!lut) {
4485                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4486                 return -ENOMEM;
4487         }
4488         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4489         if (ret)
4490                 goto out;
4491
4492         for (i = 0; i < reta_size; i++) {
4493                 idx = i / RTE_RETA_GROUP_SIZE;
4494                 shift = i % RTE_RETA_GROUP_SIZE;
4495                 if (reta_conf[idx].mask & (1ULL << shift))
4496                         lut[i] = reta_conf[idx].reta[shift];
4497         }
4498         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4499         if (ret == 0 && lut_size != reta_size) {
4500                 PMD_DRV_LOG(INFO,
4501                             "The size of hash lookup table is changed from (%d) to (%d)",
4502                             lut_size, reta_size);
4503                 pf->hash_lut_size = reta_size;
4504         }
4505
4506 out:
4507         rte_free(lut);
4508
4509         return ret;
4510 }
4511
4512 static int
4513 ice_rss_reta_query(struct rte_eth_dev *dev,
4514                    struct rte_eth_rss_reta_entry64 *reta_conf,
4515                    uint16_t reta_size)
4516 {
4517         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4518         uint16_t i, lut_size = pf->hash_lut_size;
4519         uint16_t idx, shift;
4520         uint8_t *lut;
4521         int ret;
4522
4523         if (reta_size != lut_size) {
4524                 PMD_DRV_LOG(ERR,
4525                             "The size of hash lookup table configured (%d)"
4526                             "doesn't match the number hardware can "
4527                             "supported (%d)",
4528                             reta_size, lut_size);
4529                 return -EINVAL;
4530         }
4531
4532         lut = rte_zmalloc(NULL, reta_size, 0);
4533         if (!lut) {
4534                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4535                 return -ENOMEM;
4536         }
4537
4538         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4539         if (ret)
4540                 goto out;
4541
4542         for (i = 0; i < reta_size; i++) {
4543                 idx = i / RTE_RETA_GROUP_SIZE;
4544                 shift = i % RTE_RETA_GROUP_SIZE;
4545                 if (reta_conf[idx].mask & (1ULL << shift))
4546                         reta_conf[idx].reta[shift] = lut[i];
4547         }
4548
4549 out:
4550         rte_free(lut);
4551
4552         return ret;
4553 }
4554
4555 static int
4556 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4557 {
4558         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4559         int ret = 0;
4560
4561         if (!key || key_len == 0) {
4562                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4563                 return 0;
4564         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4565                    sizeof(uint32_t)) {
4566                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4567                 return -EINVAL;
4568         }
4569
4570         struct ice_aqc_get_set_rss_keys *key_dw =
4571                 (struct ice_aqc_get_set_rss_keys *)key;
4572
4573         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4574         if (ret) {
4575                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4576                 ret = -EINVAL;
4577         }
4578
4579         return ret;
4580 }
4581
4582 static int
4583 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4584 {
4585         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4586         int ret;
4587
4588         if (!key || !key_len)
4589                 return -EINVAL;
4590
4591         ret = ice_aq_get_rss_key
4592                 (hw, vsi->idx,
4593                  (struct ice_aqc_get_set_rss_keys *)key);
4594         if (ret) {
4595                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4596                 return -EINVAL;
4597         }
4598         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4599
4600         return 0;
4601 }
4602
4603 static int
4604 ice_rss_hash_update(struct rte_eth_dev *dev,
4605                     struct rte_eth_rss_conf *rss_conf)
4606 {
4607         enum ice_status status = ICE_SUCCESS;
4608         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4609         struct ice_vsi *vsi = pf->main_vsi;
4610
4611         /* set hash key */
4612         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4613         if (status)
4614                 return status;
4615
4616         if (rss_conf->rss_hf == 0) {
4617                 pf->rss_hf = 0;
4618                 return 0;
4619         }
4620
4621         /* RSS hash configuration */
4622         ice_rss_hash_set(pf, rss_conf->rss_hf);
4623
4624         return 0;
4625 }
4626
4627 static int
4628 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4629                       struct rte_eth_rss_conf *rss_conf)
4630 {
4631         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4632         struct ice_vsi *vsi = pf->main_vsi;
4633
4634         ice_get_rss_key(vsi, rss_conf->rss_key,
4635                         &rss_conf->rss_key_len);
4636
4637         rss_conf->rss_hf = pf->rss_hf;
4638         return 0;
4639 }
4640
4641 static int
4642 ice_promisc_enable(struct rte_eth_dev *dev)
4643 {
4644         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4645         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646         struct ice_vsi *vsi = pf->main_vsi;
4647         enum ice_status status;
4648         uint8_t pmask;
4649         int ret = 0;
4650
4651         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4652                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4653
4654         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4655         switch (status) {
4656         case ICE_ERR_ALREADY_EXISTS:
4657                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4658         case ICE_SUCCESS:
4659                 break;
4660         default:
4661                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4662                 ret = -EAGAIN;
4663         }
4664
4665         return ret;
4666 }
4667
4668 static int
4669 ice_promisc_disable(struct rte_eth_dev *dev)
4670 {
4671         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4672         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4673         struct ice_vsi *vsi = pf->main_vsi;
4674         enum ice_status status;
4675         uint8_t pmask;
4676         int ret = 0;
4677
4678         if (dev->data->all_multicast == 1)
4679                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4680         else
4681                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4682                         ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4683
4684         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4685         if (status != ICE_SUCCESS) {
4686                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4687                 ret = -EAGAIN;
4688         }
4689
4690         return ret;
4691 }
4692
4693 static int
4694 ice_allmulti_enable(struct rte_eth_dev *dev)
4695 {
4696         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4697         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct ice_vsi *vsi = pf->main_vsi;
4699         enum ice_status status;
4700         uint8_t pmask;
4701         int ret = 0;
4702
4703         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4704
4705         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4706
4707         switch (status) {
4708         case ICE_ERR_ALREADY_EXISTS:
4709                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4710         case ICE_SUCCESS:
4711                 break;
4712         default:
4713                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4714                 ret = -EAGAIN;
4715         }
4716
4717         return ret;
4718 }
4719
4720 static int
4721 ice_allmulti_disable(struct rte_eth_dev *dev)
4722 {
4723         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4724         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725         struct ice_vsi *vsi = pf->main_vsi;
4726         enum ice_status status;
4727         uint8_t pmask;
4728         int ret = 0;
4729
4730         if (dev->data->promiscuous == 1)
4731                 return 0; /* must remain in all_multicast mode */
4732
4733         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4734
4735         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4736         if (status != ICE_SUCCESS) {
4737                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4738                 ret = -EAGAIN;
4739         }
4740
4741         return ret;
4742 }
4743
4744 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4745                                     uint16_t queue_id)
4746 {
4747         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4748         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4749         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750         uint32_t val;
4751         uint16_t msix_intr;
4752
4753         msix_intr = intr_handle->intr_vec[queue_id];
4754
4755         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4756               GLINT_DYN_CTL_ITR_INDX_M;
4757         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4758
4759         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4760         rte_intr_ack(&pci_dev->intr_handle);
4761
4762         return 0;
4763 }
4764
4765 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4766                                      uint16_t queue_id)
4767 {
4768         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4770         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771         uint16_t msix_intr;
4772
4773         msix_intr = intr_handle->intr_vec[queue_id];
4774
4775         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4776
4777         return 0;
4778 }
4779
4780 static int
4781 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4782 {
4783         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784         u8 ver, patch;
4785         u16 build;
4786         int ret;
4787
4788         ver = hw->flash.orom.major;
4789         patch = hw->flash.orom.patch;
4790         build = hw->flash.orom.build;
4791
4792         ret = snprintf(fw_version, fw_size,
4793                         "%x.%02x 0x%08x %d.%d.%d",
4794                         hw->flash.nvm.major,
4795                         hw->flash.nvm.minor,
4796                         hw->flash.nvm.eetrack,
4797                         ver, build, patch);
4798         if (ret < 0)
4799                 return -EINVAL;
4800
4801         /* add the size of '\0' */
4802         ret += 1;
4803         if (fw_size < (size_t)ret)
4804                 return ret;
4805         else
4806                 return 0;
4807 }
4808
4809 static int
4810 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4811 {
4812         struct ice_hw *hw;
4813         struct ice_vsi_ctx ctxt;
4814         uint8_t vlan_flags = 0;
4815         int ret;
4816
4817         if (!vsi || !info) {
4818                 PMD_DRV_LOG(ERR, "invalid parameters");
4819                 return -EINVAL;
4820         }
4821
4822         if (info->on) {
4823                 vsi->info.port_based_inner_vlan = info->config.pvid;
4824                 /**
4825                  * If insert pvid is enabled, only tagged pkts are
4826                  * allowed to be sent out.
4827                  */
4828                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4829                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4830         } else {
4831                 vsi->info.port_based_inner_vlan = 0;
4832                 if (info->config.reject.tagged == 0)
4833                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4834
4835                 if (info->config.reject.untagged == 0)
4836                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4837         }
4838         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4839                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4840         vsi->info.inner_vlan_flags |= vlan_flags;
4841         memset(&ctxt, 0, sizeof(ctxt));
4842         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4843         ctxt.info.valid_sections =
4844                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4845         ctxt.vsi_num = vsi->vsi_id;
4846
4847         hw = ICE_VSI_TO_HW(vsi);
4848         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4849         if (ret != ICE_SUCCESS) {
4850                 PMD_DRV_LOG(ERR,
4851                             "update VSI for VLAN insert failed, err %d",
4852                             ret);
4853                 return -EINVAL;
4854         }
4855
4856         vsi->info.valid_sections |=
4857                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4858
4859         return ret;
4860 }
4861
4862 static int
4863 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4864 {
4865         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4866         struct ice_vsi *vsi = pf->main_vsi;
4867         struct rte_eth_dev_data *data = pf->dev_data;
4868         struct ice_vsi_vlan_pvid_info info;
4869         int ret;
4870
4871         memset(&info, 0, sizeof(info));
4872         info.on = on;
4873         if (info.on) {
4874                 info.config.pvid = pvid;
4875         } else {
4876                 info.config.reject.tagged =
4877                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4878                 info.config.reject.untagged =
4879                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4880         }
4881
4882         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4883         if (ret < 0) {
4884                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4885                 return -EINVAL;
4886         }
4887
4888         return 0;
4889 }
4890
4891 static int
4892 ice_get_eeprom_length(struct rte_eth_dev *dev)
4893 {
4894         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895
4896         return hw->flash.flash_size;
4897 }
4898
4899 static int
4900 ice_get_eeprom(struct rte_eth_dev *dev,
4901                struct rte_dev_eeprom_info *eeprom)
4902 {
4903         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         enum ice_status status = ICE_SUCCESS;
4905         uint8_t *data = eeprom->data;
4906
4907         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4908
4909         status = ice_acquire_nvm(hw, ICE_RES_READ);
4910         if (status) {
4911                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4912                 return -EIO;
4913         }
4914
4915         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4916                                    data, false);
4917
4918         ice_release_nvm(hw);
4919
4920         if (status) {
4921                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4922                 return -EIO;
4923         }
4924
4925         return 0;
4926 }
4927
4928 static void
4929 ice_stat_update_32(struct ice_hw *hw,
4930                    uint32_t reg,
4931                    bool offset_loaded,
4932                    uint64_t *offset,
4933                    uint64_t *stat)
4934 {
4935         uint64_t new_data;
4936
4937         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4938         if (!offset_loaded)
4939                 *offset = new_data;
4940
4941         if (new_data >= *offset)
4942                 *stat = (uint64_t)(new_data - *offset);
4943         else
4944                 *stat = (uint64_t)((new_data +
4945                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4946                                    - *offset);
4947 }
4948
4949 static void
4950 ice_stat_update_40(struct ice_hw *hw,
4951                    uint32_t hireg,
4952                    uint32_t loreg,
4953                    bool offset_loaded,
4954                    uint64_t *offset,
4955                    uint64_t *stat)
4956 {
4957         uint64_t new_data;
4958
4959         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4960         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4961                     ICE_32_BIT_WIDTH;
4962
4963         if (!offset_loaded)
4964                 *offset = new_data;
4965
4966         if (new_data >= *offset)
4967                 *stat = new_data - *offset;
4968         else
4969                 *stat = (uint64_t)((new_data +
4970                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4971                                    *offset);
4972
4973         *stat &= ICE_40_BIT_MASK;
4974 }
4975
4976 /* Get all the statistics of a VSI */
4977 static void
4978 ice_update_vsi_stats(struct ice_vsi *vsi)
4979 {
4980         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4981         struct ice_eth_stats *nes = &vsi->eth_stats;
4982         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4983         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4984
4985         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4986                            vsi->offset_loaded, &oes->rx_bytes,
4987                            &nes->rx_bytes);
4988         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4989                            vsi->offset_loaded, &oes->rx_unicast,
4990                            &nes->rx_unicast);
4991         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4992                            vsi->offset_loaded, &oes->rx_multicast,
4993                            &nes->rx_multicast);
4994         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4995                            vsi->offset_loaded, &oes->rx_broadcast,
4996                            &nes->rx_broadcast);
4997         /* enlarge the limitation when rx_bytes overflowed */
4998         if (vsi->offset_loaded) {
4999                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
5000                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5001                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
5002         }
5003         vsi->old_rx_bytes = nes->rx_bytes;
5004         /* exclude CRC bytes */
5005         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
5006                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
5007
5008         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
5009                            &oes->rx_discards, &nes->rx_discards);
5010         /* GLV_REPC not supported */
5011         /* GLV_RMPC not supported */
5012         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
5013                            &oes->rx_unknown_protocol,
5014                            &nes->rx_unknown_protocol);
5015         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
5016                            vsi->offset_loaded, &oes->tx_bytes,
5017                            &nes->tx_bytes);
5018         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
5019                            vsi->offset_loaded, &oes->tx_unicast,
5020                            &nes->tx_unicast);
5021         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
5022                            vsi->offset_loaded, &oes->tx_multicast,
5023                            &nes->tx_multicast);
5024         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
5025                            vsi->offset_loaded,  &oes->tx_broadcast,
5026                            &nes->tx_broadcast);
5027         /* GLV_TDPC not supported */
5028         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
5029                            &oes->tx_errors, &nes->tx_errors);
5030         /* enlarge the limitation when tx_bytes overflowed */
5031         if (vsi->offset_loaded) {
5032                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
5033                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5034                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
5035         }
5036         vsi->old_tx_bytes = nes->tx_bytes;
5037         vsi->offset_loaded = true;
5038
5039         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
5040                     vsi->vsi_id);
5041         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
5042         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
5043         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
5044         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
5045         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
5046         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5047                     nes->rx_unknown_protocol);
5048         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
5049         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
5050         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
5051         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
5052         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
5053         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
5054         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
5055                     vsi->vsi_id);
5056 }
5057
5058 static void
5059 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
5060 {
5061         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5062         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
5063
5064         /* Get statistics of struct ice_eth_stats */
5065         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
5066                            GLPRT_GORCL(hw->port_info->lport),
5067                            pf->offset_loaded, &os->eth.rx_bytes,
5068                            &ns->eth.rx_bytes);
5069         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
5070                            GLPRT_UPRCL(hw->port_info->lport),
5071                            pf->offset_loaded, &os->eth.rx_unicast,
5072                            &ns->eth.rx_unicast);
5073         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
5074                            GLPRT_MPRCL(hw->port_info->lport),
5075                            pf->offset_loaded, &os->eth.rx_multicast,
5076                            &ns->eth.rx_multicast);
5077         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
5078                            GLPRT_BPRCL(hw->port_info->lport),
5079                            pf->offset_loaded, &os->eth.rx_broadcast,
5080                            &ns->eth.rx_broadcast);
5081         ice_stat_update_32(hw, PRTRPB_RDPC,
5082                            pf->offset_loaded, &os->eth.rx_discards,
5083                            &ns->eth.rx_discards);
5084         /* enlarge the limitation when rx_bytes overflowed */
5085         if (pf->offset_loaded) {
5086                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
5087                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5088                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
5089         }
5090         pf->old_rx_bytes = ns->eth.rx_bytes;
5091
5092         /* Workaround: CRC size should not be included in byte statistics,
5093          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
5094          * packet.
5095          */
5096         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
5097                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
5098
5099         /* GLPRT_REPC not supported */
5100         /* GLPRT_RMPC not supported */
5101         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
5102                            pf->offset_loaded,
5103                            &os->eth.rx_unknown_protocol,
5104                            &ns->eth.rx_unknown_protocol);
5105         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
5106                            GLPRT_GOTCL(hw->port_info->lport),
5107                            pf->offset_loaded, &os->eth.tx_bytes,
5108                            &ns->eth.tx_bytes);
5109         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
5110                            GLPRT_UPTCL(hw->port_info->lport),
5111                            pf->offset_loaded, &os->eth.tx_unicast,
5112                            &ns->eth.tx_unicast);
5113         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
5114                            GLPRT_MPTCL(hw->port_info->lport),
5115                            pf->offset_loaded, &os->eth.tx_multicast,
5116                            &ns->eth.tx_multicast);
5117         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
5118                            GLPRT_BPTCL(hw->port_info->lport),
5119                            pf->offset_loaded, &os->eth.tx_broadcast,
5120                            &ns->eth.tx_broadcast);
5121         /* enlarge the limitation when tx_bytes overflowed */
5122         if (pf->offset_loaded) {
5123                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
5124                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5125                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
5126         }
5127         pf->old_tx_bytes = ns->eth.tx_bytes;
5128         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
5129                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
5130
5131         /* GLPRT_TEPC not supported */
5132
5133         /* additional port specific stats */
5134         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
5135                            pf->offset_loaded, &os->tx_dropped_link_down,
5136                            &ns->tx_dropped_link_down);
5137         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
5138                            pf->offset_loaded, &os->crc_errors,
5139                            &ns->crc_errors);
5140         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
5141                            pf->offset_loaded, &os->illegal_bytes,
5142                            &ns->illegal_bytes);
5143         /* GLPRT_ERRBC not supported */
5144         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
5145                            pf->offset_loaded, &os->mac_local_faults,
5146                            &ns->mac_local_faults);
5147         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
5148                            pf->offset_loaded, &os->mac_remote_faults,
5149                            &ns->mac_remote_faults);
5150
5151         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
5152                            pf->offset_loaded, &os->rx_len_errors,
5153                            &ns->rx_len_errors);
5154
5155         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
5156                            pf->offset_loaded, &os->link_xon_rx,
5157                            &ns->link_xon_rx);
5158         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
5159                            pf->offset_loaded, &os->link_xoff_rx,
5160                            &ns->link_xoff_rx);
5161         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
5162                            pf->offset_loaded, &os->link_xon_tx,
5163                            &ns->link_xon_tx);
5164         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5165                            pf->offset_loaded, &os->link_xoff_tx,
5166                            &ns->link_xoff_tx);
5167         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5168                            GLPRT_PRC64L(hw->port_info->lport),
5169                            pf->offset_loaded, &os->rx_size_64,
5170                            &ns->rx_size_64);
5171         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5172                            GLPRT_PRC127L(hw->port_info->lport),
5173                            pf->offset_loaded, &os->rx_size_127,
5174                            &ns->rx_size_127);
5175         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5176                            GLPRT_PRC255L(hw->port_info->lport),
5177                            pf->offset_loaded, &os->rx_size_255,
5178                            &ns->rx_size_255);
5179         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5180                            GLPRT_PRC511L(hw->port_info->lport),
5181                            pf->offset_loaded, &os->rx_size_511,
5182                            &ns->rx_size_511);
5183         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5184                            GLPRT_PRC1023L(hw->port_info->lport),
5185                            pf->offset_loaded, &os->rx_size_1023,
5186                            &ns->rx_size_1023);
5187         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5188                            GLPRT_PRC1522L(hw->port_info->lport),
5189                            pf->offset_loaded, &os->rx_size_1522,
5190                            &ns->rx_size_1522);
5191         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5192                            GLPRT_PRC9522L(hw->port_info->lport),
5193                            pf->offset_loaded, &os->rx_size_big,
5194                            &ns->rx_size_big);
5195         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5196                            pf->offset_loaded, &os->rx_undersize,
5197                            &ns->rx_undersize);
5198         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5199                            pf->offset_loaded, &os->rx_fragments,
5200                            &ns->rx_fragments);
5201         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5202                            pf->offset_loaded, &os->rx_oversize,
5203                            &ns->rx_oversize);
5204         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5205                            pf->offset_loaded, &os->rx_jabber,
5206                            &ns->rx_jabber);
5207         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5208                            GLPRT_PTC64L(hw->port_info->lport),
5209                            pf->offset_loaded, &os->tx_size_64,
5210                            &ns->tx_size_64);
5211         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5212                            GLPRT_PTC127L(hw->port_info->lport),
5213                            pf->offset_loaded, &os->tx_size_127,
5214                            &ns->tx_size_127);
5215         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5216                            GLPRT_PTC255L(hw->port_info->lport),
5217                            pf->offset_loaded, &os->tx_size_255,
5218                            &ns->tx_size_255);
5219         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5220                            GLPRT_PTC511L(hw->port_info->lport),
5221                            pf->offset_loaded, &os->tx_size_511,
5222                            &ns->tx_size_511);
5223         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5224                            GLPRT_PTC1023L(hw->port_info->lport),
5225                            pf->offset_loaded, &os->tx_size_1023,
5226                            &ns->tx_size_1023);
5227         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5228                            GLPRT_PTC1522L(hw->port_info->lport),
5229                            pf->offset_loaded, &os->tx_size_1522,
5230                            &ns->tx_size_1522);
5231         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5232                            GLPRT_PTC9522L(hw->port_info->lport),
5233                            pf->offset_loaded, &os->tx_size_big,
5234                            &ns->tx_size_big);
5235
5236         /* GLPRT_MSPDC not supported */
5237         /* GLPRT_XEC not supported */
5238
5239         pf->offset_loaded = true;
5240
5241         if (pf->main_vsi)
5242                 ice_update_vsi_stats(pf->main_vsi);
5243 }
5244
5245 /* Get all statistics of a port */
5246 static int
5247 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5248 {
5249         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5250         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5252
5253         /* call read registers - updates values, now write them to struct */
5254         ice_read_stats_registers(pf, hw);
5255
5256         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5257                           pf->main_vsi->eth_stats.rx_multicast +
5258                           pf->main_vsi->eth_stats.rx_broadcast -
5259                           pf->main_vsi->eth_stats.rx_discards;
5260         stats->opackets = ns->eth.tx_unicast +
5261                           ns->eth.tx_multicast +
5262                           ns->eth.tx_broadcast;
5263         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5264         stats->obytes   = ns->eth.tx_bytes;
5265         stats->oerrors  = ns->eth.tx_errors +
5266                           pf->main_vsi->eth_stats.tx_errors;
5267
5268         /* Rx Errors */
5269         stats->imissed  = ns->eth.rx_discards +
5270                           pf->main_vsi->eth_stats.rx_discards;
5271         stats->ierrors  = ns->crc_errors +
5272                           ns->rx_undersize +
5273                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5274
5275         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5276         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5277         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5278         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5279         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5280         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5281         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5282                     pf->main_vsi->eth_stats.rx_discards);
5283         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5284                     ns->eth.rx_unknown_protocol);
5285         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5286         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5287         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5288         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5289         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5290         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5291                     pf->main_vsi->eth_stats.tx_discards);
5292         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5293
5294         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5295                     ns->tx_dropped_link_down);
5296         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5297         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5298                     ns->illegal_bytes);
5299         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5300         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5301                     ns->mac_local_faults);
5302         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5303                     ns->mac_remote_faults);
5304         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5305         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5306         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5307         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5308         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5309         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5310         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5311         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5312         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5313         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5314         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5315         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5316         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5317         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5318         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5319         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5320         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5321         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5322         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5323         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5324         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5325         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5326         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5327         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5328         return 0;
5329 }
5330
5331 /* Reset the statistics */
5332 static int
5333 ice_stats_reset(struct rte_eth_dev *dev)
5334 {
5335         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5337
5338         /* Mark PF and VSI stats to update the offset, aka "reset" */
5339         pf->offset_loaded = false;
5340         if (pf->main_vsi)
5341                 pf->main_vsi->offset_loaded = false;
5342
5343         /* read the stats, reading current register values into offset */
5344         ice_read_stats_registers(pf, hw);
5345
5346         return 0;
5347 }
5348
5349 static uint32_t
5350 ice_xstats_calc_num(void)
5351 {
5352         uint32_t num;
5353
5354         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5355
5356         return num;
5357 }
5358
5359 static int
5360 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5361                unsigned int n)
5362 {
5363         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5364         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365         unsigned int i;
5366         unsigned int count;
5367         struct ice_hw_port_stats *hw_stats = &pf->stats;
5368
5369         count = ice_xstats_calc_num();
5370         if (n < count)
5371                 return count;
5372
5373         ice_read_stats_registers(pf, hw);
5374
5375         if (!xstats)
5376                 return 0;
5377
5378         count = 0;
5379
5380         /* Get stats from ice_eth_stats struct */
5381         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5382                 xstats[count].value =
5383                         *(uint64_t *)((char *)&hw_stats->eth +
5384                                       ice_stats_strings[i].offset);
5385                 xstats[count].id = count;
5386                 count++;
5387         }
5388
5389         /* Get individiual stats from ice_hw_port struct */
5390         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5391                 xstats[count].value =
5392                         *(uint64_t *)((char *)hw_stats +
5393                                       ice_hw_port_strings[i].offset);
5394                 xstats[count].id = count;
5395                 count++;
5396         }
5397
5398         return count;
5399 }
5400
5401 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5402                                 struct rte_eth_xstat_name *xstats_names,
5403                                 __rte_unused unsigned int limit)
5404 {
5405         unsigned int count = 0;
5406         unsigned int i;
5407
5408         if (!xstats_names)
5409                 return ice_xstats_calc_num();
5410
5411         /* Note: limit checked in rte_eth_xstats_names() */
5412
5413         /* Get stats from ice_eth_stats struct */
5414         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5415                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5416                         sizeof(xstats_names[count].name));
5417                 count++;
5418         }
5419
5420         /* Get individiual stats from ice_hw_port struct */
5421         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5422                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5423                         sizeof(xstats_names[count].name));
5424                 count++;
5425         }
5426
5427         return count;
5428 }
5429
5430 static int
5431 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5432                      const struct rte_flow_ops **ops)
5433 {
5434         if (!dev)
5435                 return -EINVAL;
5436
5437         *ops = &ice_flow_ops;
5438         return 0;
5439 }
5440
5441 /* Add UDP tunneling port */
5442 static int
5443 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5444                              struct rte_eth_udp_tunnel *udp_tunnel)
5445 {
5446         int ret = 0;
5447         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448
5449         if (udp_tunnel == NULL)
5450                 return -EINVAL;
5451
5452         switch (udp_tunnel->prot_type) {
5453         case RTE_TUNNEL_TYPE_VXLAN:
5454                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5455                 break;
5456         default:
5457                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5458                 ret = -EINVAL;
5459                 break;
5460         }
5461
5462         return ret;
5463 }
5464
5465 /* Delete UDP tunneling port */
5466 static int
5467 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5468                              struct rte_eth_udp_tunnel *udp_tunnel)
5469 {
5470         int ret = 0;
5471         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5472
5473         if (udp_tunnel == NULL)
5474                 return -EINVAL;
5475
5476         switch (udp_tunnel->prot_type) {
5477         case RTE_TUNNEL_TYPE_VXLAN:
5478                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5479                 break;
5480         default:
5481                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5482                 ret = -EINVAL;
5483                 break;
5484         }
5485
5486         return ret;
5487 }
5488
5489 static int
5490 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5491               struct rte_pci_device *pci_dev)
5492 {
5493         return rte_eth_dev_pci_generic_probe(pci_dev,
5494                                              sizeof(struct ice_adapter),
5495                                              ice_dev_init);
5496 }
5497
5498 static int
5499 ice_pci_remove(struct rte_pci_device *pci_dev)
5500 {
5501         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5502 }
5503
5504 static struct rte_pci_driver rte_ice_pmd = {
5505         .id_table = pci_id_ice_map,
5506         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5507         .probe = ice_pci_probe,
5508         .remove = ice_pci_remove,
5509 };
5510
5511 /**
5512  * Driver initialization routine.
5513  * Invoked once at EAL init time.
5514  * Register itself as the [Poll Mode] Driver of PCI devices.
5515  */
5516 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5517 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5518 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5519 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5520                               ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5521                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5522                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5523                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
5524                               ICE_RX_LOW_LATENCY_ARG "=<0|1>");
5525
5526 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5527 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5528 #ifdef RTE_ETHDEV_DEBUG_RX
5529 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5530 #endif
5531 #ifdef RTE_ETHDEV_DEBUG_TX
5532 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);
5533 #endif