drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "ice_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  72
  73 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  74 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  75 #define ICE_MAX_RES_DESC_NUM        1024
  76
  77 static int ice_dev_configure(struct rte_eth_dev *dev);
  78 static int ice_dev_start(struct rte_eth_dev *dev);
  79 static void ice_dev_stop(struct rte_eth_dev *dev);
  80 static int ice_dev_close(struct rte_eth_dev *dev);
  81 static int ice_dev_reset(struct rte_eth_dev *dev);
  82 static int ice_dev_info_get(struct rte_eth_dev *dev,
  83                             struct rte_eth_dev_info *dev_info);
  84 static int ice_link_update(struct rte_eth_dev *dev,
  85                            int wait_to_complete);
  86 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  87 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  88
  89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  92                                struct rte_eth_rss_reta_entry64 *reta_conf,
  93                                uint16_t reta_size);
  94 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  95                               struct rte_eth_rss_reta_entry64 *reta_conf,
  96                               uint16_t reta_size);
  97 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  98                                struct rte_eth_rss_conf *rss_conf);
  99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 100                                  struct rte_eth_rss_conf *rss_conf);
 101 static int ice_promisc_enable(struct rte_eth_dev *dev);
 102 static int ice_promisc_disable(struct rte_eth_dev *dev);
 103 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 104 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 105 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 106                                uint16_t vlan_id,
 107                                int on);
 108 static int ice_macaddr_set(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr);
 110 static int ice_macaddr_add(struct rte_eth_dev *dev,
 111                            struct rte_ether_addr *mac_addr,
 112                            __rte_unused uint32_t index,
 113                            uint32_t pool);
 114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 116                                     uint16_t queue_id);
 117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 118                                      uint16_t queue_id);
 119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 120                               size_t fw_size);
 121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 122                              uint16_t pvid, int on);
 123 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 124 static int ice_get_eeprom(struct rte_eth_dev *dev,
 125                           struct rte_dev_eeprom_info *eeprom);
 126 static int ice_stats_get(struct rte_eth_dev *dev,
 127                          struct rte_eth_stats *stats);
 128 static int ice_stats_reset(struct rte_eth_dev *dev);
 129 static int ice_xstats_get(struct rte_eth_dev *dev,
 130                           struct rte_eth_xstat *xstats, unsigned int n);
 131 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 132                                 struct rte_eth_xstat_name *xstats_names,
 133                                 unsigned int limit);
 134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 135                         enum rte_filter_type filter_type,
 136                         enum rte_filter_op filter_op,
 137                         void *arg);
 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 139                         struct rte_eth_udp_tunnel *udp_tunnel);
 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142
 143 static const struct rte_pci_id pci_id_ice_map[] = {
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 164         { .vendor_id = 0, /* sentinel */ },
 165 };
 166
 167 static const struct eth_dev_ops ice_eth_dev_ops = {
 168         .dev_configure                = ice_dev_configure,
 169         .dev_start                    = ice_dev_start,
 170         .dev_stop                     = ice_dev_stop,
 171         .dev_close                    = ice_dev_close,
 172         .dev_reset                    = ice_dev_reset,
 173         .dev_set_link_up              = ice_dev_set_link_up,
 174         .dev_set_link_down            = ice_dev_set_link_down,
 175         .rx_queue_start               = ice_rx_queue_start,
 176         .rx_queue_stop                = ice_rx_queue_stop,
 177         .tx_queue_start               = ice_tx_queue_start,
 178         .tx_queue_stop                = ice_tx_queue_stop,
 179         .rx_queue_setup               = ice_rx_queue_setup,
 180         .rx_queue_release             = ice_rx_queue_release,
 181         .tx_queue_setup               = ice_tx_queue_setup,
 182         .tx_queue_release             = ice_tx_queue_release,
 183         .dev_infos_get                = ice_dev_info_get,
 184         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 185         .link_update                  = ice_link_update,
 186         .mtu_set                      = ice_mtu_set,
 187         .mac_addr_set                 = ice_macaddr_set,
 188         .mac_addr_add                 = ice_macaddr_add,
 189         .mac_addr_remove              = ice_macaddr_remove,
 190         .vlan_filter_set              = ice_vlan_filter_set,
 191         .vlan_offload_set             = ice_vlan_offload_set,
 192         .reta_update                  = ice_rss_reta_update,
 193         .reta_query                   = ice_rss_reta_query,
 194         .rss_hash_update              = ice_rss_hash_update,
 195         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 196         .promiscuous_enable           = ice_promisc_enable,
 197         .promiscuous_disable          = ice_promisc_disable,
 198         .allmulticast_enable          = ice_allmulti_enable,
 199         .allmulticast_disable         = ice_allmulti_disable,
 200         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 201         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 202         .fw_version_get               = ice_fw_version_get,
 203         .vlan_pvid_set                = ice_vlan_pvid_set,
 204         .rxq_info_get                 = ice_rxq_info_get,
 205         .txq_info_get                 = ice_txq_info_get,
 206         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 207         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 208         .get_eeprom_length            = ice_get_eeprom_length,
 209         .get_eeprom                   = ice_get_eeprom,
 210         .stats_get                    = ice_stats_get,
 211         .stats_reset                  = ice_stats_reset,
 212         .xstats_get                   = ice_xstats_get,
 213         .xstats_get_names             = ice_xstats_get_names,
 214         .xstats_reset                 = ice_stats_reset,
 215         .filter_ctrl                  = ice_dev_filter_ctrl,
 216         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 217         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 218         .tx_done_cleanup              = ice_tx_done_cleanup,
 219 };
 220
 221 /* store statistics names and its offset in stats structure */
 222 struct ice_xstats_name_off {
 223         char name[RTE_ETH_XSTATS_NAME_SIZE];
 224         unsigned int offset;
 225 };
 226
 227 static const struct ice_xstats_name_off ice_stats_strings[] = {
 228         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 229         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 230         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 231         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 232         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 233                 rx_unknown_protocol)},
 234         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 235         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 236         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 237         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 238 };
 239
 240 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 241                 sizeof(ice_stats_strings[0]))
 242
 243 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 244         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 245                 tx_dropped_link_down)},
 246         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 247         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 248                 illegal_bytes)},
 249         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 250         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 251                 mac_local_faults)},
 252         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 253                 mac_remote_faults)},
 254         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 255                 rx_len_errors)},
 256         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 257         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 258         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 259         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 260         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 261         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 262                 rx_size_127)},
 263         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_255)},
 265         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_511)},
 267         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_1023)},
 269         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_1522)},
 271         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_big)},
 273         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 274                 rx_undersize)},
 275         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 276                 rx_oversize)},
 277         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 278                 mac_short_pkt_dropped)},
 279         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_fragments)},
 281         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 282         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 283         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 284                 tx_size_127)},
 285         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_255)},
 287         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_511)},
 289         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_1023)},
 291         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_1522)},
 293         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_big)},
 295 };
 296
 297 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 298                 sizeof(ice_hw_port_strings[0]))
 299
 300 static void
 301 ice_init_controlq_parameter(struct ice_hw *hw)
 302 {
 303         /* fields for adminq */
 304         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 305         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 306         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 307         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 308
 309         /* fields for mailboxq, DPDK used as PF host */
 310         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 311         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 312         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 313         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 314 }
 315
 316 static int
 317 lookup_proto_xtr_type(const char *xtr_name)
 318 {
 319         static struct {
 320                 const char *name;
 321                 enum proto_xtr_type type;
 322         } xtr_type_map[] = {
 323                 { "vlan",      PROTO_XTR_VLAN      },
 324                 { "ipv4",      PROTO_XTR_IPV4      },
 325                 { "ipv6",      PROTO_XTR_IPV6      },
 326                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 327                 { "tcp",       PROTO_XTR_TCP       },
 328                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 329         };
 330         uint32_t i;
 331
 332         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 333                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 334                         return xtr_type_map[i].type;
 335         }
 336
 337         return -1;
 338 }
 339
 340 /*
 341  * Parse elem, the elem could be single number/range or '(' ')' group
 342  * 1) A single number elem, it's just a simple digit. e.g. 9
 343  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 344  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 345  *    Within group elem, '-' used for a range separator;
 346  *                       ',' used for a single number.
 347  */
 348 static int
 349 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 350 {
 351         const char *str = input;
 352         char *end = NULL;
 353         uint32_t min, max;
 354         uint32_t idx;
 355
 356         while (isblank(*str))
 357                 str++;
 358
 359         if (!isdigit(*str) && *str != '(')
 360                 return -1;
 361
 362         /* process single number or single range of number */
 363         if (*str != '(') {
 364                 errno = 0;
 365                 idx = strtoul(str, &end, 10);
 366                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 367                         return -1;
 368
 369                 while (isblank(*end))
 370                         end++;
 371
 372                 min = idx;
 373                 max = idx;
 374
 375                 /* process single <number>-<number> */
 376                 if (*end == '-') {
 377                         end++;
 378                         while (isblank(*end))
 379                                 end++;
 380                         if (!isdigit(*end))
 381                                 return -1;
 382
 383                         errno = 0;
 384                         idx = strtoul(end, &end, 10);
 385                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 386                                 return -1;
 387
 388                         max = idx;
 389                         while (isblank(*end))
 390                                 end++;
 391                 }
 392
 393                 if (*end != ':')
 394                         return -1;
 395
 396                 for (idx = RTE_MIN(min, max);
 397                      idx <= RTE_MAX(min, max); idx++)
 398                         devargs->proto_xtr[idx] = xtr_type;
 399
 400                 return 0;
 401         }
 402
 403         /* process set within bracket */
 404         str++;
 405         while (isblank(*str))
 406                 str++;
 407         if (*str == '\0')
 408                 return -1;
 409
 410         min = ICE_MAX_QUEUE_NUM;
 411         do {
 412                 /* go ahead to the first digit */
 413                 while (isblank(*str))
 414                         str++;
 415                 if (!isdigit(*str))
 416                         return -1;
 417
 418                 /* get the digit value */
 419                 errno = 0;
 420                 idx = strtoul(str, &end, 10);
 421                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 422                         return -1;
 423
 424                 /* go ahead to separator '-',',' and ')' */
 425                 while (isblank(*end))
 426                         end++;
 427                 if (*end == '-') {
 428                         if (min == ICE_MAX_QUEUE_NUM)
 429                                 min = idx;
 430                         else /* avoid continuous '-' */
 431                                 return -1;
 432                 } else if (*end == ',' || *end == ')') {
 433                         max = idx;
 434                         if (min == ICE_MAX_QUEUE_NUM)
 435                                 min = idx;
 436
 437                         for (idx = RTE_MIN(min, max);
 438                              idx <= RTE_MAX(min, max); idx++)
 439                                 devargs->proto_xtr[idx] = xtr_type;
 440
 441                         min = ICE_MAX_QUEUE_NUM;
 442                 } else {
 443                         return -1;
 444                 }
 445
 446                 str = end + 1;
 447         } while (*end != ')' && *end != '\0');
 448
 449         return 0;
 450 }
 451
 452 static int
 453 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 454 {
 455         const char *queue_start;
 456         uint32_t idx;
 457         int xtr_type;
 458         char xtr_name[32];
 459
 460         while (isblank(*queues))
 461                 queues++;
 462
 463         if (*queues != '[') {
 464                 xtr_type = lookup_proto_xtr_type(queues);
 465                 if (xtr_type < 0)
 466                         return -1;
 467
 468                 devargs->proto_xtr_dflt = xtr_type;
 469
 470                 return 0;
 471         }
 472
 473         queues++;
 474         do {
 475                 while (isblank(*queues))
 476                         queues++;
 477                 if (*queues == '\0')
 478                         return -1;
 479
 480                 queue_start = queues;
 481
 482                 /* go across a complete bracket */
 483                 if (*queue_start == '(') {
 484                         queues += strcspn(queues, ")");
 485                         if (*queues != ')')
 486                                 return -1;
 487                 }
 488
 489                 /* scan the separator ':' */
 490                 queues += strcspn(queues, ":");
 491                 if (*queues++ != ':')
 492                         return -1;
 493                 while (isblank(*queues))
 494                         queues++;
 495
 496                 for (idx = 0; ; idx++) {
 497                         if (isblank(queues[idx]) ||
 498                             queues[idx] == ',' ||
 499                             queues[idx] == ']' ||
 500                             queues[idx] == '\0')
 501                                 break;
 502
 503                         if (idx > sizeof(xtr_name) - 2)
 504                                 return -1;
 505
 506                         xtr_name[idx] = queues[idx];
 507                 }
 508                 xtr_name[idx] = '\0';
 509                 xtr_type = lookup_proto_xtr_type(xtr_name);
 510                 if (xtr_type < 0)
 511                         return -1;
 512
 513                 queues += idx;
 514
 515                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 516                         queues++;
 517
 518                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 519                         return -1;
 520         } while (*queues != '\0');
 521
 522         return 0;
 523 }
 524
 525 static int
 526 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 527                      void *extra_args)
 528 {
 529         struct ice_devargs *devargs = extra_args;
 530
 531         if (value == NULL || extra_args == NULL)
 532                 return -EINVAL;
 533
 534         if (parse_queue_proto_xtr(value, devargs) < 0) {
 535                 PMD_DRV_LOG(ERR,
 536                             "The protocol extraction parameter is wrong : '%s'",
 537                             value);
 538                 return -1;
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 ice_check_proto_xtr_support(struct ice_hw *hw)
 546 {
 547 #define FLX_REG(val, fld, idx) \
 548         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 549          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 550         static struct {
 551                 uint32_t rxdid;
 552                 uint8_t opcode;
 553                 uint8_t protid_0;
 554                 uint8_t protid_1;
 555         } xtr_sets[] = {
 556                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 557                                      ICE_RX_OPC_EXTRACT,
 558                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 559                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 560                                      ICE_RX_OPC_EXTRACT,
 561                                      ICE_PROT_IPV4_OF_OR_S,
 562                                      ICE_PROT_IPV4_OF_OR_S },
 563                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 564                                      ICE_RX_OPC_EXTRACT,
 565                                      ICE_PROT_IPV6_OF_OR_S,
 566                                      ICE_PROT_IPV6_OF_OR_S },
 567                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 568                                           ICE_RX_OPC_EXTRACT,
 569                                           ICE_PROT_IPV6_OF_OR_S,
 570                                           ICE_PROT_IPV6_OF_OR_S },
 571                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 572                                     ICE_RX_OPC_EXTRACT,
 573                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 574                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 575                                           ICE_RX_OPC_PROTID,
 576                                           ICE_PROT_IPV4_OF_OR_S,
 577                                           ICE_PROT_IPV6_OF_OR_S },
 578         };
 579         uint32_t i;
 580
 581         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 582                 uint32_t rxdid = xtr_sets[i].rxdid;
 583                 uint32_t v;
 584
 585                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 586                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 587
 588                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 589                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 590                                 ice_proto_xtr_hw_support[i] = true;
 591                 }
 592
 593                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 594                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 595
 596                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 597                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 598                                 ice_proto_xtr_hw_support[i] = true;
 599                 }
 600         }
 601 }
 602
 603 static int
 604 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 605                   uint32_t num)
 606 {
 607         struct pool_entry *entry;
 608
 609         if (!pool || !num)
 610                 return -EINVAL;
 611
 612         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 613         if (!entry) {
 614                 PMD_INIT_LOG(ERR,
 615                              "Failed to allocate memory for resource pool");
 616                 return -ENOMEM;
 617         }
 618
 619         /* queue heap initialize */
 620         pool->num_free = num;
 621         pool->num_alloc = 0;
 622         pool->base = base;
 623         LIST_INIT(&pool->alloc_list);
 624         LIST_INIT(&pool->free_list);
 625
 626         /* Initialize element  */
 627         entry->base = 0;
 628         entry->len = num;
 629
 630         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 631         return 0;
 632 }
 633
 634 static int
 635 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 636                    uint16_t num)
 637 {
 638         struct pool_entry *entry, *valid_entry;
 639
 640         if (!pool || !num) {
 641                 PMD_INIT_LOG(ERR, "Invalid parameter");
 642                 return -EINVAL;
 643         }
 644
 645         if (pool->num_free < num) {
 646                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 647                              num, pool->num_free);
 648                 return -ENOMEM;
 649         }
 650
 651         valid_entry = NULL;
 652         /* Lookup  in free list and find most fit one */
 653         LIST_FOREACH(entry, &pool->free_list, next) {
 654                 if (entry->len >= num) {
 655                         /* Find best one */
 656                         if (entry->len == num) {
 657                                 valid_entry = entry;
 658                                 break;
 659                         }
 660                         if (!valid_entry ||
 661                             valid_entry->len > entry->len)
 662                                 valid_entry = entry;
 663                 }
 664         }
 665
 666         /* Not find one to satisfy the request, return */
 667         if (!valid_entry) {
 668                 PMD_INIT_LOG(ERR, "No valid entry found");
 669                 return -ENOMEM;
 670         }
 671         /**
 672          * The entry have equal queue number as requested,
 673          * remove it from alloc_list.
 674          */
 675         if (valid_entry->len == num) {
 676                 LIST_REMOVE(valid_entry, next);
 677         } else {
 678                 /**
 679                  * The entry have more numbers than requested,
 680                  * create a new entry for alloc_list and minus its
 681                  * queue base and number in free_list.
 682                  */
 683                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 684                 if (!entry) {
 685                         PMD_INIT_LOG(ERR,
 686                                      "Failed to allocate memory for "
 687                                      "resource pool");
 688                         return -ENOMEM;
 689                 }
 690                 entry->base = valid_entry->base;
 691                 entry->len = num;
 692                 valid_entry->base += num;
 693                 valid_entry->len -= num;
 694                 valid_entry = entry;
 695         }
 696
 697         /* Insert it into alloc list, not sorted */
 698         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 699
 700         pool->num_free -= valid_entry->len;
 701         pool->num_alloc += valid_entry->len;
 702
 703         return valid_entry->base + pool->base;
 704 }
 705
 706 static void
 707 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 708 {
 709         struct pool_entry *entry, *next_entry;
 710
 711         if (!pool)
 712                 return;
 713
 714         for (entry = LIST_FIRST(&pool->alloc_list);
 715              entry && (next_entry = LIST_NEXT(entry, next), 1);
 716              entry = next_entry) {
 717                 LIST_REMOVE(entry, next);
 718                 rte_free(entry);
 719         }
 720
 721         for (entry = LIST_FIRST(&pool->free_list);
 722              entry && (next_entry = LIST_NEXT(entry, next), 1);
 723              entry = next_entry) {
 724                 LIST_REMOVE(entry, next);
 725                 rte_free(entry);
 726         }
 727
 728         pool->num_free = 0;
 729         pool->num_alloc = 0;
 730         pool->base = 0;
 731         LIST_INIT(&pool->alloc_list);
 732         LIST_INIT(&pool->free_list);
 733 }
 734
 735 static void
 736 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 737 {
 738         /* Set VSI LUT selection */
 739         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 740                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 741         /* Set Hash scheme */
 742         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 743                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 744         /* enable TC */
 745         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 746 }
 747
 748 static enum ice_status
 749 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 750                                 struct ice_aqc_vsi_props *info,
 751                                 uint8_t enabled_tcmap)
 752 {
 753         uint16_t bsf, qp_idx;
 754
 755         /* default tc 0 now. Multi-TC supporting need to be done later.
 756          * Configure TC and queue mapping parameters, for enabled TC,
 757          * allocate qpnum_per_tc queues to this traffic.
 758          */
 759         if (enabled_tcmap != 0x01) {
 760                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 761                 return -ENOTSUP;
 762         }
 763
 764         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 765         bsf = rte_bsf32(vsi->nb_qps);
 766         /* Adjust the queue number to actual queues that can be applied */
 767         vsi->nb_qps = 0x1 << bsf;
 768
 769         qp_idx = 0;
 770         /* Set tc and queue mapping with VSI */
 771         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 772                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 773                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 774
 775         /* Associate queue number with VSI */
 776         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 777         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 778         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 779         info->valid_sections |=
 780                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 781         /* Set the info.ingress_table and info.egress_table
 782          * for UP translate table. Now just set it to 1:1 map by default
 783          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 784          */
 785 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 786         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 787         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 788         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 789         return 0;
 790 }
 791
 792 static int
 793 ice_init_mac_address(struct rte_eth_dev *dev)
 794 {
 795         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 796
 797         if (!rte_is_unicast_ether_addr
 798                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 799                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 800                 return -EINVAL;
 801         }
 802
 803         rte_ether_addr_copy(
 804                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 805                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 806
 807         dev->data->mac_addrs =
 808                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 809         if (!dev->data->mac_addrs) {
 810                 PMD_INIT_LOG(ERR,
 811                              "Failed to allocate memory to store mac address");
 812                 return -ENOMEM;
 813         }
 814         /* store it to dev data */
 815         rte_ether_addr_copy(
 816                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 817                 &dev->data->mac_addrs[0]);
 818         return 0;
 819 }
 820
 821 /* Find out specific MAC filter */
 822 static struct ice_mac_filter *
 823 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 824 {
 825         struct ice_mac_filter *f;
 826
 827         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 828                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 829                         return f;
 830         }
 831
 832         return NULL;
 833 }
 834
 835 static int
 836 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 837 {
 838         struct ice_fltr_list_entry *m_list_itr = NULL;
 839         struct ice_mac_filter *f;
 840         struct LIST_HEAD_TYPE list_head;
 841         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 842         int ret = 0;
 843
 844         /* If it's added and configured, return */
 845         f = ice_find_mac_filter(vsi, mac_addr);
 846         if (f) {
 847                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 848                 return 0;
 849         }
 850
 851         INIT_LIST_HEAD(&list_head);
 852
 853         m_list_itr = (struct ice_fltr_list_entry *)
 854                 ice_malloc(hw, sizeof(*m_list_itr));
 855         if (!m_list_itr) {
 856                 ret = -ENOMEM;
 857                 goto DONE;
 858         }
 859         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 860                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 861         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 862         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 863         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 864         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 865         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 866
 867         LIST_ADD(&m_list_itr->list_entry, &list_head);
 868
 869         /* Add the mac */
 870         ret = ice_add_mac(hw, &list_head);
 871         if (ret != ICE_SUCCESS) {
 872                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 873                 ret = -EINVAL;
 874                 goto DONE;
 875         }
 876         /* Add the mac addr into mac list */
 877         f = rte_zmalloc(NULL, sizeof(*f), 0);
 878         if (!f) {
 879                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 880                 ret = -ENOMEM;
 881                 goto DONE;
 882         }
 883         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 884         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 885         vsi->mac_num++;
 886
 887         ret = 0;
 888
 889 DONE:
 890         rte_free(m_list_itr);
 891         return ret;
 892 }
 893
 894 static int
 895 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 896 {
 897         struct ice_fltr_list_entry *m_list_itr = NULL;
 898         struct ice_mac_filter *f;
 899         struct LIST_HEAD_TYPE list_head;
 900         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 901         int ret = 0;
 902
 903         /* Can't find it, return an error */
 904         f = ice_find_mac_filter(vsi, mac_addr);
 905         if (!f)
 906                 return -EINVAL;
 907
 908         INIT_LIST_HEAD(&list_head);
 909
 910         m_list_itr = (struct ice_fltr_list_entry *)
 911                 ice_malloc(hw, sizeof(*m_list_itr));
 912         if (!m_list_itr) {
 913                 ret = -ENOMEM;
 914                 goto DONE;
 915         }
 916         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 917                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 918         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 919         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 920         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 921         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 922         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 923
 924         LIST_ADD(&m_list_itr->list_entry, &list_head);
 925
 926         /* remove the mac filter */
 927         ret = ice_remove_mac(hw, &list_head);
 928         if (ret != ICE_SUCCESS) {
 929                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 930                 ret = -EINVAL;
 931                 goto DONE;
 932         }
 933
 934         /* Remove the mac addr from mac list */
 935         TAILQ_REMOVE(&vsi->mac_list, f, next);
 936         rte_free(f);
 937         vsi->mac_num--;
 938
 939         ret = 0;
 940 DONE:
 941         rte_free(m_list_itr);
 942         return ret;
 943 }
 944
 945 /* Find out specific VLAN filter */
 946 static struct ice_vlan_filter *
 947 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 948 {
 949         struct ice_vlan_filter *f;
 950
 951         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 952                 if (vlan_id == f->vlan_info.vlan_id)
 953                         return f;
 954         }
 955
 956         return NULL;
 957 }
 958
 959 static int
 960 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 961 {
 962         struct ice_fltr_list_entry *v_list_itr = NULL;
 963         struct ice_vlan_filter *f;
 964         struct LIST_HEAD_TYPE list_head;
 965         struct ice_hw *hw;
 966         int ret = 0;
 967
 968         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 969                 return -EINVAL;
 970
 971         hw = ICE_VSI_TO_HW(vsi);
 972
 973         /* If it's added and configured, return. */
 974         f = ice_find_vlan_filter(vsi, vlan_id);
 975         if (f) {
 976                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 977                 return 0;
 978         }
 979
 980         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 981                 return 0;
 982
 983         INIT_LIST_HEAD(&list_head);
 984
 985         v_list_itr = (struct ice_fltr_list_entry *)
 986                       ice_malloc(hw, sizeof(*v_list_itr));
 987         if (!v_list_itr) {
 988                 ret = -ENOMEM;
 989                 goto DONE;
 990         }
 991         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 992         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 993         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 994         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 995         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 996         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 997
 998         LIST_ADD(&v_list_itr->list_entry, &list_head);
 999
1000         /* Add the vlan */
1001         ret = ice_add_vlan(hw, &list_head);
1002         if (ret != ICE_SUCCESS) {
1003                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1004                 ret = -EINVAL;
1005                 goto DONE;
1006         }
1007
1008         /* Add vlan into vlan list */
1009         f = rte_zmalloc(NULL, sizeof(*f), 0);
1010         if (!f) {
1011                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1012                 ret = -ENOMEM;
1013                 goto DONE;
1014         }
1015         f->vlan_info.vlan_id = vlan_id;
1016         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1017         vsi->vlan_num++;
1018
1019         ret = 0;
1020
1021 DONE:
1022         rte_free(v_list_itr);
1023         return ret;
1024 }
1025
1026 static int
1027 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1028 {
1029         struct ice_fltr_list_entry *v_list_itr = NULL;
1030         struct ice_vlan_filter *f;
1031         struct LIST_HEAD_TYPE list_head;
1032         struct ice_hw *hw;
1033         int ret = 0;
1034
1035         /**
1036          * Vlan 0 is the generic filter for untagged packets
1037          * and can't be removed.
1038          */
1039         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1040                 return -EINVAL;
1041
1042         hw = ICE_VSI_TO_HW(vsi);
1043
1044         /* Can't find it, return an error */
1045         f = ice_find_vlan_filter(vsi, vlan_id);
1046         if (!f)
1047                 return -EINVAL;
1048
1049         INIT_LIST_HEAD(&list_head);
1050
1051         v_list_itr = (struct ice_fltr_list_entry *)
1052                       ice_malloc(hw, sizeof(*v_list_itr));
1053         if (!v_list_itr) {
1054                 ret = -ENOMEM;
1055                 goto DONE;
1056         }
1057
1058         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1059         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1060         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1061         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1062         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1063         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1064
1065         LIST_ADD(&v_list_itr->list_entry, &list_head);
1066
1067         /* remove the vlan filter */
1068         ret = ice_remove_vlan(hw, &list_head);
1069         if (ret != ICE_SUCCESS) {
1070                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1071                 ret = -EINVAL;
1072                 goto DONE;
1073         }
1074
1075         /* Remove the vlan id from vlan list */
1076         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1077         rte_free(f);
1078         vsi->vlan_num--;
1079
1080         ret = 0;
1081 DONE:
1082         rte_free(v_list_itr);
1083         return ret;
1084 }
1085
1086 static int
1087 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1088 {
1089         struct ice_mac_filter *m_f;
1090         struct ice_vlan_filter *v_f;
1091         int ret = 0;
1092
1093         if (!vsi || !vsi->mac_num)
1094                 return -EINVAL;
1095
1096         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1097                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1098                 if (ret != ICE_SUCCESS) {
1099                         ret = -EINVAL;
1100                         goto DONE;
1101                 }
1102         }
1103
1104         if (vsi->vlan_num == 0)
1105                 return 0;
1106
1107         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1108                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1109                 if (ret != ICE_SUCCESS) {
1110                         ret = -EINVAL;
1111                         goto DONE;
1112                 }
1113         }
1114
1115 DONE:
1116         return ret;
1117 }
1118
1119 static int
1120 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1121 {
1122         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1123         struct ice_vsi_ctx ctxt;
1124         uint8_t qinq_flags;
1125         int ret = 0;
1126
1127         /* Check if it has been already on or off */
1128         if (vsi->info.valid_sections &
1129                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1130                 if (on) {
1131                         if ((vsi->info.outer_tag_flags &
1132                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1133                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1134                                 return 0; /* already on */
1135                 } else {
1136                         if (!(vsi->info.outer_tag_flags &
1137                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1138                                 return 0; /* already off */
1139                 }
1140         }
1141
1142         if (on)
1143                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1144         else
1145                 qinq_flags = 0;
1146         /* clear global insertion and use per packet insertion */
1147         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1148         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1149         vsi->info.outer_tag_flags |= qinq_flags;
1150         /* use default vlan type 0x8100 */
1151         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1152         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1153                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1154         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1155         ctxt.info.valid_sections =
1156                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1157         ctxt.vsi_num = vsi->vsi_id;
1158         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1159         if (ret) {
1160                 PMD_DRV_LOG(INFO,
1161                             "Update VSI failed to %s qinq stripping",
1162                             on ? "enable" : "disable");
1163                 return -EINVAL;
1164         }
1165
1166         vsi->info.valid_sections |=
1167                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1168
1169         return ret;
1170 }
1171
1172 static int
1173 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1174 {
1175         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1176         struct ice_vsi_ctx ctxt;
1177         uint8_t qinq_flags;
1178         int ret = 0;
1179
1180         /* Check if it has been already on or off */
1181         if (vsi->info.valid_sections &
1182                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1183                 if (on) {
1184                         if ((vsi->info.outer_tag_flags &
1185                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1186                             ICE_AQ_VSI_OUTER_TAG_COPY)
1187                                 return 0; /* already on */
1188                 } else {
1189                         if ((vsi->info.outer_tag_flags &
1190                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1191                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1192                                 return 0; /* already off */
1193                 }
1194         }
1195
1196         if (on)
1197                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1198         else
1199                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1200         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1201         vsi->info.outer_tag_flags |= qinq_flags;
1202         /* use default vlan type 0x8100 */
1203         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1204         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1205                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1206         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1207         ctxt.info.valid_sections =
1208                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1209         ctxt.vsi_num = vsi->vsi_id;
1210         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1211         if (ret) {
1212                 PMD_DRV_LOG(INFO,
1213                             "Update VSI failed to %s qinq stripping",
1214                             on ? "enable" : "disable");
1215                 return -EINVAL;
1216         }
1217
1218         vsi->info.valid_sections |=
1219                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1220
1221         return ret;
1222 }
1223
1224 static int
1225 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1226 {
1227         int ret;
1228
1229         ret = ice_vsi_config_qinq_stripping(vsi, on);
1230         if (ret)
1231                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1232
1233         ret = ice_vsi_config_qinq_insertion(vsi, on);
1234         if (ret)
1235                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1236
1237         return ret;
1238 }
1239
1240 /* Enable IRQ0 */
1241 static void
1242 ice_pf_enable_irq0(struct ice_hw *hw)
1243 {
1244         /* reset the registers */
1245         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1246         ICE_READ_REG(hw, PFINT_OICR);
1247
1248 #ifdef ICE_LSE_SPT
1249         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1250                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1251                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1252
1253         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1254                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1255                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1256                        PFINT_OICR_CTL_ITR_INDX_M) |
1257                       PFINT_OICR_CTL_CAUSE_ENA_M);
1258
1259         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1260                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1261                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1262                        PFINT_FW_CTL_ITR_INDX_M) |
1263                       PFINT_FW_CTL_CAUSE_ENA_M);
1264 #else
1265         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1266 #endif
1267
1268         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1269                       GLINT_DYN_CTL_INTENA_M |
1270                       GLINT_DYN_CTL_CLEARPBA_M |
1271                       GLINT_DYN_CTL_ITR_INDX_M);
1272
1273         ice_flush(hw);
1274 }
1275
1276 /* Disable IRQ0 */
1277 static void
1278 ice_pf_disable_irq0(struct ice_hw *hw)
1279 {
1280         /* Disable all interrupt types */
1281         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1282         ice_flush(hw);
1283 }
1284
1285 #ifdef ICE_LSE_SPT
1286 static void
1287 ice_handle_aq_msg(struct rte_eth_dev *dev)
1288 {
1289         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         struct ice_ctl_q_info *cq = &hw->adminq;
1291         struct ice_rq_event_info event;
1292         uint16_t pending, opcode;
1293         int ret;
1294
1295         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1296         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1297         if (!event.msg_buf) {
1298                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1299                 return;
1300         }
1301
1302         pending = 1;
1303         while (pending) {
1304                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1305
1306                 if (ret != ICE_SUCCESS) {
1307                         PMD_DRV_LOG(INFO,
1308                                     "Failed to read msg from AdminQ, "
1309                                     "adminq_err: %u",
1310                                     hw->adminq.sq_last_status);
1311                         break;
1312                 }
1313                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1314
1315                 switch (opcode) {
1316                 case ice_aqc_opc_get_link_status:
1317                         ret = ice_link_update(dev, 0);
1318                         if (!ret)
1319                                 rte_eth_dev_callback_process
1320                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1321                         break;
1322                 default:
1323                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1324                                     opcode);
1325                         break;
1326                 }
1327         }
1328         rte_free(event.msg_buf);
1329 }
1330 #endif
1331
1332 /**
1333  * Interrupt handler triggered by NIC for handling
1334  * specific interrupt.
1335  *
1336  * @param handle
1337  *  Pointer to interrupt handle.
1338  * @param param
1339  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1340  *
1341  * @return
1342  *  void
1343  */
1344 static void
1345 ice_interrupt_handler(void *param)
1346 {
1347         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1348         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         uint32_t oicr;
1350         uint32_t reg;
1351         uint8_t pf_num;
1352         uint8_t event;
1353         uint16_t queue;
1354         int ret;
1355 #ifdef ICE_LSE_SPT
1356         uint32_t int_fw_ctl;
1357 #endif
1358
1359         /* Disable interrupt */
1360         ice_pf_disable_irq0(hw);
1361
1362         /* read out interrupt causes */
1363         oicr = ICE_READ_REG(hw, PFINT_OICR);
1364 #ifdef ICE_LSE_SPT
1365         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1366 #endif
1367
1368         /* No interrupt event indicated */
1369         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1370                 PMD_DRV_LOG(INFO, "No interrupt event");
1371                 goto done;
1372         }
1373
1374 #ifdef ICE_LSE_SPT
1375         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1376                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1377                 ice_handle_aq_msg(dev);
1378         }
1379 #else
1380         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1381                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1382                 ret = ice_link_update(dev, 0);
1383                 if (!ret)
1384                         rte_eth_dev_callback_process
1385                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1386         }
1387 #endif
1388
1389         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1390                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1391                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1392                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1393                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1394                                  GL_MDET_TX_PQM_PF_NUM_S;
1395                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1396                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1397                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1398                                 GL_MDET_TX_PQM_QNUM_S;
1399
1400                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1401                                     "%d by PQM on TX queue %d PF# %d",
1402                                     event, queue, pf_num);
1403                 }
1404
1405                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1406                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1407                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1408                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1409                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1410                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1411                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1412                                 GL_MDET_TX_TCLAN_QNUM_S;
1413
1414                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1415                                     "%d by TCLAN on TX queue %d PF# %d",
1416                                     event, queue, pf_num);
1417                 }
1418         }
1419 done:
1420         /* Enable interrupt */
1421         ice_pf_enable_irq0(hw);
1422         rte_intr_ack(dev->intr_handle);
1423 }
1424
1425 static void
1426 ice_init_proto_xtr(struct rte_eth_dev *dev)
1427 {
1428         struct ice_adapter *ad =
1429                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1430         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1432         const struct proto_xtr_ol_flag *ol_flag;
1433         bool proto_xtr_enable = false;
1434         int offset;
1435         uint16_t i;
1436
1437         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1438         if (unlikely(pf->proto_xtr == NULL)) {
1439                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1440                 return;
1441         }
1442
1443         for (i = 0; i < pf->lan_nb_qps; i++) {
1444                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1445                                    ad->devargs.proto_xtr[i] :
1446                                    ad->devargs.proto_xtr_dflt;
1447
1448                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1449                         uint8_t type = pf->proto_xtr[i];
1450
1451                         ice_proto_xtr_ol_flag_params[type].required = true;
1452                         proto_xtr_enable = true;
1453                 }
1454         }
1455
1456         if (likely(!proto_xtr_enable))
1457                 return;
1458
1459         ice_check_proto_xtr_support(hw);
1460
1461         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1462         if (unlikely(offset == -1)) {
1463                 PMD_DRV_LOG(ERR,
1464                             "Protocol extraction metadata is disabled in mbuf with error %d",
1465                             -rte_errno);
1466                 return;
1467         }
1468
1469         PMD_DRV_LOG(DEBUG,
1470                     "Protocol extraction metadata offset in mbuf is : %d",
1471                     offset);
1472         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1473
1474         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1475                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1476
1477                 if (!ol_flag->required)
1478                         continue;
1479
1480                 if (!ice_proto_xtr_hw_support[i]) {
1481                         PMD_DRV_LOG(ERR,
1482                                     "Protocol extraction type %u is not supported in hardware",
1483                                     i);
1484                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1485                         break;
1486                 }
1487
1488                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1489                 if (unlikely(offset == -1)) {
1490                         PMD_DRV_LOG(ERR,
1491                                     "Protocol extraction offload '%s' failed to register with error %d",
1492                                     ol_flag->param.name, -rte_errno);
1493
1494                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1495                         break;
1496                 }
1497
1498                 PMD_DRV_LOG(DEBUG,
1499                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1500                             ol_flag->param.name, offset);
1501                 *ol_flag->ol_flag = 1ULL << offset;
1502         }
1503 }
1504
1505 /*  Initialize SW parameters of PF */
1506 static int
1507 ice_pf_sw_init(struct rte_eth_dev *dev)
1508 {
1509         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1510         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1511
1512         pf->lan_nb_qp_max =
1513                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1514                                   hw->func_caps.common_cap.num_rxq);
1515
1516         pf->lan_nb_qps = pf->lan_nb_qp_max;
1517
1518         ice_init_proto_xtr(dev);
1519
1520         if (hw->func_caps.fd_fltr_guar > 0 ||
1521             hw->func_caps.fd_fltr_best_effort > 0) {
1522                 pf->flags |= ICE_FLAG_FDIR;
1523                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1524                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1525         } else {
1526                 pf->fdir_nb_qps = 0;
1527         }
1528         pf->fdir_qp_offset = 0;
1529
1530         return 0;
1531 }
1532
1533 struct ice_vsi *
1534 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1535 {
1536         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1537         struct ice_vsi *vsi = NULL;
1538         struct ice_vsi_ctx vsi_ctx;
1539         int ret;
1540         struct rte_ether_addr broadcast = {
1541                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1542         struct rte_ether_addr mac_addr;
1543         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1544         uint8_t tc_bitmap = 0x1;
1545         uint16_t cfg;
1546
1547         /* hw->num_lports = 1 in NIC mode */
1548         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1549         if (!vsi)
1550                 return NULL;
1551
1552         vsi->idx = pf->next_vsi_idx;
1553         pf->next_vsi_idx++;
1554         vsi->type = type;
1555         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1556         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1557         vsi->vlan_anti_spoof_on = 0;
1558         vsi->vlan_filter_on = 1;
1559         TAILQ_INIT(&vsi->mac_list);
1560         TAILQ_INIT(&vsi->vlan_list);
1561
1562         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1563         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1564                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1565                         hw->func_caps.common_cap.rss_table_size;
1566         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1567
1568         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1569         switch (type) {
1570         case ICE_VSI_PF:
1571                 vsi->nb_qps = pf->lan_nb_qps;
1572                 vsi->base_queue = 1;
1573                 ice_vsi_config_default_rss(&vsi_ctx.info);
1574                 vsi_ctx.alloc_from_pool = true;
1575                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1576                 /* switch_id is queried by get_switch_config aq, which is done
1577                  * by ice_init_hw
1578                  */
1579                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1580                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1581                 /* Allow all untagged or tagged packets */
1582                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1583                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1584                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1585                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1586
1587                 /* FDIR */
1588                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1589                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1590                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1591                 cfg = ICE_AQ_VSI_FD_ENABLE;
1592                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1593                 vsi_ctx.info.max_fd_fltr_dedicated =
1594                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1595                 vsi_ctx.info.max_fd_fltr_shared =
1596                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1597
1598                 /* Enable VLAN/UP trip */
1599                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1600                                                       &vsi_ctx.info,
1601                                                       ICE_DEFAULT_TCMAP);
1602                 if (ret) {
1603                         PMD_INIT_LOG(ERR,
1604                                      "tc queue mapping with vsi failed, "
1605                                      "err = %d",
1606                                      ret);
1607                         goto fail_mem;
1608                 }
1609
1610                 break;
1611         case ICE_VSI_CTRL:
1612                 vsi->nb_qps = pf->fdir_nb_qps;
1613                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1614                 vsi_ctx.alloc_from_pool = true;
1615                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1616
1617                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1618                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1619                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1620                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1621                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1622                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1623                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1624                                                       &vsi_ctx.info,
1625                                                       ICE_DEFAULT_TCMAP);
1626                 if (ret) {
1627                         PMD_INIT_LOG(ERR,
1628                                      "tc queue mapping with vsi failed, "
1629                                      "err = %d",
1630                                      ret);
1631                         goto fail_mem;
1632                 }
1633                 break;
1634         default:
1635                 /* for other types of VSI */
1636                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1637                 goto fail_mem;
1638         }
1639
1640         /* VF has MSIX interrupt in VF range, don't allocate here */
1641         if (type == ICE_VSI_PF) {
1642                 ret = ice_res_pool_alloc(&pf->msix_pool,
1643                                          RTE_MIN(vsi->nb_qps,
1644                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1645                 if (ret < 0) {
1646                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1647                                      vsi->vsi_id, ret);
1648                 }
1649                 vsi->msix_intr = ret;
1650                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1651         } else if (type == ICE_VSI_CTRL) {
1652                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1653                 if (ret < 0) {
1654                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1655                                     vsi->vsi_id, ret);
1656                 }
1657                 vsi->msix_intr = ret;
1658                 vsi->nb_msix = 1;
1659         } else {
1660                 vsi->msix_intr = 0;
1661                 vsi->nb_msix = 0;
1662         }
1663         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1664         if (ret != ICE_SUCCESS) {
1665                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1666                 goto fail_mem;
1667         }
1668         /* store vsi information is SW structure */
1669         vsi->vsi_id = vsi_ctx.vsi_num;
1670         vsi->info = vsi_ctx.info;
1671         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1672         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1673
1674         if (type == ICE_VSI_PF) {
1675                 /* MAC configuration */
1676                 rte_ether_addr_copy((struct rte_ether_addr *)
1677                                         hw->port_info->mac.perm_addr,
1678                                     &pf->dev_addr);
1679
1680                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1681                 ret = ice_add_mac_filter(vsi, &mac_addr);
1682                 if (ret != ICE_SUCCESS)
1683                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1684
1685                 rte_ether_addr_copy(&broadcast, &mac_addr);
1686                 ret = ice_add_mac_filter(vsi, &mac_addr);
1687                 if (ret != ICE_SUCCESS)
1688                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1689         }
1690
1691         /* At the beginning, only TC0. */
1692         /* What we need here is the maximam number of the TX queues.
1693          * Currently vsi->nb_qps means it.
1694          * Correct it if any change.
1695          */
1696         max_txqs[0] = vsi->nb_qps;
1697         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1698                               tc_bitmap, max_txqs);
1699         if (ret != ICE_SUCCESS)
1700                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1701
1702         return vsi;
1703 fail_mem:
1704         rte_free(vsi);
1705         pf->next_vsi_idx--;
1706         return NULL;
1707 }
1708
1709 static int
1710 ice_send_driver_ver(struct ice_hw *hw)
1711 {
1712         struct ice_driver_ver dv;
1713
1714         /* we don't have driver version use 0 for dummy */
1715         dv.major_ver = 0;
1716         dv.minor_ver = 0;
1717         dv.build_ver = 0;
1718         dv.subbuild_ver = 0;
1719         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1720
1721         return ice_aq_send_driver_ver(hw, &dv, NULL);
1722 }
1723
1724 static int
1725 ice_pf_setup(struct ice_pf *pf)
1726 {
1727         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1728         struct ice_vsi *vsi;
1729         uint16_t unused;
1730
1731         /* Clear all stats counters */
1732         pf->offset_loaded = false;
1733         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1734         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1735         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1736         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1737
1738         /* force guaranteed filter pool for PF */
1739         ice_alloc_fd_guar_item(hw, &unused,
1740                                hw->func_caps.fd_fltr_guar);
1741         /* force shared filter pool for PF */
1742         ice_alloc_fd_shrd_item(hw, &unused,
1743                                hw->func_caps.fd_fltr_best_effort);
1744
1745         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1746         if (!vsi) {
1747                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1748                 return -EINVAL;
1749         }
1750
1751         pf->main_vsi = vsi;
1752
1753         return 0;
1754 }
1755
1756 /*
1757  * Extract device serial number from PCIe Configuration Space and
1758  * determine the pkg file path according to the DSN.
1759  */
1760 static int
1761 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1762 {
1763         off_t pos;
1764         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1765         uint32_t dsn_low, dsn_high;
1766         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1767
1768         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1769
1770         if (pos) {
1771                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1772                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1773                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1774                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1775         } else {
1776                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1777                 goto fail_dsn;
1778         }
1779
1780         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1781                 ICE_MAX_PKG_FILENAME_SIZE);
1782         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1783                 return 0;
1784
1785         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1786                 ICE_MAX_PKG_FILENAME_SIZE);
1787         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1788                 return 0;
1789
1790 fail_dsn:
1791         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1792         if (!access(pkg_file, 0))
1793                 return 0;
1794         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1795         return 0;
1796 }
1797
1798 enum ice_pkg_type
1799 ice_load_pkg_type(struct ice_hw *hw)
1800 {
1801         enum ice_pkg_type package_type;
1802
1803         /* store the activated package type (OS default or Comms) */
1804         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1805                 ICE_PKG_NAME_SIZE))
1806                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1807         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1808                 ICE_PKG_NAME_SIZE))
1809                 package_type = ICE_PKG_TYPE_COMMS;
1810         else
1811                 package_type = ICE_PKG_TYPE_UNKNOWN;
1812
1813         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1814                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1815                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1816                 hw->active_pkg_name);
1817
1818         return package_type;
1819 }
1820
1821 static int ice_load_pkg(struct rte_eth_dev *dev)
1822 {
1823         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1825         int err;
1826         uint8_t *buf;
1827         int buf_len;
1828         FILE *file;
1829         struct stat fstat;
1830         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1831         struct ice_adapter *ad =
1832                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1833
1834         ice_pkg_file_search_path(pci_dev, pkg_file);
1835
1836         file = fopen(pkg_file, "rb");
1837         if (!file)  {
1838                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1839                 return -1;
1840         }
1841
1842         err = stat(pkg_file, &fstat);
1843         if (err) {
1844                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1845                 fclose(file);
1846                 return err;
1847         }
1848
1849         buf_len = fstat.st_size;
1850         buf = rte_malloc(NULL, buf_len, 0);
1851
1852         if (!buf) {
1853                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1854                                 buf_len);
1855                 fclose(file);
1856                 return -1;
1857         }
1858
1859         err = fread(buf, buf_len, 1, file);
1860         if (err != 1) {
1861                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1862                 fclose(file);
1863                 err = -1;
1864                 goto fail_exit;
1865         }
1866
1867         fclose(file);
1868
1869         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1870         if (err) {
1871                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1872                 goto fail_exit;
1873         }
1874
1875         /* store the loaded pkg type info */
1876         ad->active_pkg_type = ice_load_pkg_type(hw);
1877
1878         err = ice_init_hw_tbls(hw);
1879         if (err) {
1880                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1881                 goto fail_init_tbls;
1882         }
1883
1884         return 0;
1885
1886 fail_init_tbls:
1887         rte_free(hw->pkg_copy);
1888 fail_exit:
1889         rte_free(buf);
1890         return err;
1891 }
1892
1893 static void
1894 ice_base_queue_get(struct ice_pf *pf)
1895 {
1896         uint32_t reg;
1897         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1898
1899         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1900         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1901                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1902         } else {
1903                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1904                                         " index");
1905         }
1906 }
1907
1908 static int
1909 parse_bool(const char *key, const char *value, void *args)
1910 {
1911         int *i = (int *)args;
1912         char *end;
1913         int num;
1914
1915         num = strtoul(value, &end, 10);
1916
1917         if (num != 0 && num != 1) {
1918                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1919                         "value must be 0 or 1",
1920                         value, key);
1921                 return -1;
1922         }
1923
1924         *i = num;
1925         return 0;
1926 }
1927
1928 static int ice_parse_devargs(struct rte_eth_dev *dev)
1929 {
1930         struct ice_adapter *ad =
1931                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1932         struct rte_devargs *devargs = dev->device->devargs;
1933         struct rte_kvargs *kvlist;
1934         int ret;
1935
1936         if (devargs == NULL)
1937                 return 0;
1938
1939         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1940         if (kvlist == NULL) {
1941                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1942                 return -EINVAL;
1943         }
1944
1945         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1946         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1947                sizeof(ad->devargs.proto_xtr));
1948
1949         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1950                                  &handle_proto_xtr_arg, &ad->devargs);
1951         if (ret)
1952                 goto bail;
1953
1954         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1955                                  &parse_bool, &ad->devargs.safe_mode_support);
1956         if (ret)
1957                 goto bail;
1958
1959         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1960                                  &parse_bool, &ad->devargs.pipe_mode_support);
1961         if (ret)
1962                 goto bail;
1963
1964 bail:
1965         rte_kvargs_free(kvlist);
1966         return ret;
1967 }
1968
1969 /* Forward LLDP packets to default VSI by set switch rules */
1970 static int
1971 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1972 {
1973         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1974         struct ice_fltr_list_entry *s_list_itr = NULL;
1975         struct LIST_HEAD_TYPE list_head;
1976         int ret = 0;
1977
1978         INIT_LIST_HEAD(&list_head);
1979
1980         s_list_itr = (struct ice_fltr_list_entry *)
1981                         ice_malloc(hw, sizeof(*s_list_itr));
1982         if (!s_list_itr)
1983                 return -ENOMEM;
1984         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1985         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1986         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1987                         RTE_ETHER_TYPE_LLDP;
1988         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1989         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1990         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1991         LIST_ADD(&s_list_itr->list_entry, &list_head);
1992         if (on)
1993                 ret = ice_add_eth_mac(hw, &list_head);
1994         else
1995                 ret = ice_remove_eth_mac(hw, &list_head);
1996
1997         rte_free(s_list_itr);
1998         return ret;
1999 }
2000
2001 static enum ice_status
2002 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2003                 uint16_t num, uint16_t desc_id,
2004                 uint16_t *prof_buf, uint16_t *num_prof)
2005 {
2006         struct ice_aqc_res_elem *resp_buf;
2007         int ret;
2008         uint16_t buf_len;
2009         bool res_shared = 1;
2010         struct ice_aq_desc aq_desc;
2011         struct ice_sq_cd *cd = NULL;
2012         struct ice_aqc_get_allocd_res_desc *cmd =
2013                         &aq_desc.params.get_res_desc;
2014
2015         buf_len = sizeof(*resp_buf) * num;
2016         resp_buf = ice_malloc(hw, buf_len);
2017         if (!resp_buf)
2018                 return -ENOMEM;
2019
2020         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2021                         ice_aqc_opc_get_allocd_res_desc);
2022
2023         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2024                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2025                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2026         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2027
2028         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2029         if (!ret)
2030                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2031         else
2032                 goto exit;
2033
2034         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2035                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2036
2037 exit:
2038         rte_free(resp_buf);
2039         return ret;
2040 }
2041 static int
2042 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2043 {
2044         int ret;
2045         uint16_t prof_id;
2046         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2047         uint16_t first_desc = 1;
2048         uint16_t num_prof = 0;
2049
2050         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2051                         first_desc, prof_buf, &num_prof);
2052         if (ret) {
2053                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2054                 return ret;
2055         }
2056
2057         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2058                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2059                 if (ret) {
2060                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2061                         return ret;
2062                 }
2063         }
2064         return 0;
2065 }
2066
2067 static int
2068 ice_reset_fxp_resource(struct ice_hw *hw)
2069 {
2070         int ret;
2071
2072         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2073         if (ret) {
2074                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2075                 return ret;
2076         }
2077
2078         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2079         if (ret) {
2080                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2081                 return ret;
2082         }
2083
2084         return 0;
2085 }
2086
2087 static void
2088 ice_rss_ctx_init(struct ice_pf *pf)
2089 {
2090         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2091 }
2092
2093 static uint64_t
2094 ice_get_supported_rxdid(struct ice_hw *hw)
2095 {
2096         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2097         uint32_t regval;
2098         int i;
2099
2100         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2101
2102         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2103                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2104                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2105                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2106                         supported_rxdid |= BIT(i);
2107         }
2108         return supported_rxdid;
2109 }
2110
2111 static int
2112 ice_dev_init(struct rte_eth_dev *dev)
2113 {
2114         struct rte_pci_device *pci_dev;
2115         struct rte_intr_handle *intr_handle;
2116         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2118         struct ice_adapter *ad =
2119                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2120         struct ice_vsi *vsi;
2121         int ret;
2122
2123         dev->dev_ops = &ice_eth_dev_ops;
2124         dev->rx_queue_count = ice_rx_queue_count;
2125         dev->rx_descriptor_status = ice_rx_descriptor_status;
2126         dev->tx_descriptor_status = ice_tx_descriptor_status;
2127         dev->rx_pkt_burst = ice_recv_pkts;
2128         dev->tx_pkt_burst = ice_xmit_pkts;
2129         dev->tx_pkt_prepare = ice_prep_pkts;
2130
2131         /* for secondary processes, we don't initialise any further as primary
2132          * has already done this work.
2133          */
2134         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2135                 ice_set_rx_function(dev);
2136                 ice_set_tx_function(dev);
2137                 return 0;
2138         }
2139
2140         ice_set_default_ptype_table(dev);
2141         pci_dev = RTE_DEV_TO_PCI(dev->device);
2142         intr_handle = &pci_dev->intr_handle;
2143
2144         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2145         pf->adapter->eth_dev = dev;
2146         pf->dev_data = dev->data;
2147         hw->back = pf->adapter;
2148         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2149         hw->vendor_id = pci_dev->id.vendor_id;
2150         hw->device_id = pci_dev->id.device_id;
2151         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2152         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2153         hw->bus.device = pci_dev->addr.devid;
2154         hw->bus.func = pci_dev->addr.function;
2155
2156         ret = ice_parse_devargs(dev);
2157         if (ret) {
2158                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2159                 return -EINVAL;
2160         }
2161
2162         ice_init_controlq_parameter(hw);
2163
2164         ret = ice_init_hw(hw);
2165         if (ret) {
2166                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2167                 return -EINVAL;
2168         }
2169
2170         ret = ice_load_pkg(dev);
2171         if (ret) {
2172                 if (ad->devargs.safe_mode_support == 0) {
2173                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2174                                         "Use safe-mode-support=1 to enter Safe Mode");
2175                         return ret;
2176                 }
2177
2178                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2179                                         "Entering Safe Mode");
2180                 ad->is_safe_mode = 1;
2181         }
2182
2183         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2184                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2185                      hw->api_maj_ver, hw->api_min_ver);
2186
2187         ice_pf_sw_init(dev);
2188         ret = ice_init_mac_address(dev);
2189         if (ret) {
2190                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2191                 goto err_init_mac;
2192         }
2193
2194         ret = ice_res_pool_init(&pf->msix_pool, 1,
2195                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2196         if (ret) {
2197                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2198                 goto err_msix_pool_init;
2199         }
2200
2201         ret = ice_pf_setup(pf);
2202         if (ret) {
2203                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2204                 goto err_pf_setup;
2205         }
2206
2207         ret = ice_send_driver_ver(hw);
2208         if (ret) {
2209                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2210                 goto err_pf_setup;
2211         }
2212
2213         vsi = pf->main_vsi;
2214
2215         /* Disable double vlan by default */
2216         ice_vsi_config_double_vlan(vsi, false);
2217
2218         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2219         if (ret != ICE_SUCCESS)
2220                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2221         ret = ice_init_dcb(hw, true);
2222         if (ret != ICE_SUCCESS)
2223                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2224         /* Forward LLDP packets to default VSI */
2225         ret = ice_vsi_config_sw_lldp(vsi, true);
2226         if (ret != ICE_SUCCESS)
2227                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2228         /* register callback func to eal lib */
2229         rte_intr_callback_register(intr_handle,
2230                                    ice_interrupt_handler, dev);
2231
2232         ice_pf_enable_irq0(hw);
2233
2234         /* enable uio intr after callback register */
2235         rte_intr_enable(intr_handle);
2236
2237         /* get base queue pairs index  in the device */
2238         ice_base_queue_get(pf);
2239
2240         /* Initialize RSS context for gtpu_eh */
2241         ice_rss_ctx_init(pf);
2242
2243         if (!ad->is_safe_mode) {
2244                 ret = ice_flow_init(ad);
2245                 if (ret) {
2246                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2247                         return ret;
2248                 }
2249         }
2250
2251         ret = ice_reset_fxp_resource(hw);
2252         if (ret) {
2253                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2254                 return ret;
2255         }
2256
2257         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2258
2259         return 0;
2260
2261 err_pf_setup:
2262         ice_res_pool_destroy(&pf->msix_pool);
2263 err_msix_pool_init:
2264         rte_free(dev->data->mac_addrs);
2265         dev->data->mac_addrs = NULL;
2266 err_init_mac:
2267         ice_sched_cleanup_all(hw);
2268         rte_free(hw->port_info);
2269         ice_shutdown_all_ctrlq(hw);
2270         rte_free(pf->proto_xtr);
2271
2272         return ret;
2273 }
2274
2275 int
2276 ice_release_vsi(struct ice_vsi *vsi)
2277 {
2278         struct ice_hw *hw;
2279         struct ice_vsi_ctx vsi_ctx;
2280         enum ice_status ret;
2281         int error = 0;
2282
2283         if (!vsi)
2284                 return error;
2285
2286         hw = ICE_VSI_TO_HW(vsi);
2287
2288         ice_remove_all_mac_vlan_filters(vsi);
2289
2290         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2291
2292         vsi_ctx.vsi_num = vsi->vsi_id;
2293         vsi_ctx.info = vsi->info;
2294         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2295         if (ret != ICE_SUCCESS) {
2296                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2297                 error = -1;
2298         }
2299
2300         rte_free(vsi->rss_lut);
2301         rte_free(vsi->rss_key);
2302         rte_free(vsi);
2303         return error;
2304 }
2305
2306 void
2307 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2308 {
2309         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2310         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2311         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2312         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2313         uint16_t msix_intr, i;
2314
2315         /* disable interrupt and also clear all the exist config */
2316         for (i = 0; i < vsi->nb_qps; i++) {
2317                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2318                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2319                 rte_wmb();
2320         }
2321
2322         if (rte_intr_allow_others(intr_handle))
2323                 /* vfio-pci */
2324                 for (i = 0; i < vsi->nb_msix; i++) {
2325                         msix_intr = vsi->msix_intr + i;
2326                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2327                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2328                 }
2329         else
2330                 /* igb_uio */
2331                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2332 }
2333
2334 static void
2335 ice_dev_stop(struct rte_eth_dev *dev)
2336 {
2337         struct rte_eth_dev_data *data = dev->data;
2338         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2339         struct ice_vsi *main_vsi = pf->main_vsi;
2340         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2341         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2342         uint16_t i;
2343
2344         /* avoid stopping again */
2345         if (pf->adapter_stopped)
2346                 return;
2347
2348         /* stop and clear all Rx queues */
2349         for (i = 0; i < data->nb_rx_queues; i++)
2350                 ice_rx_queue_stop(dev, i);
2351
2352         /* stop and clear all Tx queues */
2353         for (i = 0; i < data->nb_tx_queues; i++)
2354                 ice_tx_queue_stop(dev, i);
2355
2356         /* disable all queue interrupts */
2357         ice_vsi_disable_queues_intr(main_vsi);
2358
2359         if (pf->init_link_up)
2360                 ice_dev_set_link_up(dev);
2361         else
2362                 ice_dev_set_link_down(dev);
2363
2364         /* Clean datapath event and queue/vec mapping */
2365         rte_intr_efd_disable(intr_handle);
2366         if (intr_handle->intr_vec) {
2367                 rte_free(intr_handle->intr_vec);
2368                 intr_handle->intr_vec = NULL;
2369         }
2370
2371         pf->adapter_stopped = true;
2372         dev->data->dev_started = 0;
2373 }
2374
2375 static int
2376 ice_dev_close(struct rte_eth_dev *dev)
2377 {
2378         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2379         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2381         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2382         struct ice_adapter *ad =
2383                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2384
2385         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2386                 return 0;
2387
2388         /* Since stop will make link down, then the link event will be
2389          * triggered, disable the irq firstly to avoid the port_infoe etc
2390          * resources deallocation causing the interrupt service thread
2391          * crash.
2392          */
2393         ice_pf_disable_irq0(hw);
2394
2395         ice_dev_stop(dev);
2396
2397         if (!ad->is_safe_mode)
2398                 ice_flow_uninit(ad);
2399
2400         /* release all queue resource */
2401         ice_free_queues(dev);
2402
2403         ice_res_pool_destroy(&pf->msix_pool);
2404         ice_release_vsi(pf->main_vsi);
2405         ice_sched_cleanup_all(hw);
2406         ice_free_hw_tbls(hw);
2407         rte_free(hw->port_info);
2408         hw->port_info = NULL;
2409         ice_shutdown_all_ctrlq(hw);
2410         rte_free(pf->proto_xtr);
2411         pf->proto_xtr = NULL;
2412
2413         dev->dev_ops = NULL;
2414         dev->rx_pkt_burst = NULL;
2415         dev->tx_pkt_burst = NULL;
2416
2417         /* disable uio intr before callback unregister */
2418         rte_intr_disable(intr_handle);
2419
2420         /* unregister callback func from eal lib */
2421         rte_intr_callback_unregister(intr_handle,
2422                                      ice_interrupt_handler, dev);
2423
2424         return 0;
2425 }
2426
2427 static int
2428 ice_dev_uninit(struct rte_eth_dev *dev)
2429 {
2430         ice_dev_close(dev);
2431
2432         return 0;
2433 }
2434
2435 static bool
2436 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2437 {
2438         return ((cfg->hash_func >= ICE_RSS_HASH_TOEPLITZ &&
2439                  cfg->hash_func <= ICE_RSS_HASH_JHASH) &&
2440                 (cfg->hash_flds != 0 && cfg->addl_hdrs != 0)) ?
2441                 true : false;
2442 }
2443
2444 static void
2445 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2446 {
2447         cfg->hash_flds = 0;
2448         cfg->addl_hdrs = 0;
2449         cfg->hash_func = 0;
2450 }
2451
2452 static int
2453 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2454 {
2455         enum ice_status status = ICE_SUCCESS;
2456         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2457         struct ice_vsi *vsi = pf->main_vsi;
2458
2459         if (!is_hash_cfg_valid(cfg))
2460                 return -ENOENT;
2461
2462         status = ice_rem_rss_cfg(hw, vsi->idx, cfg->hash_flds,
2463                                  cfg->addl_hdrs);
2464         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2465                 PMD_DRV_LOG(ERR,
2466                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2467                             vsi->idx, status);
2468                 return -EBUSY;
2469         }
2470
2471         return 0;
2472 }
2473
2474 static int
2475 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2476 {
2477         enum ice_status status = ICE_SUCCESS;
2478         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2479         struct ice_vsi *vsi = pf->main_vsi;
2480         bool symm;
2481
2482         if (!is_hash_cfg_valid(cfg))
2483                 return -ENOENT;
2484
2485         symm = (cfg->hash_func == ICE_RSS_HASH_TOEPLITZ_SYMMETRIC) ?
2486                 true : false;
2487
2488         status = ice_add_rss_cfg(hw, vsi->idx, cfg->hash_flds,
2489                                  cfg->addl_hdrs, symm);
2490         if (status) {
2491                 PMD_DRV_LOG(ERR,
2492                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2493                             vsi->idx, status);
2494                 return -EBUSY;
2495         }
2496
2497         return 0;
2498 }
2499
2500 static int
2501 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2502 {
2503         int ret;
2504
2505         ret = ice_hash_moveout(pf, cfg);
2506         if (ret && (ret != -ENOENT))
2507                 return ret;
2508
2509         hash_cfg_reset(cfg);
2510
2511         return 0;
2512 }
2513
2514 static int
2515 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2516                          u8 ctx_idx)
2517 {
2518         int ret;
2519
2520         switch (ctx_idx) {
2521         case ICE_HASH_GTPU_CTX_EH_IP:
2522                 ret = ice_hash_remove(pf,
2523                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2524                 if (ret && (ret != -ENOENT))
2525                         return ret;
2526
2527                 ret = ice_hash_remove(pf,
2528                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2529                 if (ret && (ret != -ENOENT))
2530                         return ret;
2531
2532                 ret = ice_hash_remove(pf,
2533                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2534                 if (ret && (ret != -ENOENT))
2535                         return ret;
2536
2537                 ret = ice_hash_remove(pf,
2538                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2539                 if (ret && (ret != -ENOENT))
2540                         return ret;
2541
2542                 ret = ice_hash_remove(pf,
2543                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2544                 if (ret && (ret != -ENOENT))
2545                         return ret;
2546
2547                 ret = ice_hash_remove(pf,
2548                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2549                 if (ret && (ret != -ENOENT))
2550                         return ret;
2551
2552                 ret = ice_hash_remove(pf,
2553                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2554                 if (ret && (ret != -ENOENT))
2555                         return ret;
2556
2557                 ret = ice_hash_remove(pf,
2558                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2559                 if (ret && (ret != -ENOENT))
2560                         return ret;
2561
2562                 break;
2563         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2564                 ret = ice_hash_remove(pf,
2565                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2566                 if (ret && (ret != -ENOENT))
2567                         return ret;
2568
2569                 ret = ice_hash_remove(pf,
2570                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2571                 if (ret && (ret != -ENOENT))
2572                         return ret;
2573
2574                 ret = ice_hash_moveout(pf,
2575                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2576                 if (ret && (ret != -ENOENT))
2577                         return ret;
2578
2579                 ret = ice_hash_moveout(pf,
2580                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2581                 if (ret && (ret != -ENOENT))
2582                         return ret;
2583
2584                 ret = ice_hash_moveout(pf,
2585                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2586                 if (ret && (ret != -ENOENT))
2587                         return ret;
2588
2589                 ret = ice_hash_moveout(pf,
2590                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2591                 if (ret && (ret != -ENOENT))
2592                         return ret;
2593
2594                 break;
2595         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2596                 ret = ice_hash_remove(pf,
2597                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2598                 if (ret && (ret != -ENOENT))
2599                         return ret;
2600
2601                 ret = ice_hash_remove(pf,
2602                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2603                 if (ret && (ret != -ENOENT))
2604                         return ret;
2605
2606                 ret = ice_hash_moveout(pf,
2607                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2608                 if (ret && (ret != -ENOENT))
2609                         return ret;
2610
2611                 ret = ice_hash_moveout(pf,
2612                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2613                 if (ret && (ret != -ENOENT))
2614                         return ret;
2615
2616                 ret = ice_hash_moveout(pf,
2617                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2618                 if (ret && (ret != -ENOENT))
2619                         return ret;
2620
2621                 ret = ice_hash_moveout(pf,
2622                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2623                 if (ret && (ret != -ENOENT))
2624                         return ret;
2625
2626                 break;
2627         case ICE_HASH_GTPU_CTX_UP_IP:
2628                 ret = ice_hash_remove(pf,
2629                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2630                 if (ret && (ret != -ENOENT))
2631                         return ret;
2632
2633                 ret = ice_hash_remove(pf,
2634                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2635                 if (ret && (ret != -ENOENT))
2636                         return ret;
2637
2638                 ret = ice_hash_moveout(pf,
2639                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2640                 if (ret && (ret != -ENOENT))
2641                         return ret;
2642
2643                 ret = ice_hash_moveout(pf,
2644                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2645                 if (ret && (ret != -ENOENT))
2646                         return ret;
2647
2648                 ret = ice_hash_moveout(pf,
2649                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2650                 if (ret && (ret != -ENOENT))
2651                         return ret;
2652
2653                 break;
2654         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2655         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2656                 ret = ice_hash_moveout(pf,
2657                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2658                 if (ret && (ret != -ENOENT))
2659                         return ret;
2660
2661                 ret = ice_hash_moveout(pf,
2662                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2663                 if (ret && (ret != -ENOENT))
2664                         return ret;
2665
2666                 ret = ice_hash_moveout(pf,
2667                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2668                 if (ret && (ret != -ENOENT))
2669                         return ret;
2670
2671                 break;
2672         case ICE_HASH_GTPU_CTX_DW_IP:
2673                 ret = ice_hash_remove(pf,
2674                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2675                 if (ret && (ret != -ENOENT))
2676                         return ret;
2677
2678                 ret = ice_hash_remove(pf,
2679                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2680                 if (ret && (ret != -ENOENT))
2681                         return ret;
2682
2683                 ret = ice_hash_moveout(pf,
2684                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2685                 if (ret && (ret != -ENOENT))
2686                         return ret;
2687
2688                 ret = ice_hash_moveout(pf,
2689                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2690                 if (ret && (ret != -ENOENT))
2691                         return ret;
2692
2693                 ret = ice_hash_moveout(pf,
2694                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2695                 if (ret && (ret != -ENOENT))
2696                         return ret;
2697
2698                 break;
2699         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2700         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2701                 ret = ice_hash_moveout(pf,
2702                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2703                 if (ret && (ret != -ENOENT))
2704                         return ret;
2705
2706                 ret = ice_hash_moveout(pf,
2707                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2708                 if (ret && (ret != -ENOENT))
2709                         return ret;
2710
2711                 ret = ice_hash_moveout(pf,
2712                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2713                 if (ret && (ret != -ENOENT))
2714                         return ret;
2715
2716                 break;
2717         default:
2718                 break;
2719         }
2720
2721         return 0;
2722 }
2723
2724 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2725 {
2726         u8 eh_idx, ip_idx;
2727
2728         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2729                 eh_idx = 0;
2730         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2731                 eh_idx = 1;
2732         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2733                 eh_idx = 2;
2734         else
2735                 return ICE_HASH_GTPU_CTX_MAX;
2736
2737         ip_idx = 0;
2738         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2739                 ip_idx = 1;
2740         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2741                 ip_idx = 2;
2742
2743         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2744                 return eh_idx * 3 + ip_idx;
2745         else
2746                 return ICE_HASH_GTPU_CTX_MAX;
2747 }
2748
2749 static int
2750 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2751 {
2752         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2753
2754         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2755                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2756                                                 gtpu_ctx_idx);
2757         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2758                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2759                                                 gtpu_ctx_idx);
2760
2761         return 0;
2762 }
2763
2764 static int
2765 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2766                           u32 hdr, u64 fld, bool symm, u8 ctx_idx)
2767 {
2768         int ret;
2769
2770         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX) {
2771                 ctx->ctx[ctx_idx].addl_hdrs = hdr;
2772                 ctx->ctx[ctx_idx].hash_flds = fld;
2773                 ctx->ctx[ctx_idx].hash_func = symm;
2774         }
2775
2776         switch (ctx_idx) {
2777         case ICE_HASH_GTPU_CTX_EH_IP:
2778                 break;
2779         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2780                 ret = ice_hash_moveback(pf,
2781                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2782                 if (ret && (ret != -ENOENT))
2783                         return ret;
2784
2785                 ret = ice_hash_moveback(pf,
2786                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2787                 if (ret && (ret != -ENOENT))
2788                         return ret;
2789
2790                 ret = ice_hash_moveback(pf,
2791                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2792                 if (ret && (ret != -ENOENT))
2793                         return ret;
2794
2795                 ret = ice_hash_moveback(pf,
2796                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2797                 if (ret && (ret != -ENOENT))
2798                         return ret;
2799
2800                 break;
2801         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2802                 ret = ice_hash_moveback(pf,
2803                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2804                 if (ret && (ret != -ENOENT))
2805                         return ret;
2806
2807                 ret = ice_hash_moveback(pf,
2808                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2809                 if (ret && (ret != -ENOENT))
2810                         return ret;
2811
2812                 ret = ice_hash_moveback(pf,
2813                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2814                 if (ret && (ret != -ENOENT))
2815                         return ret;
2816
2817                 ret = ice_hash_moveback(pf,
2818                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2819                 if (ret && (ret != -ENOENT))
2820                         return ret;
2821
2822                 break;
2823         case ICE_HASH_GTPU_CTX_UP_IP:
2824         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2825         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2826         case ICE_HASH_GTPU_CTX_DW_IP:
2827         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2828         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2829                 ret = ice_hash_moveback(pf,
2830                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2831                 if (ret && (ret != -ENOENT))
2832                         return ret;
2833
2834                 ret = ice_hash_moveback(pf,
2835                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2836                 if (ret && (ret != -ENOENT))
2837                         return ret;
2838
2839                 ret = ice_hash_moveback(pf,
2840                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2841                 if (ret && (ret != -ENOENT))
2842                         return ret;
2843
2844                 break;
2845         default:
2846                 break;
2847         }
2848
2849         return 0;
2850 }
2851
2852 static int
2853 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm)
2854 {
2855         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2856
2857         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2858                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4, hdr,
2859                                                  fld, symm, gtpu_ctx_idx);
2860         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2861                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6, hdr,
2862                                                  fld, symm, gtpu_ctx_idx);
2863
2864         return 0;
2865 }
2866
2867 static void
2868 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2869 {
2870         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2871
2872         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2873                 return;
2874
2875         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2876                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2877         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2878                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2879 }
2880
2881 int
2882 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2883                 uint64_t fld, uint32_t hdr)
2884 {
2885         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2886         int ret;
2887
2888         ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr);
2889         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2890                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2891
2892         ice_rem_rss_cfg_post(pf, hdr);
2893
2894         return 0;
2895 }
2896
2897 int
2898 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2899                 uint64_t fld, uint32_t hdr, bool symm)
2900 {
2901         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2902         int ret;
2903
2904         ret = ice_add_rss_cfg_pre(pf, hdr);
2905         if (ret)
2906                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2907
2908         ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm);
2909         if (ret)
2910                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2911
2912         ret = ice_add_rss_cfg_post(pf, hdr, fld, symm);
2913         if (ret)
2914                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2915
2916         return 0;
2917 }
2918
2919 static void
2920 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2921 {
2922         struct ice_vsi *vsi = pf->main_vsi;
2923         int ret;
2924
2925         /* Configure RSS for IPv4 with src/dst addr as input set */
2926         if (rss_hf & ETH_RSS_IPV4) {
2927                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2928                                       ICE_FLOW_SEG_HDR_IPV4 |
2929                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2930                 if (ret)
2931                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2932                                     __func__, ret);
2933         }
2934
2935         /* Configure RSS for IPv6 with src/dst addr as input set */
2936         if (rss_hf & ETH_RSS_IPV6) {
2937                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2938                                       ICE_FLOW_SEG_HDR_IPV6 |
2939                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2940                 if (ret)
2941                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2942                                     __func__, ret);
2943         }
2944
2945         /* Configure RSS for udp4 with src/dst addr and port as input set */
2946         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2947                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2948                                       ICE_FLOW_SEG_HDR_UDP |
2949                                       ICE_FLOW_SEG_HDR_IPV4 |
2950                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2951                 if (ret)
2952                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2953                                     __func__, ret);
2954         }
2955
2956         /* Configure RSS for udp6 with src/dst addr and port as input set */
2957         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2958                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2959                                       ICE_FLOW_SEG_HDR_UDP |
2960                                       ICE_FLOW_SEG_HDR_IPV6 |
2961                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2962                 if (ret)
2963                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2964                                     __func__, ret);
2965         }
2966
2967         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2968         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2969                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2970                                       ICE_FLOW_SEG_HDR_TCP |
2971                                       ICE_FLOW_SEG_HDR_IPV4 |
2972                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2973                 if (ret)
2974                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2975                                     __func__, ret);
2976         }
2977
2978         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2979         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2980                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2981                                       ICE_FLOW_SEG_HDR_TCP |
2982                                       ICE_FLOW_SEG_HDR_IPV6 |
2983                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2984                 if (ret)
2985                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2986                                     __func__, ret);
2987         }
2988
2989         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2990         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2991                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2992                                       ICE_FLOW_SEG_HDR_SCTP |
2993                                       ICE_FLOW_SEG_HDR_IPV4 |
2994                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2995                 if (ret)
2996                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2997                                     __func__, ret);
2998         }
2999
3000         /* Configure RSS for sctp6 with src/dst addr and port as input set */
3001         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3002                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
3003                                       ICE_FLOW_SEG_HDR_SCTP |
3004                                       ICE_FLOW_SEG_HDR_IPV6 |
3005                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3006                 if (ret)
3007                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3008                                     __func__, ret);
3009         }
3010
3011         if (rss_hf & ETH_RSS_IPV4) {
3012                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
3013                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3014                                 ICE_FLOW_SEG_HDR_IPV4 |
3015                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3016                 if (ret)
3017                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
3018                                     __func__, ret);
3019
3020                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
3021                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3022                                 ICE_FLOW_SEG_HDR_IPV4 |
3023                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3024                 if (ret)
3025                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
3026                                     __func__, ret);
3027
3028                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
3029                                 ICE_FLOW_SEG_HDR_PPPOE |
3030                                 ICE_FLOW_SEG_HDR_IPV4 |
3031                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3032                 if (ret)
3033                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3034                                     __func__, ret);
3035         }
3036
3037         if (rss_hf & ETH_RSS_IPV6) {
3038                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
3039                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3040                                 ICE_FLOW_SEG_HDR_IPV6 |
3041                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3042                 if (ret)
3043                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
3044                                     __func__, ret);
3045
3046                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
3047                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3048                                 ICE_FLOW_SEG_HDR_IPV6 |
3049                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3050                 if (ret)
3051                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
3052                                     __func__, ret);
3053
3054                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
3055                                 ICE_FLOW_SEG_HDR_PPPOE |
3056                                 ICE_FLOW_SEG_HDR_IPV6 |
3057                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3058                 if (ret)
3059                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3060                                     __func__, ret);
3061         }
3062
3063         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
3064                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
3065                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3066                                 ICE_FLOW_SEG_HDR_UDP |
3067                                 ICE_FLOW_SEG_HDR_IPV4 |
3068                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3069                 if (ret)
3070                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
3071                                     __func__, ret);
3072
3073                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
3074                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3075                                 ICE_FLOW_SEG_HDR_UDP |
3076                                 ICE_FLOW_SEG_HDR_IPV4 |
3077                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3078                 if (ret)
3079                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
3080                                     __func__, ret);
3081
3082                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
3083                                 ICE_FLOW_SEG_HDR_PPPOE |
3084                                 ICE_FLOW_SEG_HDR_UDP |
3085                                 ICE_FLOW_SEG_HDR_IPV4 |
3086                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3087                 if (ret)
3088                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3089                                     __func__, ret);
3090         }
3091
3092         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
3093                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
3094                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3095                                 ICE_FLOW_SEG_HDR_UDP |
3096                                 ICE_FLOW_SEG_HDR_IPV6 |
3097                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3098                 if (ret)
3099                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
3100                                     __func__, ret);
3101
3102                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
3103                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3104                                 ICE_FLOW_SEG_HDR_UDP |
3105                                 ICE_FLOW_SEG_HDR_IPV6 |
3106                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3107                 if (ret)
3108                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
3109                                     __func__, ret);
3110
3111                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
3112                                 ICE_FLOW_SEG_HDR_PPPOE |
3113                                 ICE_FLOW_SEG_HDR_UDP |
3114                                 ICE_FLOW_SEG_HDR_IPV6 |
3115                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3116                 if (ret)
3117                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3118                                     __func__, ret);
3119         }
3120
3121         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3122                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
3123                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3124                                 ICE_FLOW_SEG_HDR_TCP |
3125                                 ICE_FLOW_SEG_HDR_IPV4 |
3126                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3127                 if (ret)
3128                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3129                                     __func__, ret);
3130
3131                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
3132                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3133                                 ICE_FLOW_SEG_HDR_TCP |
3134                                 ICE_FLOW_SEG_HDR_IPV4 |
3135                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3136                 if (ret)
3137                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3138                                     __func__, ret);
3139
3140                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
3141                                 ICE_FLOW_SEG_HDR_PPPOE |
3142                                 ICE_FLOW_SEG_HDR_TCP |
3143                                 ICE_FLOW_SEG_HDR_IPV4 |
3144                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3145                 if (ret)
3146                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3147                                     __func__, ret);
3148         }
3149
3150         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3151                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
3152                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3153                                 ICE_FLOW_SEG_HDR_TCP |
3154                                 ICE_FLOW_SEG_HDR_IPV6 |
3155                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3156                 if (ret)
3157                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3158                                     __func__, ret);
3159
3160                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
3161                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3162                                 ICE_FLOW_SEG_HDR_TCP |
3163                                 ICE_FLOW_SEG_HDR_IPV6 |
3164                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3165                 if (ret)
3166                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3167                                     __func__, ret);
3168
3169                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
3170                                 ICE_FLOW_SEG_HDR_PPPOE |
3171                                 ICE_FLOW_SEG_HDR_TCP |
3172                                 ICE_FLOW_SEG_HDR_IPV6 |
3173                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3174                 if (ret)
3175                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3176                                     __func__, ret);
3177         }
3178
3179         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
3180                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3181                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3182                                 ICE_FLOW_SEG_HDR_SCTP |
3183                                 ICE_FLOW_SEG_HDR_IPV4 |
3184                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3185                 if (ret)
3186                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
3187                                     __func__, ret);
3188
3189                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
3190                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3191                                 ICE_FLOW_SEG_HDR_SCTP |
3192                                 ICE_FLOW_SEG_HDR_IPV4 |
3193                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3194                 if (ret)
3195                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
3196                                     __func__, ret);
3197         }
3198
3199         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
3200                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3201                                 ICE_FLOW_SEG_HDR_GTPU_IP |
3202                                 ICE_FLOW_SEG_HDR_SCTP |
3203                                 ICE_FLOW_SEG_HDR_IPV6 |
3204                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3205                 if (ret)
3206                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
3207                                     __func__, ret);
3208
3209                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3210                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3211                                 ICE_FLOW_SEG_HDR_SCTP |
3212                                 ICE_FLOW_SEG_HDR_IPV6 |
3213                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3214                 if (ret)
3215                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
3216                                     __func__, ret);
3217         }
3218 }
3219
3220 static int ice_init_rss(struct ice_pf *pf)
3221 {
3222         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3223         struct ice_vsi *vsi = pf->main_vsi;
3224         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3225         struct rte_eth_rss_conf *rss_conf;
3226         struct ice_aqc_get_set_rss_keys key;
3227         uint16_t i, nb_q;
3228         int ret = 0;
3229         bool is_safe_mode = pf->adapter->is_safe_mode;
3230         uint32_t reg;
3231
3232         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3233         nb_q = dev->data->nb_rx_queues;
3234         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3235         vsi->rss_lut_size = pf->hash_lut_size;
3236
3237         if (is_safe_mode) {
3238                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3239                 return 0;
3240         }
3241
3242         if (!vsi->rss_key) {
3243                 vsi->rss_key = rte_zmalloc(NULL,
3244                                            vsi->rss_key_size, 0);
3245                 if (vsi->rss_key == NULL) {
3246                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3247                         return -ENOMEM;
3248                 }
3249         }
3250         if (!vsi->rss_lut) {
3251                 vsi->rss_lut = rte_zmalloc(NULL,
3252                                            vsi->rss_lut_size, 0);
3253                 if (vsi->rss_lut == NULL) {
3254                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3255                         rte_free(vsi->rss_key);
3256                         vsi->rss_key = NULL;
3257                         return -ENOMEM;
3258                 }
3259         }
3260         /* configure RSS key */
3261         if (!rss_conf->rss_key) {
3262                 /* Calculate the default hash key */
3263                 for (i = 0; i <= vsi->rss_key_size; i++)
3264                         vsi->rss_key[i] = (uint8_t)rte_rand();
3265         } else {
3266                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3267                            RTE_MIN(rss_conf->rss_key_len,
3268                                    vsi->rss_key_size));
3269         }
3270         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3271         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3272         if (ret)
3273                 goto out;
3274
3275         /* init RSS LUT table */
3276         for (i = 0; i < vsi->rss_lut_size; i++)
3277                 vsi->rss_lut[i] = i % nb_q;
3278
3279         ret = ice_aq_set_rss_lut(hw, vsi->idx,
3280                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
3281                                  vsi->rss_lut, vsi->rss_lut_size);
3282         if (ret)
3283                 goto out;
3284
3285         /* Enable registers for symmetric_toeplitz function. */
3286         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3287         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3288                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3289         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3290
3291         /* RSS hash configuration */
3292         ice_rss_hash_set(pf, rss_conf->rss_hf);
3293
3294         return 0;
3295 out:
3296         rte_free(vsi->rss_key);
3297         vsi->rss_key = NULL;
3298         rte_free(vsi->rss_lut);
3299         vsi->rss_lut = NULL;
3300         return -EINVAL;
3301 }
3302
3303 static int
3304 ice_dev_configure(struct rte_eth_dev *dev)
3305 {
3306         struct ice_adapter *ad =
3307                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3308         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3309         int ret;
3310
3311         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3312          * bulk allocation or vector Rx preconditions we will reset it.
3313          */
3314         ad->rx_bulk_alloc_allowed = true;
3315         ad->tx_simple_allowed = true;
3316
3317         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3318                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3319
3320         ret = ice_init_rss(pf);
3321         if (ret) {
3322                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3323                 return ret;
3324         }
3325
3326         return 0;
3327 }
3328
3329 static void
3330 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3331                        int base_queue, int nb_queue)
3332 {
3333         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3334         uint32_t val, val_tx;
3335         int i;
3336
3337         for (i = 0; i < nb_queue; i++) {
3338                 /*do actual bind*/
3339                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3340                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3341                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3342                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3343
3344                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3345                             base_queue + i, msix_vect);
3346                 /* set ITR0 value */
3347                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
3348                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3349                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3350         }
3351 }
3352
3353 void
3354 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3355 {
3356         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3357         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3358         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3359         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3360         uint16_t msix_vect = vsi->msix_intr;
3361         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3362         uint16_t queue_idx = 0;
3363         int record = 0;
3364         int i;
3365
3366         /* clear Rx/Tx queue interrupt */
3367         for (i = 0; i < vsi->nb_used_qps; i++) {
3368                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3369                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3370         }
3371
3372         /* PF bind interrupt */
3373         if (rte_intr_dp_is_en(intr_handle)) {
3374                 queue_idx = 0;
3375                 record = 1;
3376         }
3377
3378         for (i = 0; i < vsi->nb_used_qps; i++) {
3379                 if (nb_msix <= 1) {
3380                         if (!rte_intr_allow_others(intr_handle))
3381                                 msix_vect = ICE_MISC_VEC_ID;
3382
3383                         /* uio mapping all queue to one msix_vect */
3384                         __vsi_queues_bind_intr(vsi, msix_vect,
3385                                                vsi->base_queue + i,
3386                                                vsi->nb_used_qps - i);
3387
3388                         for (; !!record && i < vsi->nb_used_qps; i++)
3389                                 intr_handle->intr_vec[queue_idx + i] =
3390                                         msix_vect;
3391                         break;
3392                 }
3393
3394                 /* vfio 1:1 queue/msix_vect mapping */
3395                 __vsi_queues_bind_intr(vsi, msix_vect,
3396                                        vsi->base_queue + i, 1);
3397
3398                 if (!!record)
3399                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3400
3401                 msix_vect++;
3402                 nb_msix--;
3403         }
3404 }
3405
3406 void
3407 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3408 {
3409         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3410         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3411         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3412         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3413         uint16_t msix_intr, i;
3414
3415         if (rte_intr_allow_others(intr_handle))
3416                 for (i = 0; i < vsi->nb_used_qps; i++) {
3417                         msix_intr = vsi->msix_intr + i;
3418                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3419                                       GLINT_DYN_CTL_INTENA_M |
3420                                       GLINT_DYN_CTL_CLEARPBA_M |
3421                                       GLINT_DYN_CTL_ITR_INDX_M |
3422                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3423                 }
3424         else
3425                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3426                               GLINT_DYN_CTL_INTENA_M |
3427                               GLINT_DYN_CTL_CLEARPBA_M |
3428                               GLINT_DYN_CTL_ITR_INDX_M |
3429                               GLINT_DYN_CTL_WB_ON_ITR_M);
3430 }
3431
3432 static int
3433 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3434 {
3435         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3436         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3437         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3438         struct ice_vsi *vsi = pf->main_vsi;
3439         uint32_t intr_vector = 0;
3440
3441         rte_intr_disable(intr_handle);
3442
3443         /* check and configure queue intr-vector mapping */
3444         if ((rte_intr_cap_multiple(intr_handle) ||
3445              !RTE_ETH_DEV_SRIOV(dev).active) &&
3446             dev->data->dev_conf.intr_conf.rxq != 0) {
3447                 intr_vector = dev->data->nb_rx_queues;
3448                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3449                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3450                                     ICE_MAX_INTR_QUEUE_NUM);
3451                         return -ENOTSUP;
3452                 }
3453                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3454                         return -1;
3455         }
3456
3457         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3458                 intr_handle->intr_vec =
3459                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3460                             0);
3461                 if (!intr_handle->intr_vec) {
3462                         PMD_DRV_LOG(ERR,
3463                                     "Failed to allocate %d rx_queues intr_vec",
3464                                     dev->data->nb_rx_queues);
3465                         return -ENOMEM;
3466                 }
3467         }
3468
3469         /* Map queues with MSIX interrupt */
3470         vsi->nb_used_qps = dev->data->nb_rx_queues;
3471         ice_vsi_queues_bind_intr(vsi);
3472
3473         /* Enable interrupts for all the queues */
3474         ice_vsi_enable_queues_intr(vsi);
3475
3476         rte_intr_enable(intr_handle);
3477
3478         return 0;
3479 }
3480
3481 static void
3482 ice_get_init_link_status(struct rte_eth_dev *dev)
3483 {
3484         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3486         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3487         struct ice_link_status link_status;
3488         int ret;
3489
3490         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3491                                    &link_status, NULL);
3492         if (ret != ICE_SUCCESS) {
3493                 PMD_DRV_LOG(ERR, "Failed to get link info");
3494                 pf->init_link_up = false;
3495                 return;
3496         }
3497
3498         if (link_status.link_info & ICE_AQ_LINK_UP)
3499                 pf->init_link_up = true;
3500 }
3501
3502 static int
3503 ice_dev_start(struct rte_eth_dev *dev)
3504 {
3505         struct rte_eth_dev_data *data = dev->data;
3506         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3508         struct ice_vsi *vsi = pf->main_vsi;
3509         uint16_t nb_rxq = 0;
3510         uint16_t nb_txq, i;
3511         uint16_t max_frame_size;
3512         int mask, ret;
3513
3514         /* program Tx queues' context in hardware */
3515         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3516                 ret = ice_tx_queue_start(dev, nb_txq);
3517                 if (ret) {
3518                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3519                         goto tx_err;
3520                 }
3521         }
3522
3523         /* program Rx queues' context in hardware*/
3524         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3525                 ret = ice_rx_queue_start(dev, nb_rxq);
3526                 if (ret) {
3527                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3528                         goto rx_err;
3529                 }
3530         }
3531
3532         ice_set_rx_function(dev);
3533         ice_set_tx_function(dev);
3534
3535         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3536                         ETH_VLAN_EXTEND_MASK;
3537         ret = ice_vlan_offload_set(dev, mask);
3538         if (ret) {
3539                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3540                 goto rx_err;
3541         }
3542
3543         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3544         if (ice_rxq_intr_setup(dev))
3545                 return -EIO;
3546
3547         /* Enable receiving broadcast packets and transmitting packets */
3548         ret = ice_set_vsi_promisc(hw, vsi->idx,
3549                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3550                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3551                                   0);
3552         if (ret != ICE_SUCCESS)
3553                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3554
3555         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3556                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3557                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3558                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3559                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3560                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3561                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3562                                      NULL);
3563         if (ret != ICE_SUCCESS)
3564                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3565
3566         ice_get_init_link_status(dev);
3567
3568         ice_dev_set_link_up(dev);
3569
3570         /* Call get_link_info aq commond to enable/disable LSE */
3571         ice_link_update(dev, 0);
3572
3573         pf->adapter_stopped = false;
3574
3575         /* Set the max frame size to default value*/
3576         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3577                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3578                 ICE_FRAME_SIZE_MAX;
3579
3580         /* Set the max frame size to HW*/
3581         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3582
3583         return 0;
3584
3585         /* stop the started queues if failed to start all queues */
3586 rx_err:
3587         for (i = 0; i < nb_rxq; i++)
3588                 ice_rx_queue_stop(dev, i);
3589 tx_err:
3590         for (i = 0; i < nb_txq; i++)
3591                 ice_tx_queue_stop(dev, i);
3592
3593         return -EIO;
3594 }
3595
3596 static int
3597 ice_dev_reset(struct rte_eth_dev *dev)
3598 {
3599         int ret;
3600
3601         if (dev->data->sriov.active)
3602                 return -ENOTSUP;
3603
3604         ret = ice_dev_uninit(dev);
3605         if (ret) {
3606                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3607                 return -ENXIO;
3608         }
3609
3610         ret = ice_dev_init(dev);
3611         if (ret) {
3612                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3613                 return -ENXIO;
3614         }
3615
3616         return 0;
3617 }
3618
3619 static int
3620 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3621 {
3622         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3623         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624         struct ice_vsi *vsi = pf->main_vsi;
3625         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3626         bool is_safe_mode = pf->adapter->is_safe_mode;
3627         u64 phy_type_low;
3628         u64 phy_type_high;
3629
3630         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3631         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3632         dev_info->max_rx_queues = vsi->nb_qps;
3633         dev_info->max_tx_queues = vsi->nb_qps;
3634         dev_info->max_mac_addrs = vsi->max_macaddrs;
3635         dev_info->max_vfs = pci_dev->max_vfs;
3636         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3637         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3638
3639         dev_info->rx_offload_capa =
3640                 DEV_RX_OFFLOAD_VLAN_STRIP |
3641                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3642                 DEV_RX_OFFLOAD_KEEP_CRC |
3643                 DEV_RX_OFFLOAD_SCATTER |
3644                 DEV_RX_OFFLOAD_VLAN_FILTER;
3645         dev_info->tx_offload_capa =
3646                 DEV_TX_OFFLOAD_VLAN_INSERT |
3647                 DEV_TX_OFFLOAD_TCP_TSO |
3648                 DEV_TX_OFFLOAD_MULTI_SEGS |
3649                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3650         dev_info->flow_type_rss_offloads = 0;
3651
3652         if (!is_safe_mode) {
3653                 dev_info->rx_offload_capa |=
3654                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3655                         DEV_RX_OFFLOAD_UDP_CKSUM |
3656                         DEV_RX_OFFLOAD_TCP_CKSUM |
3657                         DEV_RX_OFFLOAD_QINQ_STRIP |
3658                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3659                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3660                         DEV_RX_OFFLOAD_RSS_HASH;
3661                 dev_info->tx_offload_capa |=
3662                         DEV_TX_OFFLOAD_QINQ_INSERT |
3663                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3664                         DEV_TX_OFFLOAD_UDP_CKSUM |
3665                         DEV_TX_OFFLOAD_TCP_CKSUM |
3666                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3667                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3668                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3669                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3670         }
3671
3672         dev_info->rx_queue_offload_capa = 0;
3673         dev_info->tx_queue_offload_capa = 0;
3674
3675         dev_info->reta_size = pf->hash_lut_size;
3676         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3677
3678         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3679                 .rx_thresh = {
3680                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3681                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3682                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3683                 },
3684                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3685                 .rx_drop_en = 0,
3686                 .offloads = 0,
3687         };
3688
3689         dev_info->default_txconf = (struct rte_eth_txconf) {
3690                 .tx_thresh = {
3691                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3692                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3693                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3694                 },
3695                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3696                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3697                 .offloads = 0,
3698         };
3699
3700         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3701                 .nb_max = ICE_MAX_RING_DESC,
3702                 .nb_min = ICE_MIN_RING_DESC,
3703                 .nb_align = ICE_ALIGN_RING_DESC,
3704         };
3705
3706         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3707                 .nb_max = ICE_MAX_RING_DESC,
3708                 .nb_min = ICE_MIN_RING_DESC,
3709                 .nb_align = ICE_ALIGN_RING_DESC,
3710         };
3711
3712         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3713                                ETH_LINK_SPEED_100M |
3714                                ETH_LINK_SPEED_1G |
3715                                ETH_LINK_SPEED_2_5G |
3716                                ETH_LINK_SPEED_5G |
3717                                ETH_LINK_SPEED_10G |
3718                                ETH_LINK_SPEED_20G |
3719                                ETH_LINK_SPEED_25G;
3720
3721         phy_type_low = hw->port_info->phy.phy_type_low;
3722         phy_type_high = hw->port_info->phy.phy_type_high;
3723
3724         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3725                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3726
3727         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3728                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3729                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3730
3731         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3732         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3733
3734         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3735         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3736         dev_info->default_rxportconf.nb_queues = 1;
3737         dev_info->default_txportconf.nb_queues = 1;
3738         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3739         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3740
3741         return 0;
3742 }
3743
3744 static inline int
3745 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3746                             struct rte_eth_link *link)
3747 {
3748         struct rte_eth_link *dst = link;
3749         struct rte_eth_link *src = &dev->data->dev_link;
3750
3751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3752                                 *(uint64_t *)src) == 0)
3753                 return -1;
3754
3755         return 0;
3756 }
3757
3758 static inline int
3759 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3760                              struct rte_eth_link *link)
3761 {
3762         struct rte_eth_link *dst = &dev->data->dev_link;
3763         struct rte_eth_link *src = link;
3764
3765         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3766                                 *(uint64_t *)src) == 0)
3767                 return -1;
3768
3769         return 0;
3770 }
3771
3772 static int
3773 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3774 {
3775 #define CHECK_INTERVAL 100  /* 100ms */
3776 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3777         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3778         struct ice_link_status link_status;
3779         struct rte_eth_link link, old;
3780         int status;
3781         unsigned int rep_cnt = MAX_REPEAT_TIME;
3782         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3783
3784         memset(&link, 0, sizeof(link));
3785         memset(&old, 0, sizeof(old));
3786         memset(&link_status, 0, sizeof(link_status));
3787         ice_atomic_read_link_status(dev, &old);
3788
3789         do {
3790                 /* Get link status information from hardware */
3791                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3792                                               &link_status, NULL);
3793                 if (status != ICE_SUCCESS) {
3794                         link.link_speed = ETH_SPEED_NUM_100M;
3795                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3796                         PMD_DRV_LOG(ERR, "Failed to get link info");
3797                         goto out;
3798                 }
3799
3800                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3801                 if (!wait_to_complete || link.link_status)
3802                         break;
3803
3804                 rte_delay_ms(CHECK_INTERVAL);
3805         } while (--rep_cnt);
3806
3807         if (!link.link_status)
3808                 goto out;
3809
3810         /* Full-duplex operation at all supported speeds */
3811         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3812
3813         /* Parse the link status */
3814         switch (link_status.link_speed) {
3815         case ICE_AQ_LINK_SPEED_10MB:
3816                 link.link_speed = ETH_SPEED_NUM_10M;
3817                 break;
3818         case ICE_AQ_LINK_SPEED_100MB:
3819                 link.link_speed = ETH_SPEED_NUM_100M;
3820                 break;
3821         case ICE_AQ_LINK_SPEED_1000MB:
3822                 link.link_speed = ETH_SPEED_NUM_1G;
3823                 break;
3824         case ICE_AQ_LINK_SPEED_2500MB:
3825                 link.link_speed = ETH_SPEED_NUM_2_5G;
3826                 break;
3827         case ICE_AQ_LINK_SPEED_5GB:
3828                 link.link_speed = ETH_SPEED_NUM_5G;
3829                 break;
3830         case ICE_AQ_LINK_SPEED_10GB:
3831                 link.link_speed = ETH_SPEED_NUM_10G;
3832                 break;
3833         case ICE_AQ_LINK_SPEED_20GB:
3834                 link.link_speed = ETH_SPEED_NUM_20G;
3835                 break;
3836         case ICE_AQ_LINK_SPEED_25GB:
3837                 link.link_speed = ETH_SPEED_NUM_25G;
3838                 break;
3839         case ICE_AQ_LINK_SPEED_40GB:
3840                 link.link_speed = ETH_SPEED_NUM_40G;
3841                 break;
3842         case ICE_AQ_LINK_SPEED_50GB:
3843                 link.link_speed = ETH_SPEED_NUM_50G;
3844                 break;
3845         case ICE_AQ_LINK_SPEED_100GB:
3846                 link.link_speed = ETH_SPEED_NUM_100G;
3847                 break;
3848         case ICE_AQ_LINK_SPEED_UNKNOWN:
3849                 PMD_DRV_LOG(ERR, "Unknown link speed");
3850                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3851                 break;
3852         default:
3853                 PMD_DRV_LOG(ERR, "None link speed");
3854                 link.link_speed = ETH_SPEED_NUM_NONE;
3855                 break;
3856         }
3857
3858         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3859                               ETH_LINK_SPEED_FIXED);
3860
3861 out:
3862         ice_atomic_write_link_status(dev, &link);
3863         if (link.link_status == old.link_status)
3864                 return -1;
3865
3866         return 0;
3867 }
3868
3869 /* Force the physical link state by getting the current PHY capabilities from
3870  * hardware and setting the PHY config based on the determined capabilities. If
3871  * link changes, link event will be triggered because both the Enable Automatic
3872  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3873  */
3874 static enum ice_status
3875 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3876 {
3877         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3878         struct ice_aqc_get_phy_caps_data *pcaps;
3879         struct ice_port_info *pi;
3880         enum ice_status status;
3881
3882         if (!hw || !hw->port_info)
3883                 return ICE_ERR_PARAM;
3884
3885         pi = hw->port_info;
3886
3887         pcaps = (struct ice_aqc_get_phy_caps_data *)
3888                 ice_malloc(hw, sizeof(*pcaps));
3889         if (!pcaps)
3890                 return ICE_ERR_NO_MEMORY;
3891
3892         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3893                                      NULL);
3894         if (status)
3895                 goto out;
3896
3897         /* No change in link */
3898         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3899             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3900                 goto out;
3901
3902         cfg.phy_type_low = pcaps->phy_type_low;
3903         cfg.phy_type_high = pcaps->phy_type_high;
3904         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3905         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3906         cfg.eee_cap = pcaps->eee_cap;
3907         cfg.eeer_value = pcaps->eeer_value;
3908         cfg.link_fec_opt = pcaps->link_fec_options;
3909         if (link_up)
3910                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3911         else
3912                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3913
3914         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3915
3916 out:
3917         ice_free(hw, pcaps);
3918         return status;
3919 }
3920
3921 static int
3922 ice_dev_set_link_up(struct rte_eth_dev *dev)
3923 {
3924         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925
3926         return ice_force_phys_link_state(hw, true);
3927 }
3928
3929 static int
3930 ice_dev_set_link_down(struct rte_eth_dev *dev)
3931 {
3932         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933
3934         return ice_force_phys_link_state(hw, false);
3935 }
3936
3937 static int
3938 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3939 {
3940         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3941         struct rte_eth_dev_data *dev_data = pf->dev_data;
3942         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3943
3944         /* check if mtu is within the allowed range */
3945         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3946                 return -EINVAL;
3947
3948         /* mtu setting is forbidden if port is start */
3949         if (dev_data->dev_started) {
3950                 PMD_DRV_LOG(ERR,
3951                             "port %d must be stopped before configuration",
3952                             dev_data->port_id);
3953                 return -EBUSY;
3954         }
3955
3956         if (frame_size > RTE_ETHER_MAX_LEN)
3957                 dev_data->dev_conf.rxmode.offloads |=
3958                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3959         else
3960                 dev_data->dev_conf.rxmode.offloads &=
3961                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3962
3963         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3964
3965         return 0;
3966 }
3967
3968 static int ice_macaddr_set(struct rte_eth_dev *dev,
3969                            struct rte_ether_addr *mac_addr)
3970 {
3971         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3972         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3973         struct ice_vsi *vsi = pf->main_vsi;
3974         struct ice_mac_filter *f;
3975         uint8_t flags = 0;
3976         int ret;
3977
3978         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3979                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3980                 return -EINVAL;
3981         }
3982
3983         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3984                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3985                         break;
3986         }
3987
3988         if (!f) {
3989                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3990                 return -EIO;
3991         }
3992
3993         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3994         if (ret != ICE_SUCCESS) {
3995                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3996                 return -EIO;
3997         }
3998         ret = ice_add_mac_filter(vsi, mac_addr);
3999         if (ret != ICE_SUCCESS) {
4000                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
4001                 return -EIO;
4002         }
4003         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
4004
4005         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
4006         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
4007         if (ret != ICE_SUCCESS)
4008                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
4009
4010         return 0;
4011 }
4012
4013 /* Add a MAC address, and update filters */
4014 static int
4015 ice_macaddr_add(struct rte_eth_dev *dev,
4016                 struct rte_ether_addr *mac_addr,
4017                 __rte_unused uint32_t index,
4018                 __rte_unused uint32_t pool)
4019 {
4020         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4021         struct ice_vsi *vsi = pf->main_vsi;
4022         int ret;
4023
4024         ret = ice_add_mac_filter(vsi, mac_addr);
4025         if (ret != ICE_SUCCESS) {
4026                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
4027                 return -EINVAL;
4028         }
4029
4030         return ICE_SUCCESS;
4031 }
4032
4033 /* Remove a MAC address, and update filters */
4034 static void
4035 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4036 {
4037         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4038         struct ice_vsi *vsi = pf->main_vsi;
4039         struct rte_eth_dev_data *data = dev->data;
4040         struct rte_ether_addr *macaddr;
4041         int ret;
4042
4043         macaddr = &data->mac_addrs[index];
4044         ret = ice_remove_mac_filter(vsi, macaddr);
4045         if (ret) {
4046                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4047                 return;
4048         }
4049 }
4050
4051 static int
4052 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4053 {
4054         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4055         struct ice_vsi *vsi = pf->main_vsi;
4056         int ret;
4057
4058         PMD_INIT_FUNC_TRACE();
4059
4060         if (on) {
4061                 ret = ice_add_vlan_filter(vsi, vlan_id);
4062                 if (ret < 0) {
4063                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4064                         return -EINVAL;
4065                 }
4066         } else {
4067                 ret = ice_remove_vlan_filter(vsi, vlan_id);
4068                 if (ret < 0) {
4069                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4070                         return -EINVAL;
4071                 }
4072         }
4073
4074         return 0;
4075 }
4076
4077 /* Configure vlan filter on or off */
4078 static int
4079 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4080 {
4081         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4082         struct ice_vsi_ctx ctxt;
4083         uint8_t sec_flags, sw_flags2;
4084         int ret = 0;
4085
4086         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
4087                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
4088         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4089
4090         if (on) {
4091                 vsi->info.sec_flags |= sec_flags;
4092                 vsi->info.sw_flags2 |= sw_flags2;
4093         } else {
4094                 vsi->info.sec_flags &= ~sec_flags;
4095                 vsi->info.sw_flags2 &= ~sw_flags2;
4096         }
4097         vsi->info.sw_id = hw->port_info->sw_id;
4098         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4099         ctxt.info.valid_sections =
4100                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4101                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4102         ctxt.vsi_num = vsi->vsi_id;
4103
4104         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4105         if (ret) {
4106                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4107                             on ? "enable" : "disable");
4108                 return -EINVAL;
4109         } else {
4110                 vsi->info.valid_sections |=
4111                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4112                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4113         }
4114
4115         /* consist with other drivers, allow untagged packet when vlan filter on */
4116         if (on)
4117                 ret = ice_add_vlan_filter(vsi, 0);
4118         else
4119                 ret = ice_remove_vlan_filter(vsi, 0);
4120
4121         return 0;
4122 }
4123
4124 static int
4125 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
4126 {
4127         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4128         struct ice_vsi_ctx ctxt;
4129         uint8_t vlan_flags;
4130         int ret = 0;
4131
4132         /* Check if it has been already on or off */
4133         if (vsi->info.valid_sections &
4134                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
4135                 if (on) {
4136                         if ((vsi->info.vlan_flags &
4137                              ICE_AQ_VSI_VLAN_EMOD_M) ==
4138                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
4139                                 return 0; /* already on */
4140                 } else {
4141                         if ((vsi->info.vlan_flags &
4142                              ICE_AQ_VSI_VLAN_EMOD_M) ==
4143                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
4144                                 return 0; /* already off */
4145                 }
4146         }
4147
4148         if (on)
4149                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
4150         else
4151                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
4152         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
4153         vsi->info.vlan_flags |= vlan_flags;
4154         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4155         ctxt.info.valid_sections =
4156                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4157         ctxt.vsi_num = vsi->vsi_id;
4158         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4159         if (ret) {
4160                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4161                             on ? "enable" : "disable");
4162                 return -EINVAL;
4163         }
4164
4165         vsi->info.valid_sections |=
4166                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4167
4168         return ret;
4169 }
4170
4171 static int
4172 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4173 {
4174         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4175         struct ice_vsi *vsi = pf->main_vsi;
4176         struct rte_eth_rxmode *rxmode;
4177
4178         rxmode = &dev->data->dev_conf.rxmode;
4179         if (mask & ETH_VLAN_FILTER_MASK) {
4180                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4181                         ice_vsi_config_vlan_filter(vsi, true);
4182                 else
4183                         ice_vsi_config_vlan_filter(vsi, false);
4184         }
4185
4186         if (mask & ETH_VLAN_STRIP_MASK) {
4187                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4188                         ice_vsi_config_vlan_stripping(vsi, true);
4189                 else
4190                         ice_vsi_config_vlan_stripping(vsi, false);
4191         }
4192
4193         if (mask & ETH_VLAN_EXTEND_MASK) {
4194                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
4195                         ice_vsi_config_double_vlan(vsi, true);
4196                 else
4197                         ice_vsi_config_double_vlan(vsi, false);
4198         }
4199
4200         return 0;
4201 }
4202
4203 static int
4204 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4205 {
4206         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4207         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4208         int ret;
4209
4210         if (!lut)
4211                 return -EINVAL;
4212
4213         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4214                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
4215                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4216                 if (ret) {
4217                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4218                         return -EINVAL;
4219                 }
4220         } else {
4221                 uint64_t *lut_dw = (uint64_t *)lut;
4222                 uint16_t i, lut_size_dw = lut_size / 4;
4223
4224                 for (i = 0; i < lut_size_dw; i++)
4225                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4226         }
4227
4228         return 0;
4229 }
4230
4231 static int
4232 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4233 {
4234         struct ice_pf *pf;
4235         struct ice_hw *hw;
4236         int ret;
4237
4238         if (!vsi || !lut)
4239                 return -EINVAL;
4240
4241         pf = ICE_VSI_TO_PF(vsi);
4242         hw = ICE_VSI_TO_HW(vsi);
4243
4244         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4245                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
4246                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4247                 if (ret) {
4248                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4249                         return -EINVAL;
4250                 }
4251         } else {
4252                 uint64_t *lut_dw = (uint64_t *)lut;
4253                 uint16_t i, lut_size_dw = lut_size / 4;
4254
4255                 for (i = 0; i < lut_size_dw; i++)
4256                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4257
4258                 ice_flush(hw);
4259         }
4260
4261         return 0;
4262 }
4263
4264 static int
4265 ice_rss_reta_update(struct rte_eth_dev *dev,
4266                     struct rte_eth_rss_reta_entry64 *reta_conf,
4267                     uint16_t reta_size)
4268 {
4269         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4270         uint16_t i, lut_size = pf->hash_lut_size;
4271         uint16_t idx, shift;
4272         uint8_t *lut;
4273         int ret;
4274
4275         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4276             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4277             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4278                 PMD_DRV_LOG(ERR,
4279                             "The size of hash lookup table configured (%d)"
4280                             "doesn't match the number hardware can "
4281                             "supported (128, 512, 2048)",
4282                             reta_size);
4283                 return -EINVAL;
4284         }
4285
4286         /* It MUST use the current LUT size to get the RSS lookup table,
4287          * otherwise if will fail with -100 error code.
4288          */
4289         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4290         if (!lut) {
4291                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4292                 return -ENOMEM;
4293         }
4294         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4295         if (ret)
4296                 goto out;
4297
4298         for (i = 0; i < reta_size; i++) {
4299                 idx = i / RTE_RETA_GROUP_SIZE;
4300                 shift = i % RTE_RETA_GROUP_SIZE;
4301                 if (reta_conf[idx].mask & (1ULL << shift))
4302                         lut[i] = reta_conf[idx].reta[shift];
4303         }
4304         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4305         if (ret == 0 && lut_size != reta_size) {
4306                 PMD_DRV_LOG(INFO,
4307                             "The size of hash lookup table is changed from (%d) to (%d)",
4308                             lut_size, reta_size);
4309                 pf->hash_lut_size = reta_size;
4310         }
4311
4312 out:
4313         rte_free(lut);
4314
4315         return ret;
4316 }
4317
4318 static int
4319 ice_rss_reta_query(struct rte_eth_dev *dev,
4320                    struct rte_eth_rss_reta_entry64 *reta_conf,
4321                    uint16_t reta_size)
4322 {
4323         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4324         uint16_t i, lut_size = pf->hash_lut_size;
4325         uint16_t idx, shift;
4326         uint8_t *lut;
4327         int ret;
4328
4329         if (reta_size != lut_size) {
4330                 PMD_DRV_LOG(ERR,
4331                             "The size of hash lookup table configured (%d)"
4332                             "doesn't match the number hardware can "
4333                             "supported (%d)",
4334                             reta_size, lut_size);
4335                 return -EINVAL;
4336         }
4337
4338         lut = rte_zmalloc(NULL, reta_size, 0);
4339         if (!lut) {
4340                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4341                 return -ENOMEM;
4342         }
4343
4344         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4345         if (ret)
4346                 goto out;
4347
4348         for (i = 0; i < reta_size; i++) {
4349                 idx = i / RTE_RETA_GROUP_SIZE;
4350                 shift = i % RTE_RETA_GROUP_SIZE;
4351                 if (reta_conf[idx].mask & (1ULL << shift))
4352                         reta_conf[idx].reta[shift] = lut[i];
4353         }
4354
4355 out:
4356         rte_free(lut);
4357
4358         return ret;
4359 }
4360
4361 static int
4362 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4363 {
4364         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4365         int ret = 0;
4366
4367         if (!key || key_len == 0) {
4368                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4369                 return 0;
4370         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4371                    sizeof(uint32_t)) {
4372                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4373                 return -EINVAL;
4374         }
4375
4376         struct ice_aqc_get_set_rss_keys *key_dw =
4377                 (struct ice_aqc_get_set_rss_keys *)key;
4378
4379         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4380         if (ret) {
4381                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4382                 ret = -EINVAL;
4383         }
4384
4385         return ret;
4386 }
4387
4388 static int
4389 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4390 {
4391         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4392         int ret;
4393
4394         if (!key || !key_len)
4395                 return -EINVAL;
4396
4397         ret = ice_aq_get_rss_key
4398                 (hw, vsi->idx,
4399                  (struct ice_aqc_get_set_rss_keys *)key);
4400         if (ret) {
4401                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4402                 return -EINVAL;
4403         }
4404         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4405
4406         return 0;
4407 }
4408
4409 static int
4410 ice_rss_hash_update(struct rte_eth_dev *dev,
4411                     struct rte_eth_rss_conf *rss_conf)
4412 {
4413         enum ice_status status = ICE_SUCCESS;
4414         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4415         struct ice_vsi *vsi = pf->main_vsi;
4416
4417         /* set hash key */
4418         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4419         if (status)
4420                 return status;
4421
4422         if (rss_conf->rss_hf == 0)
4423                 return 0;
4424
4425         /* RSS hash configuration */
4426         ice_rss_hash_set(pf, rss_conf->rss_hf);
4427
4428         return 0;
4429 }
4430
4431 static int
4432 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4433                       struct rte_eth_rss_conf *rss_conf)
4434 {
4435         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4436         struct ice_vsi *vsi = pf->main_vsi;
4437
4438         ice_get_rss_key(vsi, rss_conf->rss_key,
4439                         &rss_conf->rss_key_len);
4440
4441         /* TODO: default set to 0 as hf config is not supported now */
4442         rss_conf->rss_hf = 0;
4443         return 0;
4444 }
4445
4446 static int
4447 ice_promisc_enable(struct rte_eth_dev *dev)
4448 {
4449         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4450         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451         struct ice_vsi *vsi = pf->main_vsi;
4452         enum ice_status status;
4453         uint8_t pmask;
4454         int ret = 0;
4455
4456         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4457                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4458
4459         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4460         switch (status) {
4461         case ICE_ERR_ALREADY_EXISTS:
4462                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4463         case ICE_SUCCESS:
4464                 break;
4465         default:
4466                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4467                 ret = -EAGAIN;
4468         }
4469
4470         return ret;
4471 }
4472
4473 static int
4474 ice_promisc_disable(struct rte_eth_dev *dev)
4475 {
4476         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4477         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478         struct ice_vsi *vsi = pf->main_vsi;
4479         enum ice_status status;
4480         uint8_t pmask;
4481         int ret = 0;
4482
4483         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4484                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4485
4486         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4487         if (status != ICE_SUCCESS) {
4488                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4489                 ret = -EAGAIN;
4490         }
4491
4492         return ret;
4493 }
4494
4495 static int
4496 ice_allmulti_enable(struct rte_eth_dev *dev)
4497 {
4498         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4499         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500         struct ice_vsi *vsi = pf->main_vsi;
4501         enum ice_status status;
4502         uint8_t pmask;
4503         int ret = 0;
4504
4505         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4506
4507         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4508
4509         switch (status) {
4510         case ICE_ERR_ALREADY_EXISTS:
4511                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4512         case ICE_SUCCESS:
4513                 break;
4514         default:
4515                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4516                 ret = -EAGAIN;
4517         }
4518
4519         return ret;
4520 }
4521
4522 static int
4523 ice_allmulti_disable(struct rte_eth_dev *dev)
4524 {
4525         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4526         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         struct ice_vsi *vsi = pf->main_vsi;
4528         enum ice_status status;
4529         uint8_t pmask;
4530         int ret = 0;
4531
4532         if (dev->data->promiscuous == 1)
4533                 return 0; /* must remain in all_multicast mode */
4534
4535         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4536
4537         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4538         if (status != ICE_SUCCESS) {
4539                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4540                 ret = -EAGAIN;
4541         }
4542
4543         return ret;
4544 }
4545
4546 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4547                                     uint16_t queue_id)
4548 {
4549         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4551         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4552         uint32_t val;
4553         uint16_t msix_intr;
4554
4555         msix_intr = intr_handle->intr_vec[queue_id];
4556
4557         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4558               GLINT_DYN_CTL_ITR_INDX_M;
4559         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4560
4561         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4562         rte_intr_ack(&pci_dev->intr_handle);
4563
4564         return 0;
4565 }
4566
4567 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4568                                      uint16_t queue_id)
4569 {
4570         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4571         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4572         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         uint16_t msix_intr;
4574
4575         msix_intr = intr_handle->intr_vec[queue_id];
4576
4577         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4578
4579         return 0;
4580 }
4581
4582 static int
4583 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4584 {
4585         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586         u8 ver, patch;
4587         u16 build;
4588         int ret;
4589
4590         ver = hw->flash.orom.major;
4591         patch = hw->flash.orom.patch;
4592         build = hw->flash.orom.build;
4593
4594         ret = snprintf(fw_version, fw_size,
4595                         "%x.%02x 0x%08x %d.%d.%d",
4596                         hw->flash.nvm.major,
4597                         hw->flash.nvm.minor,
4598                         hw->flash.nvm.eetrack,
4599                         ver, build, patch);
4600
4601         /* add the size of '\0' */
4602         ret += 1;
4603         if (fw_size < (u32)ret)
4604                 return ret;
4605         else
4606                 return 0;
4607 }
4608
4609 static int
4610 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4611 {
4612         struct ice_hw *hw;
4613         struct ice_vsi_ctx ctxt;
4614         uint8_t vlan_flags = 0;
4615         int ret;
4616
4617         if (!vsi || !info) {
4618                 PMD_DRV_LOG(ERR, "invalid parameters");
4619                 return -EINVAL;
4620         }
4621
4622         if (info->on) {
4623                 vsi->info.pvid = info->config.pvid;
4624                 /**
4625                  * If insert pvid is enabled, only tagged pkts are
4626                  * allowed to be sent out.
4627                  */
4628                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
4629                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4630         } else {
4631                 vsi->info.pvid = 0;
4632                 if (info->config.reject.tagged == 0)
4633                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
4634
4635                 if (info->config.reject.untagged == 0)
4636                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4637         }
4638         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
4639                                   ICE_AQ_VSI_VLAN_MODE_M);
4640         vsi->info.vlan_flags |= vlan_flags;
4641         memset(&ctxt, 0, sizeof(ctxt));
4642         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4643         ctxt.info.valid_sections =
4644                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4645         ctxt.vsi_num = vsi->vsi_id;
4646
4647         hw = ICE_VSI_TO_HW(vsi);
4648         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4649         if (ret != ICE_SUCCESS) {
4650                 PMD_DRV_LOG(ERR,
4651                             "update VSI for VLAN insert failed, err %d",
4652                             ret);
4653                 return -EINVAL;
4654         }
4655
4656         vsi->info.valid_sections |=
4657                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4658
4659         return ret;
4660 }
4661
4662 static int
4663 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4664 {
4665         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4666         struct ice_vsi *vsi = pf->main_vsi;
4667         struct rte_eth_dev_data *data = pf->dev_data;
4668         struct ice_vsi_vlan_pvid_info info;
4669         int ret;
4670
4671         memset(&info, 0, sizeof(info));
4672         info.on = on;
4673         if (info.on) {
4674                 info.config.pvid = pvid;
4675         } else {
4676                 info.config.reject.tagged =
4677                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4678                 info.config.reject.untagged =
4679                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4680         }
4681
4682         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4683         if (ret < 0) {
4684                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4685                 return -EINVAL;
4686         }
4687
4688         return 0;
4689 }
4690
4691 static int
4692 ice_get_eeprom_length(struct rte_eth_dev *dev)
4693 {
4694         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695
4696         return hw->flash.flash_size;
4697 }
4698
4699 static int
4700 ice_get_eeprom(struct rte_eth_dev *dev,
4701                struct rte_dev_eeprom_info *eeprom)
4702 {
4703         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         enum ice_status status = ICE_SUCCESS;
4705         uint8_t *data = eeprom->data;
4706
4707         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4708
4709         status = ice_acquire_nvm(hw, ICE_RES_READ);
4710         if (status) {
4711                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4712                 return -EIO;
4713         }
4714
4715         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4716                                    data, false);
4717
4718         ice_release_nvm(hw);
4719
4720         if (status) {
4721                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4722                 return -EIO;
4723         }
4724
4725         return 0;
4726 }
4727
4728 static void
4729 ice_stat_update_32(struct ice_hw *hw,
4730                    uint32_t reg,
4731                    bool offset_loaded,
4732                    uint64_t *offset,
4733                    uint64_t *stat)
4734 {
4735         uint64_t new_data;
4736
4737         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4738         if (!offset_loaded)
4739                 *offset = new_data;
4740
4741         if (new_data >= *offset)
4742                 *stat = (uint64_t)(new_data - *offset);
4743         else
4744                 *stat = (uint64_t)((new_data +
4745                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4746                                    - *offset);
4747 }
4748
4749 static void
4750 ice_stat_update_40(struct ice_hw *hw,
4751                    uint32_t hireg,
4752                    uint32_t loreg,
4753                    bool offset_loaded,
4754                    uint64_t *offset,
4755                    uint64_t *stat)
4756 {
4757         uint64_t new_data;
4758
4759         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4760         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4761                     ICE_32_BIT_WIDTH;
4762
4763         if (!offset_loaded)
4764                 *offset = new_data;
4765
4766         if (new_data >= *offset)
4767                 *stat = new_data - *offset;
4768         else
4769                 *stat = (uint64_t)((new_data +
4770                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4771                                    *offset);
4772
4773         *stat &= ICE_40_BIT_MASK;
4774 }
4775
4776 /* Get all the statistics of a VSI */
4777 static void
4778 ice_update_vsi_stats(struct ice_vsi *vsi)
4779 {
4780         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4781         struct ice_eth_stats *nes = &vsi->eth_stats;
4782         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4783         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4784
4785         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4786                            vsi->offset_loaded, &oes->rx_bytes,
4787                            &nes->rx_bytes);
4788         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4789                            vsi->offset_loaded, &oes->rx_unicast,
4790                            &nes->rx_unicast);
4791         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4792                            vsi->offset_loaded, &oes->rx_multicast,
4793                            &nes->rx_multicast);
4794         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4795                            vsi->offset_loaded, &oes->rx_broadcast,
4796                            &nes->rx_broadcast);
4797         /* enlarge the limitation when rx_bytes overflowed */
4798         if (vsi->offset_loaded) {
4799                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4800                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4801                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4802         }
4803         vsi->old_rx_bytes = nes->rx_bytes;
4804         /* exclude CRC bytes */
4805         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4806                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4807
4808         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4809                            &oes->rx_discards, &nes->rx_discards);
4810         /* GLV_REPC not supported */
4811         /* GLV_RMPC not supported */
4812         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4813                            &oes->rx_unknown_protocol,
4814                            &nes->rx_unknown_protocol);
4815         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4816                            vsi->offset_loaded, &oes->tx_bytes,
4817                            &nes->tx_bytes);
4818         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4819                            vsi->offset_loaded, &oes->tx_unicast,
4820                            &nes->tx_unicast);
4821         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4822                            vsi->offset_loaded, &oes->tx_multicast,
4823                            &nes->tx_multicast);
4824         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4825                            vsi->offset_loaded,  &oes->tx_broadcast,
4826                            &nes->tx_broadcast);
4827         /* GLV_TDPC not supported */
4828         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4829                            &oes->tx_errors, &nes->tx_errors);
4830         /* enlarge the limitation when tx_bytes overflowed */
4831         if (vsi->offset_loaded) {
4832                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4833                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4834                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4835         }
4836         vsi->old_tx_bytes = nes->tx_bytes;
4837         vsi->offset_loaded = true;
4838
4839         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4840                     vsi->vsi_id);
4841         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4842         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4843         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4844         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4845         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4846         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4847                     nes->rx_unknown_protocol);
4848         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4849         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4850         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4851         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4852         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4853         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4854         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4855                     vsi->vsi_id);
4856 }
4857
4858 static void
4859 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4860 {
4861         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4862         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4863
4864         /* Get statistics of struct ice_eth_stats */
4865         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4866                            GLPRT_GORCL(hw->port_info->lport),
4867                            pf->offset_loaded, &os->eth.rx_bytes,
4868                            &ns->eth.rx_bytes);
4869         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4870                            GLPRT_UPRCL(hw->port_info->lport),
4871                            pf->offset_loaded, &os->eth.rx_unicast,
4872                            &ns->eth.rx_unicast);
4873         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4874                            GLPRT_MPRCL(hw->port_info->lport),
4875                            pf->offset_loaded, &os->eth.rx_multicast,
4876                            &ns->eth.rx_multicast);
4877         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4878                            GLPRT_BPRCL(hw->port_info->lport),
4879                            pf->offset_loaded, &os->eth.rx_broadcast,
4880                            &ns->eth.rx_broadcast);
4881         ice_stat_update_32(hw, PRTRPB_RDPC,
4882                            pf->offset_loaded, &os->eth.rx_discards,
4883                            &ns->eth.rx_discards);
4884         /* enlarge the limitation when rx_bytes overflowed */
4885         if (pf->offset_loaded) {
4886                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4887                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4888                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4889         }
4890         pf->old_rx_bytes = ns->eth.rx_bytes;
4891
4892         /* Workaround: CRC size should not be included in byte statistics,
4893          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4894          * packet.
4895          */
4896         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4897                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4898
4899         /* GLPRT_REPC not supported */
4900         /* GLPRT_RMPC not supported */
4901         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4902                            pf->offset_loaded,
4903                            &os->eth.rx_unknown_protocol,
4904                            &ns->eth.rx_unknown_protocol);
4905         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4906                            GLPRT_GOTCL(hw->port_info->lport),
4907                            pf->offset_loaded, &os->eth.tx_bytes,
4908                            &ns->eth.tx_bytes);
4909         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4910                            GLPRT_UPTCL(hw->port_info->lport),
4911                            pf->offset_loaded, &os->eth.tx_unicast,
4912                            &ns->eth.tx_unicast);
4913         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4914                            GLPRT_MPTCL(hw->port_info->lport),
4915                            pf->offset_loaded, &os->eth.tx_multicast,
4916                            &ns->eth.tx_multicast);
4917         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4918                            GLPRT_BPTCL(hw->port_info->lport),
4919                            pf->offset_loaded, &os->eth.tx_broadcast,
4920                            &ns->eth.tx_broadcast);
4921         /* enlarge the limitation when tx_bytes overflowed */
4922         if (pf->offset_loaded) {
4923                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4924                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4925                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4926         }
4927         pf->old_tx_bytes = ns->eth.tx_bytes;
4928         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4929                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4930
4931         /* GLPRT_TEPC not supported */
4932
4933         /* additional port specific stats */
4934         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4935                            pf->offset_loaded, &os->tx_dropped_link_down,
4936                            &ns->tx_dropped_link_down);
4937         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4938                            pf->offset_loaded, &os->crc_errors,
4939                            &ns->crc_errors);
4940         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4941                            pf->offset_loaded, &os->illegal_bytes,
4942                            &ns->illegal_bytes);
4943         /* GLPRT_ERRBC not supported */
4944         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4945                            pf->offset_loaded, &os->mac_local_faults,
4946                            &ns->mac_local_faults);
4947         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4948                            pf->offset_loaded, &os->mac_remote_faults,
4949                            &ns->mac_remote_faults);
4950
4951         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4952                            pf->offset_loaded, &os->rx_len_errors,
4953                            &ns->rx_len_errors);
4954
4955         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4956                            pf->offset_loaded, &os->link_xon_rx,
4957                            &ns->link_xon_rx);
4958         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4959                            pf->offset_loaded, &os->link_xoff_rx,
4960                            &ns->link_xoff_rx);
4961         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4962                            pf->offset_loaded, &os->link_xon_tx,
4963                            &ns->link_xon_tx);
4964         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4965                            pf->offset_loaded, &os->link_xoff_tx,
4966                            &ns->link_xoff_tx);
4967         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4968                            GLPRT_PRC64L(hw->port_info->lport),
4969                            pf->offset_loaded, &os->rx_size_64,
4970                            &ns->rx_size_64);
4971         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4972                            GLPRT_PRC127L(hw->port_info->lport),
4973                            pf->offset_loaded, &os->rx_size_127,
4974                            &ns->rx_size_127);
4975         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4976                            GLPRT_PRC255L(hw->port_info->lport),
4977                            pf->offset_loaded, &os->rx_size_255,
4978                            &ns->rx_size_255);
4979         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4980                            GLPRT_PRC511L(hw->port_info->lport),
4981                            pf->offset_loaded, &os->rx_size_511,
4982                            &ns->rx_size_511);
4983         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4984                            GLPRT_PRC1023L(hw->port_info->lport),
4985                            pf->offset_loaded, &os->rx_size_1023,
4986                            &ns->rx_size_1023);
4987         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4988                            GLPRT_PRC1522L(hw->port_info->lport),
4989                            pf->offset_loaded, &os->rx_size_1522,
4990                            &ns->rx_size_1522);
4991         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4992                            GLPRT_PRC9522L(hw->port_info->lport),
4993                            pf->offset_loaded, &os->rx_size_big,
4994                            &ns->rx_size_big);
4995         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4996                            pf->offset_loaded, &os->rx_undersize,
4997                            &ns->rx_undersize);
4998         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4999                            pf->offset_loaded, &os->rx_fragments,
5000                            &ns->rx_fragments);
5001         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5002                            pf->offset_loaded, &os->rx_oversize,
5003                            &ns->rx_oversize);
5004         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5005                            pf->offset_loaded, &os->rx_jabber,
5006                            &ns->rx_jabber);
5007         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5008                            GLPRT_PTC64L(hw->port_info->lport),
5009                            pf->offset_loaded, &os->tx_size_64,
5010                            &ns->tx_size_64);
5011         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5012                            GLPRT_PTC127L(hw->port_info->lport),
5013                            pf->offset_loaded, &os->tx_size_127,
5014                            &ns->tx_size_127);
5015         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5016                            GLPRT_PTC255L(hw->port_info->lport),
5017                            pf->offset_loaded, &os->tx_size_255,
5018                            &ns->tx_size_255);
5019         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5020                            GLPRT_PTC511L(hw->port_info->lport),
5021                            pf->offset_loaded, &os->tx_size_511,
5022                            &ns->tx_size_511);
5023         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5024                            GLPRT_PTC1023L(hw->port_info->lport),
5025                            pf->offset_loaded, &os->tx_size_1023,
5026                            &ns->tx_size_1023);
5027         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5028                            GLPRT_PTC1522L(hw->port_info->lport),
5029                            pf->offset_loaded, &os->tx_size_1522,
5030                            &ns->tx_size_1522);
5031         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5032                            GLPRT_PTC9522L(hw->port_info->lport),
5033                            pf->offset_loaded, &os->tx_size_big,
5034                            &ns->tx_size_big);
5035
5036         /* GLPRT_MSPDC not supported */
5037         /* GLPRT_XEC not supported */
5038
5039         pf->offset_loaded = true;
5040
5041         if (pf->main_vsi)
5042                 ice_update_vsi_stats(pf->main_vsi);
5043 }
5044
5045 /* Get all statistics of a port */
5046 static int
5047 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5048 {
5049         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5050         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5052
5053         /* call read registers - updates values, now write them to struct */
5054         ice_read_stats_registers(pf, hw);
5055
5056         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5057                           pf->main_vsi->eth_stats.rx_multicast +
5058                           pf->main_vsi->eth_stats.rx_broadcast -
5059                           pf->main_vsi->eth_stats.rx_discards;
5060         stats->opackets = ns->eth.tx_unicast +
5061                           ns->eth.tx_multicast +
5062                           ns->eth.tx_broadcast;
5063         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5064         stats->obytes   = ns->eth.tx_bytes;
5065         stats->oerrors  = ns->eth.tx_errors +
5066                           pf->main_vsi->eth_stats.tx_errors;
5067
5068         /* Rx Errors */
5069         stats->imissed  = ns->eth.rx_discards +
5070                           pf->main_vsi->eth_stats.rx_discards;
5071         stats->ierrors  = ns->crc_errors +
5072                           ns->rx_undersize +
5073                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5074
5075         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5076         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5077         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5078         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5079         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5080         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5081         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5082                     pf->main_vsi->eth_stats.rx_discards);
5083         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5084                     ns->eth.rx_unknown_protocol);
5085         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5086         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5087         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5088         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5089         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5090         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5091                     pf->main_vsi->eth_stats.tx_discards);
5092         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5093
5094         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5095                     ns->tx_dropped_link_down);
5096         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5097         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5098                     ns->illegal_bytes);
5099         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5100         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5101                     ns->mac_local_faults);
5102         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5103                     ns->mac_remote_faults);
5104         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5105         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5106         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5107         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5108         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5109         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5110         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5111         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5112         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5113         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5114         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5115         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5116         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5117         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5118         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5119         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5120         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5121         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5122         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5123         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5124         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5125         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5126         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5127         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5128         return 0;
5129 }
5130
5131 /* Reset the statistics */
5132 static int
5133 ice_stats_reset(struct rte_eth_dev *dev)
5134 {
5135         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5136         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5137
5138         /* Mark PF and VSI stats to update the offset, aka "reset" */
5139         pf->offset_loaded = false;
5140         if (pf->main_vsi)
5141                 pf->main_vsi->offset_loaded = false;
5142
5143         /* read the stats, reading current register values into offset */
5144         ice_read_stats_registers(pf, hw);
5145
5146         return 0;
5147 }
5148
5149 static uint32_t
5150 ice_xstats_calc_num(void)
5151 {
5152         uint32_t num;
5153
5154         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5155
5156         return num;
5157 }
5158
5159 static int
5160 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5161                unsigned int n)
5162 {
5163         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5164         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165         unsigned int i;
5166         unsigned int count;
5167         struct ice_hw_port_stats *hw_stats = &pf->stats;
5168
5169         count = ice_xstats_calc_num();
5170         if (n < count)
5171                 return count;
5172
5173         ice_read_stats_registers(pf, hw);
5174
5175         if (!xstats)
5176                 return 0;
5177
5178         count = 0;
5179
5180         /* Get stats from ice_eth_stats struct */
5181         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5182                 xstats[count].value =
5183                         *(uint64_t *)((char *)&hw_stats->eth +
5184                                       ice_stats_strings[i].offset);
5185                 xstats[count].id = count;
5186                 count++;
5187         }
5188
5189         /* Get individiual stats from ice_hw_port struct */
5190         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5191                 xstats[count].value =
5192                         *(uint64_t *)((char *)hw_stats +
5193                                       ice_hw_port_strings[i].offset);
5194                 xstats[count].id = count;
5195                 count++;
5196         }
5197
5198         return count;
5199 }
5200
5201 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5202                                 struct rte_eth_xstat_name *xstats_names,
5203                                 __rte_unused unsigned int limit)
5204 {
5205         unsigned int count = 0;
5206         unsigned int i;
5207
5208         if (!xstats_names)
5209                 return ice_xstats_calc_num();
5210
5211         /* Note: limit checked in rte_eth_xstats_names() */
5212
5213         /* Get stats from ice_eth_stats struct */
5214         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5215                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5216                         sizeof(xstats_names[count].name));
5217                 count++;
5218         }
5219
5220         /* Get individiual stats from ice_hw_port struct */
5221         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5222                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5223                         sizeof(xstats_names[count].name));
5224                 count++;
5225         }
5226
5227         return count;
5228 }
5229
5230 static int
5231 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5232                      enum rte_filter_type filter_type,
5233                      enum rte_filter_op filter_op,
5234                      void *arg)
5235 {
5236         int ret = 0;
5237
5238         if (!dev)
5239                 return -EINVAL;
5240
5241         switch (filter_type) {
5242         case RTE_ETH_FILTER_GENERIC:
5243                 if (filter_op != RTE_ETH_FILTER_GET)
5244                         return -EINVAL;
5245                 *(const void **)arg = &ice_flow_ops;
5246                 break;
5247         default:
5248                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5249                                         filter_type);
5250                 ret = -EINVAL;
5251                 break;
5252         }
5253
5254         return ret;
5255 }
5256
5257 /* Add UDP tunneling port */
5258 static int
5259 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5260                              struct rte_eth_udp_tunnel *udp_tunnel)
5261 {
5262         int ret = 0;
5263         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5264
5265         if (udp_tunnel == NULL)
5266                 return -EINVAL;
5267
5268         switch (udp_tunnel->prot_type) {
5269         case RTE_TUNNEL_TYPE_VXLAN:
5270                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5271                 break;
5272         default:
5273                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5274                 ret = -EINVAL;
5275                 break;
5276         }
5277
5278         return ret;
5279 }
5280
5281 /* Delete UDP tunneling port */
5282 static int
5283 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5284                              struct rte_eth_udp_tunnel *udp_tunnel)
5285 {
5286         int ret = 0;
5287         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5288
5289         if (udp_tunnel == NULL)
5290                 return -EINVAL;
5291
5292         switch (udp_tunnel->prot_type) {
5293         case RTE_TUNNEL_TYPE_VXLAN:
5294                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5295                 break;
5296         default:
5297                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5298                 ret = -EINVAL;
5299                 break;
5300         }
5301
5302         return ret;
5303 }
5304
5305 static int
5306 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5307               struct rte_pci_device *pci_dev)
5308 {
5309         return rte_eth_dev_pci_generic_probe(pci_dev,
5310                                              sizeof(struct ice_adapter),
5311                                              ice_dev_init);
5312 }
5313
5314 static int
5315 ice_pci_remove(struct rte_pci_device *pci_dev)
5316 {
5317         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5318 }
5319
5320 static struct rte_pci_driver rte_ice_pmd = {
5321         .id_table = pci_id_ice_map,
5322         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5323         .probe = ice_pci_probe,
5324         .remove = ice_pci_remove,
5325 };
5326
5327 /**
5328  * Driver initialization routine.
5329  * Invoked once at EAL init time.
5330  * Register itself as the [Poll Mode] Driver of PCI devices.
5331  */
5332 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5333 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5334 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5335 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5336                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5337                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5338                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5339
5340 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5341 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5342 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5343 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5344 #endif
5345 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5346 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5347 #endif
5348 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5349 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5350 #endif