drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "ice_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "ice_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  72
  73 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  74 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  75 #define ICE_MAX_RES_DESC_NUM        1024
  76
  77 static int ice_dev_configure(struct rte_eth_dev *dev);
  78 static int ice_dev_start(struct rte_eth_dev *dev);
  79 static void ice_dev_stop(struct rte_eth_dev *dev);
  80 static int ice_dev_close(struct rte_eth_dev *dev);
  81 static int ice_dev_reset(struct rte_eth_dev *dev);
  82 static int ice_dev_info_get(struct rte_eth_dev *dev,
  83                             struct rte_eth_dev_info *dev_info);
  84 static int ice_link_update(struct rte_eth_dev *dev,
  85                            int wait_to_complete);
  86 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  87 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  88
  89 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  90 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  92                                struct rte_eth_rss_reta_entry64 *reta_conf,
  93                                uint16_t reta_size);
  94 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  95                               struct rte_eth_rss_reta_entry64 *reta_conf,
  96                               uint16_t reta_size);
  97 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  98                                struct rte_eth_rss_conf *rss_conf);
  99 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 100                                  struct rte_eth_rss_conf *rss_conf);
 101 static int ice_promisc_enable(struct rte_eth_dev *dev);
 102 static int ice_promisc_disable(struct rte_eth_dev *dev);
 103 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 104 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 105 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 106                                uint16_t vlan_id,
 107                                int on);
 108 static int ice_macaddr_set(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr);
 110 static int ice_macaddr_add(struct rte_eth_dev *dev,
 111                            struct rte_ether_addr *mac_addr,
 112                            __rte_unused uint32_t index,
 113                            uint32_t pool);
 114 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 115 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 116                                     uint16_t queue_id);
 117 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 118                                      uint16_t queue_id);
 119 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 120                               size_t fw_size);
 121 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 122                              uint16_t pvid, int on);
 123 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 124 static int ice_get_eeprom(struct rte_eth_dev *dev,
 125                           struct rte_dev_eeprom_info *eeprom);
 126 static int ice_stats_get(struct rte_eth_dev *dev,
 127                          struct rte_eth_stats *stats);
 128 static int ice_stats_reset(struct rte_eth_dev *dev);
 129 static int ice_xstats_get(struct rte_eth_dev *dev,
 130                           struct rte_eth_xstat *xstats, unsigned int n);
 131 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 132                                 struct rte_eth_xstat_name *xstats_names,
 133                                 unsigned int limit);
 134 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 135                         enum rte_filter_type filter_type,
 136                         enum rte_filter_op filter_op,
 137                         void *arg);
 138 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 139                         struct rte_eth_udp_tunnel *udp_tunnel);
 140 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142
 143 static const struct rte_pci_id pci_id_ice_map[] = {
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 164         { .vendor_id = 0, /* sentinel */ },
 165 };
 166
 167 static const struct eth_dev_ops ice_eth_dev_ops = {
 168         .dev_configure                = ice_dev_configure,
 169         .dev_start                    = ice_dev_start,
 170         .dev_stop                     = ice_dev_stop,
 171         .dev_close                    = ice_dev_close,
 172         .dev_reset                    = ice_dev_reset,
 173         .dev_set_link_up              = ice_dev_set_link_up,
 174         .dev_set_link_down            = ice_dev_set_link_down,
 175         .rx_queue_start               = ice_rx_queue_start,
 176         .rx_queue_stop                = ice_rx_queue_stop,
 177         .tx_queue_start               = ice_tx_queue_start,
 178         .tx_queue_stop                = ice_tx_queue_stop,
 179         .rx_queue_setup               = ice_rx_queue_setup,
 180         .rx_queue_release             = ice_rx_queue_release,
 181         .tx_queue_setup               = ice_tx_queue_setup,
 182         .tx_queue_release             = ice_tx_queue_release,
 183         .dev_infos_get                = ice_dev_info_get,
 184         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 185         .link_update                  = ice_link_update,
 186         .mtu_set                      = ice_mtu_set,
 187         .mac_addr_set                 = ice_macaddr_set,
 188         .mac_addr_add                 = ice_macaddr_add,
 189         .mac_addr_remove              = ice_macaddr_remove,
 190         .vlan_filter_set              = ice_vlan_filter_set,
 191         .vlan_offload_set             = ice_vlan_offload_set,
 192         .reta_update                  = ice_rss_reta_update,
 193         .reta_query                   = ice_rss_reta_query,
 194         .rss_hash_update              = ice_rss_hash_update,
 195         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 196         .promiscuous_enable           = ice_promisc_enable,
 197         .promiscuous_disable          = ice_promisc_disable,
 198         .allmulticast_enable          = ice_allmulti_enable,
 199         .allmulticast_disable         = ice_allmulti_disable,
 200         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 201         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 202         .fw_version_get               = ice_fw_version_get,
 203         .vlan_pvid_set                = ice_vlan_pvid_set,
 204         .rxq_info_get                 = ice_rxq_info_get,
 205         .txq_info_get                 = ice_txq_info_get,
 206         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 207         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 208         .get_eeprom_length            = ice_get_eeprom_length,
 209         .get_eeprom                   = ice_get_eeprom,
 210         .stats_get                    = ice_stats_get,
 211         .stats_reset                  = ice_stats_reset,
 212         .xstats_get                   = ice_xstats_get,
 213         .xstats_get_names             = ice_xstats_get_names,
 214         .xstats_reset                 = ice_stats_reset,
 215         .filter_ctrl                  = ice_dev_filter_ctrl,
 216         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 217         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 218         .tx_done_cleanup              = ice_tx_done_cleanup,
 219 };
 220
 221 /* store statistics names and its offset in stats structure */
 222 struct ice_xstats_name_off {
 223         char name[RTE_ETH_XSTATS_NAME_SIZE];
 224         unsigned int offset;
 225 };
 226
 227 static const struct ice_xstats_name_off ice_stats_strings[] = {
 228         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 229         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 230         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 231         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 232         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 233                 rx_unknown_protocol)},
 234         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 235         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 236         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 237         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 238 };
 239
 240 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 241                 sizeof(ice_stats_strings[0]))
 242
 243 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 244         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 245                 tx_dropped_link_down)},
 246         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 247         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 248                 illegal_bytes)},
 249         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 250         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 251                 mac_local_faults)},
 252         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 253                 mac_remote_faults)},
 254         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 255                 rx_len_errors)},
 256         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 257         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 258         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 259         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 260         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 261         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 262                 rx_size_127)},
 263         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 264                 rx_size_255)},
 265         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_511)},
 267         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_1023)},
 269         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_1522)},
 271         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_big)},
 273         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 274                 rx_undersize)},
 275         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 276                 rx_oversize)},
 277         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 278                 mac_short_pkt_dropped)},
 279         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_fragments)},
 281         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 282         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 283         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 284                 tx_size_127)},
 285         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 286                 tx_size_255)},
 287         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_511)},
 289         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_1023)},
 291         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_1522)},
 293         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_big)},
 295 };
 296
 297 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 298                 sizeof(ice_hw_port_strings[0]))
 299
 300 static void
 301 ice_init_controlq_parameter(struct ice_hw *hw)
 302 {
 303         /* fields for adminq */
 304         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 305         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 306         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 307         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 308
 309         /* fields for mailboxq, DPDK used as PF host */
 310         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 311         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 312         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 313         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 314 }
 315
 316 static int
 317 lookup_proto_xtr_type(const char *xtr_name)
 318 {
 319         static struct {
 320                 const char *name;
 321                 enum proto_xtr_type type;
 322         } xtr_type_map[] = {
 323                 { "vlan",      PROTO_XTR_VLAN      },
 324                 { "ipv4",      PROTO_XTR_IPV4      },
 325                 { "ipv6",      PROTO_XTR_IPV6      },
 326                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 327                 { "tcp",       PROTO_XTR_TCP       },
 328                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 329         };
 330         uint32_t i;
 331
 332         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 333                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 334                         return xtr_type_map[i].type;
 335         }
 336
 337         return -1;
 338 }
 339
 340 /*
 341  * Parse elem, the elem could be single number/range or '(' ')' group
 342  * 1) A single number elem, it's just a simple digit. e.g. 9
 343  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 344  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 345  *    Within group elem, '-' used for a range separator;
 346  *                       ',' used for a single number.
 347  */
 348 static int
 349 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 350 {
 351         const char *str = input;
 352         char *end = NULL;
 353         uint32_t min, max;
 354         uint32_t idx;
 355
 356         while (isblank(*str))
 357                 str++;
 358
 359         if (!isdigit(*str) && *str != '(')
 360                 return -1;
 361
 362         /* process single number or single range of number */
 363         if (*str != '(') {
 364                 errno = 0;
 365                 idx = strtoul(str, &end, 10);
 366                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 367                         return -1;
 368
 369                 while (isblank(*end))
 370                         end++;
 371
 372                 min = idx;
 373                 max = idx;
 374
 375                 /* process single <number>-<number> */
 376                 if (*end == '-') {
 377                         end++;
 378                         while (isblank(*end))
 379                                 end++;
 380                         if (!isdigit(*end))
 381                                 return -1;
 382
 383                         errno = 0;
 384                         idx = strtoul(end, &end, 10);
 385                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 386                                 return -1;
 387
 388                         max = idx;
 389                         while (isblank(*end))
 390                                 end++;
 391                 }
 392
 393                 if (*end != ':')
 394                         return -1;
 395
 396                 for (idx = RTE_MIN(min, max);
 397                      idx <= RTE_MAX(min, max); idx++)
 398                         devargs->proto_xtr[idx] = xtr_type;
 399
 400                 return 0;
 401         }
 402
 403         /* process set within bracket */
 404         str++;
 405         while (isblank(*str))
 406                 str++;
 407         if (*str == '\0')
 408                 return -1;
 409
 410         min = ICE_MAX_QUEUE_NUM;
 411         do {
 412                 /* go ahead to the first digit */
 413                 while (isblank(*str))
 414                         str++;
 415                 if (!isdigit(*str))
 416                         return -1;
 417
 418                 /* get the digit value */
 419                 errno = 0;
 420                 idx = strtoul(str, &end, 10);
 421                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 422                         return -1;
 423
 424                 /* go ahead to separator '-',',' and ')' */
 425                 while (isblank(*end))
 426                         end++;
 427                 if (*end == '-') {
 428                         if (min == ICE_MAX_QUEUE_NUM)
 429                                 min = idx;
 430                         else /* avoid continuous '-' */
 431                                 return -1;
 432                 } else if (*end == ',' || *end == ')') {
 433                         max = idx;
 434                         if (min == ICE_MAX_QUEUE_NUM)
 435                                 min = idx;
 436
 437                         for (idx = RTE_MIN(min, max);
 438                              idx <= RTE_MAX(min, max); idx++)
 439                                 devargs->proto_xtr[idx] = xtr_type;
 440
 441                         min = ICE_MAX_QUEUE_NUM;
 442                 } else {
 443                         return -1;
 444                 }
 445
 446                 str = end + 1;
 447         } while (*end != ')' && *end != '\0');
 448
 449         return 0;
 450 }
 451
 452 static int
 453 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 454 {
 455         const char *queue_start;
 456         uint32_t idx;
 457         int xtr_type;
 458         char xtr_name[32];
 459
 460         while (isblank(*queues))
 461                 queues++;
 462
 463         if (*queues != '[') {
 464                 xtr_type = lookup_proto_xtr_type(queues);
 465                 if (xtr_type < 0)
 466                         return -1;
 467
 468                 devargs->proto_xtr_dflt = xtr_type;
 469
 470                 return 0;
 471         }
 472
 473         queues++;
 474         do {
 475                 while (isblank(*queues))
 476                         queues++;
 477                 if (*queues == '\0')
 478                         return -1;
 479
 480                 queue_start = queues;
 481
 482                 /* go across a complete bracket */
 483                 if (*queue_start == '(') {
 484                         queues += strcspn(queues, ")");
 485                         if (*queues != ')')
 486                                 return -1;
 487                 }
 488
 489                 /* scan the separator ':' */
 490                 queues += strcspn(queues, ":");
 491                 if (*queues++ != ':')
 492                         return -1;
 493                 while (isblank(*queues))
 494                         queues++;
 495
 496                 for (idx = 0; ; idx++) {
 497                         if (isblank(queues[idx]) ||
 498                             queues[idx] == ',' ||
 499                             queues[idx] == ']' ||
 500                             queues[idx] == '\0')
 501                                 break;
 502
 503                         if (idx > sizeof(xtr_name) - 2)
 504                                 return -1;
 505
 506                         xtr_name[idx] = queues[idx];
 507                 }
 508                 xtr_name[idx] = '\0';
 509                 xtr_type = lookup_proto_xtr_type(xtr_name);
 510                 if (xtr_type < 0)
 511                         return -1;
 512
 513                 queues += idx;
 514
 515                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 516                         queues++;
 517
 518                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 519                         return -1;
 520         } while (*queues != '\0');
 521
 522         return 0;
 523 }
 524
 525 static int
 526 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 527                      void *extra_args)
 528 {
 529         struct ice_devargs *devargs = extra_args;
 530
 531         if (value == NULL || extra_args == NULL)
 532                 return -EINVAL;
 533
 534         if (parse_queue_proto_xtr(value, devargs) < 0) {
 535                 PMD_DRV_LOG(ERR,
 536                             "The protocol extraction parameter is wrong : '%s'",
 537                             value);
 538                 return -1;
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 ice_check_proto_xtr_support(struct ice_hw *hw)
 546 {
 547 #define FLX_REG(val, fld, idx) \
 548         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 549          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 550         static struct {
 551                 uint32_t rxdid;
 552                 uint8_t opcode;
 553                 uint8_t protid_0;
 554                 uint8_t protid_1;
 555         } xtr_sets[] = {
 556                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 557                                      ICE_RX_OPC_EXTRACT,
 558                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 559                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 560                                      ICE_RX_OPC_EXTRACT,
 561                                      ICE_PROT_IPV4_OF_OR_S,
 562                                      ICE_PROT_IPV4_OF_OR_S },
 563                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 564                                      ICE_RX_OPC_EXTRACT,
 565                                      ICE_PROT_IPV6_OF_OR_S,
 566                                      ICE_PROT_IPV6_OF_OR_S },
 567                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 568                                           ICE_RX_OPC_EXTRACT,
 569                                           ICE_PROT_IPV6_OF_OR_S,
 570                                           ICE_PROT_IPV6_OF_OR_S },
 571                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 572                                     ICE_RX_OPC_EXTRACT,
 573                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 574                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 575                                           ICE_RX_OPC_PROTID,
 576                                           ICE_PROT_IPV4_OF_OR_S,
 577                                           ICE_PROT_IPV6_OF_OR_S },
 578         };
 579         uint32_t i;
 580
 581         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 582                 uint32_t rxdid = xtr_sets[i].rxdid;
 583                 uint32_t v;
 584
 585                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 586                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 587
 588                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 589                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 590                                 ice_proto_xtr_hw_support[i] = true;
 591                 }
 592
 593                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 594                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 595
 596                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 597                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 598                                 ice_proto_xtr_hw_support[i] = true;
 599                 }
 600         }
 601 }
 602
 603 static int
 604 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 605                   uint32_t num)
 606 {
 607         struct pool_entry *entry;
 608
 609         if (!pool || !num)
 610                 return -EINVAL;
 611
 612         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 613         if (!entry) {
 614                 PMD_INIT_LOG(ERR,
 615                              "Failed to allocate memory for resource pool");
 616                 return -ENOMEM;
 617         }
 618
 619         /* queue heap initialize */
 620         pool->num_free = num;
 621         pool->num_alloc = 0;
 622         pool->base = base;
 623         LIST_INIT(&pool->alloc_list);
 624         LIST_INIT(&pool->free_list);
 625
 626         /* Initialize element  */
 627         entry->base = 0;
 628         entry->len = num;
 629
 630         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 631         return 0;
 632 }
 633
 634 static int
 635 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 636                    uint16_t num)
 637 {
 638         struct pool_entry *entry, *valid_entry;
 639
 640         if (!pool || !num) {
 641                 PMD_INIT_LOG(ERR, "Invalid parameter");
 642                 return -EINVAL;
 643         }
 644
 645         if (pool->num_free < num) {
 646                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 647                              num, pool->num_free);
 648                 return -ENOMEM;
 649         }
 650
 651         valid_entry = NULL;
 652         /* Lookup  in free list and find most fit one */
 653         LIST_FOREACH(entry, &pool->free_list, next) {
 654                 if (entry->len >= num) {
 655                         /* Find best one */
 656                         if (entry->len == num) {
 657                                 valid_entry = entry;
 658                                 break;
 659                         }
 660                         if (!valid_entry ||
 661                             valid_entry->len > entry->len)
 662                                 valid_entry = entry;
 663                 }
 664         }
 665
 666         /* Not find one to satisfy the request, return */
 667         if (!valid_entry) {
 668                 PMD_INIT_LOG(ERR, "No valid entry found");
 669                 return -ENOMEM;
 670         }
 671         /**
 672          * The entry have equal queue number as requested,
 673          * remove it from alloc_list.
 674          */
 675         if (valid_entry->len == num) {
 676                 LIST_REMOVE(valid_entry, next);
 677         } else {
 678                 /**
 679                  * The entry have more numbers than requested,
 680                  * create a new entry for alloc_list and minus its
 681                  * queue base and number in free_list.
 682                  */
 683                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 684                 if (!entry) {
 685                         PMD_INIT_LOG(ERR,
 686                                      "Failed to allocate memory for "
 687                                      "resource pool");
 688                         return -ENOMEM;
 689                 }
 690                 entry->base = valid_entry->base;
 691                 entry->len = num;
 692                 valid_entry->base += num;
 693                 valid_entry->len -= num;
 694                 valid_entry = entry;
 695         }
 696
 697         /* Insert it into alloc list, not sorted */
 698         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 699
 700         pool->num_free -= valid_entry->len;
 701         pool->num_alloc += valid_entry->len;
 702
 703         return valid_entry->base + pool->base;
 704 }
 705
 706 static void
 707 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 708 {
 709         struct pool_entry *entry, *next_entry;
 710
 711         if (!pool)
 712                 return;
 713
 714         for (entry = LIST_FIRST(&pool->alloc_list);
 715              entry && (next_entry = LIST_NEXT(entry, next), 1);
 716              entry = next_entry) {
 717                 LIST_REMOVE(entry, next);
 718                 rte_free(entry);
 719         }
 720
 721         for (entry = LIST_FIRST(&pool->free_list);
 722              entry && (next_entry = LIST_NEXT(entry, next), 1);
 723              entry = next_entry) {
 724                 LIST_REMOVE(entry, next);
 725                 rte_free(entry);
 726         }
 727
 728         pool->num_free = 0;
 729         pool->num_alloc = 0;
 730         pool->base = 0;
 731         LIST_INIT(&pool->alloc_list);
 732         LIST_INIT(&pool->free_list);
 733 }
 734
 735 static void
 736 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 737 {
 738         /* Set VSI LUT selection */
 739         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 740                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 741         /* Set Hash scheme */
 742         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 743                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 744         /* enable TC */
 745         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 746 }
 747
 748 static enum ice_status
 749 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 750                                 struct ice_aqc_vsi_props *info,
 751                                 uint8_t enabled_tcmap)
 752 {
 753         uint16_t bsf, qp_idx;
 754
 755         /* default tc 0 now. Multi-TC supporting need to be done later.
 756          * Configure TC and queue mapping parameters, for enabled TC,
 757          * allocate qpnum_per_tc queues to this traffic.
 758          */
 759         if (enabled_tcmap != 0x01) {
 760                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 761                 return -ENOTSUP;
 762         }
 763
 764         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 765         bsf = rte_bsf32(vsi->nb_qps);
 766         /* Adjust the queue number to actual queues that can be applied */
 767         vsi->nb_qps = 0x1 << bsf;
 768
 769         qp_idx = 0;
 770         /* Set tc and queue mapping with VSI */
 771         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 772                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 773                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 774
 775         /* Associate queue number with VSI */
 776         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 777         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 778         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 779         info->valid_sections |=
 780                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 781         /* Set the info.ingress_table and info.egress_table
 782          * for UP translate table. Now just set it to 1:1 map by default
 783          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 784          */
 785 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 786         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 787         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 788         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 789         return 0;
 790 }
 791
 792 static int
 793 ice_init_mac_address(struct rte_eth_dev *dev)
 794 {
 795         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 796
 797         if (!rte_is_unicast_ether_addr
 798                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 799                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 800                 return -EINVAL;
 801         }
 802
 803         rte_ether_addr_copy(
 804                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 805                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 806
 807         dev->data->mac_addrs =
 808                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 809         if (!dev->data->mac_addrs) {
 810                 PMD_INIT_LOG(ERR,
 811                              "Failed to allocate memory to store mac address");
 812                 return -ENOMEM;
 813         }
 814         /* store it to dev data */
 815         rte_ether_addr_copy(
 816                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 817                 &dev->data->mac_addrs[0]);
 818         return 0;
 819 }
 820
 821 /* Find out specific MAC filter */
 822 static struct ice_mac_filter *
 823 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 824 {
 825         struct ice_mac_filter *f;
 826
 827         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 828                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 829                         return f;
 830         }
 831
 832         return NULL;
 833 }
 834
 835 static int
 836 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 837 {
 838         struct ice_fltr_list_entry *m_list_itr = NULL;
 839         struct ice_mac_filter *f;
 840         struct LIST_HEAD_TYPE list_head;
 841         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 842         int ret = 0;
 843
 844         /* If it's added and configured, return */
 845         f = ice_find_mac_filter(vsi, mac_addr);
 846         if (f) {
 847                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 848                 return 0;
 849         }
 850
 851         INIT_LIST_HEAD(&list_head);
 852
 853         m_list_itr = (struct ice_fltr_list_entry *)
 854                 ice_malloc(hw, sizeof(*m_list_itr));
 855         if (!m_list_itr) {
 856                 ret = -ENOMEM;
 857                 goto DONE;
 858         }
 859         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 860                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 861         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 862         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 863         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 864         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 865         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 866
 867         LIST_ADD(&m_list_itr->list_entry, &list_head);
 868
 869         /* Add the mac */
 870         ret = ice_add_mac(hw, &list_head);
 871         if (ret != ICE_SUCCESS) {
 872                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 873                 ret = -EINVAL;
 874                 goto DONE;
 875         }
 876         /* Add the mac addr into mac list */
 877         f = rte_zmalloc(NULL, sizeof(*f), 0);
 878         if (!f) {
 879                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 880                 ret = -ENOMEM;
 881                 goto DONE;
 882         }
 883         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 884         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 885         vsi->mac_num++;
 886
 887         ret = 0;
 888
 889 DONE:
 890         rte_free(m_list_itr);
 891         return ret;
 892 }
 893
 894 static int
 895 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 896 {
 897         struct ice_fltr_list_entry *m_list_itr = NULL;
 898         struct ice_mac_filter *f;
 899         struct LIST_HEAD_TYPE list_head;
 900         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 901         int ret = 0;
 902
 903         /* Can't find it, return an error */
 904         f = ice_find_mac_filter(vsi, mac_addr);
 905         if (!f)
 906                 return -EINVAL;
 907
 908         INIT_LIST_HEAD(&list_head);
 909
 910         m_list_itr = (struct ice_fltr_list_entry *)
 911                 ice_malloc(hw, sizeof(*m_list_itr));
 912         if (!m_list_itr) {
 913                 ret = -ENOMEM;
 914                 goto DONE;
 915         }
 916         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 917                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 918         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 919         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 920         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 921         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 922         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 923
 924         LIST_ADD(&m_list_itr->list_entry, &list_head);
 925
 926         /* remove the mac filter */
 927         ret = ice_remove_mac(hw, &list_head);
 928         if (ret != ICE_SUCCESS) {
 929                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 930                 ret = -EINVAL;
 931                 goto DONE;
 932         }
 933
 934         /* Remove the mac addr from mac list */
 935         TAILQ_REMOVE(&vsi->mac_list, f, next);
 936         rte_free(f);
 937         vsi->mac_num--;
 938
 939         ret = 0;
 940 DONE:
 941         rte_free(m_list_itr);
 942         return ret;
 943 }
 944
 945 /* Find out specific VLAN filter */
 946 static struct ice_vlan_filter *
 947 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 948 {
 949         struct ice_vlan_filter *f;
 950
 951         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 952                 if (vlan_id == f->vlan_info.vlan_id)
 953                         return f;
 954         }
 955
 956         return NULL;
 957 }
 958
 959 static int
 960 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 961 {
 962         struct ice_fltr_list_entry *v_list_itr = NULL;
 963         struct ice_vlan_filter *f;
 964         struct LIST_HEAD_TYPE list_head;
 965         struct ice_hw *hw;
 966         int ret = 0;
 967
 968         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 969                 return -EINVAL;
 970
 971         hw = ICE_VSI_TO_HW(vsi);
 972
 973         /* If it's added and configured, return. */
 974         f = ice_find_vlan_filter(vsi, vlan_id);
 975         if (f) {
 976                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 977                 return 0;
 978         }
 979
 980         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 981                 return 0;
 982
 983         INIT_LIST_HEAD(&list_head);
 984
 985         v_list_itr = (struct ice_fltr_list_entry *)
 986                       ice_malloc(hw, sizeof(*v_list_itr));
 987         if (!v_list_itr) {
 988                 ret = -ENOMEM;
 989                 goto DONE;
 990         }
 991         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 992         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 993         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 994         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 995         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 996         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 997
 998         LIST_ADD(&v_list_itr->list_entry, &list_head);
 999
1000         /* Add the vlan */
1001         ret = ice_add_vlan(hw, &list_head);
1002         if (ret != ICE_SUCCESS) {
1003                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1004                 ret = -EINVAL;
1005                 goto DONE;
1006         }
1007
1008         /* Add vlan into vlan list */
1009         f = rte_zmalloc(NULL, sizeof(*f), 0);
1010         if (!f) {
1011                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1012                 ret = -ENOMEM;
1013                 goto DONE;
1014         }
1015         f->vlan_info.vlan_id = vlan_id;
1016         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1017         vsi->vlan_num++;
1018
1019         ret = 0;
1020
1021 DONE:
1022         rte_free(v_list_itr);
1023         return ret;
1024 }
1025
1026 static int
1027 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1028 {
1029         struct ice_fltr_list_entry *v_list_itr = NULL;
1030         struct ice_vlan_filter *f;
1031         struct LIST_HEAD_TYPE list_head;
1032         struct ice_hw *hw;
1033         int ret = 0;
1034
1035         /**
1036          * Vlan 0 is the generic filter for untagged packets
1037          * and can't be removed.
1038          */
1039         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1040                 return -EINVAL;
1041
1042         hw = ICE_VSI_TO_HW(vsi);
1043
1044         /* Can't find it, return an error */
1045         f = ice_find_vlan_filter(vsi, vlan_id);
1046         if (!f)
1047                 return -EINVAL;
1048
1049         INIT_LIST_HEAD(&list_head);
1050
1051         v_list_itr = (struct ice_fltr_list_entry *)
1052                       ice_malloc(hw, sizeof(*v_list_itr));
1053         if (!v_list_itr) {
1054                 ret = -ENOMEM;
1055                 goto DONE;
1056         }
1057
1058         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1059         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1060         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1061         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1062         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1063         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1064
1065         LIST_ADD(&v_list_itr->list_entry, &list_head);
1066
1067         /* remove the vlan filter */
1068         ret = ice_remove_vlan(hw, &list_head);
1069         if (ret != ICE_SUCCESS) {
1070                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1071                 ret = -EINVAL;
1072                 goto DONE;
1073         }
1074
1075         /* Remove the vlan id from vlan list */
1076         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1077         rte_free(f);
1078         vsi->vlan_num--;
1079
1080         ret = 0;
1081 DONE:
1082         rte_free(v_list_itr);
1083         return ret;
1084 }
1085
1086 static int
1087 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1088 {
1089         struct ice_mac_filter *m_f;
1090         struct ice_vlan_filter *v_f;
1091         int ret = 0;
1092
1093         if (!vsi || !vsi->mac_num)
1094                 return -EINVAL;
1095
1096         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1097                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1098                 if (ret != ICE_SUCCESS) {
1099                         ret = -EINVAL;
1100                         goto DONE;
1101                 }
1102         }
1103
1104         if (vsi->vlan_num == 0)
1105                 return 0;
1106
1107         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1108                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1109                 if (ret != ICE_SUCCESS) {
1110                         ret = -EINVAL;
1111                         goto DONE;
1112                 }
1113         }
1114
1115 DONE:
1116         return ret;
1117 }
1118
1119 static int
1120 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1121 {
1122         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1123         struct ice_vsi_ctx ctxt;
1124         uint8_t qinq_flags;
1125         int ret = 0;
1126
1127         /* Check if it has been already on or off */
1128         if (vsi->info.valid_sections &
1129                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1130                 if (on) {
1131                         if ((vsi->info.outer_tag_flags &
1132                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1133                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1134                                 return 0; /* already on */
1135                 } else {
1136                         if (!(vsi->info.outer_tag_flags &
1137                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1138                                 return 0; /* already off */
1139                 }
1140         }
1141
1142         if (on)
1143                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1144         else
1145                 qinq_flags = 0;
1146         /* clear global insertion and use per packet insertion */
1147         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1148         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1149         vsi->info.outer_tag_flags |= qinq_flags;
1150         /* use default vlan type 0x8100 */
1151         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1152         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1153                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1154         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1155         ctxt.info.valid_sections =
1156                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1157         ctxt.vsi_num = vsi->vsi_id;
1158         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1159         if (ret) {
1160                 PMD_DRV_LOG(INFO,
1161                             "Update VSI failed to %s qinq stripping",
1162                             on ? "enable" : "disable");
1163                 return -EINVAL;
1164         }
1165
1166         vsi->info.valid_sections |=
1167                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1168
1169         return ret;
1170 }
1171
1172 static int
1173 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1174 {
1175         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1176         struct ice_vsi_ctx ctxt;
1177         uint8_t qinq_flags;
1178         int ret = 0;
1179
1180         /* Check if it has been already on or off */
1181         if (vsi->info.valid_sections &
1182                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1183                 if (on) {
1184                         if ((vsi->info.outer_tag_flags &
1185                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1186                             ICE_AQ_VSI_OUTER_TAG_COPY)
1187                                 return 0; /* already on */
1188                 } else {
1189                         if ((vsi->info.outer_tag_flags &
1190                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1191                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
1192                                 return 0; /* already off */
1193                 }
1194         }
1195
1196         if (on)
1197                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1198         else
1199                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1200         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1201         vsi->info.outer_tag_flags |= qinq_flags;
1202         /* use default vlan type 0x8100 */
1203         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1204         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1205                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1206         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1207         ctxt.info.valid_sections =
1208                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1209         ctxt.vsi_num = vsi->vsi_id;
1210         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1211         if (ret) {
1212                 PMD_DRV_LOG(INFO,
1213                             "Update VSI failed to %s qinq stripping",
1214                             on ? "enable" : "disable");
1215                 return -EINVAL;
1216         }
1217
1218         vsi->info.valid_sections |=
1219                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1220
1221         return ret;
1222 }
1223
1224 static int
1225 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1226 {
1227         int ret;
1228
1229         ret = ice_vsi_config_qinq_stripping(vsi, on);
1230         if (ret)
1231                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1232
1233         ret = ice_vsi_config_qinq_insertion(vsi, on);
1234         if (ret)
1235                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1236
1237         return ret;
1238 }
1239
1240 /* Enable IRQ0 */
1241 static void
1242 ice_pf_enable_irq0(struct ice_hw *hw)
1243 {
1244         /* reset the registers */
1245         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1246         ICE_READ_REG(hw, PFINT_OICR);
1247
1248 #ifdef ICE_LSE_SPT
1249         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1250                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1251                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1252
1253         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1254                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1255                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1256                        PFINT_OICR_CTL_ITR_INDX_M) |
1257                       PFINT_OICR_CTL_CAUSE_ENA_M);
1258
1259         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1260                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1261                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1262                        PFINT_FW_CTL_ITR_INDX_M) |
1263                       PFINT_FW_CTL_CAUSE_ENA_M);
1264 #else
1265         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1266 #endif
1267
1268         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1269                       GLINT_DYN_CTL_INTENA_M |
1270                       GLINT_DYN_CTL_CLEARPBA_M |
1271                       GLINT_DYN_CTL_ITR_INDX_M);
1272
1273         ice_flush(hw);
1274 }
1275
1276 /* Disable IRQ0 */
1277 static void
1278 ice_pf_disable_irq0(struct ice_hw *hw)
1279 {
1280         /* Disable all interrupt types */
1281         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1282         ice_flush(hw);
1283 }
1284
1285 #ifdef ICE_LSE_SPT
1286 static void
1287 ice_handle_aq_msg(struct rte_eth_dev *dev)
1288 {
1289         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         struct ice_ctl_q_info *cq = &hw->adminq;
1291         struct ice_rq_event_info event;
1292         uint16_t pending, opcode;
1293         int ret;
1294
1295         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1296         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1297         if (!event.msg_buf) {
1298                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1299                 return;
1300         }
1301
1302         pending = 1;
1303         while (pending) {
1304                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1305
1306                 if (ret != ICE_SUCCESS) {
1307                         PMD_DRV_LOG(INFO,
1308                                     "Failed to read msg from AdminQ, "
1309                                     "adminq_err: %u",
1310                                     hw->adminq.sq_last_status);
1311                         break;
1312                 }
1313                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1314
1315                 switch (opcode) {
1316                 case ice_aqc_opc_get_link_status:
1317                         ret = ice_link_update(dev, 0);
1318                         if (!ret)
1319                                 rte_eth_dev_callback_process
1320                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1321                         break;
1322                 default:
1323                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1324                                     opcode);
1325                         break;
1326                 }
1327         }
1328         rte_free(event.msg_buf);
1329 }
1330 #endif
1331
1332 /**
1333  * Interrupt handler triggered by NIC for handling
1334  * specific interrupt.
1335  *
1336  * @param handle
1337  *  Pointer to interrupt handle.
1338  * @param param
1339  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1340  *
1341  * @return
1342  *  void
1343  */
1344 static void
1345 ice_interrupt_handler(void *param)
1346 {
1347         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1348         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         uint32_t oicr;
1350         uint32_t reg;
1351         uint8_t pf_num;
1352         uint8_t event;
1353         uint16_t queue;
1354         int ret;
1355 #ifdef ICE_LSE_SPT
1356         uint32_t int_fw_ctl;
1357 #endif
1358
1359         /* Disable interrupt */
1360         ice_pf_disable_irq0(hw);
1361
1362         /* read out interrupt causes */
1363         oicr = ICE_READ_REG(hw, PFINT_OICR);
1364 #ifdef ICE_LSE_SPT
1365         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1366 #endif
1367
1368         /* No interrupt event indicated */
1369         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1370                 PMD_DRV_LOG(INFO, "No interrupt event");
1371                 goto done;
1372         }
1373
1374 #ifdef ICE_LSE_SPT
1375         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1376                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1377                 ice_handle_aq_msg(dev);
1378         }
1379 #else
1380         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1381                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1382                 ret = ice_link_update(dev, 0);
1383                 if (!ret)
1384                         rte_eth_dev_callback_process
1385                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1386         }
1387 #endif
1388
1389         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1390                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1391                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1392                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1393                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1394                                  GL_MDET_TX_PQM_PF_NUM_S;
1395                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1396                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1397                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1398                                 GL_MDET_TX_PQM_QNUM_S;
1399
1400                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1401                                     "%d by PQM on TX queue %d PF# %d",
1402                                     event, queue, pf_num);
1403                 }
1404
1405                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1406                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1407                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1408                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1409                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1410                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1411                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1412                                 GL_MDET_TX_TCLAN_QNUM_S;
1413
1414                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1415                                     "%d by TCLAN on TX queue %d PF# %d",
1416                                     event, queue, pf_num);
1417                 }
1418         }
1419 done:
1420         /* Enable interrupt */
1421         ice_pf_enable_irq0(hw);
1422         rte_intr_ack(dev->intr_handle);
1423 }
1424
1425 static void
1426 ice_init_proto_xtr(struct rte_eth_dev *dev)
1427 {
1428         struct ice_adapter *ad =
1429                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1430         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1432         const struct proto_xtr_ol_flag *ol_flag;
1433         bool proto_xtr_enable = false;
1434         int offset;
1435         uint16_t i;
1436
1437         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1438         if (unlikely(pf->proto_xtr == NULL)) {
1439                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1440                 return;
1441         }
1442
1443         for (i = 0; i < pf->lan_nb_qps; i++) {
1444                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1445                                    ad->devargs.proto_xtr[i] :
1446                                    ad->devargs.proto_xtr_dflt;
1447
1448                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1449                         uint8_t type = pf->proto_xtr[i];
1450
1451                         ice_proto_xtr_ol_flag_params[type].required = true;
1452                         proto_xtr_enable = true;
1453                 }
1454         }
1455
1456         if (likely(!proto_xtr_enable))
1457                 return;
1458
1459         ice_check_proto_xtr_support(hw);
1460
1461         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1462         if (unlikely(offset == -1)) {
1463                 PMD_DRV_LOG(ERR,
1464                             "Protocol extraction metadata is disabled in mbuf with error %d",
1465                             -rte_errno);
1466                 return;
1467         }
1468
1469         PMD_DRV_LOG(DEBUG,
1470                     "Protocol extraction metadata offset in mbuf is : %d",
1471                     offset);
1472         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1473
1474         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1475                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1476
1477                 if (!ol_flag->required)
1478                         continue;
1479
1480                 if (!ice_proto_xtr_hw_support[i]) {
1481                         PMD_DRV_LOG(ERR,
1482                                     "Protocol extraction type %u is not supported in hardware",
1483                                     i);
1484                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1485                         break;
1486                 }
1487
1488                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1489                 if (unlikely(offset == -1)) {
1490                         PMD_DRV_LOG(ERR,
1491                                     "Protocol extraction offload '%s' failed to register with error %d",
1492                                     ol_flag->param.name, -rte_errno);
1493
1494                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1495                         break;
1496                 }
1497
1498                 PMD_DRV_LOG(DEBUG,
1499                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1500                             ol_flag->param.name, offset);
1501                 *ol_flag->ol_flag = 1ULL << offset;
1502         }
1503 }
1504
1505 /*  Initialize SW parameters of PF */
1506 static int
1507 ice_pf_sw_init(struct rte_eth_dev *dev)
1508 {
1509         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1510         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1511
1512         pf->lan_nb_qp_max =
1513                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1514                                   hw->func_caps.common_cap.num_rxq);
1515
1516         pf->lan_nb_qps = pf->lan_nb_qp_max;
1517
1518         ice_init_proto_xtr(dev);
1519
1520         if (hw->func_caps.fd_fltr_guar > 0 ||
1521             hw->func_caps.fd_fltr_best_effort > 0) {
1522                 pf->flags |= ICE_FLAG_FDIR;
1523                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1524                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1525         } else {
1526                 pf->fdir_nb_qps = 0;
1527         }
1528         pf->fdir_qp_offset = 0;
1529
1530         return 0;
1531 }
1532
1533 struct ice_vsi *
1534 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1535 {
1536         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1537         struct ice_vsi *vsi = NULL;
1538         struct ice_vsi_ctx vsi_ctx;
1539         int ret;
1540         struct rte_ether_addr broadcast = {
1541                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1542         struct rte_ether_addr mac_addr;
1543         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1544         uint8_t tc_bitmap = 0x1;
1545         uint16_t cfg;
1546
1547         /* hw->num_lports = 1 in NIC mode */
1548         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1549         if (!vsi)
1550                 return NULL;
1551
1552         vsi->idx = pf->next_vsi_idx;
1553         pf->next_vsi_idx++;
1554         vsi->type = type;
1555         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1556         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1557         vsi->vlan_anti_spoof_on = 0;
1558         vsi->vlan_filter_on = 1;
1559         TAILQ_INIT(&vsi->mac_list);
1560         TAILQ_INIT(&vsi->vlan_list);
1561
1562         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1563         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1564                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1565                         hw->func_caps.common_cap.rss_table_size;
1566         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1567
1568         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1569         switch (type) {
1570         case ICE_VSI_PF:
1571                 vsi->nb_qps = pf->lan_nb_qps;
1572                 vsi->base_queue = 1;
1573                 ice_vsi_config_default_rss(&vsi_ctx.info);
1574                 vsi_ctx.alloc_from_pool = true;
1575                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1576                 /* switch_id is queried by get_switch_config aq, which is done
1577                  * by ice_init_hw
1578                  */
1579                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1580                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1581                 /* Allow all untagged or tagged packets */
1582                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1583                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1584                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1585                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1586
1587                 /* FDIR */
1588                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1589                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1590                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1591                 cfg = ICE_AQ_VSI_FD_ENABLE;
1592                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1593                 vsi_ctx.info.max_fd_fltr_dedicated =
1594                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1595                 vsi_ctx.info.max_fd_fltr_shared =
1596                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1597
1598                 /* Enable VLAN/UP trip */
1599                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1600                                                       &vsi_ctx.info,
1601                                                       ICE_DEFAULT_TCMAP);
1602                 if (ret) {
1603                         PMD_INIT_LOG(ERR,
1604                                      "tc queue mapping with vsi failed, "
1605                                      "err = %d",
1606                                      ret);
1607                         goto fail_mem;
1608                 }
1609
1610                 break;
1611         case ICE_VSI_CTRL:
1612                 vsi->nb_qps = pf->fdir_nb_qps;
1613                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1614                 vsi_ctx.alloc_from_pool = true;
1615                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1616
1617                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1618                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1619                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1620                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1621                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1622                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1623                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1624                                                       &vsi_ctx.info,
1625                                                       ICE_DEFAULT_TCMAP);
1626                 if (ret) {
1627                         PMD_INIT_LOG(ERR,
1628                                      "tc queue mapping with vsi failed, "
1629                                      "err = %d",
1630                                      ret);
1631                         goto fail_mem;
1632                 }
1633                 break;
1634         default:
1635                 /* for other types of VSI */
1636                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1637                 goto fail_mem;
1638         }
1639
1640         /* VF has MSIX interrupt in VF range, don't allocate here */
1641         if (type == ICE_VSI_PF) {
1642                 ret = ice_res_pool_alloc(&pf->msix_pool,
1643                                          RTE_MIN(vsi->nb_qps,
1644                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1645                 if (ret < 0) {
1646                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1647                                      vsi->vsi_id, ret);
1648                 }
1649                 vsi->msix_intr = ret;
1650                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1651         } else if (type == ICE_VSI_CTRL) {
1652                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1653                 if (ret < 0) {
1654                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1655                                     vsi->vsi_id, ret);
1656                 }
1657                 vsi->msix_intr = ret;
1658                 vsi->nb_msix = 1;
1659         } else {
1660                 vsi->msix_intr = 0;
1661                 vsi->nb_msix = 0;
1662         }
1663         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1664         if (ret != ICE_SUCCESS) {
1665                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1666                 goto fail_mem;
1667         }
1668         /* store vsi information is SW structure */
1669         vsi->vsi_id = vsi_ctx.vsi_num;
1670         vsi->info = vsi_ctx.info;
1671         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1672         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1673
1674         if (type == ICE_VSI_PF) {
1675                 /* MAC configuration */
1676                 rte_ether_addr_copy((struct rte_ether_addr *)
1677                                         hw->port_info->mac.perm_addr,
1678                                     &pf->dev_addr);
1679
1680                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1681                 ret = ice_add_mac_filter(vsi, &mac_addr);
1682                 if (ret != ICE_SUCCESS)
1683                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1684
1685                 rte_ether_addr_copy(&broadcast, &mac_addr);
1686                 ret = ice_add_mac_filter(vsi, &mac_addr);
1687                 if (ret != ICE_SUCCESS)
1688                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1689         }
1690
1691         /* At the beginning, only TC0. */
1692         /* What we need here is the maximam number of the TX queues.
1693          * Currently vsi->nb_qps means it.
1694          * Correct it if any change.
1695          */
1696         max_txqs[0] = vsi->nb_qps;
1697         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1698                               tc_bitmap, max_txqs);
1699         if (ret != ICE_SUCCESS)
1700                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1701
1702         return vsi;
1703 fail_mem:
1704         rte_free(vsi);
1705         pf->next_vsi_idx--;
1706         return NULL;
1707 }
1708
1709 static int
1710 ice_send_driver_ver(struct ice_hw *hw)
1711 {
1712         struct ice_driver_ver dv;
1713
1714         /* we don't have driver version use 0 for dummy */
1715         dv.major_ver = 0;
1716         dv.minor_ver = 0;
1717         dv.build_ver = 0;
1718         dv.subbuild_ver = 0;
1719         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1720
1721         return ice_aq_send_driver_ver(hw, &dv, NULL);
1722 }
1723
1724 static int
1725 ice_pf_setup(struct ice_pf *pf)
1726 {
1727         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1728         struct ice_vsi *vsi;
1729         uint16_t unused;
1730
1731         /* Clear all stats counters */
1732         pf->offset_loaded = false;
1733         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1734         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1735         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1736         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1737
1738         /* force guaranteed filter pool for PF */
1739         ice_alloc_fd_guar_item(hw, &unused,
1740                                hw->func_caps.fd_fltr_guar);
1741         /* force shared filter pool for PF */
1742         ice_alloc_fd_shrd_item(hw, &unused,
1743                                hw->func_caps.fd_fltr_best_effort);
1744
1745         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1746         if (!vsi) {
1747                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1748                 return -EINVAL;
1749         }
1750
1751         pf->main_vsi = vsi;
1752
1753         return 0;
1754 }
1755
1756 /*
1757  * Extract device serial number from PCIe Configuration Space and
1758  * determine the pkg file path according to the DSN.
1759  */
1760 static int
1761 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1762 {
1763         off_t pos;
1764         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1765         uint32_t dsn_low, dsn_high;
1766         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1767
1768         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1769
1770         if (pos) {
1771                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1772                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1773                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1774                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1775         } else {
1776                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1777                 goto fail_dsn;
1778         }
1779
1780         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1781                 ICE_MAX_PKG_FILENAME_SIZE);
1782         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1783                 return 0;
1784
1785         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1786                 ICE_MAX_PKG_FILENAME_SIZE);
1787         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1788                 return 0;
1789
1790 fail_dsn:
1791         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1792         if (!access(pkg_file, 0))
1793                 return 0;
1794         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1795         return 0;
1796 }
1797
1798 enum ice_pkg_type
1799 ice_load_pkg_type(struct ice_hw *hw)
1800 {
1801         enum ice_pkg_type package_type;
1802
1803         /* store the activated package type (OS default or Comms) */
1804         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1805                 ICE_PKG_NAME_SIZE))
1806                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1807         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1808                 ICE_PKG_NAME_SIZE))
1809                 package_type = ICE_PKG_TYPE_COMMS;
1810         else
1811                 package_type = ICE_PKG_TYPE_UNKNOWN;
1812
1813         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1814                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1815                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1816                 hw->active_pkg_name);
1817
1818         return package_type;
1819 }
1820
1821 static int ice_load_pkg(struct rte_eth_dev *dev)
1822 {
1823         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1825         int err;
1826         uint8_t *buf;
1827         int buf_len;
1828         FILE *file;
1829         struct stat fstat;
1830         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1831         struct ice_adapter *ad =
1832                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1833
1834         ice_pkg_file_search_path(pci_dev, pkg_file);
1835
1836         file = fopen(pkg_file, "rb");
1837         if (!file)  {
1838                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1839                 return -1;
1840         }
1841
1842         err = stat(pkg_file, &fstat);
1843         if (err) {
1844                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1845                 fclose(file);
1846                 return err;
1847         }
1848
1849         buf_len = fstat.st_size;
1850         buf = rte_malloc(NULL, buf_len, 0);
1851
1852         if (!buf) {
1853                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1854                                 buf_len);
1855                 fclose(file);
1856                 return -1;
1857         }
1858
1859         err = fread(buf, buf_len, 1, file);
1860         if (err != 1) {
1861                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1862                 fclose(file);
1863                 err = -1;
1864                 goto fail_exit;
1865         }
1866
1867         fclose(file);
1868
1869         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1870         if (err) {
1871                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1872                 goto fail_exit;
1873         }
1874
1875         /* store the loaded pkg type info */
1876         ad->active_pkg_type = ice_load_pkg_type(hw);
1877
1878         err = ice_init_hw_tbls(hw);
1879         if (err) {
1880                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1881                 goto fail_init_tbls;
1882         }
1883
1884         return 0;
1885
1886 fail_init_tbls:
1887         rte_free(hw->pkg_copy);
1888 fail_exit:
1889         rte_free(buf);
1890         return err;
1891 }
1892
1893 static void
1894 ice_base_queue_get(struct ice_pf *pf)
1895 {
1896         uint32_t reg;
1897         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1898
1899         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1900         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1901                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1902         } else {
1903                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1904                                         " index");
1905         }
1906 }
1907
1908 static int
1909 parse_bool(const char *key, const char *value, void *args)
1910 {
1911         int *i = (int *)args;
1912         char *end;
1913         int num;
1914
1915         num = strtoul(value, &end, 10);
1916
1917         if (num != 0 && num != 1) {
1918                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1919                         "value must be 0 or 1",
1920                         value, key);
1921                 return -1;
1922         }
1923
1924         *i = num;
1925         return 0;
1926 }
1927
1928 static int ice_parse_devargs(struct rte_eth_dev *dev)
1929 {
1930         struct ice_adapter *ad =
1931                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1932         struct rte_devargs *devargs = dev->device->devargs;
1933         struct rte_kvargs *kvlist;
1934         int ret;
1935
1936         if (devargs == NULL)
1937                 return 0;
1938
1939         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1940         if (kvlist == NULL) {
1941                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1942                 return -EINVAL;
1943         }
1944
1945         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1946         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1947                sizeof(ad->devargs.proto_xtr));
1948
1949         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1950                                  &handle_proto_xtr_arg, &ad->devargs);
1951         if (ret)
1952                 goto bail;
1953
1954         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1955                                  &parse_bool, &ad->devargs.safe_mode_support);
1956         if (ret)
1957                 goto bail;
1958
1959         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1960                                  &parse_bool, &ad->devargs.pipe_mode_support);
1961         if (ret)
1962                 goto bail;
1963
1964 bail:
1965         rte_kvargs_free(kvlist);
1966         return ret;
1967 }
1968
1969 /* Forward LLDP packets to default VSI by set switch rules */
1970 static int
1971 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1972 {
1973         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1974         struct ice_fltr_list_entry *s_list_itr = NULL;
1975         struct LIST_HEAD_TYPE list_head;
1976         int ret = 0;
1977
1978         INIT_LIST_HEAD(&list_head);
1979
1980         s_list_itr = (struct ice_fltr_list_entry *)
1981                         ice_malloc(hw, sizeof(*s_list_itr));
1982         if (!s_list_itr)
1983                 return -ENOMEM;
1984         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1985         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1986         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1987                         RTE_ETHER_TYPE_LLDP;
1988         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1989         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1990         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1991         LIST_ADD(&s_list_itr->list_entry, &list_head);
1992         if (on)
1993                 ret = ice_add_eth_mac(hw, &list_head);
1994         else
1995                 ret = ice_remove_eth_mac(hw, &list_head);
1996
1997         rte_free(s_list_itr);
1998         return ret;
1999 }
2000
2001 static enum ice_status
2002 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2003                 uint16_t num, uint16_t desc_id,
2004                 uint16_t *prof_buf, uint16_t *num_prof)
2005 {
2006         struct ice_aqc_res_elem *resp_buf;
2007         int ret;
2008         uint16_t buf_len;
2009         bool res_shared = 1;
2010         struct ice_aq_desc aq_desc;
2011         struct ice_sq_cd *cd = NULL;
2012         struct ice_aqc_get_allocd_res_desc *cmd =
2013                         &aq_desc.params.get_res_desc;
2014
2015         buf_len = sizeof(*resp_buf) * num;
2016         resp_buf = ice_malloc(hw, buf_len);
2017         if (!resp_buf)
2018                 return -ENOMEM;
2019
2020         ice_fill_dflt_direct_cmd_desc(&aq_desc,
2021                         ice_aqc_opc_get_allocd_res_desc);
2022
2023         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2024                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
2025                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2026         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2027
2028         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2029         if (!ret)
2030                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2031         else
2032                 goto exit;
2033
2034         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2035                         (*num_prof), ICE_NONDMA_TO_NONDMA);
2036
2037 exit:
2038         rte_free(resp_buf);
2039         return ret;
2040 }
2041 static int
2042 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2043 {
2044         int ret;
2045         uint16_t prof_id;
2046         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2047         uint16_t first_desc = 1;
2048         uint16_t num_prof = 0;
2049
2050         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2051                         first_desc, prof_buf, &num_prof);
2052         if (ret) {
2053                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2054                 return ret;
2055         }
2056
2057         for (prof_id = 0; prof_id < num_prof; prof_id++) {
2058                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2059                 if (ret) {
2060                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2061                         return ret;
2062                 }
2063         }
2064         return 0;
2065 }
2066
2067 static int
2068 ice_reset_fxp_resource(struct ice_hw *hw)
2069 {
2070         int ret;
2071
2072         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2073         if (ret) {
2074                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2075                 return ret;
2076         }
2077
2078         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2079         if (ret) {
2080                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2081                 return ret;
2082         }
2083
2084         return 0;
2085 }
2086
2087 static void
2088 ice_rss_ctx_init(struct ice_pf *pf)
2089 {
2090         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2091         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2092
2093         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2094         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2095
2096         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2097         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2098 }
2099
2100 static uint64_t
2101 ice_get_supported_rxdid(struct ice_hw *hw)
2102 {
2103         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2104         uint32_t regval;
2105         int i;
2106
2107         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2108
2109         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2110                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2111                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2112                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2113                         supported_rxdid |= BIT(i);
2114         }
2115         return supported_rxdid;
2116 }
2117
2118 static int
2119 ice_dev_init(struct rte_eth_dev *dev)
2120 {
2121         struct rte_pci_device *pci_dev;
2122         struct rte_intr_handle *intr_handle;
2123         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125         struct ice_adapter *ad =
2126                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2127         struct ice_vsi *vsi;
2128         int ret;
2129
2130         dev->dev_ops = &ice_eth_dev_ops;
2131         dev->rx_queue_count = ice_rx_queue_count;
2132         dev->rx_descriptor_status = ice_rx_descriptor_status;
2133         dev->tx_descriptor_status = ice_tx_descriptor_status;
2134         dev->rx_pkt_burst = ice_recv_pkts;
2135         dev->tx_pkt_burst = ice_xmit_pkts;
2136         dev->tx_pkt_prepare = ice_prep_pkts;
2137
2138         /* for secondary processes, we don't initialise any further as primary
2139          * has already done this work.
2140          */
2141         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2142                 ice_set_rx_function(dev);
2143                 ice_set_tx_function(dev);
2144                 return 0;
2145         }
2146
2147         ice_set_default_ptype_table(dev);
2148         pci_dev = RTE_DEV_TO_PCI(dev->device);
2149         intr_handle = &pci_dev->intr_handle;
2150
2151         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2152         pf->adapter->eth_dev = dev;
2153         pf->dev_data = dev->data;
2154         hw->back = pf->adapter;
2155         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2156         hw->vendor_id = pci_dev->id.vendor_id;
2157         hw->device_id = pci_dev->id.device_id;
2158         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2159         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2160         hw->bus.device = pci_dev->addr.devid;
2161         hw->bus.func = pci_dev->addr.function;
2162
2163         ret = ice_parse_devargs(dev);
2164         if (ret) {
2165                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2166                 return -EINVAL;
2167         }
2168
2169         ice_init_controlq_parameter(hw);
2170
2171         ret = ice_init_hw(hw);
2172         if (ret) {
2173                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2174                 return -EINVAL;
2175         }
2176
2177         ret = ice_load_pkg(dev);
2178         if (ret) {
2179                 if (ad->devargs.safe_mode_support == 0) {
2180                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2181                                         "Use safe-mode-support=1 to enter Safe Mode");
2182                         return ret;
2183                 }
2184
2185                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2186                                         "Entering Safe Mode");
2187                 ad->is_safe_mode = 1;
2188         }
2189
2190         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2191                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2192                      hw->api_maj_ver, hw->api_min_ver);
2193
2194         ice_pf_sw_init(dev);
2195         ret = ice_init_mac_address(dev);
2196         if (ret) {
2197                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2198                 goto err_init_mac;
2199         }
2200
2201         ret = ice_res_pool_init(&pf->msix_pool, 1,
2202                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2203         if (ret) {
2204                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2205                 goto err_msix_pool_init;
2206         }
2207
2208         ret = ice_pf_setup(pf);
2209         if (ret) {
2210                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2211                 goto err_pf_setup;
2212         }
2213
2214         ret = ice_send_driver_ver(hw);
2215         if (ret) {
2216                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2217                 goto err_pf_setup;
2218         }
2219
2220         vsi = pf->main_vsi;
2221
2222         /* Disable double vlan by default */
2223         ice_vsi_config_double_vlan(vsi, false);
2224
2225         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2226         if (ret != ICE_SUCCESS)
2227                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2228         ret = ice_init_dcb(hw, true);
2229         if (ret != ICE_SUCCESS)
2230                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2231         /* Forward LLDP packets to default VSI */
2232         ret = ice_vsi_config_sw_lldp(vsi, true);
2233         if (ret != ICE_SUCCESS)
2234                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2235         /* register callback func to eal lib */
2236         rte_intr_callback_register(intr_handle,
2237                                    ice_interrupt_handler, dev);
2238
2239         ice_pf_enable_irq0(hw);
2240
2241         /* enable uio intr after callback register */
2242         rte_intr_enable(intr_handle);
2243
2244         /* get base queue pairs index  in the device */
2245         ice_base_queue_get(pf);
2246
2247         /* Initialize RSS context for gtpu_eh */
2248         ice_rss_ctx_init(pf);
2249
2250         if (!ad->is_safe_mode) {
2251                 ret = ice_flow_init(ad);
2252                 if (ret) {
2253                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2254                         return ret;
2255                 }
2256         }
2257
2258         ret = ice_reset_fxp_resource(hw);
2259         if (ret) {
2260                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2261                 return ret;
2262         }
2263
2264         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2265
2266         return 0;
2267
2268 err_pf_setup:
2269         ice_res_pool_destroy(&pf->msix_pool);
2270 err_msix_pool_init:
2271         rte_free(dev->data->mac_addrs);
2272         dev->data->mac_addrs = NULL;
2273 err_init_mac:
2274         ice_sched_cleanup_all(hw);
2275         rte_free(hw->port_info);
2276         ice_shutdown_all_ctrlq(hw);
2277         rte_free(pf->proto_xtr);
2278
2279         return ret;
2280 }
2281
2282 int
2283 ice_release_vsi(struct ice_vsi *vsi)
2284 {
2285         struct ice_hw *hw;
2286         struct ice_vsi_ctx vsi_ctx;
2287         enum ice_status ret;
2288         int error = 0;
2289
2290         if (!vsi)
2291                 return error;
2292
2293         hw = ICE_VSI_TO_HW(vsi);
2294
2295         ice_remove_all_mac_vlan_filters(vsi);
2296
2297         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2298
2299         vsi_ctx.vsi_num = vsi->vsi_id;
2300         vsi_ctx.info = vsi->info;
2301         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2302         if (ret != ICE_SUCCESS) {
2303                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2304                 error = -1;
2305         }
2306
2307         rte_free(vsi->rss_lut);
2308         rte_free(vsi->rss_key);
2309         rte_free(vsi);
2310         return error;
2311 }
2312
2313 void
2314 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2315 {
2316         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2317         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2320         uint16_t msix_intr, i;
2321
2322         /* disable interrupt and also clear all the exist config */
2323         for (i = 0; i < vsi->nb_qps; i++) {
2324                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2325                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2326                 rte_wmb();
2327         }
2328
2329         if (rte_intr_allow_others(intr_handle))
2330                 /* vfio-pci */
2331                 for (i = 0; i < vsi->nb_msix; i++) {
2332                         msix_intr = vsi->msix_intr + i;
2333                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2334                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2335                 }
2336         else
2337                 /* igb_uio */
2338                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2339 }
2340
2341 static void
2342 ice_dev_stop(struct rte_eth_dev *dev)
2343 {
2344         struct rte_eth_dev_data *data = dev->data;
2345         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346         struct ice_vsi *main_vsi = pf->main_vsi;
2347         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2349         uint16_t i;
2350
2351         /* avoid stopping again */
2352         if (pf->adapter_stopped)
2353                 return;
2354
2355         /* stop and clear all Rx queues */
2356         for (i = 0; i < data->nb_rx_queues; i++)
2357                 ice_rx_queue_stop(dev, i);
2358
2359         /* stop and clear all Tx queues */
2360         for (i = 0; i < data->nb_tx_queues; i++)
2361                 ice_tx_queue_stop(dev, i);
2362
2363         /* disable all queue interrupts */
2364         ice_vsi_disable_queues_intr(main_vsi);
2365
2366         if (pf->init_link_up)
2367                 ice_dev_set_link_up(dev);
2368         else
2369                 ice_dev_set_link_down(dev);
2370
2371         /* Clean datapath event and queue/vec mapping */
2372         rte_intr_efd_disable(intr_handle);
2373         if (intr_handle->intr_vec) {
2374                 rte_free(intr_handle->intr_vec);
2375                 intr_handle->intr_vec = NULL;
2376         }
2377
2378         pf->adapter_stopped = true;
2379 }
2380
2381 static int
2382 ice_dev_close(struct rte_eth_dev *dev)
2383 {
2384         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2385         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2388         struct ice_adapter *ad =
2389                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2390
2391         /* Since stop will make link down, then the link event will be
2392          * triggered, disable the irq firstly to avoid the port_infoe etc
2393          * resources deallocation causing the interrupt service thread
2394          * crash.
2395          */
2396         ice_pf_disable_irq0(hw);
2397
2398         ice_dev_stop(dev);
2399
2400         if (!ad->is_safe_mode)
2401                 ice_flow_uninit(ad);
2402
2403         /* release all queue resource */
2404         ice_free_queues(dev);
2405
2406         ice_res_pool_destroy(&pf->msix_pool);
2407         ice_release_vsi(pf->main_vsi);
2408         ice_sched_cleanup_all(hw);
2409         ice_free_hw_tbls(hw);
2410         rte_free(hw->port_info);
2411         hw->port_info = NULL;
2412         ice_shutdown_all_ctrlq(hw);
2413         rte_free(pf->proto_xtr);
2414         pf->proto_xtr = NULL;
2415
2416         dev->dev_ops = NULL;
2417         dev->rx_pkt_burst = NULL;
2418         dev->tx_pkt_burst = NULL;
2419
2420         rte_free(dev->data->mac_addrs);
2421         dev->data->mac_addrs = NULL;
2422
2423         /* disable uio intr before callback unregister */
2424         rte_intr_disable(intr_handle);
2425
2426         /* unregister callback func from eal lib */
2427         rte_intr_callback_unregister(intr_handle,
2428                                      ice_interrupt_handler, dev);
2429
2430         return 0;
2431 }
2432
2433 static int
2434 ice_dev_uninit(struct rte_eth_dev *dev)
2435 {
2436         ice_dev_close(dev);
2437
2438         return 0;
2439 }
2440
2441 static int
2442 ice_add_rss_cfg_post(struct ice_pf *pf, uint32_t hdr, uint64_t fld, bool symm)
2443 {
2444         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2445         struct ice_vsi *vsi = pf->main_vsi;
2446
2447         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2448                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2449                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2450                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr = hdr;
2451                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld = fld;
2452                         pf->gtpu_hash_ctx.ipv4_udp.symm = symm;
2453                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2454                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2455                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr = hdr;
2456                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld = fld;
2457                         pf->gtpu_hash_ctx.ipv6_udp.symm = symm;
2458                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2459                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2460                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr = hdr;
2461                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld = fld;
2462                         pf->gtpu_hash_ctx.ipv4_tcp.symm = symm;
2463                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2464                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2465                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr = hdr;
2466                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld = fld;
2467                         pf->gtpu_hash_ctx.ipv6_tcp.symm = symm;
2468                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2469                         pf->gtpu_hash_ctx.ipv4.pkt_hdr = hdr;
2470                         pf->gtpu_hash_ctx.ipv4.hash_fld = fld;
2471                         pf->gtpu_hash_ctx.ipv4.symm = symm;
2472                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2473                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2474                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2475                         pf->gtpu_hash_ctx.ipv6.pkt_hdr = hdr;
2476                         pf->gtpu_hash_ctx.ipv6.hash_fld = fld;
2477                         pf->gtpu_hash_ctx.ipv6.symm = symm;
2478                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2479                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2480                 }
2481         }
2482
2483         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2484             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2485                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2486                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2487                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2488                                 ice_add_rss_cfg(hw, vsi->idx,
2489                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2490                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2491                                         pf->gtpu_hash_ctx.ipv4.symm);
2492                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2493                         }
2494                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2495                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2496                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2497                                 ice_add_rss_cfg(hw, vsi->idx,
2498                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2499                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2500                                         pf->gtpu_hash_ctx.ipv6.symm);
2501                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2502                         }
2503                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2504                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2505                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv4)) {
2506                                 ice_add_rss_cfg(hw, vsi->idx,
2507                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2508                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr,
2509                                         pf->gtpu_hash_ctx.ipv4.symm);
2510                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv4);
2511                         }
2512                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2513                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2514                         if (ICE_HASH_CFG_IS_ROTATING(&pf->gtpu_hash_ctx.ipv6)) {
2515                                 ice_add_rss_cfg(hw, vsi->idx,
2516                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2517                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr,
2518                                         pf->gtpu_hash_ctx.ipv6.symm);
2519                                 ICE_HASH_CFG_ROTATE_STOP(&pf->gtpu_hash_ctx.ipv6);
2520                         }
2521                 }
2522         }
2523
2524         return 0;
2525 }
2526
2527 static int
2528 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2529 {
2530         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2531         struct ice_vsi *vsi = pf->main_vsi;
2532
2533         if (hdr & (ICE_FLOW_SEG_HDR_GTPU_DWN |
2534             ICE_FLOW_SEG_HDR_GTPU_UP)) {
2535                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2536                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2537                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2538                                 ice_rem_rss_cfg(hw, vsi->idx,
2539                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2540                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2541                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2542                         }
2543
2544                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2545                                 ice_rem_rss_cfg(hw, vsi->idx,
2546                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2547                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2548                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2549                         }
2550                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2551                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2552                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2553                                 ice_rem_rss_cfg(hw, vsi->idx,
2554                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2555                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2556                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2557                         }
2558
2559                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2560                                 ice_rem_rss_cfg(hw, vsi->idx,
2561                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2562                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2563                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2564                         }
2565                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2566                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2567                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2568                                 ice_rem_rss_cfg(hw, vsi->idx,
2569                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2570                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2571                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2572                         }
2573
2574                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2575                                 ice_rem_rss_cfg(hw, vsi->idx,
2576                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2577                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2578                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv4);
2579                         }
2580                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2581                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2582                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2583                                 ice_rem_rss_cfg(hw, vsi->idx,
2584                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2585                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2586                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2587                         }
2588
2589                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2590                                 ice_rem_rss_cfg(hw, vsi->idx,
2591                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2592                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2593                                 ICE_HASH_CFG_ROTATE_START(&pf->gtpu_hash_ctx.ipv6);
2594                         }
2595                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2596                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4)) {
2597                                 ice_rem_rss_cfg(hw, vsi->idx,
2598                                         pf->gtpu_hash_ctx.ipv4.hash_fld,
2599                                         pf->gtpu_hash_ctx.ipv4.pkt_hdr);
2600                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2601                         }
2602
2603                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_udp)) {
2604                                 ice_rem_rss_cfg(hw, vsi->idx,
2605                                         pf->gtpu_hash_ctx.ipv4_udp.hash_fld,
2606                                         pf->gtpu_hash_ctx.ipv4_udp.pkt_hdr);
2607                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2608                         }
2609
2610                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv4_tcp)) {
2611                                 ice_rem_rss_cfg(hw, vsi->idx,
2612                                         pf->gtpu_hash_ctx.ipv4_tcp.hash_fld,
2613                                         pf->gtpu_hash_ctx.ipv4_tcp.pkt_hdr);
2614                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2615                         }
2616                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2617                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6)) {
2618                                 ice_rem_rss_cfg(hw, vsi->idx,
2619                                         pf->gtpu_hash_ctx.ipv6.hash_fld,
2620                                         pf->gtpu_hash_ctx.ipv6.pkt_hdr);
2621                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2622                         }
2623
2624                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_udp)) {
2625                                 ice_rem_rss_cfg(hw, vsi->idx,
2626                                         pf->gtpu_hash_ctx.ipv6_udp.hash_fld,
2627                                         pf->gtpu_hash_ctx.ipv6_udp.pkt_hdr);
2628                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2629                         }
2630
2631                         if (ICE_HASH_CFG_VALID(&pf->gtpu_hash_ctx.ipv6_tcp)) {
2632                                 ice_rem_rss_cfg(hw, vsi->idx,
2633                                         pf->gtpu_hash_ctx.ipv6_tcp.hash_fld,
2634                                         pf->gtpu_hash_ctx.ipv6_tcp.pkt_hdr);
2635                                 ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2636                         }
2637                 }
2638         }
2639
2640         return 0;
2641 }
2642
2643 static int
2644 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2645 {
2646         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH) {
2647                 if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2648                     (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2649                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_udp);
2650                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2651                            (hdr & ICE_FLOW_SEG_HDR_UDP)) {
2652                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_udp);
2653                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV4) &&
2654                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2655                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4_tcp);
2656                 } else if ((hdr & ICE_FLOW_SEG_HDR_IPV6) &&
2657                            (hdr & ICE_FLOW_SEG_HDR_TCP)) {
2658                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
2659                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV4) {
2660                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv4);
2661                 } else if (hdr & ICE_FLOW_SEG_HDR_IPV6) {
2662                         ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6);
2663                 }
2664         }
2665
2666         return 0;
2667 }
2668
2669 int
2670 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2671                 uint64_t fld, uint32_t hdr)
2672 {
2673         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2674         int ret;
2675
2676         ret = ice_rem_rss_cfg(hw, vsi_id, fld, hdr);
2677         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2678                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2679
2680         ret = ice_rem_rss_cfg_post(pf, hdr);
2681         if (ret)
2682                 PMD_DRV_LOG(ERR, "remove rss cfg post failed\n");
2683
2684         return 0;
2685 }
2686
2687 int
2688 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2689                 uint64_t fld, uint32_t hdr, bool symm)
2690 {
2691         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2692         int ret;
2693
2694         ret = ice_add_rss_cfg_pre(pf, hdr);
2695         if (ret)
2696                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2697
2698         ret = ice_add_rss_cfg(hw, vsi_id, fld, hdr, symm);
2699         if (ret)
2700                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2701
2702         ret = ice_add_rss_cfg_post(pf, hdr, fld, symm);
2703         if (ret)
2704                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2705
2706         return 0;
2707 }
2708
2709 static void
2710 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2711 {
2712         struct ice_vsi *vsi = pf->main_vsi;
2713         int ret;
2714
2715         /* Configure RSS for IPv4 with src/dst addr as input set */
2716         if (rss_hf & ETH_RSS_IPV4) {
2717                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2718                                       ICE_FLOW_SEG_HDR_IPV4 |
2719                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2720                 if (ret)
2721                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2722                                     __func__, ret);
2723         }
2724
2725         /* Configure RSS for IPv6 with src/dst addr as input set */
2726         if (rss_hf & ETH_RSS_IPV6) {
2727                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2728                                       ICE_FLOW_SEG_HDR_IPV6 |
2729                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2730                 if (ret)
2731                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2732                                     __func__, ret);
2733         }
2734
2735         /* Configure RSS for udp4 with src/dst addr and port as input set */
2736         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2737                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2738                                       ICE_FLOW_SEG_HDR_UDP |
2739                                       ICE_FLOW_SEG_HDR_IPV4 |
2740                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2741                 if (ret)
2742                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2743                                     __func__, ret);
2744         }
2745
2746         /* Configure RSS for udp6 with src/dst addr and port as input set */
2747         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2748                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2749                                       ICE_FLOW_SEG_HDR_UDP |
2750                                       ICE_FLOW_SEG_HDR_IPV6 |
2751                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2752                 if (ret)
2753                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2754                                     __func__, ret);
2755         }
2756
2757         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2758         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2759                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2760                                       ICE_FLOW_SEG_HDR_TCP |
2761                                       ICE_FLOW_SEG_HDR_IPV4 |
2762                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2763                 if (ret)
2764                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2765                                     __func__, ret);
2766         }
2767
2768         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2769         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2770                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2771                                       ICE_FLOW_SEG_HDR_TCP |
2772                                       ICE_FLOW_SEG_HDR_IPV6 |
2773                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2774                 if (ret)
2775                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2776                                     __func__, ret);
2777         }
2778
2779         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2780         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2781                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2782                                       ICE_FLOW_SEG_HDR_SCTP |
2783                                       ICE_FLOW_SEG_HDR_IPV4 |
2784                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2785                 if (ret)
2786                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2787                                     __func__, ret);
2788         }
2789
2790         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2791         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2792                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2793                                       ICE_FLOW_SEG_HDR_SCTP |
2794                                       ICE_FLOW_SEG_HDR_IPV6 |
2795                                       ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2796                 if (ret)
2797                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2798                                     __func__, ret);
2799         }
2800
2801         if (rss_hf & ETH_RSS_IPV4) {
2802                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2803                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2804                                 ICE_FLOW_SEG_HDR_IPV4 |
2805                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2806                 if (ret)
2807                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2808                                     __func__, ret);
2809
2810                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2811                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2812                                 ICE_FLOW_SEG_HDR_IPV4 |
2813                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2814                 if (ret)
2815                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2816                                     __func__, ret);
2817
2818                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV4,
2819                                 ICE_FLOW_SEG_HDR_PPPOE |
2820                                 ICE_FLOW_SEG_HDR_IPV4 |
2821                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2822                 if (ret)
2823                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2824                                     __func__, ret);
2825         }
2826
2827         if (rss_hf & ETH_RSS_IPV6) {
2828                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2829                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2830                                 ICE_FLOW_SEG_HDR_IPV6 |
2831                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2832                 if (ret)
2833                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2834                                     __func__, ret);
2835
2836                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2837                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2838                                 ICE_FLOW_SEG_HDR_IPV6 |
2839                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2840                 if (ret)
2841                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2842                                     __func__, ret);
2843
2844                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_FLOW_HASH_IPV6,
2845                                 ICE_FLOW_SEG_HDR_PPPOE |
2846                                 ICE_FLOW_SEG_HDR_IPV6 |
2847                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2848                 if (ret)
2849                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2850                                     __func__, ret);
2851         }
2852
2853         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2854                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2855                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2856                                 ICE_FLOW_SEG_HDR_UDP |
2857                                 ICE_FLOW_SEG_HDR_IPV4 |
2858                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2859                 if (ret)
2860                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2861                                     __func__, ret);
2862
2863                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2864                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2865                                 ICE_FLOW_SEG_HDR_UDP |
2866                                 ICE_FLOW_SEG_HDR_IPV4 |
2867                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2868                 if (ret)
2869                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2870                                     __func__, ret);
2871
2872                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV4,
2873                                 ICE_FLOW_SEG_HDR_PPPOE |
2874                                 ICE_FLOW_SEG_HDR_UDP |
2875                                 ICE_FLOW_SEG_HDR_IPV4 |
2876                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2877                 if (ret)
2878                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2879                                     __func__, ret);
2880         }
2881
2882         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2883                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2884                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2885                                 ICE_FLOW_SEG_HDR_UDP |
2886                                 ICE_FLOW_SEG_HDR_IPV6 |
2887                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2888                 if (ret)
2889                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2890                                     __func__, ret);
2891
2892                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2893                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2894                                 ICE_FLOW_SEG_HDR_UDP |
2895                                 ICE_FLOW_SEG_HDR_IPV6 |
2896                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2897                 if (ret)
2898                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2899                                     __func__, ret);
2900
2901                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_UDP_IPV6,
2902                                 ICE_FLOW_SEG_HDR_PPPOE |
2903                                 ICE_FLOW_SEG_HDR_UDP |
2904                                 ICE_FLOW_SEG_HDR_IPV6 |
2905                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2906                 if (ret)
2907                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2908                                     __func__, ret);
2909         }
2910
2911         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2912                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2913                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2914                                 ICE_FLOW_SEG_HDR_TCP |
2915                                 ICE_FLOW_SEG_HDR_IPV4 |
2916                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2917                 if (ret)
2918                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
2919                                     __func__, ret);
2920
2921                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2922                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2923                                 ICE_FLOW_SEG_HDR_TCP |
2924                                 ICE_FLOW_SEG_HDR_IPV4 |
2925                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2926                 if (ret)
2927                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
2928                                     __func__, ret);
2929
2930                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV4,
2931                                 ICE_FLOW_SEG_HDR_PPPOE |
2932                                 ICE_FLOW_SEG_HDR_TCP |
2933                                 ICE_FLOW_SEG_HDR_IPV4 |
2934                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2935                 if (ret)
2936                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2937                                     __func__, ret);
2938         }
2939
2940         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2941                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2942                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2943                                 ICE_FLOW_SEG_HDR_TCP |
2944                                 ICE_FLOW_SEG_HDR_IPV6 |
2945                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2946                 if (ret)
2947                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
2948                                     __func__, ret);
2949
2950                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2951                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2952                                 ICE_FLOW_SEG_HDR_TCP |
2953                                 ICE_FLOW_SEG_HDR_IPV6 |
2954                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2955                 if (ret)
2956                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
2957                                     __func__, ret);
2958
2959                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_TCP_IPV6,
2960                                 ICE_FLOW_SEG_HDR_PPPOE |
2961                                 ICE_FLOW_SEG_HDR_TCP |
2962                                 ICE_FLOW_SEG_HDR_IPV6 |
2963                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2964                 if (ret)
2965                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2966                                     __func__, ret);
2967         }
2968
2969         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2970                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
2971                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2972                                 ICE_FLOW_SEG_HDR_SCTP |
2973                                 ICE_FLOW_SEG_HDR_IPV4 |
2974                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2975                 if (ret)
2976                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_SCTP rss flow fail %d",
2977                                     __func__, ret);
2978
2979                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV4,
2980                                 ICE_FLOW_SEG_HDR_GTPU_EH |
2981                                 ICE_FLOW_SEG_HDR_SCTP |
2982                                 ICE_FLOW_SEG_HDR_IPV4 |
2983                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2984                 if (ret)
2985                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_SCTP rss flow fail %d",
2986                                     __func__, ret);
2987         }
2988
2989         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2990                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
2991                                 ICE_FLOW_SEG_HDR_GTPU_IP |
2992                                 ICE_FLOW_SEG_HDR_SCTP |
2993                                 ICE_FLOW_SEG_HDR_IPV6 |
2994                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
2995                 if (ret)
2996                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_SCTP rss flow fail %d",
2997                                     __func__, ret);
2998
2999                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, ICE_HASH_SCTP_IPV6,
3000                                 ICE_FLOW_SEG_HDR_GTPU_EH |
3001                                 ICE_FLOW_SEG_HDR_SCTP |
3002                                 ICE_FLOW_SEG_HDR_IPV6 |
3003                                 ICE_FLOW_SEG_HDR_IPV_OTHER, 0);
3004                 if (ret)
3005                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_SCTP rss flow fail %d",
3006                                     __func__, ret);
3007         }
3008 }
3009
3010 static int ice_init_rss(struct ice_pf *pf)
3011 {
3012         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3013         struct ice_vsi *vsi = pf->main_vsi;
3014         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3015         struct rte_eth_rss_conf *rss_conf;
3016         struct ice_aqc_get_set_rss_keys key;
3017         uint16_t i, nb_q;
3018         int ret = 0;
3019         bool is_safe_mode = pf->adapter->is_safe_mode;
3020         uint32_t reg;
3021
3022         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3023         nb_q = dev->data->nb_rx_queues;
3024         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3025         vsi->rss_lut_size = pf->hash_lut_size;
3026
3027         if (is_safe_mode) {
3028                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3029                 return 0;
3030         }
3031
3032         if (!vsi->rss_key) {
3033                 vsi->rss_key = rte_zmalloc(NULL,
3034                                            vsi->rss_key_size, 0);
3035                 if (vsi->rss_key == NULL) {
3036                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3037                         return -ENOMEM;
3038                 }
3039         }
3040         if (!vsi->rss_lut) {
3041                 vsi->rss_lut = rte_zmalloc(NULL,
3042                                            vsi->rss_lut_size, 0);
3043                 if (vsi->rss_lut == NULL) {
3044                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3045                         rte_free(vsi->rss_key);
3046                         vsi->rss_key = NULL;
3047                         return -ENOMEM;
3048                 }
3049         }
3050         /* configure RSS key */
3051         if (!rss_conf->rss_key) {
3052                 /* Calculate the default hash key */
3053                 for (i = 0; i <= vsi->rss_key_size; i++)
3054                         vsi->rss_key[i] = (uint8_t)rte_rand();
3055         } else {
3056                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3057                            RTE_MIN(rss_conf->rss_key_len,
3058                                    vsi->rss_key_size));
3059         }
3060         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3061         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3062         if (ret)
3063                 goto out;
3064
3065         /* init RSS LUT table */
3066         for (i = 0; i < vsi->rss_lut_size; i++)
3067                 vsi->rss_lut[i] = i % nb_q;
3068
3069         ret = ice_aq_set_rss_lut(hw, vsi->idx,
3070                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
3071                                  vsi->rss_lut, vsi->rss_lut_size);
3072         if (ret)
3073                 goto out;
3074
3075         /* Enable registers for symmetric_toeplitz function. */
3076         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3077         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3078                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3079         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3080
3081         /* RSS hash configuration */
3082         ice_rss_hash_set(pf, rss_conf->rss_hf);
3083
3084         return 0;
3085 out:
3086         rte_free(vsi->rss_key);
3087         vsi->rss_key = NULL;
3088         rte_free(vsi->rss_lut);
3089         vsi->rss_lut = NULL;
3090         return -EINVAL;
3091 }
3092
3093 static int
3094 ice_dev_configure(struct rte_eth_dev *dev)
3095 {
3096         struct ice_adapter *ad =
3097                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3098         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3099         int ret;
3100
3101         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3102          * bulk allocation or vector Rx preconditions we will reset it.
3103          */
3104         ad->rx_bulk_alloc_allowed = true;
3105         ad->tx_simple_allowed = true;
3106
3107         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3108                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3109
3110         ret = ice_init_rss(pf);
3111         if (ret) {
3112                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3113                 return ret;
3114         }
3115
3116         return 0;
3117 }
3118
3119 static void
3120 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3121                        int base_queue, int nb_queue)
3122 {
3123         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3124         uint32_t val, val_tx;
3125         int i;
3126
3127         for (i = 0; i < nb_queue; i++) {
3128                 /*do actual bind*/
3129                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3130                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3131                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3132                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3133
3134                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3135                             base_queue + i, msix_vect);
3136                 /* set ITR0 value */
3137                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
3138                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3139                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3140         }
3141 }
3142
3143 void
3144 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3145 {
3146         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3147         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3148         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3149         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3150         uint16_t msix_vect = vsi->msix_intr;
3151         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3152         uint16_t queue_idx = 0;
3153         int record = 0;
3154         int i;
3155
3156         /* clear Rx/Tx queue interrupt */
3157         for (i = 0; i < vsi->nb_used_qps; i++) {
3158                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3159                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3160         }
3161
3162         /* PF bind interrupt */
3163         if (rte_intr_dp_is_en(intr_handle)) {
3164                 queue_idx = 0;
3165                 record = 1;
3166         }
3167
3168         for (i = 0; i < vsi->nb_used_qps; i++) {
3169                 if (nb_msix <= 1) {
3170                         if (!rte_intr_allow_others(intr_handle))
3171                                 msix_vect = ICE_MISC_VEC_ID;
3172
3173                         /* uio mapping all queue to one msix_vect */
3174                         __vsi_queues_bind_intr(vsi, msix_vect,
3175                                                vsi->base_queue + i,
3176                                                vsi->nb_used_qps - i);
3177
3178                         for (; !!record && i < vsi->nb_used_qps; i++)
3179                                 intr_handle->intr_vec[queue_idx + i] =
3180                                         msix_vect;
3181                         break;
3182                 }
3183
3184                 /* vfio 1:1 queue/msix_vect mapping */
3185                 __vsi_queues_bind_intr(vsi, msix_vect,
3186                                        vsi->base_queue + i, 1);
3187
3188                 if (!!record)
3189                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3190
3191                 msix_vect++;
3192                 nb_msix--;
3193         }
3194 }
3195
3196 void
3197 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3198 {
3199         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3200         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3201         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3202         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3203         uint16_t msix_intr, i;
3204
3205         if (rte_intr_allow_others(intr_handle))
3206                 for (i = 0; i < vsi->nb_used_qps; i++) {
3207                         msix_intr = vsi->msix_intr + i;
3208                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3209                                       GLINT_DYN_CTL_INTENA_M |
3210                                       GLINT_DYN_CTL_CLEARPBA_M |
3211                                       GLINT_DYN_CTL_ITR_INDX_M |
3212                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3213                 }
3214         else
3215                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3216                               GLINT_DYN_CTL_INTENA_M |
3217                               GLINT_DYN_CTL_CLEARPBA_M |
3218                               GLINT_DYN_CTL_ITR_INDX_M |
3219                               GLINT_DYN_CTL_WB_ON_ITR_M);
3220 }
3221
3222 static int
3223 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3224 {
3225         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3226         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3227         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3228         struct ice_vsi *vsi = pf->main_vsi;
3229         uint32_t intr_vector = 0;
3230
3231         rte_intr_disable(intr_handle);
3232
3233         /* check and configure queue intr-vector mapping */
3234         if ((rte_intr_cap_multiple(intr_handle) ||
3235              !RTE_ETH_DEV_SRIOV(dev).active) &&
3236             dev->data->dev_conf.intr_conf.rxq != 0) {
3237                 intr_vector = dev->data->nb_rx_queues;
3238                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3239                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3240                                     ICE_MAX_INTR_QUEUE_NUM);
3241                         return -ENOTSUP;
3242                 }
3243                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3244                         return -1;
3245         }
3246
3247         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3248                 intr_handle->intr_vec =
3249                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3250                             0);
3251                 if (!intr_handle->intr_vec) {
3252                         PMD_DRV_LOG(ERR,
3253                                     "Failed to allocate %d rx_queues intr_vec",
3254                                     dev->data->nb_rx_queues);
3255                         return -ENOMEM;
3256                 }
3257         }
3258
3259         /* Map queues with MSIX interrupt */
3260         vsi->nb_used_qps = dev->data->nb_rx_queues;
3261         ice_vsi_queues_bind_intr(vsi);
3262
3263         /* Enable interrupts for all the queues */
3264         ice_vsi_enable_queues_intr(vsi);
3265
3266         rte_intr_enable(intr_handle);
3267
3268         return 0;
3269 }
3270
3271 static void
3272 ice_get_init_link_status(struct rte_eth_dev *dev)
3273 {
3274         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3276         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3277         struct ice_link_status link_status;
3278         int ret;
3279
3280         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3281                                    &link_status, NULL);
3282         if (ret != ICE_SUCCESS) {
3283                 PMD_DRV_LOG(ERR, "Failed to get link info");
3284                 pf->init_link_up = false;
3285                 return;
3286         }
3287
3288         if (link_status.link_info & ICE_AQ_LINK_UP)
3289                 pf->init_link_up = true;
3290 }
3291
3292 static int
3293 ice_dev_start(struct rte_eth_dev *dev)
3294 {
3295         struct rte_eth_dev_data *data = dev->data;
3296         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3297         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3298         struct ice_vsi *vsi = pf->main_vsi;
3299         uint16_t nb_rxq = 0;
3300         uint16_t nb_txq, i;
3301         uint16_t max_frame_size;
3302         int mask, ret;
3303
3304         /* program Tx queues' context in hardware */
3305         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3306                 ret = ice_tx_queue_start(dev, nb_txq);
3307                 if (ret) {
3308                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3309                         goto tx_err;
3310                 }
3311         }
3312
3313         /* program Rx queues' context in hardware*/
3314         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3315                 ret = ice_rx_queue_start(dev, nb_rxq);
3316                 if (ret) {
3317                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3318                         goto rx_err;
3319                 }
3320         }
3321
3322         ice_set_rx_function(dev);
3323         ice_set_tx_function(dev);
3324
3325         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3326                         ETH_VLAN_EXTEND_MASK;
3327         ret = ice_vlan_offload_set(dev, mask);
3328         if (ret) {
3329                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3330                 goto rx_err;
3331         }
3332
3333         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3334         if (ice_rxq_intr_setup(dev))
3335                 return -EIO;
3336
3337         /* Enable receiving broadcast packets and transmitting packets */
3338         ret = ice_set_vsi_promisc(hw, vsi->idx,
3339                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3340                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3341                                   0);
3342         if (ret != ICE_SUCCESS)
3343                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3344
3345         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3346                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3347                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3348                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3349                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3350                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3351                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3352                                      NULL);
3353         if (ret != ICE_SUCCESS)
3354                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3355
3356         ice_get_init_link_status(dev);
3357
3358         ice_dev_set_link_up(dev);
3359
3360         /* Call get_link_info aq commond to enable/disable LSE */
3361         ice_link_update(dev, 0);
3362
3363         pf->adapter_stopped = false;
3364
3365         /* Set the max frame size to default value*/
3366         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3367                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3368                 ICE_FRAME_SIZE_MAX;
3369
3370         /* Set the max frame size to HW*/
3371         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3372
3373         return 0;
3374
3375         /* stop the started queues if failed to start all queues */
3376 rx_err:
3377         for (i = 0; i < nb_rxq; i++)
3378                 ice_rx_queue_stop(dev, i);
3379 tx_err:
3380         for (i = 0; i < nb_txq; i++)
3381                 ice_tx_queue_stop(dev, i);
3382
3383         return -EIO;
3384 }
3385
3386 static int
3387 ice_dev_reset(struct rte_eth_dev *dev)
3388 {
3389         int ret;
3390
3391         if (dev->data->sriov.active)
3392                 return -ENOTSUP;
3393
3394         ret = ice_dev_uninit(dev);
3395         if (ret) {
3396                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3397                 return -ENXIO;
3398         }
3399
3400         ret = ice_dev_init(dev);
3401         if (ret) {
3402                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3403                 return -ENXIO;
3404         }
3405
3406         return 0;
3407 }
3408
3409 static int
3410 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3411 {
3412         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3413         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414         struct ice_vsi *vsi = pf->main_vsi;
3415         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3416         bool is_safe_mode = pf->adapter->is_safe_mode;
3417         u64 phy_type_low;
3418         u64 phy_type_high;
3419
3420         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3421         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3422         dev_info->max_rx_queues = vsi->nb_qps;
3423         dev_info->max_tx_queues = vsi->nb_qps;
3424         dev_info->max_mac_addrs = vsi->max_macaddrs;
3425         dev_info->max_vfs = pci_dev->max_vfs;
3426         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3427         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3428
3429         dev_info->rx_offload_capa =
3430                 DEV_RX_OFFLOAD_VLAN_STRIP |
3431                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3432                 DEV_RX_OFFLOAD_KEEP_CRC |
3433                 DEV_RX_OFFLOAD_SCATTER |
3434                 DEV_RX_OFFLOAD_VLAN_FILTER;
3435         dev_info->tx_offload_capa =
3436                 DEV_TX_OFFLOAD_VLAN_INSERT |
3437                 DEV_TX_OFFLOAD_TCP_TSO |
3438                 DEV_TX_OFFLOAD_MULTI_SEGS |
3439                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3440         dev_info->flow_type_rss_offloads = 0;
3441
3442         if (!is_safe_mode) {
3443                 dev_info->rx_offload_capa |=
3444                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3445                         DEV_RX_OFFLOAD_UDP_CKSUM |
3446                         DEV_RX_OFFLOAD_TCP_CKSUM |
3447                         DEV_RX_OFFLOAD_QINQ_STRIP |
3448                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3449                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3450                         DEV_RX_OFFLOAD_RSS_HASH;
3451                 dev_info->tx_offload_capa |=
3452                         DEV_TX_OFFLOAD_QINQ_INSERT |
3453                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3454                         DEV_TX_OFFLOAD_UDP_CKSUM |
3455                         DEV_TX_OFFLOAD_TCP_CKSUM |
3456                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3457                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3458                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3459                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3460         }
3461
3462         dev_info->rx_queue_offload_capa = 0;
3463         dev_info->tx_queue_offload_capa = 0;
3464
3465         dev_info->reta_size = pf->hash_lut_size;
3466         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3467
3468         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3469                 .rx_thresh = {
3470                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3471                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3472                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3473                 },
3474                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3475                 .rx_drop_en = 0,
3476                 .offloads = 0,
3477         };
3478
3479         dev_info->default_txconf = (struct rte_eth_txconf) {
3480                 .tx_thresh = {
3481                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3482                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3483                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3484                 },
3485                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3486                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3487                 .offloads = 0,
3488         };
3489
3490         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3491                 .nb_max = ICE_MAX_RING_DESC,
3492                 .nb_min = ICE_MIN_RING_DESC,
3493                 .nb_align = ICE_ALIGN_RING_DESC,
3494         };
3495
3496         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3497                 .nb_max = ICE_MAX_RING_DESC,
3498                 .nb_min = ICE_MIN_RING_DESC,
3499                 .nb_align = ICE_ALIGN_RING_DESC,
3500         };
3501
3502         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3503                                ETH_LINK_SPEED_100M |
3504                                ETH_LINK_SPEED_1G |
3505                                ETH_LINK_SPEED_2_5G |
3506                                ETH_LINK_SPEED_5G |
3507                                ETH_LINK_SPEED_10G |
3508                                ETH_LINK_SPEED_20G |
3509                                ETH_LINK_SPEED_25G;
3510
3511         phy_type_low = hw->port_info->phy.phy_type_low;
3512         phy_type_high = hw->port_info->phy.phy_type_high;
3513
3514         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3515                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3516
3517         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3518                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3519                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3520
3521         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3522         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3523
3524         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3525         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3526         dev_info->default_rxportconf.nb_queues = 1;
3527         dev_info->default_txportconf.nb_queues = 1;
3528         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3529         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3530
3531         return 0;
3532 }
3533
3534 static inline int
3535 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3536                             struct rte_eth_link *link)
3537 {
3538         struct rte_eth_link *dst = link;
3539         struct rte_eth_link *src = &dev->data->dev_link;
3540
3541         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3542                                 *(uint64_t *)src) == 0)
3543                 return -1;
3544
3545         return 0;
3546 }
3547
3548 static inline int
3549 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3550                              struct rte_eth_link *link)
3551 {
3552         struct rte_eth_link *dst = &dev->data->dev_link;
3553         struct rte_eth_link *src = link;
3554
3555         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3556                                 *(uint64_t *)src) == 0)
3557                 return -1;
3558
3559         return 0;
3560 }
3561
3562 static int
3563 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3564 {
3565 #define CHECK_INTERVAL 100  /* 100ms */
3566 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3567         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568         struct ice_link_status link_status;
3569         struct rte_eth_link link, old;
3570         int status;
3571         unsigned int rep_cnt = MAX_REPEAT_TIME;
3572         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3573
3574         memset(&link, 0, sizeof(link));
3575         memset(&old, 0, sizeof(old));
3576         memset(&link_status, 0, sizeof(link_status));
3577         ice_atomic_read_link_status(dev, &old);
3578
3579         do {
3580                 /* Get link status information from hardware */
3581                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3582                                               &link_status, NULL);
3583                 if (status != ICE_SUCCESS) {
3584                         link.link_speed = ETH_SPEED_NUM_100M;
3585                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3586                         PMD_DRV_LOG(ERR, "Failed to get link info");
3587                         goto out;
3588                 }
3589
3590                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3591                 if (!wait_to_complete || link.link_status)
3592                         break;
3593
3594                 rte_delay_ms(CHECK_INTERVAL);
3595         } while (--rep_cnt);
3596
3597         if (!link.link_status)
3598                 goto out;
3599
3600         /* Full-duplex operation at all supported speeds */
3601         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3602
3603         /* Parse the link status */
3604         switch (link_status.link_speed) {
3605         case ICE_AQ_LINK_SPEED_10MB:
3606                 link.link_speed = ETH_SPEED_NUM_10M;
3607                 break;
3608         case ICE_AQ_LINK_SPEED_100MB:
3609                 link.link_speed = ETH_SPEED_NUM_100M;
3610                 break;
3611         case ICE_AQ_LINK_SPEED_1000MB:
3612                 link.link_speed = ETH_SPEED_NUM_1G;
3613                 break;
3614         case ICE_AQ_LINK_SPEED_2500MB:
3615                 link.link_speed = ETH_SPEED_NUM_2_5G;
3616                 break;
3617         case ICE_AQ_LINK_SPEED_5GB:
3618                 link.link_speed = ETH_SPEED_NUM_5G;
3619                 break;
3620         case ICE_AQ_LINK_SPEED_10GB:
3621                 link.link_speed = ETH_SPEED_NUM_10G;
3622                 break;
3623         case ICE_AQ_LINK_SPEED_20GB:
3624                 link.link_speed = ETH_SPEED_NUM_20G;
3625                 break;
3626         case ICE_AQ_LINK_SPEED_25GB:
3627                 link.link_speed = ETH_SPEED_NUM_25G;
3628                 break;
3629         case ICE_AQ_LINK_SPEED_40GB:
3630                 link.link_speed = ETH_SPEED_NUM_40G;
3631                 break;
3632         case ICE_AQ_LINK_SPEED_50GB:
3633                 link.link_speed = ETH_SPEED_NUM_50G;
3634                 break;
3635         case ICE_AQ_LINK_SPEED_100GB:
3636                 link.link_speed = ETH_SPEED_NUM_100G;
3637                 break;
3638         case ICE_AQ_LINK_SPEED_UNKNOWN:
3639                 PMD_DRV_LOG(ERR, "Unknown link speed");
3640                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3641                 break;
3642         default:
3643                 PMD_DRV_LOG(ERR, "None link speed");
3644                 link.link_speed = ETH_SPEED_NUM_NONE;
3645                 break;
3646         }
3647
3648         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3649                               ETH_LINK_SPEED_FIXED);
3650
3651 out:
3652         ice_atomic_write_link_status(dev, &link);
3653         if (link.link_status == old.link_status)
3654                 return -1;
3655
3656         return 0;
3657 }
3658
3659 /* Force the physical link state by getting the current PHY capabilities from
3660  * hardware and setting the PHY config based on the determined capabilities. If
3661  * link changes, link event will be triggered because both the Enable Automatic
3662  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3663  */
3664 static enum ice_status
3665 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3666 {
3667         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3668         struct ice_aqc_get_phy_caps_data *pcaps;
3669         struct ice_port_info *pi;
3670         enum ice_status status;
3671
3672         if (!hw || !hw->port_info)
3673                 return ICE_ERR_PARAM;
3674
3675         pi = hw->port_info;
3676
3677         pcaps = (struct ice_aqc_get_phy_caps_data *)
3678                 ice_malloc(hw, sizeof(*pcaps));
3679         if (!pcaps)
3680                 return ICE_ERR_NO_MEMORY;
3681
3682         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3683                                      NULL);
3684         if (status)
3685                 goto out;
3686
3687         /* No change in link */
3688         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3689             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3690                 goto out;
3691
3692         cfg.phy_type_low = pcaps->phy_type_low;
3693         cfg.phy_type_high = pcaps->phy_type_high;
3694         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3695         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3696         cfg.eee_cap = pcaps->eee_cap;
3697         cfg.eeer_value = pcaps->eeer_value;
3698         cfg.link_fec_opt = pcaps->link_fec_options;
3699         if (link_up)
3700                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3701         else
3702                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3703
3704         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3705
3706 out:
3707         ice_free(hw, pcaps);
3708         return status;
3709 }
3710
3711 static int
3712 ice_dev_set_link_up(struct rte_eth_dev *dev)
3713 {
3714         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715
3716         return ice_force_phys_link_state(hw, true);
3717 }
3718
3719 static int
3720 ice_dev_set_link_down(struct rte_eth_dev *dev)
3721 {
3722         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723
3724         return ice_force_phys_link_state(hw, false);
3725 }
3726
3727 static int
3728 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3729 {
3730         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3731         struct rte_eth_dev_data *dev_data = pf->dev_data;
3732         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3733
3734         /* check if mtu is within the allowed range */
3735         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3736                 return -EINVAL;
3737
3738         /* mtu setting is forbidden if port is start */
3739         if (dev_data->dev_started) {
3740                 PMD_DRV_LOG(ERR,
3741                             "port %d must be stopped before configuration",
3742                             dev_data->port_id);
3743                 return -EBUSY;
3744         }
3745
3746         if (frame_size > RTE_ETHER_MAX_LEN)
3747                 dev_data->dev_conf.rxmode.offloads |=
3748                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3749         else
3750                 dev_data->dev_conf.rxmode.offloads &=
3751                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3752
3753         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3754
3755         return 0;
3756 }
3757
3758 static int ice_macaddr_set(struct rte_eth_dev *dev,
3759                            struct rte_ether_addr *mac_addr)
3760 {
3761         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3762         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3763         struct ice_vsi *vsi = pf->main_vsi;
3764         struct ice_mac_filter *f;
3765         uint8_t flags = 0;
3766         int ret;
3767
3768         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3769                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3770                 return -EINVAL;
3771         }
3772
3773         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3774                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3775                         break;
3776         }
3777
3778         if (!f) {
3779                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3780                 return -EIO;
3781         }
3782
3783         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3784         if (ret != ICE_SUCCESS) {
3785                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3786                 return -EIO;
3787         }
3788         ret = ice_add_mac_filter(vsi, mac_addr);
3789         if (ret != ICE_SUCCESS) {
3790                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3791                 return -EIO;
3792         }
3793         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3794
3795         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3796         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3797         if (ret != ICE_SUCCESS)
3798                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3799
3800         return 0;
3801 }
3802
3803 /* Add a MAC address, and update filters */
3804 static int
3805 ice_macaddr_add(struct rte_eth_dev *dev,
3806                 struct rte_ether_addr *mac_addr,
3807                 __rte_unused uint32_t index,
3808                 __rte_unused uint32_t pool)
3809 {
3810         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3811         struct ice_vsi *vsi = pf->main_vsi;
3812         int ret;
3813
3814         ret = ice_add_mac_filter(vsi, mac_addr);
3815         if (ret != ICE_SUCCESS) {
3816                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3817                 return -EINVAL;
3818         }
3819
3820         return ICE_SUCCESS;
3821 }
3822
3823 /* Remove a MAC address, and update filters */
3824 static void
3825 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3826 {
3827         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3828         struct ice_vsi *vsi = pf->main_vsi;
3829         struct rte_eth_dev_data *data = dev->data;
3830         struct rte_ether_addr *macaddr;
3831         int ret;
3832
3833         macaddr = &data->mac_addrs[index];
3834         ret = ice_remove_mac_filter(vsi, macaddr);
3835         if (ret) {
3836                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3837                 return;
3838         }
3839 }
3840
3841 static int
3842 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3843 {
3844         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3845         struct ice_vsi *vsi = pf->main_vsi;
3846         int ret;
3847
3848         PMD_INIT_FUNC_TRACE();
3849
3850         if (on) {
3851                 ret = ice_add_vlan_filter(vsi, vlan_id);
3852                 if (ret < 0) {
3853                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3854                         return -EINVAL;
3855                 }
3856         } else {
3857                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3858                 if (ret < 0) {
3859                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3860                         return -EINVAL;
3861                 }
3862         }
3863
3864         return 0;
3865 }
3866
3867 /* Configure vlan filter on or off */
3868 static int
3869 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3870 {
3871         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3872         struct ice_vsi_ctx ctxt;
3873         uint8_t sec_flags, sw_flags2;
3874         int ret = 0;
3875
3876         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3877                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3878         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3879
3880         if (on) {
3881                 vsi->info.sec_flags |= sec_flags;
3882                 vsi->info.sw_flags2 |= sw_flags2;
3883         } else {
3884                 vsi->info.sec_flags &= ~sec_flags;
3885                 vsi->info.sw_flags2 &= ~sw_flags2;
3886         }
3887         vsi->info.sw_id = hw->port_info->sw_id;
3888         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3889         ctxt.info.valid_sections =
3890                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3891                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3892         ctxt.vsi_num = vsi->vsi_id;
3893
3894         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3895         if (ret) {
3896                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3897                             on ? "enable" : "disable");
3898                 return -EINVAL;
3899         } else {
3900                 vsi->info.valid_sections |=
3901                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3902                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3903         }
3904
3905         /* consist with other drivers, allow untagged packet when vlan filter on */
3906         if (on)
3907                 ret = ice_add_vlan_filter(vsi, 0);
3908         else
3909                 ret = ice_remove_vlan_filter(vsi, 0);
3910
3911         return 0;
3912 }
3913
3914 static int
3915 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3916 {
3917         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3918         struct ice_vsi_ctx ctxt;
3919         uint8_t vlan_flags;
3920         int ret = 0;
3921
3922         /* Check if it has been already on or off */
3923         if (vsi->info.valid_sections &
3924                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3925                 if (on) {
3926                         if ((vsi->info.vlan_flags &
3927                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3928                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3929                                 return 0; /* already on */
3930                 } else {
3931                         if ((vsi->info.vlan_flags &
3932                              ICE_AQ_VSI_VLAN_EMOD_M) ==
3933                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3934                                 return 0; /* already off */
3935                 }
3936         }
3937
3938         if (on)
3939                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3940         else
3941                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3942         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3943         vsi->info.vlan_flags |= vlan_flags;
3944         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3945         ctxt.info.valid_sections =
3946                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3947         ctxt.vsi_num = vsi->vsi_id;
3948         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3949         if (ret) {
3950                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3951                             on ? "enable" : "disable");
3952                 return -EINVAL;
3953         }
3954
3955         vsi->info.valid_sections |=
3956                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3957
3958         return ret;
3959 }
3960
3961 static int
3962 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3963 {
3964         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3965         struct ice_vsi *vsi = pf->main_vsi;
3966         struct rte_eth_rxmode *rxmode;
3967
3968         rxmode = &dev->data->dev_conf.rxmode;
3969         if (mask & ETH_VLAN_FILTER_MASK) {
3970                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3971                         ice_vsi_config_vlan_filter(vsi, true);
3972                 else
3973                         ice_vsi_config_vlan_filter(vsi, false);
3974         }
3975
3976         if (mask & ETH_VLAN_STRIP_MASK) {
3977                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3978                         ice_vsi_config_vlan_stripping(vsi, true);
3979                 else
3980                         ice_vsi_config_vlan_stripping(vsi, false);
3981         }
3982
3983         if (mask & ETH_VLAN_EXTEND_MASK) {
3984                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3985                         ice_vsi_config_double_vlan(vsi, true);
3986                 else
3987                         ice_vsi_config_double_vlan(vsi, false);
3988         }
3989
3990         return 0;
3991 }
3992
3993 static int
3994 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3995 {
3996         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3997         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3998         int ret;
3999
4000         if (!lut)
4001                 return -EINVAL;
4002
4003         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4004                 ret = ice_aq_get_rss_lut(hw, vsi->idx,
4005                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4006                 if (ret) {
4007                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4008                         return -EINVAL;
4009                 }
4010         } else {
4011                 uint64_t *lut_dw = (uint64_t *)lut;
4012                 uint16_t i, lut_size_dw = lut_size / 4;
4013
4014                 for (i = 0; i < lut_size_dw; i++)
4015                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4016         }
4017
4018         return 0;
4019 }
4020
4021 static int
4022 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4023 {
4024         struct ice_pf *pf;
4025         struct ice_hw *hw;
4026         int ret;
4027
4028         if (!vsi || !lut)
4029                 return -EINVAL;
4030
4031         pf = ICE_VSI_TO_PF(vsi);
4032         hw = ICE_VSI_TO_HW(vsi);
4033
4034         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4035                 ret = ice_aq_set_rss_lut(hw, vsi->idx,
4036                         ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
4037                 if (ret) {
4038                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4039                         return -EINVAL;
4040                 }
4041         } else {
4042                 uint64_t *lut_dw = (uint64_t *)lut;
4043                 uint16_t i, lut_size_dw = lut_size / 4;
4044
4045                 for (i = 0; i < lut_size_dw; i++)
4046                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4047
4048                 ice_flush(hw);
4049         }
4050
4051         return 0;
4052 }
4053
4054 static int
4055 ice_rss_reta_update(struct rte_eth_dev *dev,
4056                     struct rte_eth_rss_reta_entry64 *reta_conf,
4057                     uint16_t reta_size)
4058 {
4059         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4060         uint16_t i, lut_size = pf->hash_lut_size;
4061         uint16_t idx, shift;
4062         uint8_t *lut;
4063         int ret;
4064
4065         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4066             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4067             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4068                 PMD_DRV_LOG(ERR,
4069                             "The size of hash lookup table configured (%d)"
4070                             "doesn't match the number hardware can "
4071                             "supported (128, 512, 2048)",
4072                             reta_size);
4073                 return -EINVAL;
4074         }
4075
4076         /* It MUST use the current LUT size to get the RSS lookup table,
4077          * otherwise if will fail with -100 error code.
4078          */
4079         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4080         if (!lut) {
4081                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4082                 return -ENOMEM;
4083         }
4084         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4085         if (ret)
4086                 goto out;
4087
4088         for (i = 0; i < reta_size; i++) {
4089                 idx = i / RTE_RETA_GROUP_SIZE;
4090                 shift = i % RTE_RETA_GROUP_SIZE;
4091                 if (reta_conf[idx].mask & (1ULL << shift))
4092                         lut[i] = reta_conf[idx].reta[shift];
4093         }
4094         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4095         if (ret == 0 && lut_size != reta_size) {
4096                 PMD_DRV_LOG(INFO,
4097                             "The size of hash lookup table is changed from (%d) to (%d)",
4098                             lut_size, reta_size);
4099                 pf->hash_lut_size = reta_size;
4100         }
4101
4102 out:
4103         rte_free(lut);
4104
4105         return ret;
4106 }
4107
4108 static int
4109 ice_rss_reta_query(struct rte_eth_dev *dev,
4110                    struct rte_eth_rss_reta_entry64 *reta_conf,
4111                    uint16_t reta_size)
4112 {
4113         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4114         uint16_t i, lut_size = pf->hash_lut_size;
4115         uint16_t idx, shift;
4116         uint8_t *lut;
4117         int ret;
4118
4119         if (reta_size != lut_size) {
4120                 PMD_DRV_LOG(ERR,
4121                             "The size of hash lookup table configured (%d)"
4122                             "doesn't match the number hardware can "
4123                             "supported (%d)",
4124                             reta_size, lut_size);
4125                 return -EINVAL;
4126         }
4127
4128         lut = rte_zmalloc(NULL, reta_size, 0);
4129         if (!lut) {
4130                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4131                 return -ENOMEM;
4132         }
4133
4134         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4135         if (ret)
4136                 goto out;
4137
4138         for (i = 0; i < reta_size; i++) {
4139                 idx = i / RTE_RETA_GROUP_SIZE;
4140                 shift = i % RTE_RETA_GROUP_SIZE;
4141                 if (reta_conf[idx].mask & (1ULL << shift))
4142                         reta_conf[idx].reta[shift] = lut[i];
4143         }
4144
4145 out:
4146         rte_free(lut);
4147
4148         return ret;
4149 }
4150
4151 static int
4152 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4153 {
4154         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4155         int ret = 0;
4156
4157         if (!key || key_len == 0) {
4158                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4159                 return 0;
4160         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4161                    sizeof(uint32_t)) {
4162                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4163                 return -EINVAL;
4164         }
4165
4166         struct ice_aqc_get_set_rss_keys *key_dw =
4167                 (struct ice_aqc_get_set_rss_keys *)key;
4168
4169         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4170         if (ret) {
4171                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4172                 ret = -EINVAL;
4173         }
4174
4175         return ret;
4176 }
4177
4178 static int
4179 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4180 {
4181         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4182         int ret;
4183
4184         if (!key || !key_len)
4185                 return -EINVAL;
4186
4187         ret = ice_aq_get_rss_key
4188                 (hw, vsi->idx,
4189                  (struct ice_aqc_get_set_rss_keys *)key);
4190         if (ret) {
4191                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4192                 return -EINVAL;
4193         }
4194         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4195
4196         return 0;
4197 }
4198
4199 static int
4200 ice_rss_hash_update(struct rte_eth_dev *dev,
4201                     struct rte_eth_rss_conf *rss_conf)
4202 {
4203         enum ice_status status = ICE_SUCCESS;
4204         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4205         struct ice_vsi *vsi = pf->main_vsi;
4206
4207         /* set hash key */
4208         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4209         if (status)
4210                 return status;
4211
4212         if (rss_conf->rss_hf == 0)
4213                 return 0;
4214
4215         /* RSS hash configuration */
4216         ice_rss_hash_set(pf, rss_conf->rss_hf);
4217
4218         return 0;
4219 }
4220
4221 static int
4222 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4223                       struct rte_eth_rss_conf *rss_conf)
4224 {
4225         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4226         struct ice_vsi *vsi = pf->main_vsi;
4227
4228         ice_get_rss_key(vsi, rss_conf->rss_key,
4229                         &rss_conf->rss_key_len);
4230
4231         /* TODO: default set to 0 as hf config is not supported now */
4232         rss_conf->rss_hf = 0;
4233         return 0;
4234 }
4235
4236 static int
4237 ice_promisc_enable(struct rte_eth_dev *dev)
4238 {
4239         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4240         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4241         struct ice_vsi *vsi = pf->main_vsi;
4242         enum ice_status status;
4243         uint8_t pmask;
4244         int ret = 0;
4245
4246         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4247                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4248
4249         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4250         switch (status) {
4251         case ICE_ERR_ALREADY_EXISTS:
4252                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4253         case ICE_SUCCESS:
4254                 break;
4255         default:
4256                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4257                 ret = -EAGAIN;
4258         }
4259
4260         return ret;
4261 }
4262
4263 static int
4264 ice_promisc_disable(struct rte_eth_dev *dev)
4265 {
4266         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4267         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4268         struct ice_vsi *vsi = pf->main_vsi;
4269         enum ice_status status;
4270         uint8_t pmask;
4271         int ret = 0;
4272
4273         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4274                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4275
4276         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4277         if (status != ICE_SUCCESS) {
4278                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4279                 ret = -EAGAIN;
4280         }
4281
4282         return ret;
4283 }
4284
4285 static int
4286 ice_allmulti_enable(struct rte_eth_dev *dev)
4287 {
4288         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4289         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4290         struct ice_vsi *vsi = pf->main_vsi;
4291         enum ice_status status;
4292         uint8_t pmask;
4293         int ret = 0;
4294
4295         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4296
4297         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4298
4299         switch (status) {
4300         case ICE_ERR_ALREADY_EXISTS:
4301                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4302         case ICE_SUCCESS:
4303                 break;
4304         default:
4305                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4306                 ret = -EAGAIN;
4307         }
4308
4309         return ret;
4310 }
4311
4312 static int
4313 ice_allmulti_disable(struct rte_eth_dev *dev)
4314 {
4315         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4316         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4317         struct ice_vsi *vsi = pf->main_vsi;
4318         enum ice_status status;
4319         uint8_t pmask;
4320         int ret = 0;
4321
4322         if (dev->data->promiscuous == 1)
4323                 return 0; /* must remain in all_multicast mode */
4324
4325         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4326
4327         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4328         if (status != ICE_SUCCESS) {
4329                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4330                 ret = -EAGAIN;
4331         }
4332
4333         return ret;
4334 }
4335
4336 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4337                                     uint16_t queue_id)
4338 {
4339         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4341         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t val;
4343         uint16_t msix_intr;
4344
4345         msix_intr = intr_handle->intr_vec[queue_id];
4346
4347         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4348               GLINT_DYN_CTL_ITR_INDX_M;
4349         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4350
4351         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4352         rte_intr_ack(&pci_dev->intr_handle);
4353
4354         return 0;
4355 }
4356
4357 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4358                                      uint16_t queue_id)
4359 {
4360         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4362         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363         uint16_t msix_intr;
4364
4365         msix_intr = intr_handle->intr_vec[queue_id];
4366
4367         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4368
4369         return 0;
4370 }
4371
4372 static int
4373 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4374 {
4375         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376         u8 ver, patch;
4377         u16 build;
4378         int ret;
4379
4380         ver = hw->flash.orom.major;
4381         patch = hw->flash.orom.patch;
4382         build = hw->flash.orom.build;
4383
4384         ret = snprintf(fw_version, fw_size,
4385                         "%x.%02x 0x%08x %d.%d.%d",
4386                         hw->flash.nvm.major,
4387                         hw->flash.nvm.minor,
4388                         hw->flash.nvm.eetrack,
4389                         ver, build, patch);
4390
4391         /* add the size of '\0' */
4392         ret += 1;
4393         if (fw_size < (u32)ret)
4394                 return ret;
4395         else
4396                 return 0;
4397 }
4398
4399 static int
4400 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4401 {
4402         struct ice_hw *hw;
4403         struct ice_vsi_ctx ctxt;
4404         uint8_t vlan_flags = 0;
4405         int ret;
4406
4407         if (!vsi || !info) {
4408                 PMD_DRV_LOG(ERR, "invalid parameters");
4409                 return -EINVAL;
4410         }
4411
4412         if (info->on) {
4413                 vsi->info.pvid = info->config.pvid;
4414                 /**
4415                  * If insert pvid is enabled, only tagged pkts are
4416                  * allowed to be sent out.
4417                  */
4418                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
4419                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4420         } else {
4421                 vsi->info.pvid = 0;
4422                 if (info->config.reject.tagged == 0)
4423                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
4424
4425                 if (info->config.reject.untagged == 0)
4426                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
4427         }
4428         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
4429                                   ICE_AQ_VSI_VLAN_MODE_M);
4430         vsi->info.vlan_flags |= vlan_flags;
4431         memset(&ctxt, 0, sizeof(ctxt));
4432         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4433         ctxt.info.valid_sections =
4434                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4435         ctxt.vsi_num = vsi->vsi_id;
4436
4437         hw = ICE_VSI_TO_HW(vsi);
4438         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4439         if (ret != ICE_SUCCESS) {
4440                 PMD_DRV_LOG(ERR,
4441                             "update VSI for VLAN insert failed, err %d",
4442                             ret);
4443                 return -EINVAL;
4444         }
4445
4446         vsi->info.valid_sections |=
4447                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4448
4449         return ret;
4450 }
4451
4452 static int
4453 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4454 {
4455         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4456         struct ice_vsi *vsi = pf->main_vsi;
4457         struct rte_eth_dev_data *data = pf->dev_data;
4458         struct ice_vsi_vlan_pvid_info info;
4459         int ret;
4460
4461         memset(&info, 0, sizeof(info));
4462         info.on = on;
4463         if (info.on) {
4464                 info.config.pvid = pvid;
4465         } else {
4466                 info.config.reject.tagged =
4467                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4468                 info.config.reject.untagged =
4469                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4470         }
4471
4472         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4473         if (ret < 0) {
4474                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4475                 return -EINVAL;
4476         }
4477
4478         return 0;
4479 }
4480
4481 static int
4482 ice_get_eeprom_length(struct rte_eth_dev *dev)
4483 {
4484         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4485
4486         return hw->flash.flash_size;
4487 }
4488
4489 static int
4490 ice_get_eeprom(struct rte_eth_dev *dev,
4491                struct rte_dev_eeprom_info *eeprom)
4492 {
4493         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4494         enum ice_status status = ICE_SUCCESS;
4495         uint8_t *data = eeprom->data;
4496
4497         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4498
4499         status = ice_acquire_nvm(hw, ICE_RES_READ);
4500         if (status) {
4501                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4502                 return -EIO;
4503         }
4504
4505         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4506                                    data, false);
4507
4508         ice_release_nvm(hw);
4509
4510         if (status) {
4511                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4512                 return -EIO;
4513         }
4514
4515         return 0;
4516 }
4517
4518 static void
4519 ice_stat_update_32(struct ice_hw *hw,
4520                    uint32_t reg,
4521                    bool offset_loaded,
4522                    uint64_t *offset,
4523                    uint64_t *stat)
4524 {
4525         uint64_t new_data;
4526
4527         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4528         if (!offset_loaded)
4529                 *offset = new_data;
4530
4531         if (new_data >= *offset)
4532                 *stat = (uint64_t)(new_data - *offset);
4533         else
4534                 *stat = (uint64_t)((new_data +
4535                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4536                                    - *offset);
4537 }
4538
4539 static void
4540 ice_stat_update_40(struct ice_hw *hw,
4541                    uint32_t hireg,
4542                    uint32_t loreg,
4543                    bool offset_loaded,
4544                    uint64_t *offset,
4545                    uint64_t *stat)
4546 {
4547         uint64_t new_data;
4548
4549         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4550         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4551                     ICE_32_BIT_WIDTH;
4552
4553         if (!offset_loaded)
4554                 *offset = new_data;
4555
4556         if (new_data >= *offset)
4557                 *stat = new_data - *offset;
4558         else
4559                 *stat = (uint64_t)((new_data +
4560                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4561                                    *offset);
4562
4563         *stat &= ICE_40_BIT_MASK;
4564 }
4565
4566 /* Get all the statistics of a VSI */
4567 static void
4568 ice_update_vsi_stats(struct ice_vsi *vsi)
4569 {
4570         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4571         struct ice_eth_stats *nes = &vsi->eth_stats;
4572         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4573         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4574
4575         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4576                            vsi->offset_loaded, &oes->rx_bytes,
4577                            &nes->rx_bytes);
4578         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4579                            vsi->offset_loaded, &oes->rx_unicast,
4580                            &nes->rx_unicast);
4581         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4582                            vsi->offset_loaded, &oes->rx_multicast,
4583                            &nes->rx_multicast);
4584         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4585                            vsi->offset_loaded, &oes->rx_broadcast,
4586                            &nes->rx_broadcast);
4587         /* enlarge the limitation when rx_bytes overflowed */
4588         if (vsi->offset_loaded) {
4589                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4590                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4591                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4592         }
4593         vsi->old_rx_bytes = nes->rx_bytes;
4594         /* exclude CRC bytes */
4595         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4596                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4597
4598         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4599                            &oes->rx_discards, &nes->rx_discards);
4600         /* GLV_REPC not supported */
4601         /* GLV_RMPC not supported */
4602         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4603                            &oes->rx_unknown_protocol,
4604                            &nes->rx_unknown_protocol);
4605         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4606                            vsi->offset_loaded, &oes->tx_bytes,
4607                            &nes->tx_bytes);
4608         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4609                            vsi->offset_loaded, &oes->tx_unicast,
4610                            &nes->tx_unicast);
4611         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4612                            vsi->offset_loaded, &oes->tx_multicast,
4613                            &nes->tx_multicast);
4614         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4615                            vsi->offset_loaded,  &oes->tx_broadcast,
4616                            &nes->tx_broadcast);
4617         /* GLV_TDPC not supported */
4618         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4619                            &oes->tx_errors, &nes->tx_errors);
4620         /* enlarge the limitation when tx_bytes overflowed */
4621         if (vsi->offset_loaded) {
4622                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4623                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4624                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4625         }
4626         vsi->old_tx_bytes = nes->tx_bytes;
4627         vsi->offset_loaded = true;
4628
4629         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4630                     vsi->vsi_id);
4631         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4632         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4633         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4634         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4635         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4636         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4637                     nes->rx_unknown_protocol);
4638         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4639         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4640         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4641         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4642         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4643         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4644         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4645                     vsi->vsi_id);
4646 }
4647
4648 static void
4649 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4650 {
4651         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4652         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4653
4654         /* Get statistics of struct ice_eth_stats */
4655         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4656                            GLPRT_GORCL(hw->port_info->lport),
4657                            pf->offset_loaded, &os->eth.rx_bytes,
4658                            &ns->eth.rx_bytes);
4659         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4660                            GLPRT_UPRCL(hw->port_info->lport),
4661                            pf->offset_loaded, &os->eth.rx_unicast,
4662                            &ns->eth.rx_unicast);
4663         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4664                            GLPRT_MPRCL(hw->port_info->lport),
4665                            pf->offset_loaded, &os->eth.rx_multicast,
4666                            &ns->eth.rx_multicast);
4667         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4668                            GLPRT_BPRCL(hw->port_info->lport),
4669                            pf->offset_loaded, &os->eth.rx_broadcast,
4670                            &ns->eth.rx_broadcast);
4671         ice_stat_update_32(hw, PRTRPB_RDPC,
4672                            pf->offset_loaded, &os->eth.rx_discards,
4673                            &ns->eth.rx_discards);
4674         /* enlarge the limitation when rx_bytes overflowed */
4675         if (pf->offset_loaded) {
4676                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4677                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4678                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4679         }
4680         pf->old_rx_bytes = ns->eth.rx_bytes;
4681
4682         /* Workaround: CRC size should not be included in byte statistics,
4683          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4684          * packet.
4685          */
4686         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4687                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4688
4689         /* GLPRT_REPC not supported */
4690         /* GLPRT_RMPC not supported */
4691         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4692                            pf->offset_loaded,
4693                            &os->eth.rx_unknown_protocol,
4694                            &ns->eth.rx_unknown_protocol);
4695         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4696                            GLPRT_GOTCL(hw->port_info->lport),
4697                            pf->offset_loaded, &os->eth.tx_bytes,
4698                            &ns->eth.tx_bytes);
4699         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4700                            GLPRT_UPTCL(hw->port_info->lport),
4701                            pf->offset_loaded, &os->eth.tx_unicast,
4702                            &ns->eth.tx_unicast);
4703         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4704                            GLPRT_MPTCL(hw->port_info->lport),
4705                            pf->offset_loaded, &os->eth.tx_multicast,
4706                            &ns->eth.tx_multicast);
4707         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4708                            GLPRT_BPTCL(hw->port_info->lport),
4709                            pf->offset_loaded, &os->eth.tx_broadcast,
4710                            &ns->eth.tx_broadcast);
4711         /* enlarge the limitation when tx_bytes overflowed */
4712         if (pf->offset_loaded) {
4713                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4714                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4715                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4716         }
4717         pf->old_tx_bytes = ns->eth.tx_bytes;
4718         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4719                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4720
4721         /* GLPRT_TEPC not supported */
4722
4723         /* additional port specific stats */
4724         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4725                            pf->offset_loaded, &os->tx_dropped_link_down,
4726                            &ns->tx_dropped_link_down);
4727         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4728                            pf->offset_loaded, &os->crc_errors,
4729                            &ns->crc_errors);
4730         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4731                            pf->offset_loaded, &os->illegal_bytes,
4732                            &ns->illegal_bytes);
4733         /* GLPRT_ERRBC not supported */
4734         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4735                            pf->offset_loaded, &os->mac_local_faults,
4736                            &ns->mac_local_faults);
4737         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4738                            pf->offset_loaded, &os->mac_remote_faults,
4739                            &ns->mac_remote_faults);
4740
4741         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4742                            pf->offset_loaded, &os->rx_len_errors,
4743                            &ns->rx_len_errors);
4744
4745         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4746                            pf->offset_loaded, &os->link_xon_rx,
4747                            &ns->link_xon_rx);
4748         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4749                            pf->offset_loaded, &os->link_xoff_rx,
4750                            &ns->link_xoff_rx);
4751         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4752                            pf->offset_loaded, &os->link_xon_tx,
4753                            &ns->link_xon_tx);
4754         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4755                            pf->offset_loaded, &os->link_xoff_tx,
4756                            &ns->link_xoff_tx);
4757         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4758                            GLPRT_PRC64L(hw->port_info->lport),
4759                            pf->offset_loaded, &os->rx_size_64,
4760                            &ns->rx_size_64);
4761         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4762                            GLPRT_PRC127L(hw->port_info->lport),
4763                            pf->offset_loaded, &os->rx_size_127,
4764                            &ns->rx_size_127);
4765         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4766                            GLPRT_PRC255L(hw->port_info->lport),
4767                            pf->offset_loaded, &os->rx_size_255,
4768                            &ns->rx_size_255);
4769         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4770                            GLPRT_PRC511L(hw->port_info->lport),
4771                            pf->offset_loaded, &os->rx_size_511,
4772                            &ns->rx_size_511);
4773         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4774                            GLPRT_PRC1023L(hw->port_info->lport),
4775                            pf->offset_loaded, &os->rx_size_1023,
4776                            &ns->rx_size_1023);
4777         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4778                            GLPRT_PRC1522L(hw->port_info->lport),
4779                            pf->offset_loaded, &os->rx_size_1522,
4780                            &ns->rx_size_1522);
4781         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4782                            GLPRT_PRC9522L(hw->port_info->lport),
4783                            pf->offset_loaded, &os->rx_size_big,
4784                            &ns->rx_size_big);
4785         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4786                            pf->offset_loaded, &os->rx_undersize,
4787                            &ns->rx_undersize);
4788         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4789                            pf->offset_loaded, &os->rx_fragments,
4790                            &ns->rx_fragments);
4791         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4792                            pf->offset_loaded, &os->rx_oversize,
4793                            &ns->rx_oversize);
4794         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4795                            pf->offset_loaded, &os->rx_jabber,
4796                            &ns->rx_jabber);
4797         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4798                            GLPRT_PTC64L(hw->port_info->lport),
4799                            pf->offset_loaded, &os->tx_size_64,
4800                            &ns->tx_size_64);
4801         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4802                            GLPRT_PTC127L(hw->port_info->lport),
4803                            pf->offset_loaded, &os->tx_size_127,
4804                            &ns->tx_size_127);
4805         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4806                            GLPRT_PTC255L(hw->port_info->lport),
4807                            pf->offset_loaded, &os->tx_size_255,
4808                            &ns->tx_size_255);
4809         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4810                            GLPRT_PTC511L(hw->port_info->lport),
4811                            pf->offset_loaded, &os->tx_size_511,
4812                            &ns->tx_size_511);
4813         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4814                            GLPRT_PTC1023L(hw->port_info->lport),
4815                            pf->offset_loaded, &os->tx_size_1023,
4816                            &ns->tx_size_1023);
4817         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4818                            GLPRT_PTC1522L(hw->port_info->lport),
4819                            pf->offset_loaded, &os->tx_size_1522,
4820                            &ns->tx_size_1522);
4821         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4822                            GLPRT_PTC9522L(hw->port_info->lport),
4823                            pf->offset_loaded, &os->tx_size_big,
4824                            &ns->tx_size_big);
4825
4826         /* GLPRT_MSPDC not supported */
4827         /* GLPRT_XEC not supported */
4828
4829         pf->offset_loaded = true;
4830
4831         if (pf->main_vsi)
4832                 ice_update_vsi_stats(pf->main_vsi);
4833 }
4834
4835 /* Get all statistics of a port */
4836 static int
4837 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4838 {
4839         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4840         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4842
4843         /* call read registers - updates values, now write them to struct */
4844         ice_read_stats_registers(pf, hw);
4845
4846         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4847                           pf->main_vsi->eth_stats.rx_multicast +
4848                           pf->main_vsi->eth_stats.rx_broadcast -
4849                           pf->main_vsi->eth_stats.rx_discards;
4850         stats->opackets = ns->eth.tx_unicast +
4851                           ns->eth.tx_multicast +
4852                           ns->eth.tx_broadcast;
4853         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
4854         stats->obytes   = ns->eth.tx_bytes;
4855         stats->oerrors  = ns->eth.tx_errors +
4856                           pf->main_vsi->eth_stats.tx_errors;
4857
4858         /* Rx Errors */
4859         stats->imissed  = ns->eth.rx_discards +
4860                           pf->main_vsi->eth_stats.rx_discards;
4861         stats->ierrors  = ns->crc_errors +
4862                           ns->rx_undersize +
4863                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4864
4865         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4866         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
4867         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4868         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4869         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4870         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4871         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4872                     pf->main_vsi->eth_stats.rx_discards);
4873         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
4874                     ns->eth.rx_unknown_protocol);
4875         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
4876         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4877         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4878         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4879         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4880         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4881                     pf->main_vsi->eth_stats.tx_discards);
4882         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
4883
4884         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
4885                     ns->tx_dropped_link_down);
4886         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4887         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
4888                     ns->illegal_bytes);
4889         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
4890         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
4891                     ns->mac_local_faults);
4892         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
4893                     ns->mac_remote_faults);
4894         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
4895         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
4896         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
4897         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
4898         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
4899         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
4900         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
4901         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
4902         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
4903         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
4904         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
4905         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
4906         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
4907         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
4908         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
4909         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
4910         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
4911         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
4912         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
4913         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
4914         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
4915         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
4916         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
4917         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4918         return 0;
4919 }
4920
4921 /* Reset the statistics */
4922 static int
4923 ice_stats_reset(struct rte_eth_dev *dev)
4924 {
4925         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4926         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4927
4928         /* Mark PF and VSI stats to update the offset, aka "reset" */
4929         pf->offset_loaded = false;
4930         if (pf->main_vsi)
4931                 pf->main_vsi->offset_loaded = false;
4932
4933         /* read the stats, reading current register values into offset */
4934         ice_read_stats_registers(pf, hw);
4935
4936         return 0;
4937 }
4938
4939 static uint32_t
4940 ice_xstats_calc_num(void)
4941 {
4942         uint32_t num;
4943
4944         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4945
4946         return num;
4947 }
4948
4949 static int
4950 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4951                unsigned int n)
4952 {
4953         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4954         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         unsigned int i;
4956         unsigned int count;
4957         struct ice_hw_port_stats *hw_stats = &pf->stats;
4958
4959         count = ice_xstats_calc_num();
4960         if (n < count)
4961                 return count;
4962
4963         ice_read_stats_registers(pf, hw);
4964
4965         if (!xstats)
4966                 return 0;
4967
4968         count = 0;
4969
4970         /* Get stats from ice_eth_stats struct */
4971         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4972                 xstats[count].value =
4973                         *(uint64_t *)((char *)&hw_stats->eth +
4974                                       ice_stats_strings[i].offset);
4975                 xstats[count].id = count;
4976                 count++;
4977         }
4978
4979         /* Get individiual stats from ice_hw_port struct */
4980         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4981                 xstats[count].value =
4982                         *(uint64_t *)((char *)hw_stats +
4983                                       ice_hw_port_strings[i].offset);
4984                 xstats[count].id = count;
4985                 count++;
4986         }
4987
4988         return count;
4989 }
4990
4991 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4992                                 struct rte_eth_xstat_name *xstats_names,
4993                                 __rte_unused unsigned int limit)
4994 {
4995         unsigned int count = 0;
4996         unsigned int i;
4997
4998         if (!xstats_names)
4999                 return ice_xstats_calc_num();
5000
5001         /* Note: limit checked in rte_eth_xstats_names() */
5002
5003         /* Get stats from ice_eth_stats struct */
5004         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5005                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5006                         sizeof(xstats_names[count].name));
5007                 count++;
5008         }
5009
5010         /* Get individiual stats from ice_hw_port struct */
5011         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5012                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5013                         sizeof(xstats_names[count].name));
5014                 count++;
5015         }
5016
5017         return count;
5018 }
5019
5020 static int
5021 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5022                      enum rte_filter_type filter_type,
5023                      enum rte_filter_op filter_op,
5024                      void *arg)
5025 {
5026         int ret = 0;
5027
5028         if (!dev)
5029                 return -EINVAL;
5030
5031         switch (filter_type) {
5032         case RTE_ETH_FILTER_GENERIC:
5033                 if (filter_op != RTE_ETH_FILTER_GET)
5034                         return -EINVAL;
5035                 *(const void **)arg = &ice_flow_ops;
5036                 break;
5037         default:
5038                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5039                                         filter_type);
5040                 ret = -EINVAL;
5041                 break;
5042         }
5043
5044         return ret;
5045 }
5046
5047 /* Add UDP tunneling port */
5048 static int
5049 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5050                              struct rte_eth_udp_tunnel *udp_tunnel)
5051 {
5052         int ret = 0;
5053         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054
5055         if (udp_tunnel == NULL)
5056                 return -EINVAL;
5057
5058         switch (udp_tunnel->prot_type) {
5059         case RTE_TUNNEL_TYPE_VXLAN:
5060                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5061                 break;
5062         default:
5063                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5064                 ret = -EINVAL;
5065                 break;
5066         }
5067
5068         return ret;
5069 }
5070
5071 /* Delete UDP tunneling port */
5072 static int
5073 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5074                              struct rte_eth_udp_tunnel *udp_tunnel)
5075 {
5076         int ret = 0;
5077         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078
5079         if (udp_tunnel == NULL)
5080                 return -EINVAL;
5081
5082         switch (udp_tunnel->prot_type) {
5083         case RTE_TUNNEL_TYPE_VXLAN:
5084                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5085                 break;
5086         default:
5087                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5088                 ret = -EINVAL;
5089                 break;
5090         }
5091
5092         return ret;
5093 }
5094
5095 static int
5096 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5097               struct rte_pci_device *pci_dev)
5098 {
5099         return rte_eth_dev_pci_generic_probe(pci_dev,
5100                                              sizeof(struct ice_adapter),
5101                                              ice_dev_init);
5102 }
5103
5104 static int
5105 ice_pci_remove(struct rte_pci_device *pci_dev)
5106 {
5107         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5108 }
5109
5110 static struct rte_pci_driver rte_ice_pmd = {
5111         .id_table = pci_id_ice_map,
5112         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5113         .probe = ice_pci_probe,
5114         .remove = ice_pci_remove,
5115 };
5116
5117 /**
5118  * Driver initialization routine.
5119  * Invoked once at EAL init time.
5120  * Register itself as the [Poll Mode] Driver of PCI devices.
5121  */
5122 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5123 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5124 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5125 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5126                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5127                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5128                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5129
5130 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5131 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5132 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5133 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5134 #endif
5135 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5136 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5137 #endif
5138 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5139 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5140 #endif