1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include <rte_kvargs.h>
11 #include <ethdev_driver.h>
13 #include "base/ice_common.h"
14 #include "base/ice_adminq_cmd.h"
15 #include "base/ice_flow.h"
17 #define ICE_VLAN_TAG_SIZE 4
19 #define ICE_ADMINQ_LEN 32
20 #define ICE_SBIOQ_LEN 32
21 #define ICE_MAILBOXQ_LEN 32
22 #define ICE_SBQ_LEN 64
23 #define ICE_ADMINQ_BUF_SZ 4096
24 #define ICE_SBIOQ_BUF_SZ 4096
25 #define ICE_MAILBOXQ_BUF_SZ 4096
26 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
27 #define ICE_MAX_Q_PER_TC 64
28 #define ICE_NUM_DESC_DEFAULT 512
29 #define ICE_BUF_SIZE_MIN 1024
30 #define ICE_FRAME_SIZE_MAX 9728
31 #define ICE_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define ICE_MAX_QP_NUM_PER_VF 16
34 #define ICE_DEFAULT_QP_NUM_FDIR 1
35 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define ICE_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define ICE_MAX_VF 128
41 #define ICE_MAX_INTR_QUEUE_NUM 256
43 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
44 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET
46 #define ICE_MAX_PKT_TYPE 1024
48 /* DDP package search path */
49 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
50 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
51 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
52 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
53 #define ICE_MAX_PKG_FILENAME_SIZE 256
55 #define MAX_ACL_NORMAL_ENTRIES 256
58 * vlan_id is a 12 bit number.
59 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
60 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
61 * The higher 7 bit val specifies VFTA array index.
63 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
64 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
66 /* Default TC traffic in case DCB is not enabled */
67 #define ICE_DEFAULT_TCMAP 0x1
68 #define ICE_FDIR_QUEUE_ID 0
70 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
71 #define ICE_VMDQ_POOL_BASE 1
73 #define ICE_DEFAULT_RX_FREE_THRESH 32
74 #define ICE_DEFAULT_RX_PTHRESH 8
75 #define ICE_DEFAULT_RX_HTHRESH 8
76 #define ICE_DEFAULT_RX_WTHRESH 0
78 #define ICE_DEFAULT_TX_FREE_THRESH 32
79 #define ICE_DEFAULT_TX_PTHRESH 32
80 #define ICE_DEFAULT_TX_HTHRESH 0
81 #define ICE_DEFAULT_TX_WTHRESH 0
82 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
84 /* Bit shift and mask */
85 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2)
86 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
87 #define ICE_8_BIT_WIDTH CHAR_BIT
88 #define ICE_8_BIT_MASK UINT8_MAX
89 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
90 #define ICE_16_BIT_MASK UINT16_MAX
91 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
92 #define ICE_32_BIT_MASK UINT32_MAX
93 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
94 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
95 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
96 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
98 #define ICE_FLAG_RSS BIT_ULL(0)
99 #define ICE_FLAG_DCB BIT_ULL(1)
100 #define ICE_FLAG_VMDQ BIT_ULL(2)
101 #define ICE_FLAG_SRIOV BIT_ULL(3)
102 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
103 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
104 #define ICE_FLAG_FDIR BIT_ULL(6)
105 #define ICE_FLAG_VXLAN BIT_ULL(7)
106 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
107 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
108 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \
112 ICE_FLAG_HEADER_SPLIT_DISABLED | \
113 ICE_FLAG_HEADER_SPLIT_ENABLED | \
116 ICE_FLAG_RSS_AQ_CAPABLE | \
117 ICE_FLAG_VF_MAC_BY_PF)
119 #define ICE_RSS_OFFLOAD_ALL ( \
121 RTE_ETH_RSS_FRAG_IPV4 | \
122 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
123 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
124 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
125 RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
127 RTE_ETH_RSS_FRAG_IPV6 | \
128 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
129 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
130 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
131 RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
132 RTE_ETH_RSS_L2_PAYLOAD)
135 * The overhead from MTU to max frame size.
136 * Considering QinQ packet, the VLAN tag needs to be counted twice.
138 #define ICE_ETH_OVERHEAD \
139 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
140 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
142 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
143 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
145 /* Max number of flexible descriptor rxdid */
146 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64
148 /* Per-channel register definitions */
149 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
150 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
151 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
152 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
154 /* DDP package type */
156 ICE_PKG_TYPE_UNKNOWN,
157 ICE_PKG_TYPE_OS_DEFAULT,
170 * MAC filter structure
172 struct ice_mac_filter_info {
173 struct rte_ether_addr mac_addr;
176 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
178 /* MAC filter list structure */
179 struct ice_mac_filter {
180 TAILQ_ENTRY(ice_mac_filter) next;
181 struct ice_mac_filter_info mac_info;
189 #define ICE_VLAN(tpid, vid) \
190 ((struct ice_vlan){ tpid, vid })
193 * VLAN filter structure
195 struct ice_vlan_filter_info {
196 struct ice_vlan vlan;
199 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
201 /* VLAN filter list structure */
202 struct ice_vlan_filter {
203 TAILQ_ENTRY(ice_vlan_filter) next;
204 struct ice_vlan_filter_info vlan_info;
208 LIST_ENTRY(pool_entry) next;
213 LIST_HEAD(res_list, pool_entry);
215 struct ice_res_pool_info {
216 uint32_t base; /* Resource start index */
217 uint32_t num_alloc; /* Allocated resource number */
218 uint32_t num_free; /* Total available resource number */
219 struct res_list alloc_list; /* Allocated resource list */
220 struct res_list free_list; /* Available resource list */
223 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
227 /* VSI list structure */
228 struct ice_vsi_list {
229 TAILQ_ENTRY(ice_vsi_list) list;
237 * Structure that defines a VSI, associated with a adapter.
240 struct ice_adapter *adapter; /* Backreference to associated adapter */
241 struct ice_aqc_vsi_props info; /* VSI properties */
243 * When drivers loaded, only a default main VSI exists. In case new VSI
244 * needs to add, HW needs to know the layout that VSIs are organized.
245 * Besides that, VSI isan element and can't switch packets, which needs
246 * to add new component VEB to perform switching. So, a new VSI needs
247 * to specify the the uplink VSI (Parent VSI) before created. The
248 * uplink VSI will check whether it had a VEB to switch packets. If no,
249 * it will try to create one. Then, uplink VSI will move the new VSI
250 * into its' sib_vsi_list to manage all the downlink VSI.
251 * sib_vsi_list: the VSI list that shared the same uplink VSI.
252 * parent_vsi : the uplink VSI. It's NULL for main VSI.
253 * veb : the VEB associates with the VSI.
255 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
256 struct ice_vsi *parent_vsi;
257 enum ice_vsi_type type; /* VSI types */
258 uint16_t vlan_num; /* Total VLAN number */
259 uint16_t mac_num; /* Total mac number */
260 struct ice_mac_filter_list mac_list; /* macvlan filter list */
261 struct ice_vlan_filter_list vlan_list; /* vlan filter list */
262 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
263 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
264 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
265 uint16_t base_queue; /* The first queue index of this VSI */
266 uint16_t vsi_id; /* Hardware Id */
267 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */
268 /* VF number to which the VSI connects, valid when VSI is VF type */
270 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
271 uint16_t nb_msix; /* The max number of msix vector */
272 uint8_t enabled_tc; /* The traffic class enabled */
273 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
274 uint8_t vlan_filter_on; /* The VLAN filter enabled */
275 /* information about rss configuration */
280 struct ice_eth_stats eth_stats_offset;
281 struct ice_eth_stats eth_stats;
283 uint64_t old_rx_bytes;
284 uint64_t old_tx_bytes;
287 enum proto_xtr_type {
295 PROTO_XTR_MAX /* The last one */
298 enum ice_fdir_tunnel_type {
299 ICE_FDIR_TUNNEL_TYPE_NONE = 0,
300 ICE_FDIR_TUNNEL_TYPE_VXLAN,
301 ICE_FDIR_TUNNEL_TYPE_GTPU,
302 ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
306 TAILQ_HEAD(ice_flow_list, rte_flow);
308 struct ice_flow_parser_node;
309 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
311 struct ice_fdir_filter_conf {
312 struct ice_fdir_fltr input;
313 enum ice_fdir_tunnel_type tunnel_type;
315 struct ice_fdir_counter *counter; /* flow specific counter context */
316 struct rte_flow_action_count act_count;
318 uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */
319 uint64_t input_set_i; /* only for tunnel inner fields */
323 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
325 struct ice_fdir_fltr_pattern {
326 enum ice_fltr_ptype flow_type;
329 struct ice_fdir_v4 v4;
330 struct ice_fdir_v6 v6;
333 struct ice_fdir_udp_gtp gtpu_data;
334 struct ice_fdir_udp_gtp gtpu_mask;
336 struct ice_fdir_extra ext_data;
337 struct ice_fdir_extra ext_mask;
339 enum ice_fdir_tunnel_type tunnel_type;
342 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
343 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
344 #define ICE_FDIR_COUNTERS_PER_BLOCK 256
345 #define ICE_FDIR_COUNTER_INDEX(base_idx) \
346 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
347 struct ice_fdir_counter_pool;
349 struct ice_fdir_counter {
350 TAILQ_ENTRY(ice_fdir_counter) next;
351 struct ice_fdir_counter_pool *pool;
360 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
362 struct ice_fdir_counter_pool {
363 TAILQ_ENTRY(ice_fdir_counter_pool) next;
364 struct ice_fdir_counter_list counter_list;
365 struct ice_fdir_counter counters[0];
368 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
370 struct ice_fdir_counter_pool_container {
371 struct ice_fdir_counter_pool_list pool_list;
372 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
377 * A structure used to define fields of a FDIR related info.
379 struct ice_fdir_info {
380 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */
381 struct ice_tx_queue *txq;
382 struct ice_rx_queue *rxq;
383 void *prg_pkt; /* memory for fdir program packet */
384 uint64_t dma_addr; /* physic address of packet memory*/
385 const struct rte_memzone *mz;
386 struct ice_fdir_filter_conf conf;
388 struct ice_fdir_filter_conf **hash_map;
389 struct rte_hash *hash_table;
391 struct ice_fdir_counter_pool_container counter;
394 #define ICE_HASH_GTPU_CTX_EH_IP 0
395 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
396 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
397 #define ICE_HASH_GTPU_CTX_UP_IP 3
398 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
399 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
400 #define ICE_HASH_GTPU_CTX_DW_IP 6
401 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
402 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
403 #define ICE_HASH_GTPU_CTX_MAX 9
405 struct ice_hash_gtpu_ctx {
406 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
409 struct ice_hash_ctx {
410 struct ice_hash_gtpu_ctx gtpu4;
411 struct ice_hash_gtpu_ctx gtpu6;
414 struct ice_acl_conf {
415 struct ice_fdir_fltr input;
420 * A structure used to define fields of ACL related info.
422 struct ice_acl_info {
423 struct ice_acl_conf conf;
424 struct rte_bitmap *slots;
425 uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES];
429 struct ice_adapter *adapter; /* The adapter this PF associate to */
430 struct ice_vsi *main_vsi; /* pointer to main VSI structure */
431 /* Used for next free software vsi idx.
432 * To save the effort, we don't recycle the index.
433 * Suppose the indexes are more than enough.
435 uint16_t next_vsi_idx;
436 uint16_t vsis_allocated;
437 uint16_t vsis_unallocated;
438 struct ice_res_pool_info qp_pool; /*Queue pair pool */
439 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
440 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
441 struct rte_ether_addr dev_addr; /* PF device mac address */
442 uint64_t flags; /* PF feature flags */
443 uint16_t hash_lut_size; /* The size of hash lookup table */
444 uint16_t lan_nb_qp_max;
445 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
446 uint16_t base_queue; /* The base queue pairs index in the device */
447 uint8_t *proto_xtr; /* Protocol extraction type for all queues */
448 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
449 uint16_t fdir_qp_offset;
450 struct ice_fdir_info fdir; /* flow director info */
451 struct ice_acl_info acl; /* ACL info */
452 struct ice_hash_ctx hash_ctx;
453 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
454 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
455 struct ice_hw_port_stats stats_offset;
456 struct ice_hw_port_stats stats;
457 /* internal packet statistics, it should be excluded from the total */
458 struct ice_eth_stats internal_stats_offset;
459 struct ice_eth_stats internal_stats;
461 bool adapter_stopped;
462 struct ice_flow_list flow_list;
463 rte_spinlock_t flow_ops_lock;
464 struct ice_parser_list rss_parser_list;
465 struct ice_parser_list perm_parser_list;
466 struct ice_parser_list dist_parser_list;
468 uint64_t old_rx_bytes;
469 uint64_t old_tx_bytes;
470 uint64_t supported_rxdid; /* bitmap for supported RXDID */
474 #define ICE_MAX_QUEUE_NUM 2048
475 #define ICE_MAX_PIN_NUM 4
478 * Cache devargs parse result.
482 int safe_mode_support;
483 uint8_t proto_xtr_dflt;
484 int pipe_mode_support;
485 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
491 * Structure to store private data for each PF/VF instance.
494 /* Common for both PF and VF */
497 bool rx_bulk_alloc_allowed;
500 bool tx_simple_allowed;
501 /* ptype mapping table */
502 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
504 struct ice_devargs devargs;
505 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
506 uint16_t fdir_ref_cnt;
508 struct rte_timecounter systime_tc;
509 struct rte_timecounter rx_tstamp_tc;
510 struct rte_timecounter tx_tstamp_tc;
521 struct ice_vsi_vlan_pvid_info {
522 uint16_t on; /* Enable or disable pvid */
524 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
526 /* Valid in case 'on' is cleared. 'tagged' will reject
527 * tagged packets, while 'untagged' will reject
536 #define ICE_DEV_TO_PCI(eth_dev) \
537 RTE_DEV_TO_PCI((eth_dev)->device)
539 /* ICE_DEV_PRIVATE_TO */
540 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
541 (&((struct ice_adapter *)adapter)->pf)
542 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
543 (&((struct ice_adapter *)adapter)->hw)
544 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
545 ((struct ice_adapter *)adapter)
548 #define ICE_VSI_TO_HW(vsi) \
549 (&(((struct ice_vsi *)vsi)->adapter->hw))
550 #define ICE_VSI_TO_PF(vsi) \
551 (&(((struct ice_vsi *)vsi)->adapter->pf))
554 #define ICE_PF_TO_HW(pf) \
555 (&(((struct ice_pf *)pf)->adapter->hw))
556 #define ICE_PF_TO_ADAPTER(pf) \
557 ((struct ice_adapter *)(pf)->adapter)
558 #define ICE_PF_TO_ETH_DEV(pf) \
559 (((struct ice_pf *)pf)->adapter->eth_dev)
562 ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn);
564 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
566 ice_release_vsi(struct ice_vsi *vsi);
567 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
568 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
569 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
570 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
571 struct ice_rss_hash_cfg *cfg);
572 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
573 struct ice_rss_hash_cfg *cfg);
576 ice_align_floor(int n)
580 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
583 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
584 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
585 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
586 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
587 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
588 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
589 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
590 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
591 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
592 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
593 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
594 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
595 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
596 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
597 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
598 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
600 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
601 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
602 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
603 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
604 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
605 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
606 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
607 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
608 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
609 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
610 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
611 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
612 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
613 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
615 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
616 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
617 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
618 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
619 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
620 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
622 #endif /* _ICE_ETHDEV_H_ */