drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
  11
  12 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  13                 PKT_TX_IP_CKSUM |                \
  14                 PKT_TX_L4_MASK |                 \
  15                 PKT_TX_TCP_SEG |                 \
  16                 PKT_TX_OUTER_IP_CKSUM)
  17
  18 #define ICE_RX_ERR_BITS 0x3f
  19
  20 static enum ice_status
  21 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  22 {
  23         struct ice_vsi *vsi = rxq->vsi;
  24         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  25         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  26         struct ice_rlan_ctx rx_ctx;
  27         enum ice_status err;
  28         uint16_t buf_size, len;
  29         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  30         uint32_t regval;
  31
  32         /**
  33          * The kernel driver uses flex descriptor. It sets the register
  34          * to flex descriptor mode.
  35          * DPDK uses legacy descriptor. It should set the register back
  36          * to the default value, then uses legacy descriptor mode.
  37          */
  38         regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
  39                  QRXFLXP_CNTXT_RXDID_PRIO_M;
  40         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
  41
  42         /* Set buffer size as the head split is disabled. */
  43         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  44                               RTE_PKTMBUF_HEADROOM);
  45         rxq->rx_hdr_len = 0;
  46         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  47         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  48         rxq->max_pkt_len = RTE_MIN(len,
  49                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  50
  51         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  52                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
  53                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  54                         PMD_DRV_LOG(ERR, "maximum packet length must "
  55                                     "be larger than %u and smaller than %u,"
  56                                     "as jumbo frame is enabled",
  57                                     (uint32_t)ETHER_MAX_LEN,
  58                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  59                         return -EINVAL;
  60                 }
  61         } else {
  62                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
  63                     rxq->max_pkt_len > ETHER_MAX_LEN) {
  64                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  65                                     "larger than %u and smaller than %u, "
  66                                     "as jumbo frame is disabled",
  67                                     (uint32_t)ETHER_MIN_LEN,
  68                                     (uint32_t)ETHER_MAX_LEN);
  69                         return -EINVAL;
  70                 }
  71         }
  72
  73         memset(&rx_ctx, 0, sizeof(rx_ctx));
  74
  75         rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
  76         rx_ctx.qlen = rxq->nb_rx_desc;
  77         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  78         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  79         rx_ctx.dtype = 0; /* No Header Split mode */
  80 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  81         rx_ctx.dsize = 1; /* 32B descriptors */
  82 #endif
  83         rx_ctx.rxmax = rxq->max_pkt_len;
  84         /* TPH: Transaction Layer Packet (TLP) processing hints */
  85         rx_ctx.tphrdesc_ena = 1;
  86         rx_ctx.tphwdesc_ena = 1;
  87         rx_ctx.tphdata_ena = 1;
  88         rx_ctx.tphhead_ena = 1;
  89         /* Low Receive Queue Threshold defined in 64 descriptors units.
  90          * When the number of free descriptors goes below the lrxqthresh,
  91          * an immediate interrupt is triggered.
  92          */
  93         rx_ctx.lrxqthresh = 2;
  94         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
  95         rx_ctx.l2tsel = 1;
  96         rx_ctx.showiv = 0;
  97
  98         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
  99         if (err) {
 100                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 101                             rxq->queue_id);
 102                 return -EINVAL;
 103         }
 104         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 105         if (err) {
 106                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 107                             rxq->queue_id);
 108                 return -EINVAL;
 109         }
 110
 111         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 112                               RTE_PKTMBUF_HEADROOM);
 113
 114         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 115
 116         /* Init the Rx tail register*/
 117         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 118
 119         return 0;
 120 }
 121
 122 /* Allocate mbufs for all descriptors in rx queue */
 123 static int
 124 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 125 {
 126         struct ice_rx_entry *rxe = rxq->sw_ring;
 127         uint64_t dma_addr;
 128         uint16_t i;
 129
 130         for (i = 0; i < rxq->nb_rx_desc; i++) {
 131                 volatile union ice_rx_desc *rxd;
 132                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 133
 134                 if (unlikely(!mbuf)) {
 135                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 136                         return -ENOMEM;
 137                 }
 138
 139                 rte_mbuf_refcnt_set(mbuf, 1);
 140                 mbuf->next = NULL;
 141                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 142                 mbuf->nb_segs = 1;
 143                 mbuf->port = rxq->port_id;
 144
 145                 dma_addr =
 146                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 147
 148                 rxd = &rxq->rx_ring[i];
 149                 rxd->read.pkt_addr = dma_addr;
 150                 rxd->read.hdr_addr = 0;
 151 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 152                 rxd->read.rsvd1 = 0;
 153                 rxd->read.rsvd2 = 0;
 154 #endif
 155                 rxe[i].mbuf = mbuf;
 156         }
 157
 158         return 0;
 159 }
 160
 161 /* Free all mbufs for descriptors in rx queue */
 162 static void
 163 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 164 {
 165         uint16_t i;
 166
 167         if (!rxq || !rxq->sw_ring) {
 168                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 169                 return;
 170         }
 171
 172         for (i = 0; i < rxq->nb_rx_desc; i++) {
 173                 if (rxq->sw_ring[i].mbuf) {
 174                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 175                         rxq->sw_ring[i].mbuf = NULL;
 176                 }
 177         }
 178 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 179                 if (rxq->rx_nb_avail == 0)
 180                         return;
 181                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 182                         struct rte_mbuf *mbuf;
 183
 184                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 185                         rte_pktmbuf_free_seg(mbuf);
 186                 }
 187                 rxq->rx_nb_avail = 0;
 188 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 189 }
 190
 191 /* turn on or off rx queue
 192  * @q_idx: queue index in pf scope
 193  * @on: turn on or off the queue
 194  */
 195 static int
 196 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 197 {
 198         uint32_t reg;
 199         uint16_t j;
 200
 201         /* QRX_CTRL = QRX_ENA */
 202         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 203
 204         if (on) {
 205                 if (reg & QRX_CTRL_QENA_STAT_M)
 206                         return 0; /* Already on, skip */
 207                 reg |= QRX_CTRL_QENA_REQ_M;
 208         } else {
 209                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 210                         return 0; /* Already off, skip */
 211                 reg &= ~QRX_CTRL_QENA_REQ_M;
 212         }
 213
 214         /* Write the register */
 215         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 216         /* Check the result. It is said that QENA_STAT
 217          * follows the QENA_REQ not more than 10 use.
 218          * TODO: need to change the wait counter later
 219          */
 220         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 221                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 222                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 223                 if (on) {
 224                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 225                             (reg & QRX_CTRL_QENA_STAT_M))
 226                                 break;
 227                 } else {
 228                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 229                             !(reg & QRX_CTRL_QENA_STAT_M))
 230                                 break;
 231                 }
 232         }
 233
 234         /* Check if it is timeout */
 235         if (j >= ICE_CHK_Q_ENA_COUNT) {
 236                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 237                             (on ? "enable" : "disable"), q_idx);
 238                 return -ETIMEDOUT;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static inline int
 245 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 246 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 247 #else
 248 ice_check_rx_burst_bulk_alloc_preconditions
 249         (__rte_unused struct ice_rx_queue *rxq)
 250 #endif
 251 {
 252         int ret = 0;
 253
 254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 255         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 256                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 257                              "rxq->rx_free_thresh=%d, "
 258                              "ICE_RX_MAX_BURST=%d",
 259                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 260                 ret = -EINVAL;
 261         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 262                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 263                              "rxq->rx_free_thresh=%d, "
 264                              "rxq->nb_rx_desc=%d",
 265                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 266                 ret = -EINVAL;
 267         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 268                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 269                              "rxq->nb_rx_desc=%d, "
 270                              "rxq->rx_free_thresh=%d",
 271                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 272                 ret = -EINVAL;
 273         }
 274 #else
 275         ret = -EINVAL;
 276 #endif
 277
 278         return ret;
 279 }
 280
 281 /* reset fields in ice_rx_queue back to default */
 282 static void
 283 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 284 {
 285         unsigned int i;
 286         uint16_t len;
 287
 288         if (!rxq) {
 289                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 290                 return;
 291         }
 292
 293 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 294         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 295                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 296         else
 297 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 298                 len = rxq->nb_rx_desc;
 299
 300         for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
 301                 ((volatile char *)rxq->rx_ring)[i] = 0;
 302
 303 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 304         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 305         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 306                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 307
 308         rxq->rx_nb_avail = 0;
 309         rxq->rx_next_avail = 0;
 310         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 311 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 312
 313         rxq->rx_tail = 0;
 314         rxq->nb_rx_hold = 0;
 315         rxq->pkt_first_seg = NULL;
 316         rxq->pkt_last_seg = NULL;
 317 }
 318
 319 int
 320 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 321 {
 322         struct ice_rx_queue *rxq;
 323         int err;
 324         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 325
 326         PMD_INIT_FUNC_TRACE();
 327
 328         if (rx_queue_id >= dev->data->nb_rx_queues) {
 329                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 330                             rx_queue_id, dev->data->nb_rx_queues);
 331                 return -EINVAL;
 332         }
 333
 334         rxq = dev->data->rx_queues[rx_queue_id];
 335         if (!rxq || !rxq->q_set) {
 336                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 337                             rx_queue_id);
 338                 return -EINVAL;
 339         }
 340
 341         err = ice_program_hw_rx_queue(rxq);
 342         if (err) {
 343                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 344                             rx_queue_id);
 345                 return -EIO;
 346         }
 347
 348         err = ice_alloc_rx_queue_mbufs(rxq);
 349         if (err) {
 350                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 351                 return -ENOMEM;
 352         }
 353
 354         rte_wmb();
 355
 356         /* Init the RX tail register. */
 357         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 358
 359         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 360         if (err) {
 361                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 362                             rx_queue_id);
 363
 364                 ice_rx_queue_release_mbufs(rxq);
 365                 ice_reset_rx_queue(rxq);
 366                 return -EINVAL;
 367         }
 368
 369         dev->data->rx_queue_state[rx_queue_id] =
 370                 RTE_ETH_QUEUE_STATE_STARTED;
 371
 372         return 0;
 373 }
 374
 375 int
 376 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 377 {
 378         struct ice_rx_queue *rxq;
 379         int err;
 380         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 381
 382         if (rx_queue_id < dev->data->nb_rx_queues) {
 383                 rxq = dev->data->rx_queues[rx_queue_id];
 384
 385                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 386                 if (err) {
 387                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 388                                     rx_queue_id);
 389                         return -EINVAL;
 390                 }
 391                 ice_rx_queue_release_mbufs(rxq);
 392                 ice_reset_rx_queue(rxq);
 393                 dev->data->rx_queue_state[rx_queue_id] =
 394                         RTE_ETH_QUEUE_STATE_STOPPED;
 395         }
 396
 397         return 0;
 398 }
 399
 400 int
 401 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 402 {
 403         struct ice_tx_queue *txq;
 404         int err;
 405         struct ice_vsi *vsi;
 406         struct ice_hw *hw;
 407         struct ice_aqc_add_tx_qgrp txq_elem;
 408         struct ice_tlan_ctx tx_ctx;
 409
 410         PMD_INIT_FUNC_TRACE();
 411
 412         if (tx_queue_id >= dev->data->nb_tx_queues) {
 413                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 414                             tx_queue_id, dev->data->nb_tx_queues);
 415                 return -EINVAL;
 416         }
 417
 418         txq = dev->data->tx_queues[tx_queue_id];
 419         if (!txq || !txq->q_set) {
 420                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 421                             tx_queue_id);
 422                 return -EINVAL;
 423         }
 424
 425         vsi = txq->vsi;
 426         hw = ICE_VSI_TO_HW(vsi);
 427
 428         memset(&txq_elem, 0, sizeof(txq_elem));
 429         memset(&tx_ctx, 0, sizeof(tx_ctx));
 430         txq_elem.num_txqs = 1;
 431         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 432
 433         tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
 434         tx_ctx.qlen = txq->nb_tx_desc;
 435         tx_ctx.pf_num = hw->pf_id;
 436         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 437         tx_ctx.src_vsi = vsi->vsi_id;
 438         tx_ctx.port_num = hw->port_info->lport;
 439         tx_ctx.tso_ena = 1; /* tso enable */
 440         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 441         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 442
 443         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 444                     ice_tlan_ctx_info);
 445
 446         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 447
 448         /* Init the Tx tail register*/
 449         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 450
 451         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, 1, &txq_elem,
 452                               sizeof(txq_elem), NULL);
 453         if (err) {
 454                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 455                 return -EIO;
 456         }
 457         /* store the schedule node id */
 458         txq->q_teid = txq_elem.txqs[0].q_teid;
 459
 460         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 461         return 0;
 462 }
 463
 464 /* Free all mbufs for descriptors in tx queue */
 465 static void
 466 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 467 {
 468         uint16_t i;
 469
 470         if (!txq || !txq->sw_ring) {
 471                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 472                 return;
 473         }
 474
 475         for (i = 0; i < txq->nb_tx_desc; i++) {
 476                 if (txq->sw_ring[i].mbuf) {
 477                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 478                         txq->sw_ring[i].mbuf = NULL;
 479                 }
 480         }
 481 }
 482
 483 static void
 484 ice_reset_tx_queue(struct ice_tx_queue *txq)
 485 {
 486         struct ice_tx_entry *txe;
 487         uint16_t i, prev, size;
 488
 489         if (!txq) {
 490                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 491                 return;
 492         }
 493
 494         txe = txq->sw_ring;
 495         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 496         for (i = 0; i < size; i++)
 497                 ((volatile char *)txq->tx_ring)[i] = 0;
 498
 499         prev = (uint16_t)(txq->nb_tx_desc - 1);
 500         for (i = 0; i < txq->nb_tx_desc; i++) {
 501                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 502
 503                 txd->cmd_type_offset_bsz =
 504                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 505                 txe[i].mbuf =  NULL;
 506                 txe[i].last_id = i;
 507                 txe[prev].next_id = i;
 508                 prev = i;
 509         }
 510
 511         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 512         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 513
 514         txq->tx_tail = 0;
 515         txq->nb_tx_used = 0;
 516
 517         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 518         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 519 }
 520
 521 int
 522 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 523 {
 524         struct ice_tx_queue *txq;
 525         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 526         enum ice_status status;
 527         uint16_t q_ids[1];
 528         uint32_t q_teids[1];
 529
 530         if (tx_queue_id >= dev->data->nb_tx_queues) {
 531                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 532                             tx_queue_id, dev->data->nb_tx_queues);
 533                 return -EINVAL;
 534         }
 535
 536         txq = dev->data->tx_queues[tx_queue_id];
 537         if (!txq) {
 538                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 539                             tx_queue_id);
 540                 return -EINVAL;
 541         }
 542
 543         q_ids[0] = txq->reg_idx;
 544         q_teids[0] = txq->q_teid;
 545
 546         status = ice_dis_vsi_txq(hw->port_info, 1, q_ids, q_teids,
 547                                  ICE_NO_RESET, 0, NULL);
 548         if (status != ICE_SUCCESS) {
 549                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 550                 return -EINVAL;
 551         }
 552
 553         ice_tx_queue_release_mbufs(txq);
 554         ice_reset_tx_queue(txq);
 555         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 556
 557         return 0;
 558 }
 559
 560 int
 561 ice_rx_queue_setup(struct rte_eth_dev *dev,
 562                    uint16_t queue_idx,
 563                    uint16_t nb_desc,
 564                    unsigned int socket_id,
 565                    const struct rte_eth_rxconf *rx_conf,
 566                    struct rte_mempool *mp)
 567 {
 568         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 569         struct ice_adapter *ad =
 570                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 571         struct ice_vsi *vsi = pf->main_vsi;
 572         struct ice_rx_queue *rxq;
 573         const struct rte_memzone *rz;
 574         uint32_t ring_size;
 575         uint16_t len;
 576         int use_def_burst_func = 1;
 577
 578         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 579             nb_desc > ICE_MAX_RING_DESC ||
 580             nb_desc < ICE_MIN_RING_DESC) {
 581                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 582                              "invalid", nb_desc);
 583                 return -EINVAL;
 584         }
 585
 586         /* Free memory if needed */
 587         if (dev->data->rx_queues[queue_idx]) {
 588                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 589                 dev->data->rx_queues[queue_idx] = NULL;
 590         }
 591
 592         /* Allocate the rx queue data structure */
 593         rxq = rte_zmalloc_socket(NULL,
 594                                  sizeof(struct ice_rx_queue),
 595                                  RTE_CACHE_LINE_SIZE,
 596                                  socket_id);
 597         if (!rxq) {
 598                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 599                              "rx queue data structure");
 600                 return -ENOMEM;
 601         }
 602         rxq->mp = mp;
 603         rxq->nb_rx_desc = nb_desc;
 604         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 605         rxq->queue_id = queue_idx;
 606
 607         rxq->reg_idx = vsi->base_queue + queue_idx;
 608         rxq->port_id = dev->data->port_id;
 609         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 610                 rxq->crc_len = ETHER_CRC_LEN;
 611         else
 612                 rxq->crc_len = 0;
 613
 614         rxq->drop_en = rx_conf->rx_drop_en;
 615         rxq->vsi = vsi;
 616         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 617
 618         /* Allocate the maximun number of RX ring hardware descriptor. */
 619         len = ICE_MAX_RING_DESC;
 620
 621 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 622         /**
 623          * Allocating a little more memory because vectorized/bulk_alloc Rx
 624          * functions doesn't check boundaries each time.
 625          */
 626         len += ICE_RX_MAX_BURST;
 627 #endif
 628
 629         /* Allocate the maximum number of RX ring hardware descriptor. */
 630         ring_size = sizeof(union ice_rx_desc) * len;
 631         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 632         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 633                                       ring_size, ICE_RING_BASE_ALIGN,
 634                                       socket_id);
 635         if (!rz) {
 636                 ice_rx_queue_release(rxq);
 637                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 638                 return -ENOMEM;
 639         }
 640
 641         /* Zero all the descriptors in the ring. */
 642         memset(rz->addr, 0, ring_size);
 643
 644         rxq->rx_ring_phys_addr = rz->phys_addr;
 645         rxq->rx_ring = (union ice_rx_desc *)rz->addr;
 646
 647 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 648         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 649 #else
 650         len = nb_desc;
 651 #endif
 652
 653         /* Allocate the software ring. */
 654         rxq->sw_ring = rte_zmalloc_socket(NULL,
 655                                           sizeof(struct ice_rx_entry) * len,
 656                                           RTE_CACHE_LINE_SIZE,
 657                                           socket_id);
 658         if (!rxq->sw_ring) {
 659                 ice_rx_queue_release(rxq);
 660                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 661                 return -ENOMEM;
 662         }
 663
 664         ice_reset_rx_queue(rxq);
 665         rxq->q_set = TRUE;
 666         dev->data->rx_queues[queue_idx] = rxq;
 667
 668         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 669
 670         if (!use_def_burst_func) {
 671 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 672                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 673                              "satisfied. Rx Burst Bulk Alloc function will be "
 674                              "used on port=%d, queue=%d.",
 675                              rxq->port_id, rxq->queue_id);
 676 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 677         } else {
 678                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 679                              "not satisfied, Scattered Rx is requested, "
 680                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 681                              "not enabled on port=%d, queue=%d.",
 682                              rxq->port_id, rxq->queue_id);
 683                 ad->rx_bulk_alloc_allowed = false;
 684         }
 685
 686         return 0;
 687 }
 688
 689 void
 690 ice_rx_queue_release(void *rxq)
 691 {
 692         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 693
 694         if (!q) {
 695                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 696                 return;
 697         }
 698
 699         ice_rx_queue_release_mbufs(q);
 700         rte_free(q->sw_ring);
 701         rte_free(q);
 702 }
 703
 704 int
 705 ice_tx_queue_setup(struct rte_eth_dev *dev,
 706                    uint16_t queue_idx,
 707                    uint16_t nb_desc,
 708                    unsigned int socket_id,
 709                    const struct rte_eth_txconf *tx_conf)
 710 {
 711         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 712         struct ice_vsi *vsi = pf->main_vsi;
 713         struct ice_tx_queue *txq;
 714         const struct rte_memzone *tz;
 715         uint32_t ring_size;
 716         uint16_t tx_rs_thresh, tx_free_thresh;
 717         uint64_t offloads;
 718
 719         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 720
 721         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 722             nb_desc > ICE_MAX_RING_DESC ||
 723             nb_desc < ICE_MIN_RING_DESC) {
 724                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 725                              "invalid", nb_desc);
 726                 return -EINVAL;
 727         }
 728
 729         /**
 730          * The following two parameters control the setting of the RS bit on
 731          * transmit descriptors. TX descriptors will have their RS bit set
 732          * after txq->tx_rs_thresh descriptors have been used. The TX
 733          * descriptor ring will be cleaned after txq->tx_free_thresh
 734          * descriptors are used or if the number of descriptors required to
 735          * transmit a packet is greater than the number of free TX descriptors.
 736          *
 737          * The following constraints must be satisfied:
 738          *  - tx_rs_thresh must be greater than 0.
 739          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 740          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 741          *  - tx_rs_thresh must be a divisor of the ring size.
 742          *  - tx_free_thresh must be greater than 0.
 743          *  - tx_free_thresh must be less than the size of the ring minus 3.
 744          *
 745          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 746          * race condition, hence the maximum threshold constraints. When set
 747          * to zero use default values.
 748          */
 749         tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ?
 750                                   tx_conf->tx_rs_thresh :
 751                                   ICE_DEFAULT_TX_RSBIT_THRESH);
 752         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 753                                     tx_conf->tx_free_thresh :
 754                                     ICE_DEFAULT_TX_FREE_THRESH);
 755         if (tx_rs_thresh >= (nb_desc - 2)) {
 756                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 757                              "number of TX descriptors minus 2. "
 758                              "(tx_rs_thresh=%u port=%d queue=%d)",
 759                              (unsigned int)tx_rs_thresh,
 760                              (int)dev->data->port_id,
 761                              (int)queue_idx);
 762                 return -EINVAL;
 763         }
 764         if (tx_free_thresh >= (nb_desc - 3)) {
 765                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 766                              "tx_free_thresh must be less than the "
 767                              "number of TX descriptors minus 3. "
 768                              "(tx_free_thresh=%u port=%d queue=%d)",
 769                              (unsigned int)tx_free_thresh,
 770                              (int)dev->data->port_id,
 771                              (int)queue_idx);
 772                 return -EINVAL;
 773         }
 774         if (tx_rs_thresh > tx_free_thresh) {
 775                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 776                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 777                              " tx_rs_thresh=%u port=%d queue=%d)",
 778                              (unsigned int)tx_free_thresh,
 779                              (unsigned int)tx_rs_thresh,
 780                              (int)dev->data->port_id,
 781                              (int)queue_idx);
 782                 return -EINVAL;
 783         }
 784         if ((nb_desc % tx_rs_thresh) != 0) {
 785                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 786                              "number of TX descriptors. (tx_rs_thresh=%u"
 787                              " port=%d queue=%d)",
 788                              (unsigned int)tx_rs_thresh,
 789                              (int)dev->data->port_id,
 790                              (int)queue_idx);
 791                 return -EINVAL;
 792         }
 793         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 794                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 795                              "tx_rs_thresh is greater than 1. "
 796                              "(tx_rs_thresh=%u port=%d queue=%d)",
 797                              (unsigned int)tx_rs_thresh,
 798                              (int)dev->data->port_id,
 799                              (int)queue_idx);
 800                 return -EINVAL;
 801         }
 802
 803         /* Free memory if needed. */
 804         if (dev->data->tx_queues[queue_idx]) {
 805                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 806                 dev->data->tx_queues[queue_idx] = NULL;
 807         }
 808
 809         /* Allocate the TX queue data structure. */
 810         txq = rte_zmalloc_socket(NULL,
 811                                  sizeof(struct ice_tx_queue),
 812                                  RTE_CACHE_LINE_SIZE,
 813                                  socket_id);
 814         if (!txq) {
 815                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 816                              "tx queue structure");
 817                 return -ENOMEM;
 818         }
 819
 820         /* Allocate TX hardware ring descriptors. */
 821         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 822         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 823         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 824                                       ring_size, ICE_RING_BASE_ALIGN,
 825                                       socket_id);
 826         if (!tz) {
 827                 ice_tx_queue_release(txq);
 828                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 829                 return -ENOMEM;
 830         }
 831
 832         txq->nb_tx_desc = nb_desc;
 833         txq->tx_rs_thresh = tx_rs_thresh;
 834         txq->tx_free_thresh = tx_free_thresh;
 835         txq->pthresh = tx_conf->tx_thresh.pthresh;
 836         txq->hthresh = tx_conf->tx_thresh.hthresh;
 837         txq->wthresh = tx_conf->tx_thresh.wthresh;
 838         txq->queue_id = queue_idx;
 839
 840         txq->reg_idx = vsi->base_queue + queue_idx;
 841         txq->port_id = dev->data->port_id;
 842         txq->offloads = offloads;
 843         txq->vsi = vsi;
 844         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 845
 846         txq->tx_ring_phys_addr = tz->phys_addr;
 847         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
 848
 849         /* Allocate software ring */
 850         txq->sw_ring =
 851                 rte_zmalloc_socket(NULL,
 852                                    sizeof(struct ice_tx_entry) * nb_desc,
 853                                    RTE_CACHE_LINE_SIZE,
 854                                    socket_id);
 855         if (!txq->sw_ring) {
 856                 ice_tx_queue_release(txq);
 857                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 858                 return -ENOMEM;
 859         }
 860
 861         ice_reset_tx_queue(txq);
 862         txq->q_set = TRUE;
 863         dev->data->tx_queues[queue_idx] = txq;
 864
 865         return 0;
 866 }
 867
 868 void
 869 ice_tx_queue_release(void *txq)
 870 {
 871         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 872
 873         if (!q) {
 874                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 875                 return;
 876         }
 877
 878         ice_tx_queue_release_mbufs(q);
 879         rte_free(q->sw_ring);
 880         rte_free(q);
 881 }
 882
 883 void
 884 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 885                  struct rte_eth_rxq_info *qinfo)
 886 {
 887         struct ice_rx_queue *rxq;
 888
 889         rxq = dev->data->rx_queues[queue_id];
 890
 891         qinfo->mp = rxq->mp;
 892         qinfo->scattered_rx = dev->data->scattered_rx;
 893         qinfo->nb_desc = rxq->nb_rx_desc;
 894
 895         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 896         qinfo->conf.rx_drop_en = rxq->drop_en;
 897         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 898 }
 899
 900 void
 901 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 902                  struct rte_eth_txq_info *qinfo)
 903 {
 904         struct ice_tx_queue *txq;
 905
 906         txq = dev->data->tx_queues[queue_id];
 907
 908         qinfo->nb_desc = txq->nb_tx_desc;
 909
 910         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 911         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 912         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 913
 914         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 915         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 916         qinfo->conf.offloads = txq->offloads;
 917         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 918 }
 919
 920 uint32_t
 921 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 922 {
 923 #define ICE_RXQ_SCAN_INTERVAL 4
 924         volatile union ice_rx_desc *rxdp;
 925         struct ice_rx_queue *rxq;
 926         uint16_t desc = 0;
 927
 928         rxq = dev->data->rx_queues[rx_queue_id];
 929         rxdp = &rxq->rx_ring[rxq->rx_tail];
 930         while ((desc < rxq->nb_rx_desc) &&
 931                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 932                  ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
 933                (1 << ICE_RX_DESC_STATUS_DD_S)) {
 934                 /**
 935                  * Check the DD bit of a rx descriptor of each 4 in a group,
 936                  * to avoid checking too frequently and downgrading performance
 937                  * too much.
 938                  */
 939                 desc += ICE_RXQ_SCAN_INTERVAL;
 940                 rxdp += ICE_RXQ_SCAN_INTERVAL;
 941                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
 942                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
 943                                  desc - rxq->nb_rx_desc]);
 944         }
 945
 946         return desc;
 947 }
 948
 949 /* Rx L3/L4 checksum */
 950 static inline uint64_t
 951 ice_rxd_error_to_pkt_flags(uint64_t qword)
 952 {
 953         uint64_t flags = 0;
 954         uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
 955
 956         if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
 957                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 958                 return flags;
 959         }
 960
 961         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
 962                 flags |= PKT_RX_IP_CKSUM_BAD;
 963         else
 964                 flags |= PKT_RX_IP_CKSUM_GOOD;
 965
 966         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
 967                 flags |= PKT_RX_L4_CKSUM_BAD;
 968         else
 969                 flags |= PKT_RX_L4_CKSUM_GOOD;
 970
 971         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
 972                 flags |= PKT_RX_EIP_CKSUM_BAD;
 973
 974         return flags;
 975 }
 976
 977 const uint32_t *
 978 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 979 {
 980         static const uint32_t ptypes[] = {
 981                 /* refers to ice_get_default_pkt_type() */
 982                 RTE_PTYPE_L2_ETHER,
 983                 RTE_PTYPE_L2_ETHER_LLDP,
 984                 RTE_PTYPE_L2_ETHER_ARP,
 985                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 986                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 987                 RTE_PTYPE_L4_FRAG,
 988                 RTE_PTYPE_L4_ICMP,
 989                 RTE_PTYPE_L4_NONFRAG,
 990                 RTE_PTYPE_L4_SCTP,
 991                 RTE_PTYPE_L4_TCP,
 992                 RTE_PTYPE_L4_UDP,
 993                 RTE_PTYPE_TUNNEL_GRENAT,
 994                 RTE_PTYPE_TUNNEL_IP,
 995                 RTE_PTYPE_INNER_L2_ETHER,
 996                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 997                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 998                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 999                 RTE_PTYPE_INNER_L4_FRAG,
1000                 RTE_PTYPE_INNER_L4_ICMP,
1001                 RTE_PTYPE_INNER_L4_NONFRAG,
1002                 RTE_PTYPE_INNER_L4_SCTP,
1003                 RTE_PTYPE_INNER_L4_TCP,
1004                 RTE_PTYPE_INNER_L4_UDP,
1005                 RTE_PTYPE_TUNNEL_GTPC,
1006                 RTE_PTYPE_TUNNEL_GTPU,
1007                 RTE_PTYPE_UNKNOWN
1008         };
1009
1010         if (dev->rx_pkt_burst == ice_recv_pkts)
1011                 return ptypes;
1012         return NULL;
1013 }
1014
1015 void
1016 ice_clear_queues(struct rte_eth_dev *dev)
1017 {
1018         uint16_t i;
1019
1020         PMD_INIT_FUNC_TRACE();
1021
1022         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1023                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1024                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1025         }
1026
1027         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1028                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1029                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1030         }
1031 }
1032
1033 void
1034 ice_free_queues(struct rte_eth_dev *dev)
1035 {
1036         uint16_t i;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1041                 if (!dev->data->rx_queues[i])
1042                         continue;
1043                 ice_rx_queue_release(dev->data->rx_queues[i]);
1044                 dev->data->rx_queues[i] = NULL;
1045         }
1046         dev->data->nb_rx_queues = 0;
1047
1048         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1049                 if (!dev->data->tx_queues[i])
1050                         continue;
1051                 ice_tx_queue_release(dev->data->tx_queues[i]);
1052                 dev->data->tx_queues[i] = NULL;
1053         }
1054         dev->data->nb_tx_queues = 0;
1055 }
1056
1057 uint16_t
1058 ice_recv_pkts(void *rx_queue,
1059               struct rte_mbuf **rx_pkts,
1060               uint16_t nb_pkts)
1061 {
1062         struct ice_rx_queue *rxq = rx_queue;
1063         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1064         volatile union ice_rx_desc *rxdp;
1065         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1066         struct ice_rx_entry *rxe;
1067         struct rte_mbuf *nmb; /* new allocated mbuf */
1068         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1069         uint16_t rx_id = rxq->rx_tail;
1070         uint16_t nb_rx = 0;
1071         uint16_t nb_hold = 0;
1072         uint16_t rx_packet_len;
1073         uint32_t rx_status;
1074         uint64_t qword1;
1075         uint64_t dma_addr;
1076         uint64_t pkt_flags = 0;
1077         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1078         struct rte_eth_dev *dev;
1079
1080         while (nb_rx < nb_pkts) {
1081                 rxdp = &rx_ring[rx_id];
1082                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1083                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1084                             ICE_RXD_QW1_STATUS_S;
1085
1086                 /* Check the DD bit first */
1087                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1088                         break;
1089
1090                 /* allocate mbuf */
1091                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1092                 if (unlikely(!nmb)) {
1093                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1094                         dev->data->rx_mbuf_alloc_failed++;
1095                         break;
1096                 }
1097
1098                 nb_hold++;
1099                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1100                 rx_id++;
1101                 if (unlikely(rx_id == rxq->nb_rx_desc))
1102                         rx_id = 0;
1103                 rxm = rxe->mbuf;
1104                 rxe->mbuf = nmb;
1105                 dma_addr =
1106                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1107
1108                 /**
1109                  * fill the read format of descriptor with physic address in
1110                  * new allocated mbuf: nmb
1111                  */
1112                 rxdp->read.hdr_addr = 0;
1113                 rxdp->read.pkt_addr = dma_addr;
1114
1115                 /* calculate rx_packet_len of the received pkt */
1116                 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1117                                 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1118
1119                 /* fill old mbuf with received descriptor: rxd */
1120                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1121                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1122                 rxm->nb_segs = 1;
1123                 rxm->next = NULL;
1124                 rxm->pkt_len = rx_packet_len;
1125                 rxm->data_len = rx_packet_len;
1126                 rxm->port = rxq->port_id;
1127                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1128                                                         ICE_RXD_QW1_PTYPE_M) >>
1129                                                        ICE_RXD_QW1_PTYPE_S)];
1130                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1131                 rxm->ol_flags |= pkt_flags;
1132                 /* copy old mbuf to rx_pkts */
1133                 rx_pkts[nb_rx++] = rxm;
1134         }
1135         rxq->rx_tail = rx_id;
1136         /**
1137          * If the number of free RX descriptors is greater than the RX free
1138          * threshold of the queue, advance the receive tail register of queue.
1139          * Update that register with the value of the last processed RX
1140          * descriptor minus 1.
1141          */
1142         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1143         if (nb_hold > rxq->rx_free_thresh) {
1144                 rx_id = (uint16_t)(rx_id == 0 ?
1145                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1146                 /* write TAIL register */
1147                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1148                 nb_hold = 0;
1149         }
1150         rxq->nb_rx_hold = nb_hold;
1151
1152         /* return received packet in the burst */
1153         return nb_rx;
1154 }
1155
1156 static inline void
1157 ice_txd_enable_checksum(uint64_t ol_flags,
1158                         uint32_t *td_cmd,
1159                         uint32_t *td_offset,
1160                         union ice_tx_offload tx_offload)
1161 {
1162         /* L2 length must be set. */
1163         *td_offset |= (tx_offload.l2_len >> 1) <<
1164                       ICE_TX_DESC_LEN_MACLEN_S;
1165
1166         /* Enable L3 checksum offloads */
1167         if (ol_flags & PKT_TX_IP_CKSUM) {
1168                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1169                 *td_offset |= (tx_offload.l3_len >> 2) <<
1170                               ICE_TX_DESC_LEN_IPLEN_S;
1171         } else if (ol_flags & PKT_TX_IPV4) {
1172                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1173                 *td_offset |= (tx_offload.l3_len >> 2) <<
1174                               ICE_TX_DESC_LEN_IPLEN_S;
1175         } else if (ol_flags & PKT_TX_IPV6) {
1176                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1177                 *td_offset |= (tx_offload.l3_len >> 2) <<
1178                               ICE_TX_DESC_LEN_IPLEN_S;
1179         }
1180
1181         if (ol_flags & PKT_TX_TCP_SEG) {
1182                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1183                 *td_offset |= (tx_offload.l4_len >> 2) <<
1184                               ICE_TX_DESC_LEN_L4_LEN_S;
1185                 return;
1186         }
1187
1188         /* Enable L4 checksum offloads */
1189         switch (ol_flags & PKT_TX_L4_MASK) {
1190         case PKT_TX_TCP_CKSUM:
1191                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1192                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1193                               ICE_TX_DESC_LEN_L4_LEN_S;
1194                 break;
1195         case PKT_TX_SCTP_CKSUM:
1196                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1197                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1198                               ICE_TX_DESC_LEN_L4_LEN_S;
1199                 break;
1200         case PKT_TX_UDP_CKSUM:
1201                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1202                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1203                               ICE_TX_DESC_LEN_L4_LEN_S;
1204                 break;
1205         default:
1206                 break;
1207         }
1208 }
1209
1210 static inline int
1211 ice_xmit_cleanup(struct ice_tx_queue *txq)
1212 {
1213         struct ice_tx_entry *sw_ring = txq->sw_ring;
1214         volatile struct ice_tx_desc *txd = txq->tx_ring;
1215         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1216         uint16_t nb_tx_desc = txq->nb_tx_desc;
1217         uint16_t desc_to_clean_to;
1218         uint16_t nb_tx_to_clean;
1219
1220         /* Determine the last descriptor needing to be cleaned */
1221         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1222         if (desc_to_clean_to >= nb_tx_desc)
1223                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1224
1225         /* Check to make sure the last descriptor to clean is done */
1226         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1227         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1228             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1229                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1230                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1231                                 desc_to_clean_to,
1232                                 txq->port_id, txq->queue_id,
1233                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1234                 /* Failed to clean any descriptors */
1235                 return -1;
1236         }
1237
1238         /* Figure out how many descriptors will be cleaned */
1239         if (last_desc_cleaned > desc_to_clean_to)
1240                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1241                                             desc_to_clean_to);
1242         else
1243                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1244                                             last_desc_cleaned);
1245
1246         /* The last descriptor to clean is done, so that means all the
1247          * descriptors from the last descriptor that was cleaned
1248          * up to the last descriptor with the RS bit set
1249          * are done. Only reset the threshold descriptor.
1250          */
1251         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1252
1253         /* Update the txq to reflect the last descriptor that was cleaned */
1254         txq->last_desc_cleaned = desc_to_clean_to;
1255         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1256
1257         return 0;
1258 }
1259
1260 /* Check if the context descriptor is needed for TX offloading */
1261 static inline uint16_t
1262 ice_calc_context_desc(uint64_t flags)
1263 {
1264         static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
1265
1266         return (flags & mask) ? 1 : 0;
1267 }
1268
1269 /* set ice TSO context descriptor */
1270 static inline uint64_t
1271 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1272 {
1273         uint64_t ctx_desc = 0;
1274         uint32_t cd_cmd, hdr_len, cd_tso_len;
1275
1276         if (!tx_offload.l4_len) {
1277                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1278                 return ctx_desc;
1279         }
1280
1281         /**
1282          * in case of non tunneling packet, the outer_l2_len and
1283          * outer_l3_len must be 0.
1284          */
1285         hdr_len = tx_offload.outer_l2_len +
1286                   tx_offload.outer_l3_len +
1287                   tx_offload.l2_len +
1288                   tx_offload.l3_len +
1289                   tx_offload.l4_len;
1290
1291         cd_cmd = ICE_TX_CTX_DESC_TSO;
1292         cd_tso_len = mbuf->pkt_len - hdr_len;
1293         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1294                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1295                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1296
1297         return ctx_desc;
1298 }
1299
1300 uint16_t
1301 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1302 {
1303         struct ice_tx_queue *txq;
1304         volatile struct ice_tx_desc *tx_ring;
1305         volatile struct ice_tx_desc *txd;
1306         struct ice_tx_entry *sw_ring;
1307         struct ice_tx_entry *txe, *txn;
1308         struct rte_mbuf *tx_pkt;
1309         struct rte_mbuf *m_seg;
1310         uint16_t tx_id;
1311         uint16_t nb_tx;
1312         uint16_t nb_used;
1313         uint16_t nb_ctx;
1314         uint32_t td_cmd = 0;
1315         uint32_t td_offset = 0;
1316         uint32_t td_tag = 0;
1317         uint16_t tx_last;
1318         uint64_t buf_dma_addr;
1319         uint64_t ol_flags;
1320         union ice_tx_offload tx_offload = {0};
1321
1322         txq = tx_queue;
1323         sw_ring = txq->sw_ring;
1324         tx_ring = txq->tx_ring;
1325         tx_id = txq->tx_tail;
1326         txe = &sw_ring[tx_id];
1327
1328         /* Check if the descriptor ring needs to be cleaned. */
1329         if (txq->nb_tx_free < txq->tx_free_thresh)
1330                 ice_xmit_cleanup(txq);
1331
1332         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1333                 tx_pkt = *tx_pkts++;
1334
1335                 td_cmd = 0;
1336                 ol_flags = tx_pkt->ol_flags;
1337                 tx_offload.l2_len = tx_pkt->l2_len;
1338                 tx_offload.l3_len = tx_pkt->l3_len;
1339                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1340                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1341                 tx_offload.l4_len = tx_pkt->l4_len;
1342                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1343                 /* Calculate the number of context descriptors needed. */
1344                 nb_ctx = ice_calc_context_desc(ol_flags);
1345
1346                 /* The number of descriptors that must be allocated for
1347                  * a packet equals to the number of the segments of that
1348                  * packet plus the number of context descriptor if needed.
1349                  */
1350                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1351                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1352
1353                 /* Circular ring */
1354                 if (tx_last >= txq->nb_tx_desc)
1355                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1356
1357                 if (nb_used > txq->nb_tx_free) {
1358                         if (ice_xmit_cleanup(txq) != 0) {
1359                                 if (nb_tx == 0)
1360                                         return 0;
1361                                 goto end_of_tx;
1362                         }
1363                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1364                                 while (nb_used > txq->nb_tx_free) {
1365                                         if (ice_xmit_cleanup(txq) != 0) {
1366                                                 if (nb_tx == 0)
1367                                                         return 0;
1368                                                 goto end_of_tx;
1369                                         }
1370                                 }
1371                         }
1372                 }
1373
1374                 /* Enable checksum offloading */
1375                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
1376                         ice_txd_enable_checksum(ol_flags, &td_cmd,
1377                                                 &td_offset, tx_offload);
1378                 }
1379
1380                 if (nb_ctx) {
1381                         /* Setup TX context descriptor if required */
1382                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
1383
1384                         txn = &sw_ring[txe->next_id];
1385                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1386                         if (txe->mbuf) {
1387                                 rte_pktmbuf_free_seg(txe->mbuf);
1388                                 txe->mbuf = NULL;
1389                         }
1390
1391                         if (ol_flags & PKT_TX_TCP_SEG)
1392                                 cd_type_cmd_tso_mss |=
1393                                         ice_set_tso_ctx(tx_pkt, tx_offload);
1394
1395                         txe->last_id = tx_last;
1396                         tx_id = txe->next_id;
1397                         txe = txn;
1398                 }
1399                 m_seg = tx_pkt;
1400
1401                 do {
1402                         txd = &tx_ring[tx_id];
1403                         txn = &sw_ring[txe->next_id];
1404
1405                         if (txe->mbuf)
1406                                 rte_pktmbuf_free_seg(txe->mbuf);
1407                         txe->mbuf = m_seg;
1408
1409                         /* Setup TX Descriptor */
1410                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1411                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
1412                         txd->cmd_type_offset_bsz =
1413                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1414                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
1415                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1416                                 ((uint64_t)m_seg->data_len  <<
1417                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
1418                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
1419
1420                         txe->last_id = tx_last;
1421                         tx_id = txe->next_id;
1422                         txe = txn;
1423                         m_seg = m_seg->next;
1424                 } while (m_seg);
1425
1426                 /* fill the last descriptor with End of Packet (EOP) bit */
1427                 td_cmd |= ICE_TX_DESC_CMD_EOP;
1428                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1429                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1430
1431                 /* set RS bit on the last descriptor of one packet */
1432                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1433                         PMD_TX_FREE_LOG(DEBUG,
1434                                         "Setting RS bit on TXD id="
1435                                         "%4u (port=%d queue=%d)",
1436                                         tx_last, txq->port_id, txq->queue_id);
1437
1438                         td_cmd |= ICE_TX_DESC_CMD_RS;
1439
1440                         /* Update txq RS bit counters */
1441                         txq->nb_tx_used = 0;
1442                 }
1443                 txd->cmd_type_offset_bsz |=
1444                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1445                                          ICE_TXD_QW1_CMD_S);
1446         }
1447 end_of_tx:
1448         rte_wmb();
1449
1450         /* update Tail register */
1451         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1452         txq->tx_tail = tx_id;
1453
1454         return nb_tx;
1455 }
1456
1457 void __attribute__((cold))
1458 ice_set_rx_function(struct rte_eth_dev *dev)
1459 {
1460         dev->rx_pkt_burst = ice_recv_pkts;
1461 }
1462
1463 /*********************************************************************
1464  *
1465  *  TX prep functions
1466  *
1467  **********************************************************************/
1468 /* The default values of TSO MSS */
1469 #define ICE_MIN_TSO_MSS            64
1470 #define ICE_MAX_TSO_MSS            9728
1471 #define ICE_MAX_TSO_FRAME_SIZE     262144
1472 uint16_t
1473 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1474               uint16_t nb_pkts)
1475 {
1476         int i, ret;
1477         uint64_t ol_flags;
1478         struct rte_mbuf *m;
1479
1480         for (i = 0; i < nb_pkts; i++) {
1481                 m = tx_pkts[i];
1482                 ol_flags = m->ol_flags;
1483
1484                 if (ol_flags & PKT_TX_TCP_SEG &&
1485                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
1486                      m->tso_segsz > ICE_MAX_TSO_MSS ||
1487                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
1488                         /**
1489                          * MSS outside the range are considered malicious
1490                          */
1491                         rte_errno = -EINVAL;
1492                         return i;
1493                 }
1494
1495 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1496                 ret = rte_validate_tx_offload(m);
1497                 if (ret != 0) {
1498                         rte_errno = ret;
1499                         return i;
1500                 }
1501 #endif
1502                 ret = rte_net_intel_cksum_prepare(m);
1503                 if (ret != 0) {
1504                         rte_errno = ret;
1505                         return i;
1506                 }
1507         }
1508         return i;
1509 }
1510
1511 void __attribute__((cold))
1512 ice_set_tx_function(struct rte_eth_dev *dev)
1513 {
1514                 dev->tx_pkt_burst = ice_xmit_pkts;
1515                 dev->tx_pkt_prepare = ice_prep_pkts;
1516 }
1517
1518 /* For each value it means, datasheet of hardware can tell more details
1519  *
1520  * @note: fix ice_dev_supported_ptypes_get() if any change here.
1521  */
1522 static inline uint32_t
1523 ice_get_default_pkt_type(uint16_t ptype)
1524 {
1525         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
1526                 __rte_cache_aligned = {
1527                 /* L2 types */
1528                 /* [0] reserved */
1529                 [1] = RTE_PTYPE_L2_ETHER,
1530                 /* [2] - [5] reserved */
1531                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
1532                 /* [7] - [10] reserved */
1533                 [11] = RTE_PTYPE_L2_ETHER_ARP,
1534                 /* [12] - [21] reserved */
1535
1536                 /* Non tunneled IPv4 */
1537                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1538                        RTE_PTYPE_L4_FRAG,
1539                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1540                        RTE_PTYPE_L4_NONFRAG,
1541                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1542                        RTE_PTYPE_L4_UDP,
1543                 /* [25] reserved */
1544                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1545                        RTE_PTYPE_L4_TCP,
1546                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1547                        RTE_PTYPE_L4_SCTP,
1548                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1549                        RTE_PTYPE_L4_ICMP,
1550
1551                 /* IPv4 --> IPv4 */
1552                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1553                        RTE_PTYPE_TUNNEL_IP |
1554                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1555                        RTE_PTYPE_INNER_L4_FRAG,
1556                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1557                        RTE_PTYPE_TUNNEL_IP |
1558                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1559                        RTE_PTYPE_INNER_L4_NONFRAG,
1560                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1561                        RTE_PTYPE_TUNNEL_IP |
1562                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1563                        RTE_PTYPE_INNER_L4_UDP,
1564                 /* [32] reserved */
1565                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1566                        RTE_PTYPE_TUNNEL_IP |
1567                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1568                        RTE_PTYPE_INNER_L4_TCP,
1569                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1570                        RTE_PTYPE_TUNNEL_IP |
1571                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1572                        RTE_PTYPE_INNER_L4_SCTP,
1573                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1574                        RTE_PTYPE_TUNNEL_IP |
1575                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1576                        RTE_PTYPE_INNER_L4_ICMP,
1577
1578                 /* IPv4 --> IPv6 */
1579                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1580                        RTE_PTYPE_TUNNEL_IP |
1581                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1582                        RTE_PTYPE_INNER_L4_FRAG,
1583                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1584                        RTE_PTYPE_TUNNEL_IP |
1585                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1586                        RTE_PTYPE_INNER_L4_NONFRAG,
1587                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1588                        RTE_PTYPE_TUNNEL_IP |
1589                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1590                        RTE_PTYPE_INNER_L4_UDP,
1591                 /* [39] reserved */
1592                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1593                        RTE_PTYPE_TUNNEL_IP |
1594                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1595                        RTE_PTYPE_INNER_L4_TCP,
1596                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1597                        RTE_PTYPE_TUNNEL_IP |
1598                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1599                        RTE_PTYPE_INNER_L4_SCTP,
1600                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1601                        RTE_PTYPE_TUNNEL_IP |
1602                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1603                        RTE_PTYPE_INNER_L4_ICMP,
1604
1605                 /* IPv4 --> GRE/Teredo/VXLAN */
1606                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1607                        RTE_PTYPE_TUNNEL_GRENAT,
1608
1609                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
1610                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1611                        RTE_PTYPE_TUNNEL_GRENAT |
1612                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1613                        RTE_PTYPE_INNER_L4_FRAG,
1614                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1615                        RTE_PTYPE_TUNNEL_GRENAT |
1616                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1617                        RTE_PTYPE_INNER_L4_NONFRAG,
1618                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1619                        RTE_PTYPE_TUNNEL_GRENAT |
1620                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1621                        RTE_PTYPE_INNER_L4_UDP,
1622                 /* [47] reserved */
1623                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1624                        RTE_PTYPE_TUNNEL_GRENAT |
1625                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1626                        RTE_PTYPE_INNER_L4_TCP,
1627                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1628                        RTE_PTYPE_TUNNEL_GRENAT |
1629                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1630                        RTE_PTYPE_INNER_L4_SCTP,
1631                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1632                        RTE_PTYPE_TUNNEL_GRENAT |
1633                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1634                        RTE_PTYPE_INNER_L4_ICMP,
1635
1636                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
1637                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1638                        RTE_PTYPE_TUNNEL_GRENAT |
1639                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1640                        RTE_PTYPE_INNER_L4_FRAG,
1641                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1642                        RTE_PTYPE_TUNNEL_GRENAT |
1643                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1644                        RTE_PTYPE_INNER_L4_NONFRAG,
1645                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1646                        RTE_PTYPE_TUNNEL_GRENAT |
1647                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1648                        RTE_PTYPE_INNER_L4_UDP,
1649                 /* [54] reserved */
1650                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1651                        RTE_PTYPE_TUNNEL_GRENAT |
1652                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1653                        RTE_PTYPE_INNER_L4_TCP,
1654                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1655                        RTE_PTYPE_TUNNEL_GRENAT |
1656                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1657                        RTE_PTYPE_INNER_L4_SCTP,
1658                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1659                        RTE_PTYPE_TUNNEL_GRENAT |
1660                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1661                        RTE_PTYPE_INNER_L4_ICMP,
1662
1663                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
1664                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1665                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
1666
1667                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
1668                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1669                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1670                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1671                        RTE_PTYPE_INNER_L4_FRAG,
1672                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1673                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1674                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1675                        RTE_PTYPE_INNER_L4_NONFRAG,
1676                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1677                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1678                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1679                        RTE_PTYPE_INNER_L4_UDP,
1680                 /* [62] reserved */
1681                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1682                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1683                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1684                        RTE_PTYPE_INNER_L4_TCP,
1685                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1686                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1687                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1688                        RTE_PTYPE_INNER_L4_SCTP,
1689                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1690                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1691                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1692                        RTE_PTYPE_INNER_L4_ICMP,
1693
1694                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
1695                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1696                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1697                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1698                        RTE_PTYPE_INNER_L4_FRAG,
1699                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1700                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1701                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1702                        RTE_PTYPE_INNER_L4_NONFRAG,
1703                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1704                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1705                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1706                        RTE_PTYPE_INNER_L4_UDP,
1707                 /* [69] reserved */
1708                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1709                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1710                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1711                        RTE_PTYPE_INNER_L4_TCP,
1712                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1713                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1714                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1715                        RTE_PTYPE_INNER_L4_SCTP,
1716                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1717                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1718                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1719                        RTE_PTYPE_INNER_L4_ICMP,
1720
1721                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
1722                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1723                        RTE_PTYPE_TUNNEL_GRENAT |
1724                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
1725
1726                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
1727                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1728                        RTE_PTYPE_TUNNEL_GRENAT |
1729                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1730                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1731                        RTE_PTYPE_INNER_L4_FRAG,
1732                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1733                        RTE_PTYPE_TUNNEL_GRENAT |
1734                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1735                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1736                        RTE_PTYPE_INNER_L4_NONFRAG,
1737                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1738                        RTE_PTYPE_TUNNEL_GRENAT |
1739                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1740                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1741                        RTE_PTYPE_INNER_L4_UDP,
1742                 /* [77] reserved */
1743                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1744                        RTE_PTYPE_TUNNEL_GRENAT |
1745                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1746                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1747                        RTE_PTYPE_INNER_L4_TCP,
1748                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1749                        RTE_PTYPE_TUNNEL_GRENAT |
1750                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1751                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1752                        RTE_PTYPE_INNER_L4_SCTP,
1753                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1754                        RTE_PTYPE_TUNNEL_GRENAT |
1755                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1756                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1757                        RTE_PTYPE_INNER_L4_ICMP,
1758
1759                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
1760                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1761                        RTE_PTYPE_TUNNEL_GRENAT |
1762                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1763                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1764                        RTE_PTYPE_INNER_L4_FRAG,
1765                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1766                        RTE_PTYPE_TUNNEL_GRENAT |
1767                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1768                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1769                        RTE_PTYPE_INNER_L4_NONFRAG,
1770                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1771                        RTE_PTYPE_TUNNEL_GRENAT |
1772                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1773                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1774                        RTE_PTYPE_INNER_L4_UDP,
1775                 /* [84] reserved */
1776                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1777                        RTE_PTYPE_TUNNEL_GRENAT |
1778                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1779                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1780                        RTE_PTYPE_INNER_L4_TCP,
1781                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1782                        RTE_PTYPE_TUNNEL_GRENAT |
1783                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1784                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1785                        RTE_PTYPE_INNER_L4_SCTP,
1786                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1787                        RTE_PTYPE_TUNNEL_GRENAT |
1788                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
1789                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1790                        RTE_PTYPE_INNER_L4_ICMP,
1791
1792                 /* Non tunneled IPv6 */
1793                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1794                        RTE_PTYPE_L4_FRAG,
1795                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1796                        RTE_PTYPE_L4_NONFRAG,
1797                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1798                        RTE_PTYPE_L4_UDP,
1799                 /* [91] reserved */
1800                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1801                        RTE_PTYPE_L4_TCP,
1802                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1803                        RTE_PTYPE_L4_SCTP,
1804                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1805                        RTE_PTYPE_L4_ICMP,
1806
1807                 /* IPv6 --> IPv4 */
1808                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1809                        RTE_PTYPE_TUNNEL_IP |
1810                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1811                        RTE_PTYPE_INNER_L4_FRAG,
1812                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1813                        RTE_PTYPE_TUNNEL_IP |
1814                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1815                        RTE_PTYPE_INNER_L4_NONFRAG,
1816                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1817                        RTE_PTYPE_TUNNEL_IP |
1818                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1819                        RTE_PTYPE_INNER_L4_UDP,
1820                 /* [98] reserved */
1821                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1822                        RTE_PTYPE_TUNNEL_IP |
1823                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1824                        RTE_PTYPE_INNER_L4_TCP,
1825                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1826                         RTE_PTYPE_TUNNEL_IP |
1827                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1828                         RTE_PTYPE_INNER_L4_SCTP,
1829                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1830                         RTE_PTYPE_TUNNEL_IP |
1831                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1832                         RTE_PTYPE_INNER_L4_ICMP,
1833
1834                 /* IPv6 --> IPv6 */
1835                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1836                         RTE_PTYPE_TUNNEL_IP |
1837                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1838                         RTE_PTYPE_INNER_L4_FRAG,
1839                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1840                         RTE_PTYPE_TUNNEL_IP |
1841                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1842                         RTE_PTYPE_INNER_L4_NONFRAG,
1843                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1844                         RTE_PTYPE_TUNNEL_IP |
1845                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1846                         RTE_PTYPE_INNER_L4_UDP,
1847                 /* [105] reserved */
1848                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1849                         RTE_PTYPE_TUNNEL_IP |
1850                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1851                         RTE_PTYPE_INNER_L4_TCP,
1852                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1853                         RTE_PTYPE_TUNNEL_IP |
1854                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1855                         RTE_PTYPE_INNER_L4_SCTP,
1856                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1857                         RTE_PTYPE_TUNNEL_IP |
1858                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1859                         RTE_PTYPE_INNER_L4_ICMP,
1860
1861                 /* IPv6 --> GRE/Teredo/VXLAN */
1862                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1863                         RTE_PTYPE_TUNNEL_GRENAT,
1864
1865                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
1866                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1867                         RTE_PTYPE_TUNNEL_GRENAT |
1868                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1869                         RTE_PTYPE_INNER_L4_FRAG,
1870                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1871                         RTE_PTYPE_TUNNEL_GRENAT |
1872                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1873                         RTE_PTYPE_INNER_L4_NONFRAG,
1874                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1875                         RTE_PTYPE_TUNNEL_GRENAT |
1876                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1877                         RTE_PTYPE_INNER_L4_UDP,
1878                 /* [113] reserved */
1879                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1880                         RTE_PTYPE_TUNNEL_GRENAT |
1881                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1882                         RTE_PTYPE_INNER_L4_TCP,
1883                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1884                         RTE_PTYPE_TUNNEL_GRENAT |
1885                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1886                         RTE_PTYPE_INNER_L4_SCTP,
1887                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1888                         RTE_PTYPE_TUNNEL_GRENAT |
1889                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1890                         RTE_PTYPE_INNER_L4_ICMP,
1891
1892                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
1893                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1894                         RTE_PTYPE_TUNNEL_GRENAT |
1895                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1896                         RTE_PTYPE_INNER_L4_FRAG,
1897                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1898                         RTE_PTYPE_TUNNEL_GRENAT |
1899                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1900                         RTE_PTYPE_INNER_L4_NONFRAG,
1901                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1902                         RTE_PTYPE_TUNNEL_GRENAT |
1903                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1904                         RTE_PTYPE_INNER_L4_UDP,
1905                 /* [120] reserved */
1906                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1907                         RTE_PTYPE_TUNNEL_GRENAT |
1908                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1909                         RTE_PTYPE_INNER_L4_TCP,
1910                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1911                         RTE_PTYPE_TUNNEL_GRENAT |
1912                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1913                         RTE_PTYPE_INNER_L4_SCTP,
1914                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1915                         RTE_PTYPE_TUNNEL_GRENAT |
1916                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1917                         RTE_PTYPE_INNER_L4_ICMP,
1918
1919                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
1920                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1921                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
1922
1923                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
1924                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1925                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1926                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1927                         RTE_PTYPE_INNER_L4_FRAG,
1928                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1929                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1930                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1931                         RTE_PTYPE_INNER_L4_NONFRAG,
1932                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1933                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1934                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1935                         RTE_PTYPE_INNER_L4_UDP,
1936                 /* [128] reserved */
1937                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1938                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1939                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1940                         RTE_PTYPE_INNER_L4_TCP,
1941                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1942                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1943                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1944                         RTE_PTYPE_INNER_L4_SCTP,
1945                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1946                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1947                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1948                         RTE_PTYPE_INNER_L4_ICMP,
1949
1950                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
1951                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1952                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1953                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1954                         RTE_PTYPE_INNER_L4_FRAG,
1955                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1956                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1957                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1958                         RTE_PTYPE_INNER_L4_NONFRAG,
1959                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1960                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1961                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1962                         RTE_PTYPE_INNER_L4_UDP,
1963                 /* [135] reserved */
1964                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1965                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1966                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1967                         RTE_PTYPE_INNER_L4_TCP,
1968                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1969                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1970                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1971                         RTE_PTYPE_INNER_L4_SCTP,
1972                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1973                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1974                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1975                         RTE_PTYPE_INNER_L4_ICMP,
1976
1977                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
1978                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1979                         RTE_PTYPE_TUNNEL_GRENAT |
1980                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
1981
1982                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
1983                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1984                         RTE_PTYPE_TUNNEL_GRENAT |
1985                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
1986                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1987                         RTE_PTYPE_INNER_L4_FRAG,
1988                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1989                         RTE_PTYPE_TUNNEL_GRENAT |
1990                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
1991                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1992                         RTE_PTYPE_INNER_L4_NONFRAG,
1993                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1994                         RTE_PTYPE_TUNNEL_GRENAT |
1995                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
1996                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1997                         RTE_PTYPE_INNER_L4_UDP,
1998                 /* [143] reserved */
1999                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2000                         RTE_PTYPE_TUNNEL_GRENAT |
2001                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2002                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2003                         RTE_PTYPE_INNER_L4_TCP,
2004                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2005                         RTE_PTYPE_TUNNEL_GRENAT |
2006                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2007                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2008                         RTE_PTYPE_INNER_L4_SCTP,
2009                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2010                         RTE_PTYPE_TUNNEL_GRENAT |
2011                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2012                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2013                         RTE_PTYPE_INNER_L4_ICMP,
2014
2015                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2016                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2017                         RTE_PTYPE_TUNNEL_GRENAT |
2018                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2019                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2020                         RTE_PTYPE_INNER_L4_FRAG,
2021                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2022                         RTE_PTYPE_TUNNEL_GRENAT |
2023                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2024                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2025                         RTE_PTYPE_INNER_L4_NONFRAG,
2026                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2027                         RTE_PTYPE_TUNNEL_GRENAT |
2028                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2029                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2030                         RTE_PTYPE_INNER_L4_UDP,
2031                 /* [150] reserved */
2032                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2033                         RTE_PTYPE_TUNNEL_GRENAT |
2034                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2035                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2036                         RTE_PTYPE_INNER_L4_TCP,
2037                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2038                         RTE_PTYPE_TUNNEL_GRENAT |
2039                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2040                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2041                         RTE_PTYPE_INNER_L4_SCTP,
2042                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2043                         RTE_PTYPE_TUNNEL_GRENAT |
2044                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2045                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2046                         RTE_PTYPE_INNER_L4_ICMP,
2047                 /* [154] - [255] reserved */
2048                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2049                         RTE_PTYPE_TUNNEL_GTPC,
2050                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2051                         RTE_PTYPE_TUNNEL_GTPC,
2052                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2053                                 RTE_PTYPE_TUNNEL_GTPU,
2054                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2055                                 RTE_PTYPE_TUNNEL_GTPU,
2056                 /* [260] - [263] reserved */
2057                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2058                         RTE_PTYPE_TUNNEL_GTPC,
2059                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2060                         RTE_PTYPE_TUNNEL_GTPC,
2061                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2062                                 RTE_PTYPE_TUNNEL_GTPU,
2063                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2064                                 RTE_PTYPE_TUNNEL_GTPU,
2065
2066                 /* All others reserved */
2067         };
2068
2069         return type_table[ptype];
2070 }
2071
2072 void __attribute__((cold))
2073 ice_set_default_ptype_table(struct rte_eth_dev *dev)
2074 {
2075         struct ice_adapter *ad =
2076                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2077         int i;
2078
2079         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
2080                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
2081 }