drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  14                 PKT_TX_IP_CKSUM |                \
  15                 PKT_TX_L4_MASK |                 \
  16                 PKT_TX_TCP_SEG |                 \
  17                 PKT_TX_OUTER_IP_CKSUM)
  18
  19 /* Offset of mbuf dynamic field for protocol extraction data */
  20 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  21
  22 /* Mask of mbuf dynamic flags for protocol extraction type */
  23 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  28 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  29
  30 int
  31 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  32 {
  33         volatile union ice_rx_flex_desc *rxdp;
  34         struct ice_rx_queue *rxq = rx_queue;
  35         uint16_t desc;
  36
  37         desc = rxq->rx_tail;
  38         rxdp = &rxq->rx_ring[desc];
  39         /* watch for changes in status bit */
  40         pmc->addr = &rxdp->wb.status_error0;
  41
  42         /*
  43          * we expect the DD bit to be set to 1 if this descriptor was already
  44          * written to.
  45          */
  46         pmc->val = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  47         pmc->mask = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  48
  49         /* register is 16-bit */
  50         pmc->size = sizeof(uint16_t);
  51
  52         return 0;
  53 }
  54
  55
  56 static inline uint8_t
  57 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  58 {
  59         static uint8_t rxdid_map[] = {
  60                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  61                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  62                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  63                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  64                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  65                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  66                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  67         };
  68
  69         return xtr_type < RTE_DIM(rxdid_map) ?
  70                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  71 }
  72
  73 static inline void
  74 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  75                                        struct rte_mbuf *mb,
  76                                        volatile union ice_rx_flex_desc *rxdp)
  77 {
  78         volatile struct ice_32b_rx_flex_desc_comms *desc =
  79                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  80         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  81
  82         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  83                 mb->ol_flags |= PKT_RX_RSS_HASH;
  84                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  85         }
  86
  87 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  88         if (desc->flow_id != 0xFFFFFFFF) {
  89                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  90                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  91         }
  92 #endif
  93 }
  94
  95 static inline void
  96 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
  97                                    struct rte_mbuf *mb,
  98                                    volatile union ice_rx_flex_desc *rxdp)
  99 {
 100         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 101                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 102 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 103         uint16_t stat_err;
 104 #endif
 105
 106         if (desc->flow_id != 0xFFFFFFFF) {
 107                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 108                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 109         }
 110
 111 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 112         stat_err = rte_le_to_cpu_16(desc->status_error0);
 113         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 114                 mb->ol_flags |= PKT_RX_RSS_HASH;
 115                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 116         }
 117 #endif
 118 }
 119
 120 static inline void
 121 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 122                                       struct rte_mbuf *mb,
 123                                       volatile union ice_rx_flex_desc *rxdp)
 124 {
 125         volatile struct ice_32b_rx_flex_desc_comms *desc =
 126                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 127         uint16_t stat_err;
 128
 129         stat_err = rte_le_to_cpu_16(desc->status_error0);
 130         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 131                 mb->ol_flags |= PKT_RX_RSS_HASH;
 132                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 133         }
 134
 135 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 136         if (desc->flow_id != 0xFFFFFFFF) {
 137                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 138                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 139         }
 140
 141         if (rxq->xtr_ol_flag) {
 142                 uint32_t metadata = 0;
 143
 144                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 145
 146                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 147                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 148
 149                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 150                         metadata |=
 151                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 152
 153                 if (metadata) {
 154                         mb->ol_flags |= rxq->xtr_ol_flag;
 155
 156                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 157                 }
 158         }
 159 #endif
 160 }
 161
 162 static inline void
 163 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 164                                       struct rte_mbuf *mb,
 165                                       volatile union ice_rx_flex_desc *rxdp)
 166 {
 167         volatile struct ice_32b_rx_flex_desc_comms *desc =
 168                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 169         uint16_t stat_err;
 170
 171         stat_err = rte_le_to_cpu_16(desc->status_error0);
 172         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 173                 mb->ol_flags |= PKT_RX_RSS_HASH;
 174                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 175         }
 176
 177 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 178         if (desc->flow_id != 0xFFFFFFFF) {
 179                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 180                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 181         }
 182
 183         if (rxq->xtr_ol_flag) {
 184                 uint32_t metadata = 0;
 185
 186                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 187                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 188                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 189                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 190
 191                 if (metadata) {
 192                         mb->ol_flags |= rxq->xtr_ol_flag;
 193
 194                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 195                 }
 196         }
 197 #endif
 198 }
 199
 200 void
 201 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 202 {
 203         switch (rxdid) {
 204         case ICE_RXDID_COMMS_AUX_VLAN:
 205                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 206                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 207                 break;
 208
 209         case ICE_RXDID_COMMS_AUX_IPV4:
 210                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 211                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 212                 break;
 213
 214         case ICE_RXDID_COMMS_AUX_IPV6:
 215                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 216                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 217                 break;
 218
 219         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 220                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 221                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 222                 break;
 223
 224         case ICE_RXDID_COMMS_AUX_TCP:
 225                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 226                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 227                 break;
 228
 229         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 230                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 231                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
 232                 break;
 233
 234         case ICE_RXDID_COMMS_GENERIC:
 235                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
 236                 break;
 237
 238         case ICE_RXDID_COMMS_OVS:
 239                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 240                 break;
 241
 242         default:
 243                 /* update this according to the RXDID for PROTO_XTR_NONE */
 244                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 245                 break;
 246         }
 247
 248         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 249                 rxq->xtr_ol_flag = 0;
 250 }
 251
 252 static enum ice_status
 253 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 254 {
 255         struct ice_vsi *vsi = rxq->vsi;
 256         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 257         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 258         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
 259         struct ice_rlan_ctx rx_ctx;
 260         enum ice_status err;
 261         uint16_t buf_size, len;
 262         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 263         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 264         uint32_t regval;
 265
 266         /* Set buffer size as the head split is disabled. */
 267         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 268                               RTE_PKTMBUF_HEADROOM);
 269         rxq->rx_hdr_len = 0;
 270         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 271         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
 272         rxq->max_pkt_len = RTE_MIN(len,
 273                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
 274
 275         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 276                 if (rxq->max_pkt_len <= ICE_ETH_MAX_LEN ||
 277                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 278                         PMD_DRV_LOG(ERR, "maximum packet length must "
 279                                     "be larger than %u and smaller than %u,"
 280                                     "as jumbo frame is enabled",
 281                                     (uint32_t)ICE_ETH_MAX_LEN,
 282                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 283                         return -EINVAL;
 284                 }
 285         } else {
 286                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 287                     rxq->max_pkt_len > ICE_ETH_MAX_LEN) {
 288                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 289                                     "larger than %u and smaller than %u, "
 290                                     "as jumbo frame is disabled",
 291                                     (uint32_t)RTE_ETHER_MIN_LEN,
 292                                     (uint32_t)ICE_ETH_MAX_LEN);
 293                         return -EINVAL;
 294                 }
 295         }
 296
 297         memset(&rx_ctx, 0, sizeof(rx_ctx));
 298
 299         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 300         rx_ctx.qlen = rxq->nb_rx_desc;
 301         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 302         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 303         rx_ctx.dtype = 0; /* No Header Split mode */
 304 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 305         rx_ctx.dsize = 1; /* 32B descriptors */
 306 #endif
 307         rx_ctx.rxmax = rxq->max_pkt_len;
 308         /* TPH: Transaction Layer Packet (TLP) processing hints */
 309         rx_ctx.tphrdesc_ena = 1;
 310         rx_ctx.tphwdesc_ena = 1;
 311         rx_ctx.tphdata_ena = 1;
 312         rx_ctx.tphhead_ena = 1;
 313         /* Low Receive Queue Threshold defined in 64 descriptors units.
 314          * When the number of free descriptors goes below the lrxqthresh,
 315          * an immediate interrupt is triggered.
 316          */
 317         rx_ctx.lrxqthresh = 2;
 318         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 319         rx_ctx.l2tsel = 1;
 320         rx_ctx.showiv = 0;
 321         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 322
 323         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 324
 325         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 326                     rxq->port_id, rxq->queue_id, rxdid);
 327
 328         if (!(pf->supported_rxdid & BIT(rxdid))) {
 329                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 330                             rxdid);
 331                 return -EINVAL;
 332         }
 333
 334         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 335
 336         /* Enable Flexible Descriptors in the queue context which
 337          * allows this driver to select a specific receive descriptor format
 338          */
 339         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 340                 QRXFLXP_CNTXT_RXDID_IDX_M;
 341
 342         /* increasing context priority to pick up profile ID;
 343          * default is 0x01; setting to 0x03 to ensure profile
 344          * is programming if prev context is of same priority
 345          */
 346         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 347                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 348
 349         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 350
 351         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 352         if (err) {
 353                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 354                             rxq->queue_id);
 355                 return -EINVAL;
 356         }
 357         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 358         if (err) {
 359                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 360                             rxq->queue_id);
 361                 return -EINVAL;
 362         }
 363
 364         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 365                               RTE_PKTMBUF_HEADROOM);
 366
 367         /* Check if scattered RX needs to be used. */
 368         if (rxq->max_pkt_len > buf_size)
 369                 dev->data->scattered_rx = 1;
 370
 371         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 372
 373         /* Init the Rx tail register*/
 374         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 375
 376         return 0;
 377 }
 378
 379 /* Allocate mbufs for all descriptors in rx queue */
 380 static int
 381 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 382 {
 383         struct ice_rx_entry *rxe = rxq->sw_ring;
 384         uint64_t dma_addr;
 385         uint16_t i;
 386
 387         for (i = 0; i < rxq->nb_rx_desc; i++) {
 388                 volatile union ice_rx_flex_desc *rxd;
 389                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 390
 391                 if (unlikely(!mbuf)) {
 392                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 393                         return -ENOMEM;
 394                 }
 395
 396                 rte_mbuf_refcnt_set(mbuf, 1);
 397                 mbuf->next = NULL;
 398                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 399                 mbuf->nb_segs = 1;
 400                 mbuf->port = rxq->port_id;
 401
 402                 dma_addr =
 403                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 404
 405                 rxd = &rxq->rx_ring[i];
 406                 rxd->read.pkt_addr = dma_addr;
 407                 rxd->read.hdr_addr = 0;
 408 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 409                 rxd->read.rsvd1 = 0;
 410                 rxd->read.rsvd2 = 0;
 411 #endif
 412                 rxe[i].mbuf = mbuf;
 413         }
 414
 415         return 0;
 416 }
 417
 418 /* Free all mbufs for descriptors in rx queue */
 419 static void
 420 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 421 {
 422         uint16_t i;
 423
 424         if (!rxq || !rxq->sw_ring) {
 425                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 426                 return;
 427         }
 428
 429         for (i = 0; i < rxq->nb_rx_desc; i++) {
 430                 if (rxq->sw_ring[i].mbuf) {
 431                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 432                         rxq->sw_ring[i].mbuf = NULL;
 433                 }
 434         }
 435         if (rxq->rx_nb_avail == 0)
 436                 return;
 437         for (i = 0; i < rxq->rx_nb_avail; i++)
 438                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 439
 440         rxq->rx_nb_avail = 0;
 441 }
 442
 443 /* turn on or off rx queue
 444  * @q_idx: queue index in pf scope
 445  * @on: turn on or off the queue
 446  */
 447 static int
 448 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 449 {
 450         uint32_t reg;
 451         uint16_t j;
 452
 453         /* QRX_CTRL = QRX_ENA */
 454         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 455
 456         if (on) {
 457                 if (reg & QRX_CTRL_QENA_STAT_M)
 458                         return 0; /* Already on, skip */
 459                 reg |= QRX_CTRL_QENA_REQ_M;
 460         } else {
 461                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 462                         return 0; /* Already off, skip */
 463                 reg &= ~QRX_CTRL_QENA_REQ_M;
 464         }
 465
 466         /* Write the register */
 467         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 468         /* Check the result. It is said that QENA_STAT
 469          * follows the QENA_REQ not more than 10 use.
 470          * TODO: need to change the wait counter later
 471          */
 472         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 473                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 474                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 475                 if (on) {
 476                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 477                             (reg & QRX_CTRL_QENA_STAT_M))
 478                                 break;
 479                 } else {
 480                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 481                             !(reg & QRX_CTRL_QENA_STAT_M))
 482                                 break;
 483                 }
 484         }
 485
 486         /* Check if it is timeout */
 487         if (j >= ICE_CHK_Q_ENA_COUNT) {
 488                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 489                             (on ? "enable" : "disable"), q_idx);
 490                 return -ETIMEDOUT;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static inline int
 497 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 498 {
 499         int ret = 0;
 500
 501         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 502                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 503                              "rxq->rx_free_thresh=%d, "
 504                              "ICE_RX_MAX_BURST=%d",
 505                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 506                 ret = -EINVAL;
 507         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 508                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 509                              "rxq->rx_free_thresh=%d, "
 510                              "rxq->nb_rx_desc=%d",
 511                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 512                 ret = -EINVAL;
 513         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 514                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 515                              "rxq->nb_rx_desc=%d, "
 516                              "rxq->rx_free_thresh=%d",
 517                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 518                 ret = -EINVAL;
 519         }
 520
 521         return ret;
 522 }
 523
 524 /* reset fields in ice_rx_queue back to default */
 525 static void
 526 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 527 {
 528         unsigned int i;
 529         uint16_t len;
 530
 531         if (!rxq) {
 532                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 533                 return;
 534         }
 535
 536         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 537
 538         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 539                 ((volatile char *)rxq->rx_ring)[i] = 0;
 540
 541         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 542         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 543                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 544
 545         rxq->rx_nb_avail = 0;
 546         rxq->rx_next_avail = 0;
 547         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 548
 549         rxq->rx_tail = 0;
 550         rxq->nb_rx_hold = 0;
 551         rxq->pkt_first_seg = NULL;
 552         rxq->pkt_last_seg = NULL;
 553
 554         rxq->rxrearm_start = 0;
 555         rxq->rxrearm_nb = 0;
 556 }
 557
 558 int
 559 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 560 {
 561         struct ice_rx_queue *rxq;
 562         int err;
 563         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 564
 565         PMD_INIT_FUNC_TRACE();
 566
 567         if (rx_queue_id >= dev->data->nb_rx_queues) {
 568                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 569                             rx_queue_id, dev->data->nb_rx_queues);
 570                 return -EINVAL;
 571         }
 572
 573         rxq = dev->data->rx_queues[rx_queue_id];
 574         if (!rxq || !rxq->q_set) {
 575                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 576                             rx_queue_id);
 577                 return -EINVAL;
 578         }
 579
 580         err = ice_program_hw_rx_queue(rxq);
 581         if (err) {
 582                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 583                             rx_queue_id);
 584                 return -EIO;
 585         }
 586
 587         err = ice_alloc_rx_queue_mbufs(rxq);
 588         if (err) {
 589                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 590                 return -ENOMEM;
 591         }
 592
 593         /* Init the RX tail register. */
 594         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 595
 596         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 597         if (err) {
 598                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 599                             rx_queue_id);
 600
 601                 rxq->rx_rel_mbufs(rxq);
 602                 ice_reset_rx_queue(rxq);
 603                 return -EINVAL;
 604         }
 605
 606         dev->data->rx_queue_state[rx_queue_id] =
 607                 RTE_ETH_QUEUE_STATE_STARTED;
 608
 609         return 0;
 610 }
 611
 612 int
 613 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 614 {
 615         struct ice_rx_queue *rxq;
 616         int err;
 617         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 618
 619         if (rx_queue_id < dev->data->nb_rx_queues) {
 620                 rxq = dev->data->rx_queues[rx_queue_id];
 621
 622                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 623                 if (err) {
 624                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 625                                     rx_queue_id);
 626                         return -EINVAL;
 627                 }
 628                 rxq->rx_rel_mbufs(rxq);
 629                 ice_reset_rx_queue(rxq);
 630                 dev->data->rx_queue_state[rx_queue_id] =
 631                         RTE_ETH_QUEUE_STATE_STOPPED;
 632         }
 633
 634         return 0;
 635 }
 636
 637 int
 638 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 639 {
 640         struct ice_tx_queue *txq;
 641         int err;
 642         struct ice_vsi *vsi;
 643         struct ice_hw *hw;
 644         struct ice_aqc_add_tx_qgrp *txq_elem;
 645         struct ice_tlan_ctx tx_ctx;
 646         int buf_len;
 647
 648         PMD_INIT_FUNC_TRACE();
 649
 650         if (tx_queue_id >= dev->data->nb_tx_queues) {
 651                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 652                             tx_queue_id, dev->data->nb_tx_queues);
 653                 return -EINVAL;
 654         }
 655
 656         txq = dev->data->tx_queues[tx_queue_id];
 657         if (!txq || !txq->q_set) {
 658                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 659                             tx_queue_id);
 660                 return -EINVAL;
 661         }
 662
 663         buf_len = ice_struct_size(txq_elem, txqs, 1);
 664         txq_elem = ice_malloc(hw, buf_len);
 665         if (!txq_elem)
 666                 return -ENOMEM;
 667
 668         vsi = txq->vsi;
 669         hw = ICE_VSI_TO_HW(vsi);
 670
 671         memset(&tx_ctx, 0, sizeof(tx_ctx));
 672         txq_elem->num_txqs = 1;
 673         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 674
 675         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 676         tx_ctx.qlen = txq->nb_tx_desc;
 677         tx_ctx.pf_num = hw->pf_id;
 678         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 679         tx_ctx.src_vsi = vsi->vsi_id;
 680         tx_ctx.port_num = hw->port_info->lport;
 681         tx_ctx.tso_ena = 1; /* tso enable */
 682         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 683         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 684
 685         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 686                     ice_tlan_ctx_info);
 687
 688         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 689
 690         /* Init the Tx tail register*/
 691         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 692
 693         /* Fix me, we assume TC always 0 here */
 694         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 695                         txq_elem, buf_len, NULL);
 696         if (err) {
 697                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 698                 rte_free(txq_elem);
 699                 return -EIO;
 700         }
 701         /* store the schedule node id */
 702         txq->q_teid = txq_elem->txqs[0].q_teid;
 703
 704         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 705
 706         rte_free(txq_elem);
 707         return 0;
 708 }
 709
 710 static enum ice_status
 711 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 712 {
 713         struct ice_vsi *vsi = rxq->vsi;
 714         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 715         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 716         struct ice_rlan_ctx rx_ctx;
 717         enum ice_status err;
 718         uint32_t regval;
 719
 720         rxq->rx_hdr_len = 0;
 721         rxq->rx_buf_len = 1024;
 722
 723         memset(&rx_ctx, 0, sizeof(rx_ctx));
 724
 725         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 726         rx_ctx.qlen = rxq->nb_rx_desc;
 727         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 728         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 729         rx_ctx.dtype = 0; /* No Header Split mode */
 730         rx_ctx.dsize = 1; /* 32B descriptors */
 731         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 732         /* TPH: Transaction Layer Packet (TLP) processing hints */
 733         rx_ctx.tphrdesc_ena = 1;
 734         rx_ctx.tphwdesc_ena = 1;
 735         rx_ctx.tphdata_ena = 1;
 736         rx_ctx.tphhead_ena = 1;
 737         /* Low Receive Queue Threshold defined in 64 descriptors units.
 738          * When the number of free descriptors goes below the lrxqthresh,
 739          * an immediate interrupt is triggered.
 740          */
 741         rx_ctx.lrxqthresh = 2;
 742         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 743         rx_ctx.l2tsel = 1;
 744         rx_ctx.showiv = 0;
 745         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 746
 747         /* Enable Flexible Descriptors in the queue context which
 748          * allows this driver to select a specific receive descriptor format
 749          */
 750         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 751                 QRXFLXP_CNTXT_RXDID_IDX_M;
 752
 753         /* increasing context priority to pick up profile ID;
 754          * default is 0x01; setting to 0x03 to ensure profile
 755          * is programming if prev context is of same priority
 756          */
 757         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 758                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 759
 760         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 761
 762         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 763         if (err) {
 764                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 765                             rxq->queue_id);
 766                 return -EINVAL;
 767         }
 768         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 769         if (err) {
 770                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 771                             rxq->queue_id);
 772                 return -EINVAL;
 773         }
 774
 775         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 776
 777         /* Init the Rx tail register*/
 778         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 779
 780         return 0;
 781 }
 782
 783 int
 784 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 785 {
 786         struct ice_rx_queue *rxq;
 787         int err;
 788         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 789         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 790
 791         PMD_INIT_FUNC_TRACE();
 792
 793         rxq = pf->fdir.rxq;
 794         if (!rxq || !rxq->q_set) {
 795                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 796                             rx_queue_id);
 797                 return -EINVAL;
 798         }
 799
 800         err = ice_fdir_program_hw_rx_queue(rxq);
 801         if (err) {
 802                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 803                             rx_queue_id);
 804                 return -EIO;
 805         }
 806
 807         /* Init the RX tail register. */
 808         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 809
 810         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 811         if (err) {
 812                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 813                             rx_queue_id);
 814
 815                 ice_reset_rx_queue(rxq);
 816                 return -EINVAL;
 817         }
 818
 819         return 0;
 820 }
 821
 822 int
 823 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 824 {
 825         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 826         struct ice_tx_queue *txq;
 827         int err;
 828         struct ice_vsi *vsi;
 829         struct ice_hw *hw;
 830         struct ice_aqc_add_tx_qgrp *txq_elem;
 831         struct ice_tlan_ctx tx_ctx;
 832         int buf_len;
 833
 834         PMD_INIT_FUNC_TRACE();
 835
 836         txq = pf->fdir.txq;
 837         if (!txq || !txq->q_set) {
 838                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 839                             tx_queue_id);
 840                 return -EINVAL;
 841         }
 842
 843         buf_len = ice_struct_size(txq_elem, txqs, 1);
 844         txq_elem = ice_malloc(hw, buf_len);
 845         if (!txq_elem)
 846                 return -ENOMEM;
 847
 848         vsi = txq->vsi;
 849         hw = ICE_VSI_TO_HW(vsi);
 850
 851         memset(&tx_ctx, 0, sizeof(tx_ctx));
 852         txq_elem->num_txqs = 1;
 853         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 854
 855         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 856         tx_ctx.qlen = txq->nb_tx_desc;
 857         tx_ctx.pf_num = hw->pf_id;
 858         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 859         tx_ctx.src_vsi = vsi->vsi_id;
 860         tx_ctx.port_num = hw->port_info->lport;
 861         tx_ctx.tso_ena = 1; /* tso enable */
 862         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 863         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 864
 865         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 866                     ice_tlan_ctx_info);
 867
 868         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 869
 870         /* Init the Tx tail register*/
 871         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 872
 873         /* Fix me, we assume TC always 0 here */
 874         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 875                               txq_elem, buf_len, NULL);
 876         if (err) {
 877                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 878                 rte_free(txq_elem);
 879                 return -EIO;
 880         }
 881         /* store the schedule node id */
 882         txq->q_teid = txq_elem->txqs[0].q_teid;
 883
 884         rte_free(txq_elem);
 885         return 0;
 886 }
 887
 888 /* Free all mbufs for descriptors in tx queue */
 889 static void
 890 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 891 {
 892         uint16_t i;
 893
 894         if (!txq || !txq->sw_ring) {
 895                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 896                 return;
 897         }
 898
 899         for (i = 0; i < txq->nb_tx_desc; i++) {
 900                 if (txq->sw_ring[i].mbuf) {
 901                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 902                         txq->sw_ring[i].mbuf = NULL;
 903                 }
 904         }
 905 }
 906
 907 static void
 908 ice_reset_tx_queue(struct ice_tx_queue *txq)
 909 {
 910         struct ice_tx_entry *txe;
 911         uint16_t i, prev, size;
 912
 913         if (!txq) {
 914                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 915                 return;
 916         }
 917
 918         txe = txq->sw_ring;
 919         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 920         for (i = 0; i < size; i++)
 921                 ((volatile char *)txq->tx_ring)[i] = 0;
 922
 923         prev = (uint16_t)(txq->nb_tx_desc - 1);
 924         for (i = 0; i < txq->nb_tx_desc; i++) {
 925                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 926
 927                 txd->cmd_type_offset_bsz =
 928                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 929                 txe[i].mbuf =  NULL;
 930                 txe[i].last_id = i;
 931                 txe[prev].next_id = i;
 932                 prev = i;
 933         }
 934
 935         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 936         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 937
 938         txq->tx_tail = 0;
 939         txq->nb_tx_used = 0;
 940
 941         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 942         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 943 }
 944
 945 int
 946 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 947 {
 948         struct ice_tx_queue *txq;
 949         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 951         struct ice_vsi *vsi = pf->main_vsi;
 952         enum ice_status status;
 953         uint16_t q_ids[1];
 954         uint32_t q_teids[1];
 955         uint16_t q_handle = tx_queue_id;
 956
 957         if (tx_queue_id >= dev->data->nb_tx_queues) {
 958                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 959                             tx_queue_id, dev->data->nb_tx_queues);
 960                 return -EINVAL;
 961         }
 962
 963         txq = dev->data->tx_queues[tx_queue_id];
 964         if (!txq) {
 965                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 966                             tx_queue_id);
 967                 return -EINVAL;
 968         }
 969
 970         q_ids[0] = txq->reg_idx;
 971         q_teids[0] = txq->q_teid;
 972
 973         /* Fix me, we assume TC always 0 here */
 974         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 975                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 976         if (status != ICE_SUCCESS) {
 977                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 978                 return -EINVAL;
 979         }
 980
 981         txq->tx_rel_mbufs(txq);
 982         ice_reset_tx_queue(txq);
 983         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 984
 985         return 0;
 986 }
 987
 988 int
 989 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 990 {
 991         struct ice_rx_queue *rxq;
 992         int err;
 993         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 994         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 995
 996         rxq = pf->fdir.rxq;
 997
 998         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 999         if (err) {
1000                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1001                             rx_queue_id);
1002                 return -EINVAL;
1003         }
1004         rxq->rx_rel_mbufs(rxq);
1005
1006         return 0;
1007 }
1008
1009 int
1010 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1011 {
1012         struct ice_tx_queue *txq;
1013         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1015         struct ice_vsi *vsi = pf->main_vsi;
1016         enum ice_status status;
1017         uint16_t q_ids[1];
1018         uint32_t q_teids[1];
1019         uint16_t q_handle = tx_queue_id;
1020
1021         txq = pf->fdir.txq;
1022         if (!txq) {
1023                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1024                             tx_queue_id);
1025                 return -EINVAL;
1026         }
1027         vsi = txq->vsi;
1028
1029         q_ids[0] = txq->reg_idx;
1030         q_teids[0] = txq->q_teid;
1031
1032         /* Fix me, we assume TC always 0 here */
1033         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1034                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1035         if (status != ICE_SUCCESS) {
1036                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1037                 return -EINVAL;
1038         }
1039
1040         txq->tx_rel_mbufs(txq);
1041
1042         return 0;
1043 }
1044
1045 int
1046 ice_rx_queue_setup(struct rte_eth_dev *dev,
1047                    uint16_t queue_idx,
1048                    uint16_t nb_desc,
1049                    unsigned int socket_id,
1050                    const struct rte_eth_rxconf *rx_conf,
1051                    struct rte_mempool *mp)
1052 {
1053         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1054         struct ice_adapter *ad =
1055                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1056         struct ice_vsi *vsi = pf->main_vsi;
1057         struct ice_rx_queue *rxq;
1058         const struct rte_memzone *rz;
1059         uint32_t ring_size;
1060         uint16_t len;
1061         int use_def_burst_func = 1;
1062
1063         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1064             nb_desc > ICE_MAX_RING_DESC ||
1065             nb_desc < ICE_MIN_RING_DESC) {
1066                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1067                              "invalid", nb_desc);
1068                 return -EINVAL;
1069         }
1070
1071         /* Free memory if needed */
1072         if (dev->data->rx_queues[queue_idx]) {
1073                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1074                 dev->data->rx_queues[queue_idx] = NULL;
1075         }
1076
1077         /* Allocate the rx queue data structure */
1078         rxq = rte_zmalloc_socket(NULL,
1079                                  sizeof(struct ice_rx_queue),
1080                                  RTE_CACHE_LINE_SIZE,
1081                                  socket_id);
1082         if (!rxq) {
1083                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1084                              "rx queue data structure");
1085                 return -ENOMEM;
1086         }
1087         rxq->mp = mp;
1088         rxq->nb_rx_desc = nb_desc;
1089         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1090         rxq->queue_id = queue_idx;
1091
1092         rxq->reg_idx = vsi->base_queue + queue_idx;
1093         rxq->port_id = dev->data->port_id;
1094         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1095                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1096         else
1097                 rxq->crc_len = 0;
1098
1099         rxq->drop_en = rx_conf->rx_drop_en;
1100         rxq->vsi = vsi;
1101         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1102         rxq->proto_xtr = pf->proto_xtr != NULL ?
1103                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1104
1105         /* Allocate the maximun number of RX ring hardware descriptor. */
1106         len = ICE_MAX_RING_DESC;
1107
1108         /**
1109          * Allocating a little more memory because vectorized/bulk_alloc Rx
1110          * functions doesn't check boundaries each time.
1111          */
1112         len += ICE_RX_MAX_BURST;
1113
1114         /* Allocate the maximum number of RX ring hardware descriptor. */
1115         ring_size = sizeof(union ice_rx_flex_desc) * len;
1116         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1117         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1118                                       ring_size, ICE_RING_BASE_ALIGN,
1119                                       socket_id);
1120         if (!rz) {
1121                 ice_rx_queue_release(rxq);
1122                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1123                 return -ENOMEM;
1124         }
1125
1126         /* Zero all the descriptors in the ring. */
1127         memset(rz->addr, 0, ring_size);
1128
1129         rxq->rx_ring_dma = rz->iova;
1130         rxq->rx_ring = rz->addr;
1131
1132         /* always reserve more for bulk alloc */
1133         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1134
1135         /* Allocate the software ring. */
1136         rxq->sw_ring = rte_zmalloc_socket(NULL,
1137                                           sizeof(struct ice_rx_entry) * len,
1138                                           RTE_CACHE_LINE_SIZE,
1139                                           socket_id);
1140         if (!rxq->sw_ring) {
1141                 ice_rx_queue_release(rxq);
1142                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1143                 return -ENOMEM;
1144         }
1145
1146         ice_reset_rx_queue(rxq);
1147         rxq->q_set = true;
1148         dev->data->rx_queues[queue_idx] = rxq;
1149         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1150
1151         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1152
1153         if (!use_def_burst_func) {
1154                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1155                              "satisfied. Rx Burst Bulk Alloc function will be "
1156                              "used on port=%d, queue=%d.",
1157                              rxq->port_id, rxq->queue_id);
1158         } else {
1159                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1160                              "not satisfied, Scattered Rx is requested. "
1161                              "on port=%d, queue=%d.",
1162                              rxq->port_id, rxq->queue_id);
1163                 ad->rx_bulk_alloc_allowed = false;
1164         }
1165
1166         return 0;
1167 }
1168
1169 void
1170 ice_rx_queue_release(void *rxq)
1171 {
1172         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1173
1174         if (!q) {
1175                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1176                 return;
1177         }
1178
1179         q->rx_rel_mbufs(q);
1180         rte_free(q->sw_ring);
1181         rte_free(q);
1182 }
1183
1184 int
1185 ice_tx_queue_setup(struct rte_eth_dev *dev,
1186                    uint16_t queue_idx,
1187                    uint16_t nb_desc,
1188                    unsigned int socket_id,
1189                    const struct rte_eth_txconf *tx_conf)
1190 {
1191         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1192         struct ice_vsi *vsi = pf->main_vsi;
1193         struct ice_tx_queue *txq;
1194         const struct rte_memzone *tz;
1195         uint32_t ring_size;
1196         uint16_t tx_rs_thresh, tx_free_thresh;
1197         uint64_t offloads;
1198
1199         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1200
1201         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1202             nb_desc > ICE_MAX_RING_DESC ||
1203             nb_desc < ICE_MIN_RING_DESC) {
1204                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1205                              "invalid", nb_desc);
1206                 return -EINVAL;
1207         }
1208
1209         /**
1210          * The following two parameters control the setting of the RS bit on
1211          * transmit descriptors. TX descriptors will have their RS bit set
1212          * after txq->tx_rs_thresh descriptors have been used. The TX
1213          * descriptor ring will be cleaned after txq->tx_free_thresh
1214          * descriptors are used or if the number of descriptors required to
1215          * transmit a packet is greater than the number of free TX descriptors.
1216          *
1217          * The following constraints must be satisfied:
1218          *  - tx_rs_thresh must be greater than 0.
1219          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1220          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1221          *  - tx_rs_thresh must be a divisor of the ring size.
1222          *  - tx_free_thresh must be greater than 0.
1223          *  - tx_free_thresh must be less than the size of the ring minus 3.
1224          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1225          *
1226          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1227          * race condition, hence the maximum threshold constraints. When set
1228          * to zero use default values.
1229          */
1230         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1231                                     tx_conf->tx_free_thresh :
1232                                     ICE_DEFAULT_TX_FREE_THRESH);
1233         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1234         tx_rs_thresh =
1235                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1236                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1237         if (tx_conf->tx_rs_thresh)
1238                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1239         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1240                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1241                                 "exceed nb_desc. (tx_rs_thresh=%u "
1242                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1243                                 (unsigned int)tx_rs_thresh,
1244                                 (unsigned int)tx_free_thresh,
1245                                 (unsigned int)nb_desc,
1246                                 (int)dev->data->port_id,
1247                                 (int)queue_idx);
1248                 return -EINVAL;
1249         }
1250         if (tx_rs_thresh >= (nb_desc - 2)) {
1251                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1252                              "number of TX descriptors minus 2. "
1253                              "(tx_rs_thresh=%u port=%d queue=%d)",
1254                              (unsigned int)tx_rs_thresh,
1255                              (int)dev->data->port_id,
1256                              (int)queue_idx);
1257                 return -EINVAL;
1258         }
1259         if (tx_free_thresh >= (nb_desc - 3)) {
1260                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1261                              "tx_free_thresh must be less than the "
1262                              "number of TX descriptors minus 3. "
1263                              "(tx_free_thresh=%u port=%d queue=%d)",
1264                              (unsigned int)tx_free_thresh,
1265                              (int)dev->data->port_id,
1266                              (int)queue_idx);
1267                 return -EINVAL;
1268         }
1269         if (tx_rs_thresh > tx_free_thresh) {
1270                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1271                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1272                              " tx_rs_thresh=%u port=%d queue=%d)",
1273                              (unsigned int)tx_free_thresh,
1274                              (unsigned int)tx_rs_thresh,
1275                              (int)dev->data->port_id,
1276                              (int)queue_idx);
1277                 return -EINVAL;
1278         }
1279         if ((nb_desc % tx_rs_thresh) != 0) {
1280                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1281                              "number of TX descriptors. (tx_rs_thresh=%u"
1282                              " port=%d queue=%d)",
1283                              (unsigned int)tx_rs_thresh,
1284                              (int)dev->data->port_id,
1285                              (int)queue_idx);
1286                 return -EINVAL;
1287         }
1288         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1289                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1290                              "tx_rs_thresh is greater than 1. "
1291                              "(tx_rs_thresh=%u port=%d queue=%d)",
1292                              (unsigned int)tx_rs_thresh,
1293                              (int)dev->data->port_id,
1294                              (int)queue_idx);
1295                 return -EINVAL;
1296         }
1297
1298         /* Free memory if needed. */
1299         if (dev->data->tx_queues[queue_idx]) {
1300                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1301                 dev->data->tx_queues[queue_idx] = NULL;
1302         }
1303
1304         /* Allocate the TX queue data structure. */
1305         txq = rte_zmalloc_socket(NULL,
1306                                  sizeof(struct ice_tx_queue),
1307                                  RTE_CACHE_LINE_SIZE,
1308                                  socket_id);
1309         if (!txq) {
1310                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1311                              "tx queue structure");
1312                 return -ENOMEM;
1313         }
1314
1315         /* Allocate TX hardware ring descriptors. */
1316         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1317         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1318         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1319                                       ring_size, ICE_RING_BASE_ALIGN,
1320                                       socket_id);
1321         if (!tz) {
1322                 ice_tx_queue_release(txq);
1323                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1324                 return -ENOMEM;
1325         }
1326
1327         txq->nb_tx_desc = nb_desc;
1328         txq->tx_rs_thresh = tx_rs_thresh;
1329         txq->tx_free_thresh = tx_free_thresh;
1330         txq->pthresh = tx_conf->tx_thresh.pthresh;
1331         txq->hthresh = tx_conf->tx_thresh.hthresh;
1332         txq->wthresh = tx_conf->tx_thresh.wthresh;
1333         txq->queue_id = queue_idx;
1334
1335         txq->reg_idx = vsi->base_queue + queue_idx;
1336         txq->port_id = dev->data->port_id;
1337         txq->offloads = offloads;
1338         txq->vsi = vsi;
1339         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1340
1341         txq->tx_ring_dma = tz->iova;
1342         txq->tx_ring = tz->addr;
1343
1344         /* Allocate software ring */
1345         txq->sw_ring =
1346                 rte_zmalloc_socket(NULL,
1347                                    sizeof(struct ice_tx_entry) * nb_desc,
1348                                    RTE_CACHE_LINE_SIZE,
1349                                    socket_id);
1350         if (!txq->sw_ring) {
1351                 ice_tx_queue_release(txq);
1352                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1353                 return -ENOMEM;
1354         }
1355
1356         ice_reset_tx_queue(txq);
1357         txq->q_set = true;
1358         dev->data->tx_queues[queue_idx] = txq;
1359         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1360         ice_set_tx_function_flag(dev, txq);
1361
1362         return 0;
1363 }
1364
1365 void
1366 ice_tx_queue_release(void *txq)
1367 {
1368         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1369
1370         if (!q) {
1371                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1372                 return;
1373         }
1374
1375         q->tx_rel_mbufs(q);
1376         rte_free(q->sw_ring);
1377         rte_free(q);
1378 }
1379
1380 void
1381 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1382                  struct rte_eth_rxq_info *qinfo)
1383 {
1384         struct ice_rx_queue *rxq;
1385
1386         rxq = dev->data->rx_queues[queue_id];
1387
1388         qinfo->mp = rxq->mp;
1389         qinfo->scattered_rx = dev->data->scattered_rx;
1390         qinfo->nb_desc = rxq->nb_rx_desc;
1391
1392         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1393         qinfo->conf.rx_drop_en = rxq->drop_en;
1394         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1395 }
1396
1397 void
1398 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1399                  struct rte_eth_txq_info *qinfo)
1400 {
1401         struct ice_tx_queue *txq;
1402
1403         txq = dev->data->tx_queues[queue_id];
1404
1405         qinfo->nb_desc = txq->nb_tx_desc;
1406
1407         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1408         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1409         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1410
1411         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1412         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1413         qinfo->conf.offloads = txq->offloads;
1414         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1415 }
1416
1417 uint32_t
1418 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1419 {
1420 #define ICE_RXQ_SCAN_INTERVAL 4
1421         volatile union ice_rx_flex_desc *rxdp;
1422         struct ice_rx_queue *rxq;
1423         uint16_t desc = 0;
1424
1425         rxq = dev->data->rx_queues[rx_queue_id];
1426         rxdp = &rxq->rx_ring[rxq->rx_tail];
1427         while ((desc < rxq->nb_rx_desc) &&
1428                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1429                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1430                 /**
1431                  * Check the DD bit of a rx descriptor of each 4 in a group,
1432                  * to avoid checking too frequently and downgrading performance
1433                  * too much.
1434                  */
1435                 desc += ICE_RXQ_SCAN_INTERVAL;
1436                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1437                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1438                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1439                                  desc - rxq->nb_rx_desc]);
1440         }
1441
1442         return desc;
1443 }
1444
1445 #define ICE_RX_FLEX_ERR0_BITS   \
1446         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1447          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1448          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1449          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1450          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1451          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1452
1453 /* Rx L3/L4 checksum */
1454 static inline uint64_t
1455 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1456 {
1457         uint64_t flags = 0;
1458
1459         /* check if HW has decoded the packet and checksum */
1460         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1461                 return 0;
1462
1463         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1464                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1465                 return flags;
1466         }
1467
1468         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1469                 flags |= PKT_RX_IP_CKSUM_BAD;
1470         else
1471                 flags |= PKT_RX_IP_CKSUM_GOOD;
1472
1473         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1474                 flags |= PKT_RX_L4_CKSUM_BAD;
1475         else
1476                 flags |= PKT_RX_L4_CKSUM_GOOD;
1477
1478         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1479                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1480
1481         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1482                 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1483         else
1484                 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1485
1486         return flags;
1487 }
1488
1489 static inline void
1490 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1491 {
1492         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1493             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1494                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1495                 mb->vlan_tci =
1496                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1497                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1498                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1499         } else {
1500                 mb->vlan_tci = 0;
1501         }
1502
1503 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1504         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1505             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1506                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1507                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1508                 mb->vlan_tci_outer = mb->vlan_tci;
1509                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1510                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1511                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1512                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1513         } else {
1514                 mb->vlan_tci_outer = 0;
1515         }
1516 #endif
1517         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1518                    mb->vlan_tci, mb->vlan_tci_outer);
1519 }
1520
1521 #define ICE_LOOK_AHEAD 8
1522 #if (ICE_LOOK_AHEAD != 8)
1523 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1524 #endif
1525 static inline int
1526 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1527 {
1528         volatile union ice_rx_flex_desc *rxdp;
1529         struct ice_rx_entry *rxep;
1530         struct rte_mbuf *mb;
1531         uint16_t stat_err0;
1532         uint16_t pkt_len;
1533         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1534         int32_t i, j, nb_rx = 0;
1535         uint64_t pkt_flags = 0;
1536         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1537
1538         rxdp = &rxq->rx_ring[rxq->rx_tail];
1539         rxep = &rxq->sw_ring[rxq->rx_tail];
1540
1541         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1542
1543         /* Make sure there is at least 1 packet to receive */
1544         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1545                 return 0;
1546
1547         /**
1548          * Scan LOOK_AHEAD descriptors at a time to determine which
1549          * descriptors reference packets that are ready to be received.
1550          */
1551         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1552              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1553                 /* Read desc statuses backwards to avoid race condition */
1554                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1555                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1556
1557                 rte_smp_rmb();
1558
1559                 /* Compute how many status bits were set */
1560                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1561                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1562
1563                 nb_rx += nb_dd;
1564
1565                 /* Translate descriptor info to mbuf parameters */
1566                 for (j = 0; j < nb_dd; j++) {
1567                         mb = rxep[j].mbuf;
1568                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1569                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1570                         mb->data_len = pkt_len;
1571                         mb->pkt_len = pkt_len;
1572                         mb->ol_flags = 0;
1573                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1574                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1575                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1576                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1577                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1578                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1579
1580                         mb->ol_flags |= pkt_flags;
1581                 }
1582
1583                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1584                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1585
1586                 if (nb_dd != ICE_LOOK_AHEAD)
1587                         break;
1588         }
1589
1590         /* Clear software ring entries */
1591         for (i = 0; i < nb_rx; i++)
1592                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1593
1594         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1595                    "port_id=%u, queue_id=%u, nb_rx=%d",
1596                    rxq->port_id, rxq->queue_id, nb_rx);
1597
1598         return nb_rx;
1599 }
1600
1601 static inline uint16_t
1602 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1603                        struct rte_mbuf **rx_pkts,
1604                        uint16_t nb_pkts)
1605 {
1606         uint16_t i;
1607         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1608
1609         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1610
1611         for (i = 0; i < nb_pkts; i++)
1612                 rx_pkts[i] = stage[i];
1613
1614         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1615         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1616
1617         return nb_pkts;
1618 }
1619
1620 static inline int
1621 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1622 {
1623         volatile union ice_rx_flex_desc *rxdp;
1624         struct ice_rx_entry *rxep;
1625         struct rte_mbuf *mb;
1626         uint16_t alloc_idx, i;
1627         uint64_t dma_addr;
1628         int diag;
1629
1630         /* Allocate buffers in bulk */
1631         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1632                                (rxq->rx_free_thresh - 1));
1633         rxep = &rxq->sw_ring[alloc_idx];
1634         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1635                                     rxq->rx_free_thresh);
1636         if (unlikely(diag != 0)) {
1637                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1638                 return -ENOMEM;
1639         }
1640
1641         rxdp = &rxq->rx_ring[alloc_idx];
1642         for (i = 0; i < rxq->rx_free_thresh; i++) {
1643                 if (likely(i < (rxq->rx_free_thresh - 1)))
1644                         /* Prefetch next mbuf */
1645                         rte_prefetch0(rxep[i + 1].mbuf);
1646
1647                 mb = rxep[i].mbuf;
1648                 rte_mbuf_refcnt_set(mb, 1);
1649                 mb->next = NULL;
1650                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1651                 mb->nb_segs = 1;
1652                 mb->port = rxq->port_id;
1653                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1654                 rxdp[i].read.hdr_addr = 0;
1655                 rxdp[i].read.pkt_addr = dma_addr;
1656         }
1657
1658         /* Update rx tail regsiter */
1659         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1660
1661         rxq->rx_free_trigger =
1662                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1663         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1664                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1665
1666         return 0;
1667 }
1668
1669 static inline uint16_t
1670 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1671 {
1672         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1673         uint16_t nb_rx = 0;
1674         struct rte_eth_dev *dev;
1675
1676         if (!nb_pkts)
1677                 return 0;
1678
1679         if (rxq->rx_nb_avail)
1680                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1681
1682         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1683         rxq->rx_next_avail = 0;
1684         rxq->rx_nb_avail = nb_rx;
1685         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1686
1687         if (rxq->rx_tail > rxq->rx_free_trigger) {
1688                 if (ice_rx_alloc_bufs(rxq) != 0) {
1689                         uint16_t i, j;
1690
1691                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1692                         dev->data->rx_mbuf_alloc_failed +=
1693                                 rxq->rx_free_thresh;
1694                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1695                                    "port_id=%u, queue_id=%u",
1696                                    rxq->port_id, rxq->queue_id);
1697                         rxq->rx_nb_avail = 0;
1698                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1699                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1700                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1701
1702                         return 0;
1703                 }
1704         }
1705
1706         if (rxq->rx_tail >= rxq->nb_rx_desc)
1707                 rxq->rx_tail = 0;
1708
1709         if (rxq->rx_nb_avail)
1710                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1711
1712         return 0;
1713 }
1714
1715 static uint16_t
1716 ice_recv_pkts_bulk_alloc(void *rx_queue,
1717                          struct rte_mbuf **rx_pkts,
1718                          uint16_t nb_pkts)
1719 {
1720         uint16_t nb_rx = 0;
1721         uint16_t n;
1722         uint16_t count;
1723
1724         if (unlikely(nb_pkts == 0))
1725                 return nb_rx;
1726
1727         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1728                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1729
1730         while (nb_pkts) {
1731                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1732                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1733                 nb_rx = (uint16_t)(nb_rx + count);
1734                 nb_pkts = (uint16_t)(nb_pkts - count);
1735                 if (count < n)
1736                         break;
1737         }
1738
1739         return nb_rx;
1740 }
1741
1742 static uint16_t
1743 ice_recv_scattered_pkts(void *rx_queue,
1744                         struct rte_mbuf **rx_pkts,
1745                         uint16_t nb_pkts)
1746 {
1747         struct ice_rx_queue *rxq = rx_queue;
1748         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1749         volatile union ice_rx_flex_desc *rxdp;
1750         union ice_rx_flex_desc rxd;
1751         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1752         struct ice_rx_entry *rxe;
1753         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1754         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1755         struct rte_mbuf *nmb; /* new allocated mbuf */
1756         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1757         uint16_t rx_id = rxq->rx_tail;
1758         uint16_t nb_rx = 0;
1759         uint16_t nb_hold = 0;
1760         uint16_t rx_packet_len;
1761         uint16_t rx_stat_err0;
1762         uint64_t dma_addr;
1763         uint64_t pkt_flags;
1764         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1765         struct rte_eth_dev *dev;
1766
1767         while (nb_rx < nb_pkts) {
1768                 rxdp = &rx_ring[rx_id];
1769                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1770
1771                 /* Check the DD bit first */
1772                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1773                         break;
1774
1775                 /* allocate mbuf */
1776                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1777                 if (unlikely(!nmb)) {
1778                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1779                         dev->data->rx_mbuf_alloc_failed++;
1780                         break;
1781                 }
1782                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1783
1784                 nb_hold++;
1785                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1786                 rx_id++;
1787                 if (unlikely(rx_id == rxq->nb_rx_desc))
1788                         rx_id = 0;
1789
1790                 /* Prefetch next mbuf */
1791                 rte_prefetch0(sw_ring[rx_id].mbuf);
1792
1793                 /**
1794                  * When next RX descriptor is on a cache line boundary,
1795                  * prefetch the next 4 RX descriptors and next 8 pointers
1796                  * to mbufs.
1797                  */
1798                 if ((rx_id & 0x3) == 0) {
1799                         rte_prefetch0(&rx_ring[rx_id]);
1800                         rte_prefetch0(&sw_ring[rx_id]);
1801                 }
1802
1803                 rxm = rxe->mbuf;
1804                 rxe->mbuf = nmb;
1805                 dma_addr =
1806                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1807
1808                 /* Set data buffer address and data length of the mbuf */
1809                 rxdp->read.hdr_addr = 0;
1810                 rxdp->read.pkt_addr = dma_addr;
1811                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1812                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1813                 rxm->data_len = rx_packet_len;
1814                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1815
1816                 /**
1817                  * If this is the first buffer of the received packet, set the
1818                  * pointer to the first mbuf of the packet and initialize its
1819                  * context. Otherwise, update the total length and the number
1820                  * of segments of the current scattered packet, and update the
1821                  * pointer to the last mbuf of the current packet.
1822                  */
1823                 if (!first_seg) {
1824                         first_seg = rxm;
1825                         first_seg->nb_segs = 1;
1826                         first_seg->pkt_len = rx_packet_len;
1827                 } else {
1828                         first_seg->pkt_len =
1829                                 (uint16_t)(first_seg->pkt_len +
1830                                            rx_packet_len);
1831                         first_seg->nb_segs++;
1832                         last_seg->next = rxm;
1833                 }
1834
1835                 /**
1836                  * If this is not the last buffer of the received packet,
1837                  * update the pointer to the last mbuf of the current scattered
1838                  * packet and continue to parse the RX ring.
1839                  */
1840                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1841                         last_seg = rxm;
1842                         continue;
1843                 }
1844
1845                 /**
1846                  * This is the last buffer of the received packet. If the CRC
1847                  * is not stripped by the hardware:
1848                  *  - Subtract the CRC length from the total packet length.
1849                  *  - If the last buffer only contains the whole CRC or a part
1850                  *  of it, free the mbuf associated to the last buffer. If part
1851                  *  of the CRC is also contained in the previous mbuf, subtract
1852                  *  the length of that CRC part from the data length of the
1853                  *  previous mbuf.
1854                  */
1855                 rxm->next = NULL;
1856                 if (unlikely(rxq->crc_len > 0)) {
1857                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1858                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1859                                 rte_pktmbuf_free_seg(rxm);
1860                                 first_seg->nb_segs--;
1861                                 last_seg->data_len =
1862                                         (uint16_t)(last_seg->data_len -
1863                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1864                                 last_seg->next = NULL;
1865                         } else
1866                                 rxm->data_len = (uint16_t)(rx_packet_len -
1867                                                            RTE_ETHER_CRC_LEN);
1868                 }
1869
1870                 first_seg->port = rxq->port_id;
1871                 first_seg->ol_flags = 0;
1872                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1873                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1874                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1875                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1876                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1877                 first_seg->ol_flags |= pkt_flags;
1878                 /* Prefetch data of first segment, if configured to do so. */
1879                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1880                                           first_seg->data_off));
1881                 rx_pkts[nb_rx++] = first_seg;
1882                 first_seg = NULL;
1883         }
1884
1885         /* Record index of the next RX descriptor to probe. */
1886         rxq->rx_tail = rx_id;
1887         rxq->pkt_first_seg = first_seg;
1888         rxq->pkt_last_seg = last_seg;
1889
1890         /**
1891          * If the number of free RX descriptors is greater than the RX free
1892          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1893          * register. Update the RDT with the value of the last processed RX
1894          * descriptor minus 1, to guarantee that the RDT register is never
1895          * equal to the RDH register, which creates a "full" ring situtation
1896          * from the hardware point of view.
1897          */
1898         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1899         if (nb_hold > rxq->rx_free_thresh) {
1900                 rx_id = (uint16_t)(rx_id == 0 ?
1901                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1902                 /* write TAIL register */
1903                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1904                 nb_hold = 0;
1905         }
1906         rxq->nb_rx_hold = nb_hold;
1907
1908         /* return received packet in the burst */
1909         return nb_rx;
1910 }
1911
1912 const uint32_t *
1913 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1914 {
1915         struct ice_adapter *ad =
1916                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1917         const uint32_t *ptypes;
1918
1919         static const uint32_t ptypes_os[] = {
1920                 /* refers to ice_get_default_pkt_type() */
1921                 RTE_PTYPE_L2_ETHER,
1922                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1923                 RTE_PTYPE_L2_ETHER_LLDP,
1924                 RTE_PTYPE_L2_ETHER_ARP,
1925                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1926                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1927                 RTE_PTYPE_L4_FRAG,
1928                 RTE_PTYPE_L4_ICMP,
1929                 RTE_PTYPE_L4_NONFRAG,
1930                 RTE_PTYPE_L4_SCTP,
1931                 RTE_PTYPE_L4_TCP,
1932                 RTE_PTYPE_L4_UDP,
1933                 RTE_PTYPE_TUNNEL_GRENAT,
1934                 RTE_PTYPE_TUNNEL_IP,
1935                 RTE_PTYPE_INNER_L2_ETHER,
1936                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1937                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1938                 RTE_PTYPE_INNER_L4_FRAG,
1939                 RTE_PTYPE_INNER_L4_ICMP,
1940                 RTE_PTYPE_INNER_L4_NONFRAG,
1941                 RTE_PTYPE_INNER_L4_SCTP,
1942                 RTE_PTYPE_INNER_L4_TCP,
1943                 RTE_PTYPE_INNER_L4_UDP,
1944                 RTE_PTYPE_UNKNOWN
1945         };
1946
1947         static const uint32_t ptypes_comms[] = {
1948                 /* refers to ice_get_default_pkt_type() */
1949                 RTE_PTYPE_L2_ETHER,
1950                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1951                 RTE_PTYPE_L2_ETHER_LLDP,
1952                 RTE_PTYPE_L2_ETHER_ARP,
1953                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1954                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1955                 RTE_PTYPE_L4_FRAG,
1956                 RTE_PTYPE_L4_ICMP,
1957                 RTE_PTYPE_L4_NONFRAG,
1958                 RTE_PTYPE_L4_SCTP,
1959                 RTE_PTYPE_L4_TCP,
1960                 RTE_PTYPE_L4_UDP,
1961                 RTE_PTYPE_TUNNEL_GRENAT,
1962                 RTE_PTYPE_TUNNEL_IP,
1963                 RTE_PTYPE_INNER_L2_ETHER,
1964                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1965                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1966                 RTE_PTYPE_INNER_L4_FRAG,
1967                 RTE_PTYPE_INNER_L4_ICMP,
1968                 RTE_PTYPE_INNER_L4_NONFRAG,
1969                 RTE_PTYPE_INNER_L4_SCTP,
1970                 RTE_PTYPE_INNER_L4_TCP,
1971                 RTE_PTYPE_INNER_L4_UDP,
1972                 RTE_PTYPE_TUNNEL_GTPC,
1973                 RTE_PTYPE_TUNNEL_GTPU,
1974                 RTE_PTYPE_L2_ETHER_PPPOE,
1975                 RTE_PTYPE_UNKNOWN
1976         };
1977
1978         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1979                 ptypes = ptypes_comms;
1980         else
1981                 ptypes = ptypes_os;
1982
1983         if (dev->rx_pkt_burst == ice_recv_pkts ||
1984             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1985             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1986                 return ptypes;
1987
1988 #ifdef RTE_ARCH_X86
1989         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1990             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1991 #ifdef CC_AVX512_SUPPORT
1992             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
1993             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
1994 #endif
1995             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1996             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1997                 return ptypes;
1998 #endif
1999
2000         return NULL;
2001 }
2002
2003 int
2004 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2005 {
2006         volatile union ice_rx_flex_desc *rxdp;
2007         struct ice_rx_queue *rxq = rx_queue;
2008         uint32_t desc;
2009
2010         if (unlikely(offset >= rxq->nb_rx_desc))
2011                 return -EINVAL;
2012
2013         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2014                 return RTE_ETH_RX_DESC_UNAVAIL;
2015
2016         desc = rxq->rx_tail + offset;
2017         if (desc >= rxq->nb_rx_desc)
2018                 desc -= rxq->nb_rx_desc;
2019
2020         rxdp = &rxq->rx_ring[desc];
2021         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2022             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2023                 return RTE_ETH_RX_DESC_DONE;
2024
2025         return RTE_ETH_RX_DESC_AVAIL;
2026 }
2027
2028 int
2029 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2030 {
2031         struct ice_tx_queue *txq = tx_queue;
2032         volatile uint64_t *status;
2033         uint64_t mask, expect;
2034         uint32_t desc;
2035
2036         if (unlikely(offset >= txq->nb_tx_desc))
2037                 return -EINVAL;
2038
2039         desc = txq->tx_tail + offset;
2040         /* go to next desc that has the RS bit */
2041         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2042                 txq->tx_rs_thresh;
2043         if (desc >= txq->nb_tx_desc) {
2044                 desc -= txq->nb_tx_desc;
2045                 if (desc >= txq->nb_tx_desc)
2046                         desc -= txq->nb_tx_desc;
2047         }
2048
2049         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2050         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2051         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2052                                   ICE_TXD_QW1_DTYPE_S);
2053         if ((*status & mask) == expect)
2054                 return RTE_ETH_TX_DESC_DONE;
2055
2056         return RTE_ETH_TX_DESC_FULL;
2057 }
2058
2059 void
2060 ice_free_queues(struct rte_eth_dev *dev)
2061 {
2062         uint16_t i;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2067                 if (!dev->data->rx_queues[i])
2068                         continue;
2069                 ice_rx_queue_release(dev->data->rx_queues[i]);
2070                 dev->data->rx_queues[i] = NULL;
2071                 rte_eth_dma_zone_free(dev, "rx_ring", i);
2072         }
2073         dev->data->nb_rx_queues = 0;
2074
2075         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2076                 if (!dev->data->tx_queues[i])
2077                         continue;
2078                 ice_tx_queue_release(dev->data->tx_queues[i]);
2079                 dev->data->tx_queues[i] = NULL;
2080                 rte_eth_dma_zone_free(dev, "tx_ring", i);
2081         }
2082         dev->data->nb_tx_queues = 0;
2083 }
2084
2085 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2086 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2087
2088 int
2089 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2090 {
2091         struct ice_tx_queue *txq;
2092         const struct rte_memzone *tz = NULL;
2093         uint32_t ring_size;
2094         struct rte_eth_dev *dev;
2095
2096         if (!pf) {
2097                 PMD_DRV_LOG(ERR, "PF is not available");
2098                 return -EINVAL;
2099         }
2100
2101         dev = pf->adapter->eth_dev;
2102
2103         /* Allocate the TX queue data structure. */
2104         txq = rte_zmalloc_socket("ice fdir tx queue",
2105                                  sizeof(struct ice_tx_queue),
2106                                  RTE_CACHE_LINE_SIZE,
2107                                  SOCKET_ID_ANY);
2108         if (!txq) {
2109                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2110                             "tx queue structure.");
2111                 return -ENOMEM;
2112         }
2113
2114         /* Allocate TX hardware ring descriptors. */
2115         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2116         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2117
2118         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2119                                       ICE_FDIR_QUEUE_ID, ring_size,
2120                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2121         if (!tz) {
2122                 ice_tx_queue_release(txq);
2123                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2124                 return -ENOMEM;
2125         }
2126
2127         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2128         txq->queue_id = ICE_FDIR_QUEUE_ID;
2129         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2130         txq->vsi = pf->fdir.fdir_vsi;
2131
2132         txq->tx_ring_dma = tz->iova;
2133         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2134         /*
2135          * don't need to allocate software ring and reset for the fdir
2136          * program queue just set the queue has been configured.
2137          */
2138         txq->q_set = true;
2139         pf->fdir.txq = txq;
2140
2141         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2142
2143         return ICE_SUCCESS;
2144 }
2145
2146 int
2147 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2148 {
2149         struct ice_rx_queue *rxq;
2150         const struct rte_memzone *rz = NULL;
2151         uint32_t ring_size;
2152         struct rte_eth_dev *dev;
2153
2154         if (!pf) {
2155                 PMD_DRV_LOG(ERR, "PF is not available");
2156                 return -EINVAL;
2157         }
2158
2159         dev = pf->adapter->eth_dev;
2160
2161         /* Allocate the RX queue data structure. */
2162         rxq = rte_zmalloc_socket("ice fdir rx queue",
2163                                  sizeof(struct ice_rx_queue),
2164                                  RTE_CACHE_LINE_SIZE,
2165                                  SOCKET_ID_ANY);
2166         if (!rxq) {
2167                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2168                             "rx queue structure.");
2169                 return -ENOMEM;
2170         }
2171
2172         /* Allocate RX hardware ring descriptors. */
2173         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2174         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2175
2176         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2177                                       ICE_FDIR_QUEUE_ID, ring_size,
2178                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2179         if (!rz) {
2180                 ice_rx_queue_release(rxq);
2181                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2182                 return -ENOMEM;
2183         }
2184
2185         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2186         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2187         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2188         rxq->vsi = pf->fdir.fdir_vsi;
2189
2190         rxq->rx_ring_dma = rz->iova;
2191         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2192                sizeof(union ice_32byte_rx_desc));
2193         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2194
2195         /*
2196          * Don't need to allocate software ring and reset for the fdir
2197          * rx queue, just set the queue has been configured.
2198          */
2199         rxq->q_set = true;
2200         pf->fdir.rxq = rxq;
2201
2202         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2203
2204         return ICE_SUCCESS;
2205 }
2206
2207 uint16_t
2208 ice_recv_pkts(void *rx_queue,
2209               struct rte_mbuf **rx_pkts,
2210               uint16_t nb_pkts)
2211 {
2212         struct ice_rx_queue *rxq = rx_queue;
2213         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2214         volatile union ice_rx_flex_desc *rxdp;
2215         union ice_rx_flex_desc rxd;
2216         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2217         struct ice_rx_entry *rxe;
2218         struct rte_mbuf *nmb; /* new allocated mbuf */
2219         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2220         uint16_t rx_id = rxq->rx_tail;
2221         uint16_t nb_rx = 0;
2222         uint16_t nb_hold = 0;
2223         uint16_t rx_packet_len;
2224         uint16_t rx_stat_err0;
2225         uint64_t dma_addr;
2226         uint64_t pkt_flags;
2227         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2228         struct rte_eth_dev *dev;
2229
2230         while (nb_rx < nb_pkts) {
2231                 rxdp = &rx_ring[rx_id];
2232                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2233
2234                 /* Check the DD bit first */
2235                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2236                         break;
2237
2238                 /* allocate mbuf */
2239                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2240                 if (unlikely(!nmb)) {
2241                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2242                         dev->data->rx_mbuf_alloc_failed++;
2243                         break;
2244                 }
2245                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2246
2247                 nb_hold++;
2248                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2249                 rx_id++;
2250                 if (unlikely(rx_id == rxq->nb_rx_desc))
2251                         rx_id = 0;
2252                 rxm = rxe->mbuf;
2253                 rxe->mbuf = nmb;
2254                 dma_addr =
2255                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2256
2257                 /**
2258                  * fill the read format of descriptor with physic address in
2259                  * new allocated mbuf: nmb
2260                  */
2261                 rxdp->read.hdr_addr = 0;
2262                 rxdp->read.pkt_addr = dma_addr;
2263
2264                 /* calculate rx_packet_len of the received pkt */
2265                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2266                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2267
2268                 /* fill old mbuf with received descriptor: rxd */
2269                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2270                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2271                 rxm->nb_segs = 1;
2272                 rxm->next = NULL;
2273                 rxm->pkt_len = rx_packet_len;
2274                 rxm->data_len = rx_packet_len;
2275                 rxm->port = rxq->port_id;
2276                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2277                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2278                 ice_rxd_to_vlan_tci(rxm, &rxd);
2279                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2280                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2281                 rxm->ol_flags |= pkt_flags;
2282                 /* copy old mbuf to rx_pkts */
2283                 rx_pkts[nb_rx++] = rxm;
2284         }
2285         rxq->rx_tail = rx_id;
2286         /**
2287          * If the number of free RX descriptors is greater than the RX free
2288          * threshold of the queue, advance the receive tail register of queue.
2289          * Update that register with the value of the last processed RX
2290          * descriptor minus 1.
2291          */
2292         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2293         if (nb_hold > rxq->rx_free_thresh) {
2294                 rx_id = (uint16_t)(rx_id == 0 ?
2295                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2296                 /* write TAIL register */
2297                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2298                 nb_hold = 0;
2299         }
2300         rxq->nb_rx_hold = nb_hold;
2301
2302         /* return received packet in the burst */
2303         return nb_rx;
2304 }
2305
2306 static inline void
2307 ice_parse_tunneling_params(uint64_t ol_flags,
2308                             union ice_tx_offload tx_offload,
2309                             uint32_t *cd_tunneling)
2310 {
2311         /* EIPT: External (outer) IP header type */
2312         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2313                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2314         else if (ol_flags & PKT_TX_OUTER_IPV4)
2315                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2316         else if (ol_flags & PKT_TX_OUTER_IPV6)
2317                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2318
2319         /* EIPLEN: External (outer) IP header length, in DWords */
2320         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2321                 ICE_TXD_CTX_QW0_EIPLEN_S;
2322
2323         /* L4TUNT: L4 Tunneling Type */
2324         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2325         case PKT_TX_TUNNEL_IPIP:
2326                 /* for non UDP / GRE tunneling, set to 00b */
2327                 break;
2328         case PKT_TX_TUNNEL_VXLAN:
2329         case PKT_TX_TUNNEL_GTP:
2330         case PKT_TX_TUNNEL_GENEVE:
2331                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2332                 break;
2333         case PKT_TX_TUNNEL_GRE:
2334                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2335                 break;
2336         default:
2337                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2338                 return;
2339         }
2340
2341         /* L4TUNLEN: L4 Tunneling Length, in Words
2342          *
2343          * We depend on app to set rte_mbuf.l2_len correctly.
2344          * For IP in GRE it should be set to the length of the GRE
2345          * header;
2346          * For MAC in GRE or MAC in UDP it should be set to the length
2347          * of the GRE or UDP headers plus the inner MAC up to including
2348          * its last Ethertype.
2349          * If MPLS labels exists, it should include them as well.
2350          */
2351         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2352                 ICE_TXD_CTX_QW0_NATLEN_S;
2353
2354         /**
2355          * Calculate the tunneling UDP checksum.
2356          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2357          */
2358         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2359             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2360                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2361 }
2362
2363 static inline void
2364 ice_txd_enable_checksum(uint64_t ol_flags,
2365                         uint32_t *td_cmd,
2366                         uint32_t *td_offset,
2367                         union ice_tx_offload tx_offload)
2368 {
2369         /* Set MACLEN */
2370         if (ol_flags & PKT_TX_TUNNEL_MASK)
2371                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2372                         << ICE_TX_DESC_LEN_MACLEN_S;
2373         else
2374                 *td_offset |= (tx_offload.l2_len >> 1)
2375                         << ICE_TX_DESC_LEN_MACLEN_S;
2376
2377         /* Enable L3 checksum offloads */
2378         if (ol_flags & PKT_TX_IP_CKSUM) {
2379                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2380                 *td_offset |= (tx_offload.l3_len >> 2) <<
2381                               ICE_TX_DESC_LEN_IPLEN_S;
2382         } else if (ol_flags & PKT_TX_IPV4) {
2383                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2384                 *td_offset |= (tx_offload.l3_len >> 2) <<
2385                               ICE_TX_DESC_LEN_IPLEN_S;
2386         } else if (ol_flags & PKT_TX_IPV6) {
2387                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2388                 *td_offset |= (tx_offload.l3_len >> 2) <<
2389                               ICE_TX_DESC_LEN_IPLEN_S;
2390         }
2391
2392         if (ol_flags & PKT_TX_TCP_SEG) {
2393                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2394                 *td_offset |= (tx_offload.l4_len >> 2) <<
2395                               ICE_TX_DESC_LEN_L4_LEN_S;
2396                 return;
2397         }
2398
2399         /* Enable L4 checksum offloads */
2400         switch (ol_flags & PKT_TX_L4_MASK) {
2401         case PKT_TX_TCP_CKSUM:
2402                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2403                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2404                               ICE_TX_DESC_LEN_L4_LEN_S;
2405                 break;
2406         case PKT_TX_SCTP_CKSUM:
2407                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2408                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2409                               ICE_TX_DESC_LEN_L4_LEN_S;
2410                 break;
2411         case PKT_TX_UDP_CKSUM:
2412                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2413                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2414                               ICE_TX_DESC_LEN_L4_LEN_S;
2415                 break;
2416         default:
2417                 break;
2418         }
2419 }
2420
2421 static inline int
2422 ice_xmit_cleanup(struct ice_tx_queue *txq)
2423 {
2424         struct ice_tx_entry *sw_ring = txq->sw_ring;
2425         volatile struct ice_tx_desc *txd = txq->tx_ring;
2426         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2427         uint16_t nb_tx_desc = txq->nb_tx_desc;
2428         uint16_t desc_to_clean_to;
2429         uint16_t nb_tx_to_clean;
2430
2431         /* Determine the last descriptor needing to be cleaned */
2432         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2433         if (desc_to_clean_to >= nb_tx_desc)
2434                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2435
2436         /* Check to make sure the last descriptor to clean is done */
2437         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2438         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2439             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2440                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2441                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2442                            desc_to_clean_to,
2443                            txq->port_id, txq->queue_id,
2444                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2445                 /* Failed to clean any descriptors */
2446                 return -1;
2447         }
2448
2449         /* Figure out how many descriptors will be cleaned */
2450         if (last_desc_cleaned > desc_to_clean_to)
2451                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2452                                             desc_to_clean_to);
2453         else
2454                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2455                                             last_desc_cleaned);
2456
2457         /* The last descriptor to clean is done, so that means all the
2458          * descriptors from the last descriptor that was cleaned
2459          * up to the last descriptor with the RS bit set
2460          * are done. Only reset the threshold descriptor.
2461          */
2462         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2463
2464         /* Update the txq to reflect the last descriptor that was cleaned */
2465         txq->last_desc_cleaned = desc_to_clean_to;
2466         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2467
2468         return 0;
2469 }
2470
2471 /* Construct the tx flags */
2472 static inline uint64_t
2473 ice_build_ctob(uint32_t td_cmd,
2474                uint32_t td_offset,
2475                uint16_t size,
2476                uint32_t td_tag)
2477 {
2478         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2479                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2480                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2481                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2482                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2483 }
2484
2485 /* Check if the context descriptor is needed for TX offloading */
2486 static inline uint16_t
2487 ice_calc_context_desc(uint64_t flags)
2488 {
2489         static uint64_t mask = PKT_TX_TCP_SEG |
2490                 PKT_TX_QINQ |
2491                 PKT_TX_OUTER_IP_CKSUM |
2492                 PKT_TX_TUNNEL_MASK;
2493
2494         return (flags & mask) ? 1 : 0;
2495 }
2496
2497 /* set ice TSO context descriptor */
2498 static inline uint64_t
2499 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2500 {
2501         uint64_t ctx_desc = 0;
2502         uint32_t cd_cmd, hdr_len, cd_tso_len;
2503
2504         if (!tx_offload.l4_len) {
2505                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2506                 return ctx_desc;
2507         }
2508
2509         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2510         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2511                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2512
2513         cd_cmd = ICE_TX_CTX_DESC_TSO;
2514         cd_tso_len = mbuf->pkt_len - hdr_len;
2515         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2516                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2517                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2518
2519         return ctx_desc;
2520 }
2521
2522 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2523 #define ICE_MAX_DATA_PER_TXD \
2524         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2525 /* Calculate the number of TX descriptors needed for each pkt */
2526 static inline uint16_t
2527 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2528 {
2529         struct rte_mbuf *txd = tx_pkt;
2530         uint16_t count = 0;
2531
2532         while (txd != NULL) {
2533                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2534                 txd = txd->next;
2535         }
2536
2537         return count;
2538 }
2539
2540 uint16_t
2541 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2542 {
2543         struct ice_tx_queue *txq;
2544         volatile struct ice_tx_desc *tx_ring;
2545         volatile struct ice_tx_desc *txd;
2546         struct ice_tx_entry *sw_ring;
2547         struct ice_tx_entry *txe, *txn;
2548         struct rte_mbuf *tx_pkt;
2549         struct rte_mbuf *m_seg;
2550         uint32_t cd_tunneling_params;
2551         uint16_t tx_id;
2552         uint16_t nb_tx;
2553         uint16_t nb_used;
2554         uint16_t nb_ctx;
2555         uint32_t td_cmd = 0;
2556         uint32_t td_offset = 0;
2557         uint32_t td_tag = 0;
2558         uint16_t tx_last;
2559         uint16_t slen;
2560         uint64_t buf_dma_addr;
2561         uint64_t ol_flags;
2562         union ice_tx_offload tx_offload = {0};
2563
2564         txq = tx_queue;
2565         sw_ring = txq->sw_ring;
2566         tx_ring = txq->tx_ring;
2567         tx_id = txq->tx_tail;
2568         txe = &sw_ring[tx_id];
2569
2570         /* Check if the descriptor ring needs to be cleaned. */
2571         if (txq->nb_tx_free < txq->tx_free_thresh)
2572                 (void)ice_xmit_cleanup(txq);
2573
2574         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2575                 tx_pkt = *tx_pkts++;
2576
2577                 td_cmd = 0;
2578                 td_tag = 0;
2579                 td_offset = 0;
2580                 ol_flags = tx_pkt->ol_flags;
2581                 tx_offload.l2_len = tx_pkt->l2_len;
2582                 tx_offload.l3_len = tx_pkt->l3_len;
2583                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2584                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2585                 tx_offload.l4_len = tx_pkt->l4_len;
2586                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2587                 /* Calculate the number of context descriptors needed. */
2588                 nb_ctx = ice_calc_context_desc(ol_flags);
2589
2590                 /* The number of descriptors that must be allocated for
2591                  * a packet equals to the number of the segments of that
2592                  * packet plus the number of context descriptor if needed.
2593                  * Recalculate the needed tx descs when TSO enabled in case
2594                  * the mbuf data size exceeds max data size that hw allows
2595                  * per tx desc.
2596                  */
2597                 if (ol_flags & PKT_TX_TCP_SEG)
2598                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2599                                              nb_ctx);
2600                 else
2601                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2602                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2603
2604                 /* Circular ring */
2605                 if (tx_last >= txq->nb_tx_desc)
2606                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2607
2608                 if (nb_used > txq->nb_tx_free) {
2609                         if (ice_xmit_cleanup(txq) != 0) {
2610                                 if (nb_tx == 0)
2611                                         return 0;
2612                                 goto end_of_tx;
2613                         }
2614                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2615                                 while (nb_used > txq->nb_tx_free) {
2616                                         if (ice_xmit_cleanup(txq) != 0) {
2617                                                 if (nb_tx == 0)
2618                                                         return 0;
2619                                                 goto end_of_tx;
2620                                         }
2621                                 }
2622                         }
2623                 }
2624
2625                 /* Descriptor based VLAN insertion */
2626                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2627                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2628                         td_tag = tx_pkt->vlan_tci;
2629                 }
2630
2631                 /* Fill in tunneling parameters if necessary */
2632                 cd_tunneling_params = 0;
2633                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2634                         ice_parse_tunneling_params(ol_flags, tx_offload,
2635                                                    &cd_tunneling_params);
2636
2637                 /* Enable checksum offloading */
2638                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2639                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2640                                                 &td_offset, tx_offload);
2641
2642                 if (nb_ctx) {
2643                         /* Setup TX context descriptor if required */
2644                         volatile struct ice_tx_ctx_desc *ctx_txd =
2645                                 (volatile struct ice_tx_ctx_desc *)
2646                                         &tx_ring[tx_id];
2647                         uint16_t cd_l2tag2 = 0;
2648                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2649
2650                         txn = &sw_ring[txe->next_id];
2651                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2652                         if (txe->mbuf) {
2653                                 rte_pktmbuf_free_seg(txe->mbuf);
2654                                 txe->mbuf = NULL;
2655                         }
2656
2657                         if (ol_flags & PKT_TX_TCP_SEG)
2658                                 cd_type_cmd_tso_mss |=
2659                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2660
2661                         ctx_txd->tunneling_params =
2662                                 rte_cpu_to_le_32(cd_tunneling_params);
2663
2664                         /* TX context descriptor based double VLAN insert */
2665                         if (ol_flags & PKT_TX_QINQ) {
2666                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2667                                 cd_type_cmd_tso_mss |=
2668                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2669                                          ICE_TXD_CTX_QW1_CMD_S);
2670                         }
2671                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2672                         ctx_txd->qw1 =
2673                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2674
2675                         txe->last_id = tx_last;
2676                         tx_id = txe->next_id;
2677                         txe = txn;
2678                 }
2679                 m_seg = tx_pkt;
2680
2681                 do {
2682                         txd = &tx_ring[tx_id];
2683                         txn = &sw_ring[txe->next_id];
2684
2685                         if (txe->mbuf)
2686                                 rte_pktmbuf_free_seg(txe->mbuf);
2687                         txe->mbuf = m_seg;
2688
2689                         /* Setup TX Descriptor */
2690                         slen = m_seg->data_len;
2691                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2692
2693                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2694                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2695                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2696                                 txd->cmd_type_offset_bsz =
2697                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2698                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2699                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2700                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2701                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2702                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2703
2704                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2705                                 slen -= ICE_MAX_DATA_PER_TXD;
2706
2707                                 txe->last_id = tx_last;
2708                                 tx_id = txe->next_id;
2709                                 txe = txn;
2710                                 txd = &tx_ring[tx_id];
2711                                 txn = &sw_ring[txe->next_id];
2712                         }
2713
2714                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2715                         txd->cmd_type_offset_bsz =
2716                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2717                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2718                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2719                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2720                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2721
2722                         txe->last_id = tx_last;
2723                         tx_id = txe->next_id;
2724                         txe = txn;
2725                         m_seg = m_seg->next;
2726                 } while (m_seg);
2727
2728                 /* fill the last descriptor with End of Packet (EOP) bit */
2729                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2730                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2731                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2732
2733                 /* set RS bit on the last descriptor of one packet */
2734                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2735                         PMD_TX_LOG(DEBUG,
2736                                    "Setting RS bit on TXD id="
2737                                    "%4u (port=%d queue=%d)",
2738                                    tx_last, txq->port_id, txq->queue_id);
2739
2740                         td_cmd |= ICE_TX_DESC_CMD_RS;
2741
2742                         /* Update txq RS bit counters */
2743                         txq->nb_tx_used = 0;
2744                 }
2745                 txd->cmd_type_offset_bsz |=
2746                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2747                                          ICE_TXD_QW1_CMD_S);
2748         }
2749 end_of_tx:
2750         /* update Tail register */
2751         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2752         txq->tx_tail = tx_id;
2753
2754         return nb_tx;
2755 }
2756
2757 static __rte_always_inline int
2758 ice_tx_free_bufs(struct ice_tx_queue *txq)
2759 {
2760         struct ice_tx_entry *txep;
2761         uint16_t i;
2762
2763         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2764              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2765             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2766                 return 0;
2767
2768         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2769
2770         for (i = 0; i < txq->tx_rs_thresh; i++)
2771                 rte_prefetch0((txep + i)->mbuf);
2772
2773         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2774                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2775                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2776                         txep->mbuf = NULL;
2777                 }
2778         } else {
2779                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2780                         rte_pktmbuf_free_seg(txep->mbuf);
2781                         txep->mbuf = NULL;
2782                 }
2783         }
2784
2785         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2786         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2787         if (txq->tx_next_dd >= txq->nb_tx_desc)
2788                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2789
2790         return txq->tx_rs_thresh;
2791 }
2792
2793 static int
2794 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2795                         uint32_t free_cnt)
2796 {
2797         struct ice_tx_entry *swr_ring = txq->sw_ring;
2798         uint16_t i, tx_last, tx_id;
2799         uint16_t nb_tx_free_last;
2800         uint16_t nb_tx_to_clean;
2801         uint32_t pkt_cnt;
2802
2803         /* Start free mbuf from the next of tx_tail */
2804         tx_last = txq->tx_tail;
2805         tx_id  = swr_ring[tx_last].next_id;
2806
2807         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2808                 return 0;
2809
2810         nb_tx_to_clean = txq->nb_tx_free;
2811         nb_tx_free_last = txq->nb_tx_free;
2812         if (!free_cnt)
2813                 free_cnt = txq->nb_tx_desc;
2814
2815         /* Loop through swr_ring to count the amount of
2816          * freeable mubfs and packets.
2817          */
2818         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2819                 for (i = 0; i < nb_tx_to_clean &&
2820                         pkt_cnt < free_cnt &&
2821                         tx_id != tx_last; i++) {
2822                         if (swr_ring[tx_id].mbuf != NULL) {
2823                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2824                                 swr_ring[tx_id].mbuf = NULL;
2825
2826                                 /*
2827                                  * last segment in the packet,
2828                                  * increment packet count
2829                                  */
2830                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2831                         }
2832
2833                         tx_id = swr_ring[tx_id].next_id;
2834                 }
2835
2836                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2837                         txq->nb_tx_free || tx_id == tx_last)
2838                         break;
2839
2840                 if (pkt_cnt < free_cnt) {
2841                         if (ice_xmit_cleanup(txq))
2842                                 break;
2843
2844                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2845                         nb_tx_free_last = txq->nb_tx_free;
2846                 }
2847         }
2848
2849         return (int)pkt_cnt;
2850 }
2851
2852 #ifdef RTE_ARCH_X86
2853 static int
2854 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2855                         uint32_t free_cnt __rte_unused)
2856 {
2857         return -ENOTSUP;
2858 }
2859 #endif
2860
2861 static int
2862 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2863                         uint32_t free_cnt)
2864 {
2865         int i, n, cnt;
2866
2867         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2868                 free_cnt = txq->nb_tx_desc;
2869
2870         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2871
2872         for (i = 0; i < cnt; i += n) {
2873                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2874                         break;
2875
2876                 n = ice_tx_free_bufs(txq);
2877
2878                 if (n == 0)
2879                         break;
2880         }
2881
2882         return i;
2883 }
2884
2885 int
2886 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2887 {
2888         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2889         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2890         struct ice_adapter *ad =
2891                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2892
2893 #ifdef RTE_ARCH_X86
2894         if (ad->tx_vec_allowed)
2895                 return ice_tx_done_cleanup_vec(q, free_cnt);
2896 #endif
2897         if (ad->tx_simple_allowed)
2898                 return ice_tx_done_cleanup_simple(q, free_cnt);
2899         else
2900                 return ice_tx_done_cleanup_full(q, free_cnt);
2901 }
2902
2903 /* Populate 4 descriptors with data from 4 mbufs */
2904 static inline void
2905 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2906 {
2907         uint64_t dma_addr;
2908         uint32_t i;
2909
2910         for (i = 0; i < 4; i++, txdp++, pkts++) {
2911                 dma_addr = rte_mbuf_data_iova(*pkts);
2912                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2913                 txdp->cmd_type_offset_bsz =
2914                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2915                                        (*pkts)->data_len, 0);
2916         }
2917 }
2918
2919 /* Populate 1 descriptor with data from 1 mbuf */
2920 static inline void
2921 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2922 {
2923         uint64_t dma_addr;
2924
2925         dma_addr = rte_mbuf_data_iova(*pkts);
2926         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2927         txdp->cmd_type_offset_bsz =
2928                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2929                                (*pkts)->data_len, 0);
2930 }
2931
2932 static inline void
2933 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2934                     uint16_t nb_pkts)
2935 {
2936         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2937         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2938         const int N_PER_LOOP = 4;
2939         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2940         int mainpart, leftover;
2941         int i, j;
2942
2943         /**
2944          * Process most of the packets in chunks of N pkts.  Any
2945          * leftover packets will get processed one at a time.
2946          */
2947         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2948         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2949         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2950                 /* Copy N mbuf pointers to the S/W ring */
2951                 for (j = 0; j < N_PER_LOOP; ++j)
2952                         (txep + i + j)->mbuf = *(pkts + i + j);
2953                 tx4(txdp + i, pkts + i);
2954         }
2955
2956         if (unlikely(leftover > 0)) {
2957                 for (i = 0; i < leftover; ++i) {
2958                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2959                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2960                 }
2961         }
2962 }
2963
2964 static inline uint16_t
2965 tx_xmit_pkts(struct ice_tx_queue *txq,
2966              struct rte_mbuf **tx_pkts,
2967              uint16_t nb_pkts)
2968 {
2969         volatile struct ice_tx_desc *txr = txq->tx_ring;
2970         uint16_t n = 0;
2971
2972         /**
2973          * Begin scanning the H/W ring for done descriptors when the number
2974          * of available descriptors drops below tx_free_thresh. For each done
2975          * descriptor, free the associated buffer.
2976          */
2977         if (txq->nb_tx_free < txq->tx_free_thresh)
2978                 ice_tx_free_bufs(txq);
2979
2980         /* Use available descriptor only */
2981         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2982         if (unlikely(!nb_pkts))
2983                 return 0;
2984
2985         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2986         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2987                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2988                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2989                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2990                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2991                                          ICE_TXD_QW1_CMD_S);
2992                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2993                 txq->tx_tail = 0;
2994         }
2995
2996         /* Fill hardware descriptor ring with mbuf data */
2997         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2998         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2999
3000         /* Determin if RS bit needs to be set */
3001         if (txq->tx_tail > txq->tx_next_rs) {
3002                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3003                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3004                                          ICE_TXD_QW1_CMD_S);
3005                 txq->tx_next_rs =
3006                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3007                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3008                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3009         }
3010
3011         if (txq->tx_tail >= txq->nb_tx_desc)
3012                 txq->tx_tail = 0;
3013
3014         /* Update the tx tail register */
3015         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3016
3017         return nb_pkts;
3018 }
3019
3020 static uint16_t
3021 ice_xmit_pkts_simple(void *tx_queue,
3022                      struct rte_mbuf **tx_pkts,
3023                      uint16_t nb_pkts)
3024 {
3025         uint16_t nb_tx = 0;
3026
3027         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3028                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3029                                     tx_pkts, nb_pkts);
3030
3031         while (nb_pkts) {
3032                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3033                                                       ICE_TX_MAX_BURST);
3034
3035                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3036                                    &tx_pkts[nb_tx], num);
3037                 nb_tx = (uint16_t)(nb_tx + ret);
3038                 nb_pkts = (uint16_t)(nb_pkts - ret);
3039                 if (ret < num)
3040                         break;
3041         }
3042
3043         return nb_tx;
3044 }
3045
3046 void __rte_cold
3047 ice_set_rx_function(struct rte_eth_dev *dev)
3048 {
3049         PMD_INIT_FUNC_TRACE();
3050         struct ice_adapter *ad =
3051                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3052 #ifdef RTE_ARCH_X86
3053         struct ice_rx_queue *rxq;
3054         int i;
3055         bool use_avx512 = false;
3056         bool use_avx2 = false;
3057
3058         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3059                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
3060                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3061                         ad->rx_vec_allowed = true;
3062                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3063                                 rxq = dev->data->rx_queues[i];
3064                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3065                                         ad->rx_vec_allowed = false;
3066                                         break;
3067                                 }
3068                         }
3069
3070                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3071                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3072                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3073 #ifdef CC_AVX512_SUPPORT
3074                                 use_avx512 = true;
3075 #else
3076                         PMD_DRV_LOG(NOTICE,
3077                                 "AVX512 is not supported in build env");
3078 #endif
3079                         if (!use_avx512 &&
3080                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3081                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3082                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3083                                 use_avx2 = true;
3084
3085                 } else {
3086                         ad->rx_vec_allowed = false;
3087                 }
3088         }
3089
3090         if (ad->rx_vec_allowed) {
3091                 if (dev->data->scattered_rx) {
3092                         if (use_avx512) {
3093 #ifdef CC_AVX512_SUPPORT
3094                                 PMD_DRV_LOG(NOTICE,
3095                                         "Using AVX512 Vector Scattered Rx (port %d).",
3096                                         dev->data->port_id);
3097                                 dev->rx_pkt_burst =
3098                                         ice_recv_scattered_pkts_vec_avx512;
3099 #endif
3100                         } else {
3101                                 PMD_DRV_LOG(DEBUG,
3102                                         "Using %sVector Scattered Rx (port %d).",
3103                                         use_avx2 ? "avx2 " : "",
3104                                         dev->data->port_id);
3105                                 dev->rx_pkt_burst = use_avx2 ?
3106                                         ice_recv_scattered_pkts_vec_avx2 :
3107                                         ice_recv_scattered_pkts_vec;
3108                         }
3109                 } else {
3110                         if (use_avx512) {
3111 #ifdef CC_AVX512_SUPPORT
3112                                 PMD_DRV_LOG(NOTICE,
3113                                         "Using AVX512 Vector Rx (port %d).",
3114                                         dev->data->port_id);
3115                                 dev->rx_pkt_burst =
3116                                         ice_recv_pkts_vec_avx512;
3117 #endif
3118                         } else {
3119                                 PMD_DRV_LOG(DEBUG,
3120                                         "Using %sVector Rx (port %d).",
3121                                         use_avx2 ? "avx2 " : "",
3122                                         dev->data->port_id);
3123                                 dev->rx_pkt_burst = use_avx2 ?
3124                                         ice_recv_pkts_vec_avx2 :
3125                                         ice_recv_pkts_vec;
3126                         }
3127                 }
3128                 return;
3129         }
3130
3131 #endif
3132
3133         if (dev->data->scattered_rx) {
3134                 /* Set the non-LRO scattered function */
3135                 PMD_INIT_LOG(DEBUG,
3136                              "Using a Scattered function on port %d.",
3137                              dev->data->port_id);
3138                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3139         } else if (ad->rx_bulk_alloc_allowed) {
3140                 PMD_INIT_LOG(DEBUG,
3141                              "Rx Burst Bulk Alloc Preconditions are "
3142                              "satisfied. Rx Burst Bulk Alloc function "
3143                              "will be used on port %d.",
3144                              dev->data->port_id);
3145                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3146         } else {
3147                 PMD_INIT_LOG(DEBUG,
3148                              "Rx Burst Bulk Alloc Preconditions are not "
3149                              "satisfied, Normal Rx will be used on port %d.",
3150                              dev->data->port_id);
3151                 dev->rx_pkt_burst = ice_recv_pkts;
3152         }
3153 }
3154
3155 static const struct {
3156         eth_rx_burst_t pkt_burst;
3157         const char *info;
3158 } ice_rx_burst_infos[] = {
3159         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3160         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3161         { ice_recv_pkts,                    "Scalar" },
3162 #ifdef RTE_ARCH_X86
3163 #ifdef CC_AVX512_SUPPORT
3164         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3165         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3166 #endif
3167         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3168         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3169         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3170         { ice_recv_pkts_vec,                "Vector SSE" },
3171 #endif
3172 };
3173
3174 int
3175 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3176                       struct rte_eth_burst_mode *mode)
3177 {
3178         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3179         int ret = -EINVAL;
3180         unsigned int i;
3181
3182         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3183                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3184                         snprintf(mode->info, sizeof(mode->info), "%s",
3185                                  ice_rx_burst_infos[i].info);
3186                         ret = 0;
3187                         break;
3188                 }
3189         }
3190
3191         return ret;
3192 }
3193
3194 void __rte_cold
3195 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3196 {
3197         struct ice_adapter *ad =
3198                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3199
3200         /* Use a simple Tx queue if possible (only fast free is allowed) */
3201         ad->tx_simple_allowed =
3202                 (txq->offloads ==
3203                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3204                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3205
3206         if (ad->tx_simple_allowed)
3207                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3208                              txq->queue_id);
3209         else
3210                 PMD_INIT_LOG(DEBUG,
3211                              "Simple Tx can NOT be enabled on Tx queue %u.",
3212                              txq->queue_id);
3213 }
3214
3215 /*********************************************************************
3216  *
3217  *  TX prep functions
3218  *
3219  **********************************************************************/
3220 /* The default values of TSO MSS */
3221 #define ICE_MIN_TSO_MSS            64
3222 #define ICE_MAX_TSO_MSS            9728
3223 #define ICE_MAX_TSO_FRAME_SIZE     262144
3224 uint16_t
3225 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3226               uint16_t nb_pkts)
3227 {
3228         int i, ret;
3229         uint64_t ol_flags;
3230         struct rte_mbuf *m;
3231
3232         for (i = 0; i < nb_pkts; i++) {
3233                 m = tx_pkts[i];
3234                 ol_flags = m->ol_flags;
3235
3236                 if (ol_flags & PKT_TX_TCP_SEG &&
3237                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3238                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3239                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3240                         /**
3241                          * MSS outside the range are considered malicious
3242                          */
3243                         rte_errno = EINVAL;
3244                         return i;
3245                 }
3246
3247 #ifdef RTE_ETHDEV_DEBUG_TX
3248                 ret = rte_validate_tx_offload(m);
3249                 if (ret != 0) {
3250                         rte_errno = -ret;
3251                         return i;
3252                 }
3253 #endif
3254                 ret = rte_net_intel_cksum_prepare(m);
3255                 if (ret != 0) {
3256                         rte_errno = -ret;
3257                         return i;
3258                 }
3259         }
3260         return i;
3261 }
3262
3263 void __rte_cold
3264 ice_set_tx_function(struct rte_eth_dev *dev)
3265 {
3266         struct ice_adapter *ad =
3267                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3268 #ifdef RTE_ARCH_X86
3269         struct ice_tx_queue *txq;
3270         int i;
3271         int tx_check_ret;
3272         bool use_avx512 = false;
3273         bool use_avx2 = false;
3274
3275         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3276                 tx_check_ret = ice_tx_vec_dev_check(dev);
3277                 if (tx_check_ret >= 0 &&
3278                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3279                         ad->tx_vec_allowed = true;
3280                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3281                                 txq = dev->data->tx_queues[i];
3282                                 if (txq && ice_txq_vec_setup(txq)) {
3283                                         ad->tx_vec_allowed = false;
3284                                         break;
3285                                 }
3286                         }
3287
3288                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3289                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3290                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3291 #ifdef CC_AVX512_SUPPORT
3292                                 use_avx512 = true;
3293 #else
3294                         PMD_DRV_LOG(NOTICE,
3295                                 "AVX512 is not supported in build env");
3296 #endif
3297                         if (!use_avx512 && tx_check_ret == ICE_VECTOR_PATH &&
3298                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3299                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3300                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3301                                 use_avx2 = true;
3302
3303                         if (!use_avx512 && tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3304                                 ad->tx_vec_allowed = false;
3305
3306                 } else {
3307                         ad->tx_vec_allowed = false;
3308                 }
3309         }
3310
3311         if (ad->tx_vec_allowed) {
3312                 if (use_avx512) {
3313 #ifdef CC_AVX512_SUPPORT
3314                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3315                                 PMD_DRV_LOG(NOTICE,
3316                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3317                                             dev->data->port_id);
3318                                 dev->tx_pkt_burst =
3319                                         ice_xmit_pkts_vec_avx512_offload;
3320                         } else {
3321                                 PMD_DRV_LOG(NOTICE,
3322                                             "Using AVX512 Vector Tx (port %d).",
3323                                             dev->data->port_id);
3324                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3325                         }
3326 #endif
3327                 } else {
3328                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3329                                     use_avx2 ? "avx2 " : "",
3330                                     dev->data->port_id);
3331                         dev->tx_pkt_burst = use_avx2 ?
3332                                             ice_xmit_pkts_vec_avx2 :
3333                                             ice_xmit_pkts_vec;
3334                 }
3335                 dev->tx_pkt_prepare = NULL;
3336
3337                 return;
3338         }
3339 #endif
3340
3341         if (ad->tx_simple_allowed) {
3342                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3343                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3344                 dev->tx_pkt_prepare = NULL;
3345         } else {
3346                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3347                 dev->tx_pkt_burst = ice_xmit_pkts;
3348                 dev->tx_pkt_prepare = ice_prep_pkts;
3349         }
3350 }
3351
3352 static const struct {
3353         eth_tx_burst_t pkt_burst;
3354         const char *info;
3355 } ice_tx_burst_infos[] = {
3356         { ice_xmit_pkts_simple,   "Scalar Simple" },
3357         { ice_xmit_pkts,          "Scalar" },
3358 #ifdef RTE_ARCH_X86
3359 #ifdef CC_AVX512_SUPPORT
3360         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3361         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3362 #endif
3363         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3364         { ice_xmit_pkts_vec,      "Vector SSE" },
3365 #endif
3366 };
3367
3368 int
3369 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3370                       struct rte_eth_burst_mode *mode)
3371 {
3372         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3373         int ret = -EINVAL;
3374         unsigned int i;
3375
3376         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3377                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3378                         snprintf(mode->info, sizeof(mode->info), "%s",
3379                                  ice_tx_burst_infos[i].info);
3380                         ret = 0;
3381                         break;
3382                 }
3383         }
3384
3385         return ret;
3386 }
3387
3388 /* For each value it means, datasheet of hardware can tell more details
3389  *
3390  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3391  */
3392 static inline uint32_t
3393 ice_get_default_pkt_type(uint16_t ptype)
3394 {
3395         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3396                 __rte_cache_aligned = {
3397                 /* L2 types */
3398                 /* [0] reserved */
3399                 [1] = RTE_PTYPE_L2_ETHER,
3400                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3401                 /* [3] - [5] reserved */
3402                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3403                 /* [7] - [10] reserved */
3404                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3405                 /* [12] - [21] reserved */
3406
3407                 /* Non tunneled IPv4 */
3408                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3409                        RTE_PTYPE_L4_FRAG,
3410                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3411                        RTE_PTYPE_L4_NONFRAG,
3412                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3413                        RTE_PTYPE_L4_UDP,
3414                 /* [25] reserved */
3415                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3416                        RTE_PTYPE_L4_TCP,
3417                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3418                        RTE_PTYPE_L4_SCTP,
3419                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3420                        RTE_PTYPE_L4_ICMP,
3421
3422                 /* IPv4 --> IPv4 */
3423                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3424                        RTE_PTYPE_TUNNEL_IP |
3425                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3426                        RTE_PTYPE_INNER_L4_FRAG,
3427                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3428                        RTE_PTYPE_TUNNEL_IP |
3429                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3430                        RTE_PTYPE_INNER_L4_NONFRAG,
3431                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3432                        RTE_PTYPE_TUNNEL_IP |
3433                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3434                        RTE_PTYPE_INNER_L4_UDP,
3435                 /* [32] reserved */
3436                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3437                        RTE_PTYPE_TUNNEL_IP |
3438                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3439                        RTE_PTYPE_INNER_L4_TCP,
3440                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3441                        RTE_PTYPE_TUNNEL_IP |
3442                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3443                        RTE_PTYPE_INNER_L4_SCTP,
3444                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3445                        RTE_PTYPE_TUNNEL_IP |
3446                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3447                        RTE_PTYPE_INNER_L4_ICMP,
3448
3449                 /* IPv4 --> IPv6 */
3450                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3451                        RTE_PTYPE_TUNNEL_IP |
3452                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3453                        RTE_PTYPE_INNER_L4_FRAG,
3454                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3455                        RTE_PTYPE_TUNNEL_IP |
3456                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3457                        RTE_PTYPE_INNER_L4_NONFRAG,
3458                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3459                        RTE_PTYPE_TUNNEL_IP |
3460                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3461                        RTE_PTYPE_INNER_L4_UDP,
3462                 /* [39] reserved */
3463                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3464                        RTE_PTYPE_TUNNEL_IP |
3465                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3466                        RTE_PTYPE_INNER_L4_TCP,
3467                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3468                        RTE_PTYPE_TUNNEL_IP |
3469                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3470                        RTE_PTYPE_INNER_L4_SCTP,
3471                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3472                        RTE_PTYPE_TUNNEL_IP |
3473                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3474                        RTE_PTYPE_INNER_L4_ICMP,
3475
3476                 /* IPv4 --> GRE/Teredo/VXLAN */
3477                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3478                        RTE_PTYPE_TUNNEL_GRENAT,
3479
3480                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3481                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3482                        RTE_PTYPE_TUNNEL_GRENAT |
3483                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3484                        RTE_PTYPE_INNER_L4_FRAG,
3485                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3486                        RTE_PTYPE_TUNNEL_GRENAT |
3487                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3488                        RTE_PTYPE_INNER_L4_NONFRAG,
3489                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3490                        RTE_PTYPE_TUNNEL_GRENAT |
3491                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3492                        RTE_PTYPE_INNER_L4_UDP,
3493                 /* [47] reserved */
3494                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3495                        RTE_PTYPE_TUNNEL_GRENAT |
3496                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3497                        RTE_PTYPE_INNER_L4_TCP,
3498                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3499                        RTE_PTYPE_TUNNEL_GRENAT |
3500                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3501                        RTE_PTYPE_INNER_L4_SCTP,
3502                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3503                        RTE_PTYPE_TUNNEL_GRENAT |
3504                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3505                        RTE_PTYPE_INNER_L4_ICMP,
3506
3507                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3508                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3509                        RTE_PTYPE_TUNNEL_GRENAT |
3510                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3511                        RTE_PTYPE_INNER_L4_FRAG,
3512                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3513                        RTE_PTYPE_TUNNEL_GRENAT |
3514                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3515                        RTE_PTYPE_INNER_L4_NONFRAG,
3516                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3517                        RTE_PTYPE_TUNNEL_GRENAT |
3518                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3519                        RTE_PTYPE_INNER_L4_UDP,
3520                 /* [54] reserved */
3521                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3522                        RTE_PTYPE_TUNNEL_GRENAT |
3523                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3524                        RTE_PTYPE_INNER_L4_TCP,
3525                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3526                        RTE_PTYPE_TUNNEL_GRENAT |
3527                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3528                        RTE_PTYPE_INNER_L4_SCTP,
3529                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3530                        RTE_PTYPE_TUNNEL_GRENAT |
3531                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3532                        RTE_PTYPE_INNER_L4_ICMP,
3533
3534                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3535                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3536                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3537
3538                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3539                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3540                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3541                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3542                        RTE_PTYPE_INNER_L4_FRAG,
3543                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3544                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3545                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3546                        RTE_PTYPE_INNER_L4_NONFRAG,
3547                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3548                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3549                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3550                        RTE_PTYPE_INNER_L4_UDP,
3551                 /* [62] reserved */
3552                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3553                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3554                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3555                        RTE_PTYPE_INNER_L4_TCP,
3556                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3557                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3558                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3559                        RTE_PTYPE_INNER_L4_SCTP,
3560                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3561                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3562                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3563                        RTE_PTYPE_INNER_L4_ICMP,
3564
3565                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3566                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3567                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3568                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3569                        RTE_PTYPE_INNER_L4_FRAG,
3570                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3571                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3572                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3573                        RTE_PTYPE_INNER_L4_NONFRAG,
3574                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3575                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3576                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3577                        RTE_PTYPE_INNER_L4_UDP,
3578                 /* [69] reserved */
3579                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3580                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3581                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3582                        RTE_PTYPE_INNER_L4_TCP,
3583                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3584                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3585                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3586                        RTE_PTYPE_INNER_L4_SCTP,
3587                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3588                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3589                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3590                        RTE_PTYPE_INNER_L4_ICMP,
3591                 /* [73] - [87] reserved */
3592
3593                 /* Non tunneled IPv6 */
3594                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3595                        RTE_PTYPE_L4_FRAG,
3596                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3597                        RTE_PTYPE_L4_NONFRAG,
3598                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3599                        RTE_PTYPE_L4_UDP,
3600                 /* [91] reserved */
3601                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3602                        RTE_PTYPE_L4_TCP,
3603                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3604                        RTE_PTYPE_L4_SCTP,
3605                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3606                        RTE_PTYPE_L4_ICMP,
3607
3608                 /* IPv6 --> IPv4 */
3609                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3610                        RTE_PTYPE_TUNNEL_IP |
3611                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3612                        RTE_PTYPE_INNER_L4_FRAG,
3613                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3614                        RTE_PTYPE_TUNNEL_IP |
3615                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3616                        RTE_PTYPE_INNER_L4_NONFRAG,
3617                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3618                        RTE_PTYPE_TUNNEL_IP |
3619                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3620                        RTE_PTYPE_INNER_L4_UDP,
3621                 /* [98] reserved */
3622                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3623                        RTE_PTYPE_TUNNEL_IP |
3624                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3625                        RTE_PTYPE_INNER_L4_TCP,
3626                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3627                         RTE_PTYPE_TUNNEL_IP |
3628                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3629                         RTE_PTYPE_INNER_L4_SCTP,
3630                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3631                         RTE_PTYPE_TUNNEL_IP |
3632                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3633                         RTE_PTYPE_INNER_L4_ICMP,
3634
3635                 /* IPv6 --> IPv6 */
3636                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3637                         RTE_PTYPE_TUNNEL_IP |
3638                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3639                         RTE_PTYPE_INNER_L4_FRAG,
3640                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3641                         RTE_PTYPE_TUNNEL_IP |
3642                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3643                         RTE_PTYPE_INNER_L4_NONFRAG,
3644                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3645                         RTE_PTYPE_TUNNEL_IP |
3646                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3647                         RTE_PTYPE_INNER_L4_UDP,
3648                 /* [105] reserved */
3649                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3650                         RTE_PTYPE_TUNNEL_IP |
3651                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3652                         RTE_PTYPE_INNER_L4_TCP,
3653                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_IP |
3655                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3656                         RTE_PTYPE_INNER_L4_SCTP,
3657                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3658                         RTE_PTYPE_TUNNEL_IP |
3659                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3660                         RTE_PTYPE_INNER_L4_ICMP,
3661
3662                 /* IPv6 --> GRE/Teredo/VXLAN */
3663                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3664                         RTE_PTYPE_TUNNEL_GRENAT,
3665
3666                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3667                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3668                         RTE_PTYPE_TUNNEL_GRENAT |
3669                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3670                         RTE_PTYPE_INNER_L4_FRAG,
3671                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3672                         RTE_PTYPE_TUNNEL_GRENAT |
3673                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3674                         RTE_PTYPE_INNER_L4_NONFRAG,
3675                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3676                         RTE_PTYPE_TUNNEL_GRENAT |
3677                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3678                         RTE_PTYPE_INNER_L4_UDP,
3679                 /* [113] reserved */
3680                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_TUNNEL_GRENAT |
3682                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3683                         RTE_PTYPE_INNER_L4_TCP,
3684                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3685                         RTE_PTYPE_TUNNEL_GRENAT |
3686                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3687                         RTE_PTYPE_INNER_L4_SCTP,
3688                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3689                         RTE_PTYPE_TUNNEL_GRENAT |
3690                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3691                         RTE_PTYPE_INNER_L4_ICMP,
3692
3693                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3694                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3695                         RTE_PTYPE_TUNNEL_GRENAT |
3696                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3697                         RTE_PTYPE_INNER_L4_FRAG,
3698                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3699                         RTE_PTYPE_TUNNEL_GRENAT |
3700                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3701                         RTE_PTYPE_INNER_L4_NONFRAG,
3702                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3703                         RTE_PTYPE_TUNNEL_GRENAT |
3704                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3705                         RTE_PTYPE_INNER_L4_UDP,
3706                 /* [120] reserved */
3707                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3708                         RTE_PTYPE_TUNNEL_GRENAT |
3709                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3710                         RTE_PTYPE_INNER_L4_TCP,
3711                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3712                         RTE_PTYPE_TUNNEL_GRENAT |
3713                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3714                         RTE_PTYPE_INNER_L4_SCTP,
3715                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3716                         RTE_PTYPE_TUNNEL_GRENAT |
3717                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3718                         RTE_PTYPE_INNER_L4_ICMP,
3719
3720                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3721                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3722                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3723
3724                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3725                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3726                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3727                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3728                         RTE_PTYPE_INNER_L4_FRAG,
3729                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3731                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3732                         RTE_PTYPE_INNER_L4_NONFRAG,
3733                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3734                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3735                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3736                         RTE_PTYPE_INNER_L4_UDP,
3737                 /* [128] reserved */
3738                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3739                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3740                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3741                         RTE_PTYPE_INNER_L4_TCP,
3742                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3743                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3744                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3745                         RTE_PTYPE_INNER_L4_SCTP,
3746                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3747                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3748                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3749                         RTE_PTYPE_INNER_L4_ICMP,
3750
3751                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3752                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3753                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3754                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3755                         RTE_PTYPE_INNER_L4_FRAG,
3756                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3757                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3758                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3759                         RTE_PTYPE_INNER_L4_NONFRAG,
3760                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3761                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3762                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3763                         RTE_PTYPE_INNER_L4_UDP,
3764                 /* [135] reserved */
3765                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3766                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3767                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3768                         RTE_PTYPE_INNER_L4_TCP,
3769                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3770                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3771                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3772                         RTE_PTYPE_INNER_L4_SCTP,
3773                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3774                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3775                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3776                         RTE_PTYPE_INNER_L4_ICMP,
3777                 /* [139] - [299] reserved */
3778
3779                 /* PPPoE */
3780                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3781                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3782
3783                 /* PPPoE --> IPv4 */
3784                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3785                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3786                         RTE_PTYPE_L4_FRAG,
3787                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3788                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3789                         RTE_PTYPE_L4_NONFRAG,
3790                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3791                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3792                         RTE_PTYPE_L4_UDP,
3793                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3794                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3795                         RTE_PTYPE_L4_TCP,
3796                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3797                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3798                         RTE_PTYPE_L4_SCTP,
3799                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3800                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3801                         RTE_PTYPE_L4_ICMP,
3802
3803                 /* PPPoE --> IPv6 */
3804                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3805                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806                         RTE_PTYPE_L4_FRAG,
3807                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3808                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3809                         RTE_PTYPE_L4_NONFRAG,
3810                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3811                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3812                         RTE_PTYPE_L4_UDP,
3813                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3814                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815                         RTE_PTYPE_L4_TCP,
3816                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3817                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3818                         RTE_PTYPE_L4_SCTP,
3819                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3820                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3821                         RTE_PTYPE_L4_ICMP,
3822                 /* [314] - [324] reserved */
3823
3824                 /* IPv4/IPv6 --> GTPC/GTPU */
3825                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3826                         RTE_PTYPE_TUNNEL_GTPC,
3827                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828                         RTE_PTYPE_TUNNEL_GTPC,
3829                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3830                         RTE_PTYPE_TUNNEL_GTPC,
3831                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3832                         RTE_PTYPE_TUNNEL_GTPC,
3833                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3834                         RTE_PTYPE_TUNNEL_GTPU,
3835                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3836                         RTE_PTYPE_TUNNEL_GTPU,
3837
3838                 /* IPv4 --> GTPU --> IPv4 */
3839                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3840                         RTE_PTYPE_TUNNEL_GTPU |
3841                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3842                         RTE_PTYPE_INNER_L4_FRAG,
3843                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3844                         RTE_PTYPE_TUNNEL_GTPU |
3845                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3846                         RTE_PTYPE_INNER_L4_NONFRAG,
3847                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3848                         RTE_PTYPE_TUNNEL_GTPU |
3849                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3850                         RTE_PTYPE_INNER_L4_UDP,
3851                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3852                         RTE_PTYPE_TUNNEL_GTPU |
3853                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3854                         RTE_PTYPE_INNER_L4_TCP,
3855                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3856                         RTE_PTYPE_TUNNEL_GTPU |
3857                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3858                         RTE_PTYPE_INNER_L4_ICMP,
3859
3860                 /* IPv6 --> GTPU --> IPv4 */
3861                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3862                         RTE_PTYPE_TUNNEL_GTPU |
3863                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3864                         RTE_PTYPE_INNER_L4_FRAG,
3865                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3866                         RTE_PTYPE_TUNNEL_GTPU |
3867                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3868                         RTE_PTYPE_INNER_L4_NONFRAG,
3869                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3870                         RTE_PTYPE_TUNNEL_GTPU |
3871                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3872                         RTE_PTYPE_INNER_L4_UDP,
3873                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3874                         RTE_PTYPE_TUNNEL_GTPU |
3875                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3876                         RTE_PTYPE_INNER_L4_TCP,
3877                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3878                         RTE_PTYPE_TUNNEL_GTPU |
3879                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3880                         RTE_PTYPE_INNER_L4_ICMP,
3881
3882                 /* IPv4 --> GTPU --> IPv6 */
3883                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3884                         RTE_PTYPE_TUNNEL_GTPU |
3885                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3886                         RTE_PTYPE_INNER_L4_FRAG,
3887                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3888                         RTE_PTYPE_TUNNEL_GTPU |
3889                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3890                         RTE_PTYPE_INNER_L4_NONFRAG,
3891                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3892                         RTE_PTYPE_TUNNEL_GTPU |
3893                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3894                         RTE_PTYPE_INNER_L4_UDP,
3895                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3896                         RTE_PTYPE_TUNNEL_GTPU |
3897                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3898                         RTE_PTYPE_INNER_L4_TCP,
3899                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3900                         RTE_PTYPE_TUNNEL_GTPU |
3901                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3902                         RTE_PTYPE_INNER_L4_ICMP,
3903
3904                 /* IPv6 --> GTPU --> IPv6 */
3905                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3906                         RTE_PTYPE_TUNNEL_GTPU |
3907                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3908                         RTE_PTYPE_INNER_L4_FRAG,
3909                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3910                         RTE_PTYPE_TUNNEL_GTPU |
3911                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3912                         RTE_PTYPE_INNER_L4_NONFRAG,
3913                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3914                         RTE_PTYPE_TUNNEL_GTPU |
3915                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3916                         RTE_PTYPE_INNER_L4_UDP,
3917                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3918                         RTE_PTYPE_TUNNEL_GTPU |
3919                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3920                         RTE_PTYPE_INNER_L4_TCP,
3921                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3922                         RTE_PTYPE_TUNNEL_GTPU |
3923                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3924                         RTE_PTYPE_INNER_L4_ICMP,
3925
3926                 /* IPv4 --> UDP ECPRI */
3927                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3928                         RTE_PTYPE_L4_UDP,
3929                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3930                         RTE_PTYPE_L4_UDP,
3931                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3932                         RTE_PTYPE_L4_UDP,
3933                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3934                         RTE_PTYPE_L4_UDP,
3935                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3936                         RTE_PTYPE_L4_UDP,
3937                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3938                         RTE_PTYPE_L4_UDP,
3939                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3940                         RTE_PTYPE_L4_UDP,
3941                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3942                         RTE_PTYPE_L4_UDP,
3943                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3944                         RTE_PTYPE_L4_UDP,
3945                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3946                         RTE_PTYPE_L4_UDP,
3947
3948                 /* IPV6 --> UDP ECPRI */
3949                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3950                         RTE_PTYPE_L4_UDP,
3951                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3952                         RTE_PTYPE_L4_UDP,
3953                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3954                         RTE_PTYPE_L4_UDP,
3955                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3956                         RTE_PTYPE_L4_UDP,
3957                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3958                         RTE_PTYPE_L4_UDP,
3959                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3960                         RTE_PTYPE_L4_UDP,
3961                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3962                         RTE_PTYPE_L4_UDP,
3963                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3964                         RTE_PTYPE_L4_UDP,
3965                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3966                         RTE_PTYPE_L4_UDP,
3967                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3968                         RTE_PTYPE_L4_UDP,
3969                 /* All others reserved */
3970         };
3971
3972         return type_table[ptype];
3973 }
3974
3975 void __rte_cold
3976 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3977 {
3978         struct ice_adapter *ad =
3979                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3980         int i;
3981
3982         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3983                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3984 }
3985
3986 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3987 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3988                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3989 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3990 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3991
3992 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3993 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3994         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3995 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3996 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3997         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3998
3999 /*
4000  * check the programming status descriptor in rx queue.
4001  * done after Programming Flow Director is programmed on
4002  * tx queue
4003  */
4004 static inline int
4005 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4006 {
4007         volatile union ice_32byte_rx_desc *rxdp;
4008         uint64_t qword1;
4009         uint32_t rx_status;
4010         uint32_t error;
4011         uint32_t id;
4012         int ret = -EAGAIN;
4013
4014         rxdp = (volatile union ice_32byte_rx_desc *)
4015                 (&rxq->rx_ring[rxq->rx_tail]);
4016         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4017         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4018                         >> ICE_RXD_QW1_STATUS_S;
4019
4020         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4021                 ret = 0;
4022                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4023                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4024                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4025                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4026                 if (error) {
4027                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4028                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4029                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4030                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4031                         ret = -EINVAL;
4032                         goto err;
4033                 }
4034                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4035                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4036                 if (error) {
4037                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4038                         ret = -EINVAL;
4039                 }
4040 err:
4041                 rxdp->wb.qword1.status_error_len = 0;
4042                 rxq->rx_tail++;
4043                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4044                         rxq->rx_tail = 0;
4045                 if (rxq->rx_tail == 0)
4046                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4047                 else
4048                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4049         }
4050
4051         return ret;
4052 }
4053
4054 #define ICE_FDIR_MAX_WAIT_US 10000
4055
4056 int
4057 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4058 {
4059         struct ice_tx_queue *txq = pf->fdir.txq;
4060         struct ice_rx_queue *rxq = pf->fdir.rxq;
4061         volatile struct ice_fltr_desc *fdirdp;
4062         volatile struct ice_tx_desc *txdp;
4063         uint32_t td_cmd;
4064         uint16_t i;
4065
4066         fdirdp = (volatile struct ice_fltr_desc *)
4067                 (&txq->tx_ring[txq->tx_tail]);
4068         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4069         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4070
4071         txdp = &txq->tx_ring[txq->tx_tail + 1];
4072         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4073         td_cmd = ICE_TX_DESC_CMD_EOP |
4074                 ICE_TX_DESC_CMD_RS  |
4075                 ICE_TX_DESC_CMD_DUMMY;
4076
4077         txdp->cmd_type_offset_bsz =
4078                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4079
4080         txq->tx_tail += 2;
4081         if (txq->tx_tail >= txq->nb_tx_desc)
4082                 txq->tx_tail = 0;
4083         /* Update the tx tail register */
4084         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4085         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4086                 if ((txdp->cmd_type_offset_bsz &
4087                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4088                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4089                         break;
4090                 rte_delay_us(1);
4091         }
4092         if (i >= ICE_FDIR_MAX_WAIT_US) {
4093                 PMD_DRV_LOG(ERR,
4094                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4095                 return -ETIMEDOUT;
4096         }
4097
4098         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4099                 int ret;
4100
4101                 ret = ice_check_fdir_programming_status(rxq);
4102                 if (ret == -EAGAIN)
4103                         rte_delay_us(1);
4104                 else
4105                         return ret;
4106         }
4107
4108         PMD_DRV_LOG(ERR,
4109                     "Failed to program FDIR filter: programming status reported.");
4110         return -ETIMEDOUT;
4111
4112
4113 }