drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  11                 PKT_TX_IP_CKSUM |                \
  12                 PKT_TX_L4_MASK |                 \
  13                 PKT_TX_TCP_SEG |                 \
  14                 PKT_TX_OUTER_IP_CKSUM)
  15
  16 #define ICE_RX_ERR_BITS 0x3f
  17
  18 static enum ice_status
  19 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  20 {
  21         struct ice_vsi *vsi = rxq->vsi;
  22         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  23         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  24         struct ice_rlan_ctx rx_ctx;
  25         enum ice_status err;
  26         uint16_t buf_size, len;
  27         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  28         uint32_t regval;
  29
  30         /**
  31          * The kernel driver uses flex descriptor. It sets the register
  32          * to flex descriptor mode.
  33          * DPDK uses legacy descriptor. It should set the register back
  34          * to the default value, then uses legacy descriptor mode.
  35          */
  36         regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
  37                  QRXFLXP_CNTXT_RXDID_PRIO_M;
  38         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
  39
  40         /* Set buffer size as the head split is disabled. */
  41         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  42                               RTE_PKTMBUF_HEADROOM);
  43         rxq->rx_hdr_len = 0;
  44         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  45         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  46         rxq->max_pkt_len = RTE_MIN(len,
  47                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  48
  49         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  50                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
  51                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  52                         PMD_DRV_LOG(ERR, "maximum packet length must "
  53                                     "be larger than %u and smaller than %u,"
  54                                     "as jumbo frame is enabled",
  55                                     (uint32_t)RTE_ETHER_MAX_LEN,
  56                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  57                         return -EINVAL;
  58                 }
  59         } else {
  60                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
  61                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
  62                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  63                                     "larger than %u and smaller than %u, "
  64                                     "as jumbo frame is disabled",
  65                                     (uint32_t)RTE_ETHER_MIN_LEN,
  66                                     (uint32_t)RTE_ETHER_MAX_LEN);
  67                         return -EINVAL;
  68                 }
  69         }
  70
  71         memset(&rx_ctx, 0, sizeof(rx_ctx));
  72
  73         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
  74         rx_ctx.qlen = rxq->nb_rx_desc;
  75         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  76         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  77         rx_ctx.dtype = 0; /* No Header Split mode */
  78 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  79         rx_ctx.dsize = 1; /* 32B descriptors */
  80 #endif
  81         rx_ctx.rxmax = rxq->max_pkt_len;
  82         /* TPH: Transaction Layer Packet (TLP) processing hints */
  83         rx_ctx.tphrdesc_ena = 1;
  84         rx_ctx.tphwdesc_ena = 1;
  85         rx_ctx.tphdata_ena = 1;
  86         rx_ctx.tphhead_ena = 1;
  87         /* Low Receive Queue Threshold defined in 64 descriptors units.
  88          * When the number of free descriptors goes below the lrxqthresh,
  89          * an immediate interrupt is triggered.
  90          */
  91         rx_ctx.lrxqthresh = 2;
  92         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
  93         rx_ctx.l2tsel = 1;
  94         rx_ctx.showiv = 0;
  95         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
  96
  97         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
  98         if (err) {
  99                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 100                             rxq->queue_id);
 101                 return -EINVAL;
 102         }
 103         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 104         if (err) {
 105                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 106                             rxq->queue_id);
 107                 return -EINVAL;
 108         }
 109
 110         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 111                               RTE_PKTMBUF_HEADROOM);
 112
 113         /* Check if scattered RX needs to be used. */
 114         if (rxq->max_pkt_len > buf_size)
 115                 dev->data->scattered_rx = 1;
 116
 117         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 118
 119         /* Init the Rx tail register*/
 120         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 121
 122         return 0;
 123 }
 124
 125 /* Allocate mbufs for all descriptors in rx queue */
 126 static int
 127 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 128 {
 129         struct ice_rx_entry *rxe = rxq->sw_ring;
 130         uint64_t dma_addr;
 131         uint16_t i;
 132
 133         for (i = 0; i < rxq->nb_rx_desc; i++) {
 134                 volatile union ice_rx_desc *rxd;
 135                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 136
 137                 if (unlikely(!mbuf)) {
 138                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 139                         return -ENOMEM;
 140                 }
 141
 142                 rte_mbuf_refcnt_set(mbuf, 1);
 143                 mbuf->next = NULL;
 144                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 145                 mbuf->nb_segs = 1;
 146                 mbuf->port = rxq->port_id;
 147
 148                 dma_addr =
 149                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 150
 151                 rxd = &rxq->rx_ring[i];
 152                 rxd->read.pkt_addr = dma_addr;
 153                 rxd->read.hdr_addr = 0;
 154 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 155                 rxd->read.rsvd1 = 0;
 156                 rxd->read.rsvd2 = 0;
 157 #endif
 158                 rxe[i].mbuf = mbuf;
 159         }
 160
 161         return 0;
 162 }
 163
 164 /* Free all mbufs for descriptors in rx queue */
 165 static void
 166 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 167 {
 168         uint16_t i;
 169
 170         if (!rxq || !rxq->sw_ring) {
 171                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 172                 return;
 173         }
 174
 175         for (i = 0; i < rxq->nb_rx_desc; i++) {
 176                 if (rxq->sw_ring[i].mbuf) {
 177                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 178                         rxq->sw_ring[i].mbuf = NULL;
 179                 }
 180         }
 181 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 182                 if (rxq->rx_nb_avail == 0)
 183                         return;
 184                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 185                         struct rte_mbuf *mbuf;
 186
 187                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 188                         rte_pktmbuf_free_seg(mbuf);
 189                 }
 190                 rxq->rx_nb_avail = 0;
 191 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 192 }
 193
 194 static void
 195 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 196 {
 197         rxq->rx_rel_mbufs(rxq);
 198 }
 199
 200 /* turn on or off rx queue
 201  * @q_idx: queue index in pf scope
 202  * @on: turn on or off the queue
 203  */
 204 static int
 205 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 206 {
 207         uint32_t reg;
 208         uint16_t j;
 209
 210         /* QRX_CTRL = QRX_ENA */
 211         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 212
 213         if (on) {
 214                 if (reg & QRX_CTRL_QENA_STAT_M)
 215                         return 0; /* Already on, skip */
 216                 reg |= QRX_CTRL_QENA_REQ_M;
 217         } else {
 218                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 219                         return 0; /* Already off, skip */
 220                 reg &= ~QRX_CTRL_QENA_REQ_M;
 221         }
 222
 223         /* Write the register */
 224         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 225         /* Check the result. It is said that QENA_STAT
 226          * follows the QENA_REQ not more than 10 use.
 227          * TODO: need to change the wait counter later
 228          */
 229         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 230                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 231                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 232                 if (on) {
 233                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 234                             (reg & QRX_CTRL_QENA_STAT_M))
 235                                 break;
 236                 } else {
 237                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 238                             !(reg & QRX_CTRL_QENA_STAT_M))
 239                                 break;
 240                 }
 241         }
 242
 243         /* Check if it is timeout */
 244         if (j >= ICE_CHK_Q_ENA_COUNT) {
 245                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 246                             (on ? "enable" : "disable"), q_idx);
 247                 return -ETIMEDOUT;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static inline int
 254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 255 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 256 #else
 257 ice_check_rx_burst_bulk_alloc_preconditions
 258         (__rte_unused struct ice_rx_queue *rxq)
 259 #endif
 260 {
 261         int ret = 0;
 262
 263 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 264         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 265                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 266                              "rxq->rx_free_thresh=%d, "
 267                              "ICE_RX_MAX_BURST=%d",
 268                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 269                 ret = -EINVAL;
 270         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 271                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 272                              "rxq->rx_free_thresh=%d, "
 273                              "rxq->nb_rx_desc=%d",
 274                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 275                 ret = -EINVAL;
 276         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 277                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 278                              "rxq->nb_rx_desc=%d, "
 279                              "rxq->rx_free_thresh=%d",
 280                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 281                 ret = -EINVAL;
 282         }
 283 #else
 284         ret = -EINVAL;
 285 #endif
 286
 287         return ret;
 288 }
 289
 290 /* reset fields in ice_rx_queue back to default */
 291 static void
 292 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 293 {
 294         unsigned int i;
 295         uint16_t len;
 296
 297         if (!rxq) {
 298                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 299                 return;
 300         }
 301
 302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 303         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 304                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 305         else
 306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 307                 len = rxq->nb_rx_desc;
 308
 309         for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
 310                 ((volatile char *)rxq->rx_ring)[i] = 0;
 311
 312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 313         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 314         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 315                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 316
 317         rxq->rx_nb_avail = 0;
 318         rxq->rx_next_avail = 0;
 319         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 320 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 321
 322         rxq->rx_tail = 0;
 323         rxq->nb_rx_hold = 0;
 324         rxq->pkt_first_seg = NULL;
 325         rxq->pkt_last_seg = NULL;
 326
 327         rxq->rxrearm_start = 0;
 328         rxq->rxrearm_nb = 0;
 329 }
 330
 331 int
 332 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 333 {
 334         struct ice_rx_queue *rxq;
 335         int err;
 336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337
 338         PMD_INIT_FUNC_TRACE();
 339
 340         if (rx_queue_id >= dev->data->nb_rx_queues) {
 341                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 342                             rx_queue_id, dev->data->nb_rx_queues);
 343                 return -EINVAL;
 344         }
 345
 346         rxq = dev->data->rx_queues[rx_queue_id];
 347         if (!rxq || !rxq->q_set) {
 348                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 349                             rx_queue_id);
 350                 return -EINVAL;
 351         }
 352
 353         err = ice_program_hw_rx_queue(rxq);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 356                             rx_queue_id);
 357                 return -EIO;
 358         }
 359
 360         err = ice_alloc_rx_queue_mbufs(rxq);
 361         if (err) {
 362                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 363                 return -ENOMEM;
 364         }
 365
 366         rte_wmb();
 367
 368         /* Init the RX tail register. */
 369         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 370
 371         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 372         if (err) {
 373                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 374                             rx_queue_id);
 375
 376                 ice_rx_queue_release_mbufs(rxq);
 377                 ice_reset_rx_queue(rxq);
 378                 return -EINVAL;
 379         }
 380
 381         dev->data->rx_queue_state[rx_queue_id] =
 382                 RTE_ETH_QUEUE_STATE_STARTED;
 383
 384         return 0;
 385 }
 386
 387 int
 388 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 389 {
 390         struct ice_rx_queue *rxq;
 391         int err;
 392         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 393
 394         if (rx_queue_id < dev->data->nb_rx_queues) {
 395                 rxq = dev->data->rx_queues[rx_queue_id];
 396
 397                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 398                 if (err) {
 399                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 400                                     rx_queue_id);
 401                         return -EINVAL;
 402                 }
 403                 ice_rx_queue_release_mbufs(rxq);
 404                 ice_reset_rx_queue(rxq);
 405                 dev->data->rx_queue_state[rx_queue_id] =
 406                         RTE_ETH_QUEUE_STATE_STOPPED;
 407         }
 408
 409         return 0;
 410 }
 411
 412 int
 413 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 414 {
 415         struct ice_tx_queue *txq;
 416         int err;
 417         struct ice_vsi *vsi;
 418         struct ice_hw *hw;
 419         struct ice_aqc_add_tx_qgrp txq_elem;
 420         struct ice_tlan_ctx tx_ctx;
 421
 422         PMD_INIT_FUNC_TRACE();
 423
 424         if (tx_queue_id >= dev->data->nb_tx_queues) {
 425                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 426                             tx_queue_id, dev->data->nb_tx_queues);
 427                 return -EINVAL;
 428         }
 429
 430         txq = dev->data->tx_queues[tx_queue_id];
 431         if (!txq || !txq->q_set) {
 432                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 433                             tx_queue_id);
 434                 return -EINVAL;
 435         }
 436
 437         vsi = txq->vsi;
 438         hw = ICE_VSI_TO_HW(vsi);
 439
 440         memset(&txq_elem, 0, sizeof(txq_elem));
 441         memset(&tx_ctx, 0, sizeof(tx_ctx));
 442         txq_elem.num_txqs = 1;
 443         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 444
 445         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 446         tx_ctx.qlen = txq->nb_tx_desc;
 447         tx_ctx.pf_num = hw->pf_id;
 448         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 449         tx_ctx.src_vsi = vsi->vsi_id;
 450         tx_ctx.port_num = hw->port_info->lport;
 451         tx_ctx.tso_ena = 1; /* tso enable */
 452         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 453         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 454
 455         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 456                     ice_tlan_ctx_info);
 457
 458         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 459
 460         /* Init the Tx tail register*/
 461         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 462
 463         /* Fix me, we assume TC always 0 here */
 464         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 465                         &txq_elem, sizeof(txq_elem), NULL);
 466         if (err) {
 467                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 468                 return -EIO;
 469         }
 470         /* store the schedule node id */
 471         txq->q_teid = txq_elem.txqs[0].q_teid;
 472
 473         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 474         return 0;
 475 }
 476
 477 /* Free all mbufs for descriptors in tx queue */
 478 static void
 479 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 480 {
 481         uint16_t i;
 482
 483         if (!txq || !txq->sw_ring) {
 484                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 485                 return;
 486         }
 487
 488         for (i = 0; i < txq->nb_tx_desc; i++) {
 489                 if (txq->sw_ring[i].mbuf) {
 490                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 491                         txq->sw_ring[i].mbuf = NULL;
 492                 }
 493         }
 494 }
 495 static void
 496 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 497 {
 498         txq->tx_rel_mbufs(txq);
 499 }
 500
 501 static void
 502 ice_reset_tx_queue(struct ice_tx_queue *txq)
 503 {
 504         struct ice_tx_entry *txe;
 505         uint16_t i, prev, size;
 506
 507         if (!txq) {
 508                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 509                 return;
 510         }
 511
 512         txe = txq->sw_ring;
 513         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 514         for (i = 0; i < size; i++)
 515                 ((volatile char *)txq->tx_ring)[i] = 0;
 516
 517         prev = (uint16_t)(txq->nb_tx_desc - 1);
 518         for (i = 0; i < txq->nb_tx_desc; i++) {
 519                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 520
 521                 txd->cmd_type_offset_bsz =
 522                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 523                 txe[i].mbuf =  NULL;
 524                 txe[i].last_id = i;
 525                 txe[prev].next_id = i;
 526                 prev = i;
 527         }
 528
 529         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 530         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 531
 532         txq->tx_tail = 0;
 533         txq->nb_tx_used = 0;
 534
 535         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 536         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 537 }
 538
 539 int
 540 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 541 {
 542         struct ice_tx_queue *txq;
 543         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 544         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 545         struct ice_vsi *vsi = pf->main_vsi;
 546         enum ice_status status;
 547         uint16_t q_ids[1];
 548         uint32_t q_teids[1];
 549         uint16_t q_handle = tx_queue_id;
 550
 551         if (tx_queue_id >= dev->data->nb_tx_queues) {
 552                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 553                             tx_queue_id, dev->data->nb_tx_queues);
 554                 return -EINVAL;
 555         }
 556
 557         txq = dev->data->tx_queues[tx_queue_id];
 558         if (!txq) {
 559                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 560                             tx_queue_id);
 561                 return -EINVAL;
 562         }
 563
 564         q_ids[0] = txq->reg_idx;
 565         q_teids[0] = txq->q_teid;
 566
 567         /* Fix me, we assume TC always 0 here */
 568         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 569                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 570         if (status != ICE_SUCCESS) {
 571                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 572                 return -EINVAL;
 573         }
 574
 575         ice_tx_queue_release_mbufs(txq);
 576         ice_reset_tx_queue(txq);
 577         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 578
 579         return 0;
 580 }
 581
 582 int
 583 ice_rx_queue_setup(struct rte_eth_dev *dev,
 584                    uint16_t queue_idx,
 585                    uint16_t nb_desc,
 586                    unsigned int socket_id,
 587                    const struct rte_eth_rxconf *rx_conf,
 588                    struct rte_mempool *mp)
 589 {
 590         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 591         struct ice_adapter *ad =
 592                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 593         struct ice_vsi *vsi = pf->main_vsi;
 594         struct ice_rx_queue *rxq;
 595         const struct rte_memzone *rz;
 596         uint32_t ring_size;
 597         uint16_t len;
 598         int use_def_burst_func = 1;
 599
 600         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 601             nb_desc > ICE_MAX_RING_DESC ||
 602             nb_desc < ICE_MIN_RING_DESC) {
 603                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 604                              "invalid", nb_desc);
 605                 return -EINVAL;
 606         }
 607
 608         /* Free memory if needed */
 609         if (dev->data->rx_queues[queue_idx]) {
 610                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 611                 dev->data->rx_queues[queue_idx] = NULL;
 612         }
 613
 614         /* Allocate the rx queue data structure */
 615         rxq = rte_zmalloc_socket(NULL,
 616                                  sizeof(struct ice_rx_queue),
 617                                  RTE_CACHE_LINE_SIZE,
 618                                  socket_id);
 619         if (!rxq) {
 620                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 621                              "rx queue data structure");
 622                 return -ENOMEM;
 623         }
 624         rxq->mp = mp;
 625         rxq->nb_rx_desc = nb_desc;
 626         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 627         rxq->queue_id = queue_idx;
 628
 629         rxq->reg_idx = vsi->base_queue + queue_idx;
 630         rxq->port_id = dev->data->port_id;
 631         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 632                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 633         else
 634                 rxq->crc_len = 0;
 635
 636         rxq->drop_en = rx_conf->rx_drop_en;
 637         rxq->vsi = vsi;
 638         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 639
 640         /* Allocate the maximun number of RX ring hardware descriptor. */
 641         len = ICE_MAX_RING_DESC;
 642
 643 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 644         /**
 645          * Allocating a little more memory because vectorized/bulk_alloc Rx
 646          * functions doesn't check boundaries each time.
 647          */
 648         len += ICE_RX_MAX_BURST;
 649 #endif
 650
 651         /* Allocate the maximum number of RX ring hardware descriptor. */
 652         ring_size = sizeof(union ice_rx_desc) * len;
 653         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 654         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 655                                       ring_size, ICE_RING_BASE_ALIGN,
 656                                       socket_id);
 657         if (!rz) {
 658                 ice_rx_queue_release(rxq);
 659                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 660                 return -ENOMEM;
 661         }
 662
 663         /* Zero all the descriptors in the ring. */
 664         memset(rz->addr, 0, ring_size);
 665
 666         rxq->rx_ring_dma = rz->iova;
 667         rxq->rx_ring = rz->addr;
 668
 669 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 670         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 671 #else
 672         len = nb_desc;
 673 #endif
 674
 675         /* Allocate the software ring. */
 676         rxq->sw_ring = rte_zmalloc_socket(NULL,
 677                                           sizeof(struct ice_rx_entry) * len,
 678                                           RTE_CACHE_LINE_SIZE,
 679                                           socket_id);
 680         if (!rxq->sw_ring) {
 681                 ice_rx_queue_release(rxq);
 682                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 683                 return -ENOMEM;
 684         }
 685
 686         ice_reset_rx_queue(rxq);
 687         rxq->q_set = TRUE;
 688         dev->data->rx_queues[queue_idx] = rxq;
 689         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 690
 691         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 692
 693         if (!use_def_burst_func) {
 694 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 695                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 696                              "satisfied. Rx Burst Bulk Alloc function will be "
 697                              "used on port=%d, queue=%d.",
 698                              rxq->port_id, rxq->queue_id);
 699 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 700         } else {
 701                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 702                              "not satisfied, Scattered Rx is requested, "
 703                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 704                              "not enabled on port=%d, queue=%d.",
 705                              rxq->port_id, rxq->queue_id);
 706                 ad->rx_bulk_alloc_allowed = false;
 707         }
 708
 709         return 0;
 710 }
 711
 712 void
 713 ice_rx_queue_release(void *rxq)
 714 {
 715         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 716
 717         if (!q) {
 718                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 719                 return;
 720         }
 721
 722         ice_rx_queue_release_mbufs(q);
 723         rte_free(q->sw_ring);
 724         rte_free(q);
 725 }
 726
 727 int
 728 ice_tx_queue_setup(struct rte_eth_dev *dev,
 729                    uint16_t queue_idx,
 730                    uint16_t nb_desc,
 731                    unsigned int socket_id,
 732                    const struct rte_eth_txconf *tx_conf)
 733 {
 734         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 735         struct ice_vsi *vsi = pf->main_vsi;
 736         struct ice_tx_queue *txq;
 737         const struct rte_memzone *tz;
 738         uint32_t ring_size;
 739         uint16_t tx_rs_thresh, tx_free_thresh;
 740         uint64_t offloads;
 741
 742         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 743
 744         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 745             nb_desc > ICE_MAX_RING_DESC ||
 746             nb_desc < ICE_MIN_RING_DESC) {
 747                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 748                              "invalid", nb_desc);
 749                 return -EINVAL;
 750         }
 751
 752         /**
 753          * The following two parameters control the setting of the RS bit on
 754          * transmit descriptors. TX descriptors will have their RS bit set
 755          * after txq->tx_rs_thresh descriptors have been used. The TX
 756          * descriptor ring will be cleaned after txq->tx_free_thresh
 757          * descriptors are used or if the number of descriptors required to
 758          * transmit a packet is greater than the number of free TX descriptors.
 759          *
 760          * The following constraints must be satisfied:
 761          *  - tx_rs_thresh must be greater than 0.
 762          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 763          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 764          *  - tx_rs_thresh must be a divisor of the ring size.
 765          *  - tx_free_thresh must be greater than 0.
 766          *  - tx_free_thresh must be less than the size of the ring minus 3.
 767          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
 768          *
 769          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 770          * race condition, hence the maximum threshold constraints. When set
 771          * to zero use default values.
 772          */
 773         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 774                                     tx_conf->tx_free_thresh :
 775                                     ICE_DEFAULT_TX_FREE_THRESH);
 776         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
 777         tx_rs_thresh =
 778                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
 779                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
 780         if (tx_conf->tx_rs_thresh)
 781                 tx_rs_thresh = tx_conf->tx_rs_thresh;
 782         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
 783                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
 784                                 "exceed nb_desc. (tx_rs_thresh=%u "
 785                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
 786                                 (unsigned int)tx_rs_thresh,
 787                                 (unsigned int)tx_free_thresh,
 788                                 (unsigned int)nb_desc,
 789                                 (int)dev->data->port_id,
 790                                 (int)queue_idx);
 791                 return -EINVAL;
 792         }
 793         if (tx_rs_thresh >= (nb_desc - 2)) {
 794                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 795                              "number of TX descriptors minus 2. "
 796                              "(tx_rs_thresh=%u port=%d queue=%d)",
 797                              (unsigned int)tx_rs_thresh,
 798                              (int)dev->data->port_id,
 799                              (int)queue_idx);
 800                 return -EINVAL;
 801         }
 802         if (tx_free_thresh >= (nb_desc - 3)) {
 803                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 804                              "tx_free_thresh must be less than the "
 805                              "number of TX descriptors minus 3. "
 806                              "(tx_free_thresh=%u port=%d queue=%d)",
 807                              (unsigned int)tx_free_thresh,
 808                              (int)dev->data->port_id,
 809                              (int)queue_idx);
 810                 return -EINVAL;
 811         }
 812         if (tx_rs_thresh > tx_free_thresh) {
 813                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 814                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 815                              " tx_rs_thresh=%u port=%d queue=%d)",
 816                              (unsigned int)tx_free_thresh,
 817                              (unsigned int)tx_rs_thresh,
 818                              (int)dev->data->port_id,
 819                              (int)queue_idx);
 820                 return -EINVAL;
 821         }
 822         if ((nb_desc % tx_rs_thresh) != 0) {
 823                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 824                              "number of TX descriptors. (tx_rs_thresh=%u"
 825                              " port=%d queue=%d)",
 826                              (unsigned int)tx_rs_thresh,
 827                              (int)dev->data->port_id,
 828                              (int)queue_idx);
 829                 return -EINVAL;
 830         }
 831         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 832                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 833                              "tx_rs_thresh is greater than 1. "
 834                              "(tx_rs_thresh=%u port=%d queue=%d)",
 835                              (unsigned int)tx_rs_thresh,
 836                              (int)dev->data->port_id,
 837                              (int)queue_idx);
 838                 return -EINVAL;
 839         }
 840
 841         /* Free memory if needed. */
 842         if (dev->data->tx_queues[queue_idx]) {
 843                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 844                 dev->data->tx_queues[queue_idx] = NULL;
 845         }
 846
 847         /* Allocate the TX queue data structure. */
 848         txq = rte_zmalloc_socket(NULL,
 849                                  sizeof(struct ice_tx_queue),
 850                                  RTE_CACHE_LINE_SIZE,
 851                                  socket_id);
 852         if (!txq) {
 853                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 854                              "tx queue structure");
 855                 return -ENOMEM;
 856         }
 857
 858         /* Allocate TX hardware ring descriptors. */
 859         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 860         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 861         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 862                                       ring_size, ICE_RING_BASE_ALIGN,
 863                                       socket_id);
 864         if (!tz) {
 865                 ice_tx_queue_release(txq);
 866                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 867                 return -ENOMEM;
 868         }
 869
 870         txq->nb_tx_desc = nb_desc;
 871         txq->tx_rs_thresh = tx_rs_thresh;
 872         txq->tx_free_thresh = tx_free_thresh;
 873         txq->pthresh = tx_conf->tx_thresh.pthresh;
 874         txq->hthresh = tx_conf->tx_thresh.hthresh;
 875         txq->wthresh = tx_conf->tx_thresh.wthresh;
 876         txq->queue_id = queue_idx;
 877
 878         txq->reg_idx = vsi->base_queue + queue_idx;
 879         txq->port_id = dev->data->port_id;
 880         txq->offloads = offloads;
 881         txq->vsi = vsi;
 882         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 883
 884         txq->tx_ring_dma = tz->iova;
 885         txq->tx_ring = tz->addr;
 886
 887         /* Allocate software ring */
 888         txq->sw_ring =
 889                 rte_zmalloc_socket(NULL,
 890                                    sizeof(struct ice_tx_entry) * nb_desc,
 891                                    RTE_CACHE_LINE_SIZE,
 892                                    socket_id);
 893         if (!txq->sw_ring) {
 894                 ice_tx_queue_release(txq);
 895                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 896                 return -ENOMEM;
 897         }
 898
 899         ice_reset_tx_queue(txq);
 900         txq->q_set = TRUE;
 901         dev->data->tx_queues[queue_idx] = txq;
 902         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
 903         ice_set_tx_function_flag(dev, txq);
 904
 905         return 0;
 906 }
 907
 908 void
 909 ice_tx_queue_release(void *txq)
 910 {
 911         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 912
 913         if (!q) {
 914                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 915                 return;
 916         }
 917
 918         ice_tx_queue_release_mbufs(q);
 919         rte_free(q->sw_ring);
 920         rte_free(q);
 921 }
 922
 923 void
 924 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 925                  struct rte_eth_rxq_info *qinfo)
 926 {
 927         struct ice_rx_queue *rxq;
 928
 929         rxq = dev->data->rx_queues[queue_id];
 930
 931         qinfo->mp = rxq->mp;
 932         qinfo->scattered_rx = dev->data->scattered_rx;
 933         qinfo->nb_desc = rxq->nb_rx_desc;
 934
 935         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 936         qinfo->conf.rx_drop_en = rxq->drop_en;
 937         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 938 }
 939
 940 void
 941 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 942                  struct rte_eth_txq_info *qinfo)
 943 {
 944         struct ice_tx_queue *txq;
 945
 946         txq = dev->data->tx_queues[queue_id];
 947
 948         qinfo->nb_desc = txq->nb_tx_desc;
 949
 950         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 951         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 952         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 953
 954         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 955         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 956         qinfo->conf.offloads = txq->offloads;
 957         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 958 }
 959
 960 uint32_t
 961 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 962 {
 963 #define ICE_RXQ_SCAN_INTERVAL 4
 964         volatile union ice_rx_desc *rxdp;
 965         struct ice_rx_queue *rxq;
 966         uint16_t desc = 0;
 967
 968         rxq = dev->data->rx_queues[rx_queue_id];
 969         rxdp = &rxq->rx_ring[rxq->rx_tail];
 970         while ((desc < rxq->nb_rx_desc) &&
 971                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 972                  ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
 973                (1 << ICE_RX_DESC_STATUS_DD_S)) {
 974                 /**
 975                  * Check the DD bit of a rx descriptor of each 4 in a group,
 976                  * to avoid checking too frequently and downgrading performance
 977                  * too much.
 978                  */
 979                 desc += ICE_RXQ_SCAN_INTERVAL;
 980                 rxdp += ICE_RXQ_SCAN_INTERVAL;
 981                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
 982                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
 983                                  desc - rxq->nb_rx_desc]);
 984         }
 985
 986         return desc;
 987 }
 988
 989 /* Translate the rx descriptor status to pkt flags */
 990 static inline uint64_t
 991 ice_rxd_status_to_pkt_flags(uint64_t qword)
 992 {
 993         uint64_t flags;
 994
 995         /* Check if RSS_HASH */
 996         flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) &
 997                   ICE_RX_DESC_FLTSTAT_RSS_HASH) ==
 998                  ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 999
1000         return flags;
1001 }
1002
1003 /* Rx L3/L4 checksum */
1004 static inline uint64_t
1005 ice_rxd_error_to_pkt_flags(uint64_t qword)
1006 {
1007         uint64_t flags = 0;
1008         uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
1009
1010         if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
1011                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1012                 return flags;
1013         }
1014
1015         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
1016                 flags |= PKT_RX_IP_CKSUM_BAD;
1017         else
1018                 flags |= PKT_RX_IP_CKSUM_GOOD;
1019
1020         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
1021                 flags |= PKT_RX_L4_CKSUM_BAD;
1022         else
1023                 flags |= PKT_RX_L4_CKSUM_GOOD;
1024
1025         if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
1026                 flags |= PKT_RX_EIP_CKSUM_BAD;
1027
1028         return flags;
1029 }
1030
1031 static inline void
1032 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp)
1033 {
1034         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1035             (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) {
1036                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1037                 mb->vlan_tci =
1038                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1039                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1040                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
1041         } else {
1042                 mb->vlan_tci = 0;
1043         }
1044
1045 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1046         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
1047             (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) {
1048                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1049                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1050                 mb->vlan_tci_outer = mb->vlan_tci;
1051                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
1052                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1053                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
1054                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
1055         } else {
1056                 mb->vlan_tci_outer = 0;
1057         }
1058 #endif
1059         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1060                    mb->vlan_tci, mb->vlan_tci_outer);
1061 }
1062
1063 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1064 #define ICE_LOOK_AHEAD 8
1065 #if (ICE_LOOK_AHEAD != 8)
1066 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1067 #endif
1068 static inline int
1069 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1070 {
1071         volatile union ice_rx_desc *rxdp;
1072         struct ice_rx_entry *rxep;
1073         struct rte_mbuf *mb;
1074         uint16_t pkt_len;
1075         uint64_t qword1;
1076         uint32_t rx_status;
1077         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1078         int32_t i, j, nb_rx = 0;
1079         uint64_t pkt_flags = 0;
1080         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1081
1082         rxdp = &rxq->rx_ring[rxq->rx_tail];
1083         rxep = &rxq->sw_ring[rxq->rx_tail];
1084
1085         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1086         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S;
1087
1088         /* Make sure there is at least 1 packet to receive */
1089         if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1090                 return 0;
1091
1092         /**
1093          * Scan LOOK_AHEAD descriptors at a time to determine which
1094          * descriptors reference packets that are ready to be received.
1095          */
1096         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1097              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1098                 /* Read desc statuses backwards to avoid race condition */
1099                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) {
1100                         qword1 = rte_le_to_cpu_64(
1101                                         rxdp[j].wb.qword1.status_error_len);
1102                         s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1103                                ICE_RXD_QW1_STATUS_S;
1104                 }
1105
1106                 rte_smp_rmb();
1107
1108                 /* Compute how many status bits were set */
1109                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1110                         nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S);
1111
1112                 nb_rx += nb_dd;
1113
1114                 /* Translate descriptor info to mbuf parameters */
1115                 for (j = 0; j < nb_dd; j++) {
1116                         mb = rxep[j].mbuf;
1117                         qword1 = rte_le_to_cpu_64(
1118                                         rxdp[j].wb.qword1.status_error_len);
1119                         pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1120                                    ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1121                         mb->data_len = pkt_len;
1122                         mb->pkt_len = pkt_len;
1123                         mb->ol_flags = 0;
1124                         pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1125                         pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1126                         if (pkt_flags & PKT_RX_RSS_HASH)
1127                                 mb->hash.rss =
1128                                         rte_le_to_cpu_32(
1129                                                 rxdp[j].wb.qword0.hi_dword.rss);
1130                         mb->packet_type = ptype_tbl[(uint8_t)(
1131                                                 (qword1 &
1132                                                  ICE_RXD_QW1_PTYPE_M) >>
1133                                                 ICE_RXD_QW1_PTYPE_S)];
1134                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1135
1136                         mb->ol_flags |= pkt_flags;
1137                 }
1138
1139                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1140                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1141
1142                 if (nb_dd != ICE_LOOK_AHEAD)
1143                         break;
1144         }
1145
1146         /* Clear software ring entries */
1147         for (i = 0; i < nb_rx; i++)
1148                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1149
1150         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1151                    "port_id=%u, queue_id=%u, nb_rx=%d",
1152                    rxq->port_id, rxq->queue_id, nb_rx);
1153
1154         return nb_rx;
1155 }
1156
1157 static inline uint16_t
1158 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1159                        struct rte_mbuf **rx_pkts,
1160                        uint16_t nb_pkts)
1161 {
1162         uint16_t i;
1163         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1164
1165         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1166
1167         for (i = 0; i < nb_pkts; i++)
1168                 rx_pkts[i] = stage[i];
1169
1170         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1171         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1172
1173         return nb_pkts;
1174 }
1175
1176 static inline int
1177 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1178 {
1179         volatile union ice_rx_desc *rxdp;
1180         struct ice_rx_entry *rxep;
1181         struct rte_mbuf *mb;
1182         uint16_t alloc_idx, i;
1183         uint64_t dma_addr;
1184         int diag;
1185
1186         /* Allocate buffers in bulk */
1187         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1188                                (rxq->rx_free_thresh - 1));
1189         rxep = &rxq->sw_ring[alloc_idx];
1190         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1191                                     rxq->rx_free_thresh);
1192         if (unlikely(diag != 0)) {
1193                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1194                 return -ENOMEM;
1195         }
1196
1197         rxdp = &rxq->rx_ring[alloc_idx];
1198         for (i = 0; i < rxq->rx_free_thresh; i++) {
1199                 if (likely(i < (rxq->rx_free_thresh - 1)))
1200                         /* Prefetch next mbuf */
1201                         rte_prefetch0(rxep[i + 1].mbuf);
1202
1203                 mb = rxep[i].mbuf;
1204                 rte_mbuf_refcnt_set(mb, 1);
1205                 mb->next = NULL;
1206                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1207                 mb->nb_segs = 1;
1208                 mb->port = rxq->port_id;
1209                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1210                 rxdp[i].read.hdr_addr = 0;
1211                 rxdp[i].read.pkt_addr = dma_addr;
1212         }
1213
1214         /* Update rx tail regsiter */
1215         rte_wmb();
1216         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1217
1218         rxq->rx_free_trigger =
1219                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1220         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1221                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1222
1223         return 0;
1224 }
1225
1226 static inline uint16_t
1227 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1228 {
1229         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1230         uint16_t nb_rx = 0;
1231         struct rte_eth_dev *dev;
1232
1233         if (!nb_pkts)
1234                 return 0;
1235
1236         if (rxq->rx_nb_avail)
1237                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1238
1239         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1240         rxq->rx_next_avail = 0;
1241         rxq->rx_nb_avail = nb_rx;
1242         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1243
1244         if (rxq->rx_tail > rxq->rx_free_trigger) {
1245                 if (ice_rx_alloc_bufs(rxq) != 0) {
1246                         uint16_t i, j;
1247
1248                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1249                         dev->data->rx_mbuf_alloc_failed +=
1250                                 rxq->rx_free_thresh;
1251                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1252                                    "port_id=%u, queue_id=%u",
1253                                    rxq->port_id, rxq->queue_id);
1254                         rxq->rx_nb_avail = 0;
1255                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1256                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1257                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1258
1259                         return 0;
1260                 }
1261         }
1262
1263         if (rxq->rx_tail >= rxq->nb_rx_desc)
1264                 rxq->rx_tail = 0;
1265
1266         if (rxq->rx_nb_avail)
1267                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1268
1269         return 0;
1270 }
1271
1272 static uint16_t
1273 ice_recv_pkts_bulk_alloc(void *rx_queue,
1274                          struct rte_mbuf **rx_pkts,
1275                          uint16_t nb_pkts)
1276 {
1277         uint16_t nb_rx = 0;
1278         uint16_t n;
1279         uint16_t count;
1280
1281         if (unlikely(nb_pkts == 0))
1282                 return nb_rx;
1283
1284         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1285                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1286
1287         while (nb_pkts) {
1288                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1289                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1290                 nb_rx = (uint16_t)(nb_rx + count);
1291                 nb_pkts = (uint16_t)(nb_pkts - count);
1292                 if (count < n)
1293                         break;
1294         }
1295
1296         return nb_rx;
1297 }
1298 #else
1299 static uint16_t
1300 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1301                          struct rte_mbuf __rte_unused **rx_pkts,
1302                          uint16_t __rte_unused nb_pkts)
1303 {
1304         return 0;
1305 }
1306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1307
1308 static uint16_t
1309 ice_recv_scattered_pkts(void *rx_queue,
1310                         struct rte_mbuf **rx_pkts,
1311                         uint16_t nb_pkts)
1312 {
1313         struct ice_rx_queue *rxq = rx_queue;
1314         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1315         volatile union ice_rx_desc *rxdp;
1316         union ice_rx_desc rxd;
1317         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1318         struct ice_rx_entry *rxe;
1319         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1320         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1321         struct rte_mbuf *nmb; /* new allocated mbuf */
1322         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1323         uint16_t rx_id = rxq->rx_tail;
1324         uint16_t nb_rx = 0;
1325         uint16_t nb_hold = 0;
1326         uint16_t rx_packet_len;
1327         uint32_t rx_status;
1328         uint64_t qword1;
1329         uint64_t dma_addr;
1330         uint64_t pkt_flags = 0;
1331         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1332         struct rte_eth_dev *dev;
1333
1334         while (nb_rx < nb_pkts) {
1335                 rxdp = &rx_ring[rx_id];
1336                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1337                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1338                             ICE_RXD_QW1_STATUS_S;
1339
1340                 /* Check the DD bit first */
1341                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1342                         break;
1343
1344                 /* allocate mbuf */
1345                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1346                 if (unlikely(!nmb)) {
1347                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1348                         dev->data->rx_mbuf_alloc_failed++;
1349                         break;
1350                 }
1351                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1352
1353                 nb_hold++;
1354                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1355                 rx_id++;
1356                 if (unlikely(rx_id == rxq->nb_rx_desc))
1357                         rx_id = 0;
1358
1359                 /* Prefetch next mbuf */
1360                 rte_prefetch0(sw_ring[rx_id].mbuf);
1361
1362                 /**
1363                  * When next RX descriptor is on a cache line boundary,
1364                  * prefetch the next 4 RX descriptors and next 8 pointers
1365                  * to mbufs.
1366                  */
1367                 if ((rx_id & 0x3) == 0) {
1368                         rte_prefetch0(&rx_ring[rx_id]);
1369                         rte_prefetch0(&sw_ring[rx_id]);
1370                 }
1371
1372                 rxm = rxe->mbuf;
1373                 rxe->mbuf = nmb;
1374                 dma_addr =
1375                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1376
1377                 /* Set data buffer address and data length of the mbuf */
1378                 rxdp->read.hdr_addr = 0;
1379                 rxdp->read.pkt_addr = dma_addr;
1380                 rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1381                                 ICE_RXD_QW1_LEN_PBUF_S;
1382                 rxm->data_len = rx_packet_len;
1383                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1384                 ice_rxd_to_vlan_tci(rxm, rxdp);
1385                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1386                                                         ICE_RXD_QW1_PTYPE_M) >>
1387                                                        ICE_RXD_QW1_PTYPE_S)];
1388
1389                 /**
1390                  * If this is the first buffer of the received packet, set the
1391                  * pointer to the first mbuf of the packet and initialize its
1392                  * context. Otherwise, update the total length and the number
1393                  * of segments of the current scattered packet, and update the
1394                  * pointer to the last mbuf of the current packet.
1395                  */
1396                 if (!first_seg) {
1397                         first_seg = rxm;
1398                         first_seg->nb_segs = 1;
1399                         first_seg->pkt_len = rx_packet_len;
1400                 } else {
1401                         first_seg->pkt_len =
1402                                 (uint16_t)(first_seg->pkt_len +
1403                                            rx_packet_len);
1404                         first_seg->nb_segs++;
1405                         last_seg->next = rxm;
1406                 }
1407
1408                 /**
1409                  * If this is not the last buffer of the received packet,
1410                  * update the pointer to the last mbuf of the current scattered
1411                  * packet and continue to parse the RX ring.
1412                  */
1413                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) {
1414                         last_seg = rxm;
1415                         continue;
1416                 }
1417
1418                 /**
1419                  * This is the last buffer of the received packet. If the CRC
1420                  * is not stripped by the hardware:
1421                  *  - Subtract the CRC length from the total packet length.
1422                  *  - If the last buffer only contains the whole CRC or a part
1423                  *  of it, free the mbuf associated to the last buffer. If part
1424                  *  of the CRC is also contained in the previous mbuf, subtract
1425                  *  the length of that CRC part from the data length of the
1426                  *  previous mbuf.
1427                  */
1428                 rxm->next = NULL;
1429                 if (unlikely(rxq->crc_len > 0)) {
1430                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1431                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1432                                 rte_pktmbuf_free_seg(rxm);
1433                                 first_seg->nb_segs--;
1434                                 last_seg->data_len =
1435                                         (uint16_t)(last_seg->data_len -
1436                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1437                                 last_seg->next = NULL;
1438                         } else
1439                                 rxm->data_len = (uint16_t)(rx_packet_len -
1440                                                            RTE_ETHER_CRC_LEN);
1441                 }
1442
1443                 first_seg->port = rxq->port_id;
1444                 first_seg->ol_flags = 0;
1445
1446                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1447                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1448                 if (pkt_flags & PKT_RX_RSS_HASH)
1449                         first_seg->hash.rss =
1450                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1451
1452                 first_seg->ol_flags |= pkt_flags;
1453                 /* Prefetch data of first segment, if configured to do so. */
1454                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1455                                           first_seg->data_off));
1456                 rx_pkts[nb_rx++] = first_seg;
1457                 first_seg = NULL;
1458         }
1459
1460         /* Record index of the next RX descriptor to probe. */
1461         rxq->rx_tail = rx_id;
1462         rxq->pkt_first_seg = first_seg;
1463         rxq->pkt_last_seg = last_seg;
1464
1465         /**
1466          * If the number of free RX descriptors is greater than the RX free
1467          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1468          * register. Update the RDT with the value of the last processed RX
1469          * descriptor minus 1, to guarantee that the RDT register is never
1470          * equal to the RDH register, which creates a "full" ring situtation
1471          * from the hardware point of view.
1472          */
1473         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1474         if (nb_hold > rxq->rx_free_thresh) {
1475                 rx_id = (uint16_t)(rx_id == 0 ?
1476                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1477                 /* write TAIL register */
1478                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1479                 nb_hold = 0;
1480         }
1481         rxq->nb_rx_hold = nb_hold;
1482
1483         /* return received packet in the burst */
1484         return nb_rx;
1485 }
1486
1487 const uint32_t *
1488 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1489 {
1490         static const uint32_t ptypes[] = {
1491                 /* refers to ice_get_default_pkt_type() */
1492                 RTE_PTYPE_L2_ETHER,
1493                 RTE_PTYPE_L2_ETHER_LLDP,
1494                 RTE_PTYPE_L2_ETHER_ARP,
1495                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1496                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1497                 RTE_PTYPE_L4_FRAG,
1498                 RTE_PTYPE_L4_ICMP,
1499                 RTE_PTYPE_L4_NONFRAG,
1500                 RTE_PTYPE_L4_SCTP,
1501                 RTE_PTYPE_L4_TCP,
1502                 RTE_PTYPE_L4_UDP,
1503                 RTE_PTYPE_TUNNEL_GRENAT,
1504                 RTE_PTYPE_TUNNEL_IP,
1505                 RTE_PTYPE_INNER_L2_ETHER,
1506                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1507                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1508                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1509                 RTE_PTYPE_INNER_L4_FRAG,
1510                 RTE_PTYPE_INNER_L4_ICMP,
1511                 RTE_PTYPE_INNER_L4_NONFRAG,
1512                 RTE_PTYPE_INNER_L4_SCTP,
1513                 RTE_PTYPE_INNER_L4_TCP,
1514                 RTE_PTYPE_INNER_L4_UDP,
1515                 RTE_PTYPE_TUNNEL_GTPC,
1516                 RTE_PTYPE_TUNNEL_GTPU,
1517                 RTE_PTYPE_UNKNOWN
1518         };
1519
1520         if (dev->rx_pkt_burst == ice_recv_pkts ||
1521 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1522             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1523 #endif
1524             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1525                 return ptypes;
1526
1527 #ifdef RTE_ARCH_X86
1528         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1529             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1530             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1531             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1532                 return ptypes;
1533 #endif
1534
1535         return NULL;
1536 }
1537
1538 int
1539 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1540 {
1541         struct ice_rx_queue *rxq = rx_queue;
1542         volatile uint64_t *status;
1543         uint64_t mask;
1544         uint32_t desc;
1545
1546         if (unlikely(offset >= rxq->nb_rx_desc))
1547                 return -EINVAL;
1548
1549         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1550                 return RTE_ETH_RX_DESC_UNAVAIL;
1551
1552         desc = rxq->rx_tail + offset;
1553         if (desc >= rxq->nb_rx_desc)
1554                 desc -= rxq->nb_rx_desc;
1555
1556         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1557         mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) <<
1558                                 ICE_RXD_QW1_STATUS_S);
1559         if (*status & mask)
1560                 return RTE_ETH_RX_DESC_DONE;
1561
1562         return RTE_ETH_RX_DESC_AVAIL;
1563 }
1564
1565 int
1566 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1567 {
1568         struct ice_tx_queue *txq = tx_queue;
1569         volatile uint64_t *status;
1570         uint64_t mask, expect;
1571         uint32_t desc;
1572
1573         if (unlikely(offset >= txq->nb_tx_desc))
1574                 return -EINVAL;
1575
1576         desc = txq->tx_tail + offset;
1577         /* go to next desc that has the RS bit */
1578         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1579                 txq->tx_rs_thresh;
1580         if (desc >= txq->nb_tx_desc) {
1581                 desc -= txq->nb_tx_desc;
1582                 if (desc >= txq->nb_tx_desc)
1583                         desc -= txq->nb_tx_desc;
1584         }
1585
1586         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1587         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1588         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1589                                   ICE_TXD_QW1_DTYPE_S);
1590         if ((*status & mask) == expect)
1591                 return RTE_ETH_TX_DESC_DONE;
1592
1593         return RTE_ETH_TX_DESC_FULL;
1594 }
1595
1596 void
1597 ice_clear_queues(struct rte_eth_dev *dev)
1598 {
1599         uint16_t i;
1600
1601         PMD_INIT_FUNC_TRACE();
1602
1603         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1604                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1605                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1606         }
1607
1608         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1609                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1610                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1611         }
1612 }
1613
1614 void
1615 ice_free_queues(struct rte_eth_dev *dev)
1616 {
1617         uint16_t i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1622                 if (!dev->data->rx_queues[i])
1623                         continue;
1624                 ice_rx_queue_release(dev->data->rx_queues[i]);
1625                 dev->data->rx_queues[i] = NULL;
1626         }
1627         dev->data->nb_rx_queues = 0;
1628
1629         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1630                 if (!dev->data->tx_queues[i])
1631                         continue;
1632                 ice_tx_queue_release(dev->data->tx_queues[i]);
1633                 dev->data->tx_queues[i] = NULL;
1634         }
1635         dev->data->nb_tx_queues = 0;
1636 }
1637
1638 uint16_t
1639 ice_recv_pkts(void *rx_queue,
1640               struct rte_mbuf **rx_pkts,
1641               uint16_t nb_pkts)
1642 {
1643         struct ice_rx_queue *rxq = rx_queue;
1644         volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1645         volatile union ice_rx_desc *rxdp;
1646         union ice_rx_desc rxd;
1647         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1648         struct ice_rx_entry *rxe;
1649         struct rte_mbuf *nmb; /* new allocated mbuf */
1650         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1651         uint16_t rx_id = rxq->rx_tail;
1652         uint16_t nb_rx = 0;
1653         uint16_t nb_hold = 0;
1654         uint16_t rx_packet_len;
1655         uint32_t rx_status;
1656         uint64_t qword1;
1657         uint64_t dma_addr;
1658         uint64_t pkt_flags = 0;
1659         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1660         struct rte_eth_dev *dev;
1661
1662         while (nb_rx < nb_pkts) {
1663                 rxdp = &rx_ring[rx_id];
1664                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1665                 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1666                             ICE_RXD_QW1_STATUS_S;
1667
1668                 /* Check the DD bit first */
1669                 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1670                         break;
1671
1672                 /* allocate mbuf */
1673                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1674                 if (unlikely(!nmb)) {
1675                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1676                         dev->data->rx_mbuf_alloc_failed++;
1677                         break;
1678                 }
1679                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1680
1681                 nb_hold++;
1682                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1683                 rx_id++;
1684                 if (unlikely(rx_id == rxq->nb_rx_desc))
1685                         rx_id = 0;
1686                 rxm = rxe->mbuf;
1687                 rxe->mbuf = nmb;
1688                 dma_addr =
1689                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1690
1691                 /**
1692                  * fill the read format of descriptor with physic address in
1693                  * new allocated mbuf: nmb
1694                  */
1695                 rxdp->read.hdr_addr = 0;
1696                 rxdp->read.pkt_addr = dma_addr;
1697
1698                 /* calculate rx_packet_len of the received pkt */
1699                 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1700                                 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1701
1702                 /* fill old mbuf with received descriptor: rxd */
1703                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1704                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1705                 rxm->nb_segs = 1;
1706                 rxm->next = NULL;
1707                 rxm->pkt_len = rx_packet_len;
1708                 rxm->data_len = rx_packet_len;
1709                 rxm->port = rxq->port_id;
1710                 ice_rxd_to_vlan_tci(rxm, rxdp);
1711                 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1712                                                         ICE_RXD_QW1_PTYPE_M) >>
1713                                                        ICE_RXD_QW1_PTYPE_S)];
1714                 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1715                 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1716                 if (pkt_flags & PKT_RX_RSS_HASH)
1717                         rxm->hash.rss =
1718                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1719                 rxm->ol_flags |= pkt_flags;
1720                 /* copy old mbuf to rx_pkts */
1721                 rx_pkts[nb_rx++] = rxm;
1722         }
1723         rxq->rx_tail = rx_id;
1724         /**
1725          * If the number of free RX descriptors is greater than the RX free
1726          * threshold of the queue, advance the receive tail register of queue.
1727          * Update that register with the value of the last processed RX
1728          * descriptor minus 1.
1729          */
1730         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1731         if (nb_hold > rxq->rx_free_thresh) {
1732                 rx_id = (uint16_t)(rx_id == 0 ?
1733                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1734                 /* write TAIL register */
1735                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1736                 nb_hold = 0;
1737         }
1738         rxq->nb_rx_hold = nb_hold;
1739
1740         /* return received packet in the burst */
1741         return nb_rx;
1742 }
1743
1744 static inline void
1745 ice_parse_tunneling_params(uint64_t ol_flags,
1746                             union ice_tx_offload tx_offload,
1747                             uint32_t *cd_tunneling)
1748 {
1749         /* EIPT: External (outer) IP header type */
1750         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1751                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
1752         else if (ol_flags & PKT_TX_OUTER_IPV4)
1753                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
1754         else if (ol_flags & PKT_TX_OUTER_IPV6)
1755                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
1756
1757         /* EIPLEN: External (outer) IP header length, in DWords */
1758         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
1759                 ICE_TXD_CTX_QW0_EIPLEN_S;
1760
1761         /* L4TUNT: L4 Tunneling Type */
1762         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
1763         case PKT_TX_TUNNEL_IPIP:
1764                 /* for non UDP / GRE tunneling, set to 00b */
1765                 break;
1766         case PKT_TX_TUNNEL_VXLAN:
1767         case PKT_TX_TUNNEL_GENEVE:
1768                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
1769                 break;
1770         case PKT_TX_TUNNEL_GRE:
1771                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
1772                 break;
1773         default:
1774                 PMD_TX_LOG(ERR, "Tunnel type not supported");
1775                 return;
1776         }
1777
1778         /* L4TUNLEN: L4 Tunneling Length, in Words
1779          *
1780          * We depend on app to set rte_mbuf.l2_len correctly.
1781          * For IP in GRE it should be set to the length of the GRE
1782          * header;
1783          * For MAC in GRE or MAC in UDP it should be set to the length
1784          * of the GRE or UDP headers plus the inner MAC up to including
1785          * its last Ethertype.
1786          * If MPLS labels exists, it should include them as well.
1787          */
1788         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
1789                 ICE_TXD_CTX_QW0_NATLEN_S;
1790
1791         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
1792             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
1793             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
1794                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
1795 }
1796
1797 static inline void
1798 ice_txd_enable_checksum(uint64_t ol_flags,
1799                         uint32_t *td_cmd,
1800                         uint32_t *td_offset,
1801                         union ice_tx_offload tx_offload)
1802 {
1803         /* Set MACLEN */
1804         if (ol_flags & PKT_TX_TUNNEL_MASK)
1805                 *td_offset |= (tx_offload.outer_l2_len >> 1)
1806                         << ICE_TX_DESC_LEN_MACLEN_S;
1807         else
1808                 *td_offset |= (tx_offload.l2_len >> 1)
1809                         << ICE_TX_DESC_LEN_MACLEN_S;
1810
1811         /* Enable L3 checksum offloads */
1812         if (ol_flags & PKT_TX_IP_CKSUM) {
1813                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1814                 *td_offset |= (tx_offload.l3_len >> 2) <<
1815                               ICE_TX_DESC_LEN_IPLEN_S;
1816         } else if (ol_flags & PKT_TX_IPV4) {
1817                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1818                 *td_offset |= (tx_offload.l3_len >> 2) <<
1819                               ICE_TX_DESC_LEN_IPLEN_S;
1820         } else if (ol_flags & PKT_TX_IPV6) {
1821                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1822                 *td_offset |= (tx_offload.l3_len >> 2) <<
1823                               ICE_TX_DESC_LEN_IPLEN_S;
1824         }
1825
1826         if (ol_flags & PKT_TX_TCP_SEG) {
1827                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1828                 *td_offset |= (tx_offload.l4_len >> 2) <<
1829                               ICE_TX_DESC_LEN_L4_LEN_S;
1830                 return;
1831         }
1832
1833         /* Enable L4 checksum offloads */
1834         switch (ol_flags & PKT_TX_L4_MASK) {
1835         case PKT_TX_TCP_CKSUM:
1836                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1837                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1838                               ICE_TX_DESC_LEN_L4_LEN_S;
1839                 break;
1840         case PKT_TX_SCTP_CKSUM:
1841                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1842                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1843                               ICE_TX_DESC_LEN_L4_LEN_S;
1844                 break;
1845         case PKT_TX_UDP_CKSUM:
1846                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1847                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1848                               ICE_TX_DESC_LEN_L4_LEN_S;
1849                 break;
1850         default:
1851                 break;
1852         }
1853 }
1854
1855 static inline int
1856 ice_xmit_cleanup(struct ice_tx_queue *txq)
1857 {
1858         struct ice_tx_entry *sw_ring = txq->sw_ring;
1859         volatile struct ice_tx_desc *txd = txq->tx_ring;
1860         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1861         uint16_t nb_tx_desc = txq->nb_tx_desc;
1862         uint16_t desc_to_clean_to;
1863         uint16_t nb_tx_to_clean;
1864
1865         /* Determine the last descriptor needing to be cleaned */
1866         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1867         if (desc_to_clean_to >= nb_tx_desc)
1868                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1869
1870         /* Check to make sure the last descriptor to clean is done */
1871         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1872         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1873             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1874                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1875                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1876                                 desc_to_clean_to,
1877                                 txq->port_id, txq->queue_id,
1878                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1879                 /* Failed to clean any descriptors */
1880                 return -1;
1881         }
1882
1883         /* Figure out how many descriptors will be cleaned */
1884         if (last_desc_cleaned > desc_to_clean_to)
1885                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1886                                             desc_to_clean_to);
1887         else
1888                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1889                                             last_desc_cleaned);
1890
1891         /* The last descriptor to clean is done, so that means all the
1892          * descriptors from the last descriptor that was cleaned
1893          * up to the last descriptor with the RS bit set
1894          * are done. Only reset the threshold descriptor.
1895          */
1896         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1897
1898         /* Update the txq to reflect the last descriptor that was cleaned */
1899         txq->last_desc_cleaned = desc_to_clean_to;
1900         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1901
1902         return 0;
1903 }
1904
1905 /* Construct the tx flags */
1906 static inline uint64_t
1907 ice_build_ctob(uint32_t td_cmd,
1908                uint32_t td_offset,
1909                uint16_t size,
1910                uint32_t td_tag)
1911 {
1912         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1913                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1914                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1915                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1916                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1917 }
1918
1919 /* Check if the context descriptor is needed for TX offloading */
1920 static inline uint16_t
1921 ice_calc_context_desc(uint64_t flags)
1922 {
1923         static uint64_t mask = PKT_TX_TCP_SEG |
1924                 PKT_TX_QINQ |
1925                 PKT_TX_OUTER_IP_CKSUM |
1926                 PKT_TX_TUNNEL_MASK;
1927
1928         return (flags & mask) ? 1 : 0;
1929 }
1930
1931 /* set ice TSO context descriptor */
1932 static inline uint64_t
1933 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1934 {
1935         uint64_t ctx_desc = 0;
1936         uint32_t cd_cmd, hdr_len, cd_tso_len;
1937
1938         if (!tx_offload.l4_len) {
1939                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1940                 return ctx_desc;
1941         }
1942
1943         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1944         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1945                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1946
1947         cd_cmd = ICE_TX_CTX_DESC_TSO;
1948         cd_tso_len = mbuf->pkt_len - hdr_len;
1949         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1950                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1951                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1952
1953         return ctx_desc;
1954 }
1955
1956 uint16_t
1957 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1958 {
1959         struct ice_tx_queue *txq;
1960         volatile struct ice_tx_desc *tx_ring;
1961         volatile struct ice_tx_desc *txd;
1962         struct ice_tx_entry *sw_ring;
1963         struct ice_tx_entry *txe, *txn;
1964         struct rte_mbuf *tx_pkt;
1965         struct rte_mbuf *m_seg;
1966         uint32_t cd_tunneling_params;
1967         uint16_t tx_id;
1968         uint16_t nb_tx;
1969         uint16_t nb_used;
1970         uint16_t nb_ctx;
1971         uint32_t td_cmd = 0;
1972         uint32_t td_offset = 0;
1973         uint32_t td_tag = 0;
1974         uint16_t tx_last;
1975         uint64_t buf_dma_addr;
1976         uint64_t ol_flags;
1977         union ice_tx_offload tx_offload = {0};
1978
1979         txq = tx_queue;
1980         sw_ring = txq->sw_ring;
1981         tx_ring = txq->tx_ring;
1982         tx_id = txq->tx_tail;
1983         txe = &sw_ring[tx_id];
1984
1985         /* Check if the descriptor ring needs to be cleaned. */
1986         if (txq->nb_tx_free < txq->tx_free_thresh)
1987                 ice_xmit_cleanup(txq);
1988
1989         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1990                 tx_pkt = *tx_pkts++;
1991
1992                 td_cmd = 0;
1993                 ol_flags = tx_pkt->ol_flags;
1994                 tx_offload.l2_len = tx_pkt->l2_len;
1995                 tx_offload.l3_len = tx_pkt->l3_len;
1996                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1997                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1998                 tx_offload.l4_len = tx_pkt->l4_len;
1999                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2000                 /* Calculate the number of context descriptors needed. */
2001                 nb_ctx = ice_calc_context_desc(ol_flags);
2002
2003                 /* The number of descriptors that must be allocated for
2004                  * a packet equals to the number of the segments of that
2005                  * packet plus the number of context descriptor if needed.
2006                  */
2007                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2008                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2009
2010                 /* Circular ring */
2011                 if (tx_last >= txq->nb_tx_desc)
2012                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2013
2014                 if (nb_used > txq->nb_tx_free) {
2015                         if (ice_xmit_cleanup(txq) != 0) {
2016                                 if (nb_tx == 0)
2017                                         return 0;
2018                                 goto end_of_tx;
2019                         }
2020                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2021                                 while (nb_used > txq->nb_tx_free) {
2022                                         if (ice_xmit_cleanup(txq) != 0) {
2023                                                 if (nb_tx == 0)
2024                                                         return 0;
2025                                                 goto end_of_tx;
2026                                         }
2027                                 }
2028                         }
2029                 }
2030
2031                 /* Descriptor based VLAN insertion */
2032                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2033                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2034                         td_tag = tx_pkt->vlan_tci;
2035                 }
2036
2037                 /* Fill in tunneling parameters if necessary */
2038                 cd_tunneling_params = 0;
2039                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2040                         ice_parse_tunneling_params(ol_flags, tx_offload,
2041                                                    &cd_tunneling_params);
2042
2043                 /* Enable checksum offloading */
2044                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2045                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2046                                                 &td_offset, tx_offload);
2047                 }
2048
2049                 if (nb_ctx) {
2050                         /* Setup TX context descriptor if required */
2051                         volatile struct ice_tx_ctx_desc *ctx_txd =
2052                                 (volatile struct ice_tx_ctx_desc *)
2053                                         &tx_ring[tx_id];
2054                         uint16_t cd_l2tag2 = 0;
2055                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2056
2057                         txn = &sw_ring[txe->next_id];
2058                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2059                         if (txe->mbuf) {
2060                                 rte_pktmbuf_free_seg(txe->mbuf);
2061                                 txe->mbuf = NULL;
2062                         }
2063
2064                         if (ol_flags & PKT_TX_TCP_SEG)
2065                                 cd_type_cmd_tso_mss |=
2066                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2067
2068                         ctx_txd->tunneling_params =
2069                                 rte_cpu_to_le_32(cd_tunneling_params);
2070
2071                         /* TX context descriptor based double VLAN insert */
2072                         if (ol_flags & PKT_TX_QINQ) {
2073                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2074                                 cd_type_cmd_tso_mss |=
2075                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2076                                          ICE_TXD_CTX_QW1_CMD_S);
2077                         }
2078                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2079                         ctx_txd->qw1 =
2080                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2081
2082                         txe->last_id = tx_last;
2083                         tx_id = txe->next_id;
2084                         txe = txn;
2085                 }
2086                 m_seg = tx_pkt;
2087
2088                 do {
2089                         txd = &tx_ring[tx_id];
2090                         txn = &sw_ring[txe->next_id];
2091
2092                         if (txe->mbuf)
2093                                 rte_pktmbuf_free_seg(txe->mbuf);
2094                         txe->mbuf = m_seg;
2095
2096                         /* Setup TX Descriptor */
2097                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2098                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2099                         txd->cmd_type_offset_bsz =
2100                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2101                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2102                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2103                                 ((uint64_t)m_seg->data_len  <<
2104                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2105                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2106
2107                         txe->last_id = tx_last;
2108                         tx_id = txe->next_id;
2109                         txe = txn;
2110                         m_seg = m_seg->next;
2111                 } while (m_seg);
2112
2113                 /* fill the last descriptor with End of Packet (EOP) bit */
2114                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2115                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2116                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2117
2118                 /* set RS bit on the last descriptor of one packet */
2119                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2120                         PMD_TX_FREE_LOG(DEBUG,
2121                                         "Setting RS bit on TXD id="
2122                                         "%4u (port=%d queue=%d)",
2123                                         tx_last, txq->port_id, txq->queue_id);
2124
2125                         td_cmd |= ICE_TX_DESC_CMD_RS;
2126
2127                         /* Update txq RS bit counters */
2128                         txq->nb_tx_used = 0;
2129                 }
2130                 txd->cmd_type_offset_bsz |=
2131                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2132                                          ICE_TXD_QW1_CMD_S);
2133         }
2134 end_of_tx:
2135         rte_wmb();
2136
2137         /* update Tail register */
2138         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2139         txq->tx_tail = tx_id;
2140
2141         return nb_tx;
2142 }
2143
2144 static inline int __attribute__((always_inline))
2145 ice_tx_free_bufs(struct ice_tx_queue *txq)
2146 {
2147         struct ice_tx_entry *txep;
2148         uint16_t i;
2149
2150         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2151              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2152             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2153                 return 0;
2154
2155         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2156
2157         for (i = 0; i < txq->tx_rs_thresh; i++)
2158                 rte_prefetch0((txep + i)->mbuf);
2159
2160         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2161                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2162                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2163                         txep->mbuf = NULL;
2164                 }
2165         } else {
2166                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2167                         rte_pktmbuf_free_seg(txep->mbuf);
2168                         txep->mbuf = NULL;
2169                 }
2170         }
2171
2172         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2173         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2174         if (txq->tx_next_dd >= txq->nb_tx_desc)
2175                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2176
2177         return txq->tx_rs_thresh;
2178 }
2179
2180 /* Populate 4 descriptors with data from 4 mbufs */
2181 static inline void
2182 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2183 {
2184         uint64_t dma_addr;
2185         uint32_t i;
2186
2187         for (i = 0; i < 4; i++, txdp++, pkts++) {
2188                 dma_addr = rte_mbuf_data_iova(*pkts);
2189                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2190                 txdp->cmd_type_offset_bsz =
2191                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2192                                        (*pkts)->data_len, 0);
2193         }
2194 }
2195
2196 /* Populate 1 descriptor with data from 1 mbuf */
2197 static inline void
2198 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2199 {
2200         uint64_t dma_addr;
2201
2202         dma_addr = rte_mbuf_data_iova(*pkts);
2203         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2204         txdp->cmd_type_offset_bsz =
2205                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2206                                (*pkts)->data_len, 0);
2207 }
2208
2209 static inline void
2210 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2211                     uint16_t nb_pkts)
2212 {
2213         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2214         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2215         const int N_PER_LOOP = 4;
2216         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2217         int mainpart, leftover;
2218         int i, j;
2219
2220         /**
2221          * Process most of the packets in chunks of N pkts.  Any
2222          * leftover packets will get processed one at a time.
2223          */
2224         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2225         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2226         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2227                 /* Copy N mbuf pointers to the S/W ring */
2228                 for (j = 0; j < N_PER_LOOP; ++j)
2229                         (txep + i + j)->mbuf = *(pkts + i + j);
2230                 tx4(txdp + i, pkts + i);
2231         }
2232
2233         if (unlikely(leftover > 0)) {
2234                 for (i = 0; i < leftover; ++i) {
2235                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2236                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2237                 }
2238         }
2239 }
2240
2241 static inline uint16_t
2242 tx_xmit_pkts(struct ice_tx_queue *txq,
2243              struct rte_mbuf **tx_pkts,
2244              uint16_t nb_pkts)
2245 {
2246         volatile struct ice_tx_desc *txr = txq->tx_ring;
2247         uint16_t n = 0;
2248
2249         /**
2250          * Begin scanning the H/W ring for done descriptors when the number
2251          * of available descriptors drops below tx_free_thresh. For each done
2252          * descriptor, free the associated buffer.
2253          */
2254         if (txq->nb_tx_free < txq->tx_free_thresh)
2255                 ice_tx_free_bufs(txq);
2256
2257         /* Use available descriptor only */
2258         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2259         if (unlikely(!nb_pkts))
2260                 return 0;
2261
2262         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2263         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2264                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2265                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2266                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2267                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2268                                          ICE_TXD_QW1_CMD_S);
2269                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2270                 txq->tx_tail = 0;
2271         }
2272
2273         /* Fill hardware descriptor ring with mbuf data */
2274         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2275         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2276
2277         /* Determin if RS bit needs to be set */
2278         if (txq->tx_tail > txq->tx_next_rs) {
2279                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2280                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2281                                          ICE_TXD_QW1_CMD_S);
2282                 txq->tx_next_rs =
2283                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2284                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2285                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2286         }
2287
2288         if (txq->tx_tail >= txq->nb_tx_desc)
2289                 txq->tx_tail = 0;
2290
2291         /* Update the tx tail register */
2292         rte_wmb();
2293         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2294
2295         return nb_pkts;
2296 }
2297
2298 static uint16_t
2299 ice_xmit_pkts_simple(void *tx_queue,
2300                      struct rte_mbuf **tx_pkts,
2301                      uint16_t nb_pkts)
2302 {
2303         uint16_t nb_tx = 0;
2304
2305         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2306                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2307                                     tx_pkts, nb_pkts);
2308
2309         while (nb_pkts) {
2310                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2311                                                       ICE_TX_MAX_BURST);
2312
2313                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2314                                    &tx_pkts[nb_tx], num);
2315                 nb_tx = (uint16_t)(nb_tx + ret);
2316                 nb_pkts = (uint16_t)(nb_pkts - ret);
2317                 if (ret < num)
2318                         break;
2319         }
2320
2321         return nb_tx;
2322 }
2323
2324 void __attribute__((cold))
2325 ice_set_rx_function(struct rte_eth_dev *dev)
2326 {
2327         PMD_INIT_FUNC_TRACE();
2328         struct ice_adapter *ad =
2329                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2330 #ifdef RTE_ARCH_X86
2331         struct ice_rx_queue *rxq;
2332         int i;
2333         bool use_avx2 = false;
2334
2335         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2336                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2337                         ad->rx_vec_allowed = true;
2338                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2339                                 rxq = dev->data->rx_queues[i];
2340                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2341                                         ad->rx_vec_allowed = false;
2342                                         break;
2343                                 }
2344                         }
2345
2346                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2347                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2348                                 use_avx2 = true;
2349
2350                 } else {
2351                         ad->rx_vec_allowed = false;
2352                 }
2353         }
2354
2355         if (ad->rx_vec_allowed) {
2356                 if (dev->data->scattered_rx) {
2357                         PMD_DRV_LOG(DEBUG,
2358                                         "Using %sVector Scattered Rx (port %d).",
2359                                         use_avx2 ? "avx2 " : "",
2360                                         dev->data->port_id);
2361                         dev->rx_pkt_burst = use_avx2 ?
2362                                         ice_recv_scattered_pkts_vec_avx2 :
2363                                         ice_recv_scattered_pkts_vec;
2364                 } else {
2365                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2366                                         use_avx2 ? "avx2 " : "",
2367                                         dev->data->port_id);
2368                         dev->rx_pkt_burst = use_avx2 ?
2369                                                 ice_recv_pkts_vec_avx2 :
2370                                                 ice_recv_pkts_vec;
2371                 }
2372                 return;
2373         }
2374
2375 #endif
2376
2377         if (dev->data->scattered_rx) {
2378                 /* Set the non-LRO scattered function */
2379                 PMD_INIT_LOG(DEBUG,
2380                              "Using a Scattered function on port %d.",
2381                              dev->data->port_id);
2382                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2383         } else if (ad->rx_bulk_alloc_allowed) {
2384                 PMD_INIT_LOG(DEBUG,
2385                              "Rx Burst Bulk Alloc Preconditions are "
2386                              "satisfied. Rx Burst Bulk Alloc function "
2387                              "will be used on port %d.",
2388                              dev->data->port_id);
2389                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2390         } else {
2391                 PMD_INIT_LOG(DEBUG,
2392                              "Rx Burst Bulk Alloc Preconditions are not "
2393                              "satisfied, Normal Rx will be used on port %d.",
2394                              dev->data->port_id);
2395                 dev->rx_pkt_burst = ice_recv_pkts;
2396         }
2397 }
2398
2399 void __attribute__((cold))
2400 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2401 {
2402         struct ice_adapter *ad =
2403                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2404
2405         /* Use a simple Tx queue if possible (only fast free is allowed) */
2406         ad->tx_simple_allowed =
2407                 (txq->offloads ==
2408                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2409                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2410
2411         if (ad->tx_simple_allowed)
2412                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2413                              txq->queue_id);
2414         else
2415                 PMD_INIT_LOG(DEBUG,
2416                              "Simple Tx can NOT be enabled on Tx queue %u.",
2417                              txq->queue_id);
2418 }
2419
2420 /*********************************************************************
2421  *
2422  *  TX prep functions
2423  *
2424  **********************************************************************/
2425 /* The default values of TSO MSS */
2426 #define ICE_MIN_TSO_MSS            64
2427 #define ICE_MAX_TSO_MSS            9728
2428 #define ICE_MAX_TSO_FRAME_SIZE     262144
2429 uint16_t
2430 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2431               uint16_t nb_pkts)
2432 {
2433         int i, ret;
2434         uint64_t ol_flags;
2435         struct rte_mbuf *m;
2436
2437         for (i = 0; i < nb_pkts; i++) {
2438                 m = tx_pkts[i];
2439                 ol_flags = m->ol_flags;
2440
2441                 if (ol_flags & PKT_TX_TCP_SEG &&
2442                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2443                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2444                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2445                         /**
2446                          * MSS outside the range are considered malicious
2447                          */
2448                         rte_errno = EINVAL;
2449                         return i;
2450                 }
2451
2452 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2453                 ret = rte_validate_tx_offload(m);
2454                 if (ret != 0) {
2455                         rte_errno = -ret;
2456                         return i;
2457                 }
2458 #endif
2459                 ret = rte_net_intel_cksum_prepare(m);
2460                 if (ret != 0) {
2461                         rte_errno = -ret;
2462                         return i;
2463                 }
2464         }
2465         return i;
2466 }
2467
2468 void __attribute__((cold))
2469 ice_set_tx_function(struct rte_eth_dev *dev)
2470 {
2471         struct ice_adapter *ad =
2472                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2473 #ifdef RTE_ARCH_X86
2474         struct ice_tx_queue *txq;
2475         int i;
2476         bool use_avx2 = false;
2477
2478         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2479                 if (!ice_tx_vec_dev_check(dev)) {
2480                         ad->tx_vec_allowed = true;
2481                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2482                                 txq = dev->data->tx_queues[i];
2483                                 if (txq && ice_txq_vec_setup(txq)) {
2484                                         ad->tx_vec_allowed = false;
2485                                         break;
2486                                 }
2487                         }
2488
2489                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2490                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2491                                 use_avx2 = true;
2492
2493                 } else {
2494                         ad->tx_vec_allowed = false;
2495                 }
2496         }
2497
2498         if (ad->tx_vec_allowed) {
2499                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2500                             use_avx2 ? "avx2 " : "",
2501                             dev->data->port_id);
2502                 dev->tx_pkt_burst = use_avx2 ?
2503                                     ice_xmit_pkts_vec_avx2 :
2504                                     ice_xmit_pkts_vec;
2505                 dev->tx_pkt_prepare = NULL;
2506
2507                 return;
2508         }
2509 #endif
2510
2511         if (ad->tx_simple_allowed) {
2512                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2513                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2514                 dev->tx_pkt_prepare = NULL;
2515         } else {
2516                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2517                 dev->tx_pkt_burst = ice_xmit_pkts;
2518                 dev->tx_pkt_prepare = ice_prep_pkts;
2519         }
2520 }
2521
2522 /* For each value it means, datasheet of hardware can tell more details
2523  *
2524  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2525  */
2526 static inline uint32_t
2527 ice_get_default_pkt_type(uint16_t ptype)
2528 {
2529         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2530                 __rte_cache_aligned = {
2531                 /* L2 types */
2532                 /* [0] reserved */
2533                 [1] = RTE_PTYPE_L2_ETHER,
2534                 /* [2] - [5] reserved */
2535                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2536                 /* [7] - [10] reserved */
2537                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2538                 /* [12] - [21] reserved */
2539
2540                 /* Non tunneled IPv4 */
2541                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2542                        RTE_PTYPE_L4_FRAG,
2543                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2544                        RTE_PTYPE_L4_NONFRAG,
2545                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2546                        RTE_PTYPE_L4_UDP,
2547                 /* [25] reserved */
2548                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2549                        RTE_PTYPE_L4_TCP,
2550                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2551                        RTE_PTYPE_L4_SCTP,
2552                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2553                        RTE_PTYPE_L4_ICMP,
2554
2555                 /* IPv4 --> IPv4 */
2556                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2557                        RTE_PTYPE_TUNNEL_IP |
2558                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2559                        RTE_PTYPE_INNER_L4_FRAG,
2560                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2561                        RTE_PTYPE_TUNNEL_IP |
2562                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2563                        RTE_PTYPE_INNER_L4_NONFRAG,
2564                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2565                        RTE_PTYPE_TUNNEL_IP |
2566                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2567                        RTE_PTYPE_INNER_L4_UDP,
2568                 /* [32] reserved */
2569                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2570                        RTE_PTYPE_TUNNEL_IP |
2571                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2572                        RTE_PTYPE_INNER_L4_TCP,
2573                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2574                        RTE_PTYPE_TUNNEL_IP |
2575                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2576                        RTE_PTYPE_INNER_L4_SCTP,
2577                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2578                        RTE_PTYPE_TUNNEL_IP |
2579                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2580                        RTE_PTYPE_INNER_L4_ICMP,
2581
2582                 /* IPv4 --> IPv6 */
2583                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2584                        RTE_PTYPE_TUNNEL_IP |
2585                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2586                        RTE_PTYPE_INNER_L4_FRAG,
2587                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2588                        RTE_PTYPE_TUNNEL_IP |
2589                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2590                        RTE_PTYPE_INNER_L4_NONFRAG,
2591                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2592                        RTE_PTYPE_TUNNEL_IP |
2593                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2594                        RTE_PTYPE_INNER_L4_UDP,
2595                 /* [39] reserved */
2596                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2597                        RTE_PTYPE_TUNNEL_IP |
2598                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2599                        RTE_PTYPE_INNER_L4_TCP,
2600                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2601                        RTE_PTYPE_TUNNEL_IP |
2602                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2603                        RTE_PTYPE_INNER_L4_SCTP,
2604                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2605                        RTE_PTYPE_TUNNEL_IP |
2606                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2607                        RTE_PTYPE_INNER_L4_ICMP,
2608
2609                 /* IPv4 --> GRE/Teredo/VXLAN */
2610                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2611                        RTE_PTYPE_TUNNEL_GRENAT,
2612
2613                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2614                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2615                        RTE_PTYPE_TUNNEL_GRENAT |
2616                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2617                        RTE_PTYPE_INNER_L4_FRAG,
2618                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2619                        RTE_PTYPE_TUNNEL_GRENAT |
2620                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2621                        RTE_PTYPE_INNER_L4_NONFRAG,
2622                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2623                        RTE_PTYPE_TUNNEL_GRENAT |
2624                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2625                        RTE_PTYPE_INNER_L4_UDP,
2626                 /* [47] reserved */
2627                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2628                        RTE_PTYPE_TUNNEL_GRENAT |
2629                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2630                        RTE_PTYPE_INNER_L4_TCP,
2631                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2632                        RTE_PTYPE_TUNNEL_GRENAT |
2633                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2634                        RTE_PTYPE_INNER_L4_SCTP,
2635                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2636                        RTE_PTYPE_TUNNEL_GRENAT |
2637                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2638                        RTE_PTYPE_INNER_L4_ICMP,
2639
2640                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2641                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2642                        RTE_PTYPE_TUNNEL_GRENAT |
2643                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2644                        RTE_PTYPE_INNER_L4_FRAG,
2645                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2646                        RTE_PTYPE_TUNNEL_GRENAT |
2647                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2648                        RTE_PTYPE_INNER_L4_NONFRAG,
2649                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2650                        RTE_PTYPE_TUNNEL_GRENAT |
2651                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2652                        RTE_PTYPE_INNER_L4_UDP,
2653                 /* [54] reserved */
2654                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2655                        RTE_PTYPE_TUNNEL_GRENAT |
2656                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2657                        RTE_PTYPE_INNER_L4_TCP,
2658                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2659                        RTE_PTYPE_TUNNEL_GRENAT |
2660                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2661                        RTE_PTYPE_INNER_L4_SCTP,
2662                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2663                        RTE_PTYPE_TUNNEL_GRENAT |
2664                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2665                        RTE_PTYPE_INNER_L4_ICMP,
2666
2667                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2668                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2669                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2670
2671                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2672                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2673                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2674                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2675                        RTE_PTYPE_INNER_L4_FRAG,
2676                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2677                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2678                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2679                        RTE_PTYPE_INNER_L4_NONFRAG,
2680                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2681                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2682                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2683                        RTE_PTYPE_INNER_L4_UDP,
2684                 /* [62] reserved */
2685                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2686                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2687                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2688                        RTE_PTYPE_INNER_L4_TCP,
2689                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2690                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2691                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2692                        RTE_PTYPE_INNER_L4_SCTP,
2693                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2694                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2695                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2696                        RTE_PTYPE_INNER_L4_ICMP,
2697
2698                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2699                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2700                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2701                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2702                        RTE_PTYPE_INNER_L4_FRAG,
2703                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2704                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2705                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2706                        RTE_PTYPE_INNER_L4_NONFRAG,
2707                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2708                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2709                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2710                        RTE_PTYPE_INNER_L4_UDP,
2711                 /* [69] reserved */
2712                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2713                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2714                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2715                        RTE_PTYPE_INNER_L4_TCP,
2716                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2717                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2718                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2719                        RTE_PTYPE_INNER_L4_SCTP,
2720                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2721                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2722                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2723                        RTE_PTYPE_INNER_L4_ICMP,
2724
2725                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2726                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2727                        RTE_PTYPE_TUNNEL_GRENAT |
2728                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2729
2730                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2731                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2732                        RTE_PTYPE_TUNNEL_GRENAT |
2733                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2734                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2735                        RTE_PTYPE_INNER_L4_FRAG,
2736                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2737                        RTE_PTYPE_TUNNEL_GRENAT |
2738                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2739                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2740                        RTE_PTYPE_INNER_L4_NONFRAG,
2741                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2742                        RTE_PTYPE_TUNNEL_GRENAT |
2743                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2744                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2745                        RTE_PTYPE_INNER_L4_UDP,
2746                 /* [77] reserved */
2747                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2748                        RTE_PTYPE_TUNNEL_GRENAT |
2749                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2750                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2751                        RTE_PTYPE_INNER_L4_TCP,
2752                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2753                        RTE_PTYPE_TUNNEL_GRENAT |
2754                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2755                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2756                        RTE_PTYPE_INNER_L4_SCTP,
2757                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2758                        RTE_PTYPE_TUNNEL_GRENAT |
2759                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2760                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2761                        RTE_PTYPE_INNER_L4_ICMP,
2762
2763                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2764                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2765                        RTE_PTYPE_TUNNEL_GRENAT |
2766                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2767                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2768                        RTE_PTYPE_INNER_L4_FRAG,
2769                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2770                        RTE_PTYPE_TUNNEL_GRENAT |
2771                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2772                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2773                        RTE_PTYPE_INNER_L4_NONFRAG,
2774                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2775                        RTE_PTYPE_TUNNEL_GRENAT |
2776                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2777                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2778                        RTE_PTYPE_INNER_L4_UDP,
2779                 /* [84] reserved */
2780                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2781                        RTE_PTYPE_TUNNEL_GRENAT |
2782                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2783                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2784                        RTE_PTYPE_INNER_L4_TCP,
2785                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2786                        RTE_PTYPE_TUNNEL_GRENAT |
2787                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2788                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2789                        RTE_PTYPE_INNER_L4_SCTP,
2790                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2791                        RTE_PTYPE_TUNNEL_GRENAT |
2792                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2793                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2794                        RTE_PTYPE_INNER_L4_ICMP,
2795
2796                 /* Non tunneled IPv6 */
2797                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2798                        RTE_PTYPE_L4_FRAG,
2799                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2800                        RTE_PTYPE_L4_NONFRAG,
2801                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2802                        RTE_PTYPE_L4_UDP,
2803                 /* [91] reserved */
2804                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2805                        RTE_PTYPE_L4_TCP,
2806                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2807                        RTE_PTYPE_L4_SCTP,
2808                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2809                        RTE_PTYPE_L4_ICMP,
2810
2811                 /* IPv6 --> IPv4 */
2812                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2813                        RTE_PTYPE_TUNNEL_IP |
2814                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2815                        RTE_PTYPE_INNER_L4_FRAG,
2816                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2817                        RTE_PTYPE_TUNNEL_IP |
2818                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2819                        RTE_PTYPE_INNER_L4_NONFRAG,
2820                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2821                        RTE_PTYPE_TUNNEL_IP |
2822                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2823                        RTE_PTYPE_INNER_L4_UDP,
2824                 /* [98] reserved */
2825                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2826                        RTE_PTYPE_TUNNEL_IP |
2827                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2828                        RTE_PTYPE_INNER_L4_TCP,
2829                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2830                         RTE_PTYPE_TUNNEL_IP |
2831                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2832                         RTE_PTYPE_INNER_L4_SCTP,
2833                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2834                         RTE_PTYPE_TUNNEL_IP |
2835                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2836                         RTE_PTYPE_INNER_L4_ICMP,
2837
2838                 /* IPv6 --> IPv6 */
2839                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2840                         RTE_PTYPE_TUNNEL_IP |
2841                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2842                         RTE_PTYPE_INNER_L4_FRAG,
2843                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2844                         RTE_PTYPE_TUNNEL_IP |
2845                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2846                         RTE_PTYPE_INNER_L4_NONFRAG,
2847                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2848                         RTE_PTYPE_TUNNEL_IP |
2849                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2850                         RTE_PTYPE_INNER_L4_UDP,
2851                 /* [105] reserved */
2852                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2853                         RTE_PTYPE_TUNNEL_IP |
2854                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2855                         RTE_PTYPE_INNER_L4_TCP,
2856                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2857                         RTE_PTYPE_TUNNEL_IP |
2858                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2859                         RTE_PTYPE_INNER_L4_SCTP,
2860                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2861                         RTE_PTYPE_TUNNEL_IP |
2862                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2863                         RTE_PTYPE_INNER_L4_ICMP,
2864
2865                 /* IPv6 --> GRE/Teredo/VXLAN */
2866                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2867                         RTE_PTYPE_TUNNEL_GRENAT,
2868
2869                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2870                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2871                         RTE_PTYPE_TUNNEL_GRENAT |
2872                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2873                         RTE_PTYPE_INNER_L4_FRAG,
2874                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2875                         RTE_PTYPE_TUNNEL_GRENAT |
2876                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2877                         RTE_PTYPE_INNER_L4_NONFRAG,
2878                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2879                         RTE_PTYPE_TUNNEL_GRENAT |
2880                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2881                         RTE_PTYPE_INNER_L4_UDP,
2882                 /* [113] reserved */
2883                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2884                         RTE_PTYPE_TUNNEL_GRENAT |
2885                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2886                         RTE_PTYPE_INNER_L4_TCP,
2887                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2888                         RTE_PTYPE_TUNNEL_GRENAT |
2889                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2890                         RTE_PTYPE_INNER_L4_SCTP,
2891                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2892                         RTE_PTYPE_TUNNEL_GRENAT |
2893                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2894                         RTE_PTYPE_INNER_L4_ICMP,
2895
2896                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2897                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2898                         RTE_PTYPE_TUNNEL_GRENAT |
2899                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2900                         RTE_PTYPE_INNER_L4_FRAG,
2901                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2902                         RTE_PTYPE_TUNNEL_GRENAT |
2903                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2904                         RTE_PTYPE_INNER_L4_NONFRAG,
2905                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2906                         RTE_PTYPE_TUNNEL_GRENAT |
2907                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2908                         RTE_PTYPE_INNER_L4_UDP,
2909                 /* [120] reserved */
2910                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2911                         RTE_PTYPE_TUNNEL_GRENAT |
2912                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2913                         RTE_PTYPE_INNER_L4_TCP,
2914                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2915                         RTE_PTYPE_TUNNEL_GRENAT |
2916                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2917                         RTE_PTYPE_INNER_L4_SCTP,
2918                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2919                         RTE_PTYPE_TUNNEL_GRENAT |
2920                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2921                         RTE_PTYPE_INNER_L4_ICMP,
2922
2923                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2924                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2925                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2926
2927                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2928                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2929                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2930                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2931                         RTE_PTYPE_INNER_L4_FRAG,
2932                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2933                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2934                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2935                         RTE_PTYPE_INNER_L4_NONFRAG,
2936                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2937                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2938                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2939                         RTE_PTYPE_INNER_L4_UDP,
2940                 /* [128] reserved */
2941                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2942                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2943                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2944                         RTE_PTYPE_INNER_L4_TCP,
2945                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2946                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2947                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2948                         RTE_PTYPE_INNER_L4_SCTP,
2949                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2950                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2951                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2952                         RTE_PTYPE_INNER_L4_ICMP,
2953
2954                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2955                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2956                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2957                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2958                         RTE_PTYPE_INNER_L4_FRAG,
2959                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2960                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2961                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2962                         RTE_PTYPE_INNER_L4_NONFRAG,
2963                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2964                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2965                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2966                         RTE_PTYPE_INNER_L4_UDP,
2967                 /* [135] reserved */
2968                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2969                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2970                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2971                         RTE_PTYPE_INNER_L4_TCP,
2972                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2973                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2974                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2975                         RTE_PTYPE_INNER_L4_SCTP,
2976                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2977                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2978                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2979                         RTE_PTYPE_INNER_L4_ICMP,
2980
2981                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2982                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2983                         RTE_PTYPE_TUNNEL_GRENAT |
2984                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
2985
2986                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2987                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2988                         RTE_PTYPE_TUNNEL_GRENAT |
2989                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2990                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2991                         RTE_PTYPE_INNER_L4_FRAG,
2992                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2993                         RTE_PTYPE_TUNNEL_GRENAT |
2994                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
2995                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2996                         RTE_PTYPE_INNER_L4_NONFRAG,
2997                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2998                         RTE_PTYPE_TUNNEL_GRENAT |
2999                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3000                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3001                         RTE_PTYPE_INNER_L4_UDP,
3002                 /* [143] reserved */
3003                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3004                         RTE_PTYPE_TUNNEL_GRENAT |
3005                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3006                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3007                         RTE_PTYPE_INNER_L4_TCP,
3008                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3009                         RTE_PTYPE_TUNNEL_GRENAT |
3010                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3011                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3012                         RTE_PTYPE_INNER_L4_SCTP,
3013                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3014                         RTE_PTYPE_TUNNEL_GRENAT |
3015                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3016                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3017                         RTE_PTYPE_INNER_L4_ICMP,
3018
3019                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
3020                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3021                         RTE_PTYPE_TUNNEL_GRENAT |
3022                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3023                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3024                         RTE_PTYPE_INNER_L4_FRAG,
3025                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3026                         RTE_PTYPE_TUNNEL_GRENAT |
3027                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3028                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3029                         RTE_PTYPE_INNER_L4_NONFRAG,
3030                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3031                         RTE_PTYPE_TUNNEL_GRENAT |
3032                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3033                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3034                         RTE_PTYPE_INNER_L4_UDP,
3035                 /* [150] reserved */
3036                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3037                         RTE_PTYPE_TUNNEL_GRENAT |
3038                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3039                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3040                         RTE_PTYPE_INNER_L4_TCP,
3041                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3042                         RTE_PTYPE_TUNNEL_GRENAT |
3043                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3044                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3045                         RTE_PTYPE_INNER_L4_SCTP,
3046                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3047                         RTE_PTYPE_TUNNEL_GRENAT |
3048                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3049                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3050                         RTE_PTYPE_INNER_L4_ICMP,
3051                 /* [154] - [255] reserved */
3052                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3053                         RTE_PTYPE_TUNNEL_GTPC,
3054                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3055                         RTE_PTYPE_TUNNEL_GTPC,
3056                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3057                                 RTE_PTYPE_TUNNEL_GTPU,
3058                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3059                                 RTE_PTYPE_TUNNEL_GTPU,
3060                 /* [260] - [263] reserved */
3061                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3062                         RTE_PTYPE_TUNNEL_GTPC,
3063                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3064                         RTE_PTYPE_TUNNEL_GTPC,
3065                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3066                                 RTE_PTYPE_TUNNEL_GTPU,
3067                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3068                                 RTE_PTYPE_TUNNEL_GTPU,
3069
3070                 /* All others reserved */
3071         };
3072
3073         return type_table[ptype];
3074 }
3075
3076 void __attribute__((cold))
3077 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3078 {
3079         struct ice_adapter *ad =
3080                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3081         int i;
3082
3083         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3084                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3085 }