drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11
  12 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  13                 PKT_TX_IP_CKSUM |                \
  14                 PKT_TX_L4_MASK |                 \
  15                 PKT_TX_TCP_SEG |                 \
  16                 PKT_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static inline uint8_t
  30 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  31 {
  32         static uint8_t rxdid_map[] = {
  33                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  34                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  35                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  36                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  37                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  38                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  39                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  40         };
  41
  42         return xtr_type < RTE_DIM(rxdid_map) ?
  43                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  44 }
  45
  46 static inline void
  47 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  48                                        struct rte_mbuf *mb,
  49                                        volatile union ice_rx_flex_desc *rxdp)
  50 {
  51         volatile struct ice_32b_rx_flex_desc_comms *desc =
  52                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  53         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  54
  55         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  56                 mb->ol_flags |= PKT_RX_RSS_HASH;
  57                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  58         }
  59
  60 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  61         if (desc->flow_id != 0xFFFFFFFF) {
  62                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  63                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  64         }
  65 #endif
  66 }
  67
  68 static inline void
  69 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
  70                                    struct rte_mbuf *mb,
  71                                    volatile union ice_rx_flex_desc *rxdp)
  72 {
  73         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
  74                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
  75 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  76         uint16_t stat_err;
  77 #endif
  78
  79         if (desc->flow_id != 0xFFFFFFFF) {
  80                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  81                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  82         }
  83
  84 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  85         stat_err = rte_le_to_cpu_16(desc->status_error0);
  86         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  87                 mb->ol_flags |= PKT_RX_RSS_HASH;
  88                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  89         }
  90 #endif
  91 }
  92
  93 static inline void
  94 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
  95                                       struct rte_mbuf *mb,
  96                                       volatile union ice_rx_flex_desc *rxdp)
  97 {
  98         volatile struct ice_32b_rx_flex_desc_comms *desc =
  99                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 100         uint16_t stat_err;
 101
 102         stat_err = rte_le_to_cpu_16(desc->status_error0);
 103         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 104                 mb->ol_flags |= PKT_RX_RSS_HASH;
 105                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 106         }
 107
 108 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 109         if (desc->flow_id != 0xFFFFFFFF) {
 110                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 111                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 112         }
 113
 114         if (rxq->xtr_ol_flag) {
 115                 uint32_t metadata = 0;
 116
 117                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 118
 119                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 120                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 121
 122                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 123                         metadata |=
 124                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 125
 126                 if (metadata) {
 127                         mb->ol_flags |= rxq->xtr_ol_flag;
 128
 129                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 130                 }
 131         }
 132 #endif
 133 }
 134
 135 static inline void
 136 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 137                                       struct rte_mbuf *mb,
 138                                       volatile union ice_rx_flex_desc *rxdp)
 139 {
 140         volatile struct ice_32b_rx_flex_desc_comms *desc =
 141                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 142         uint16_t stat_err;
 143
 144         stat_err = rte_le_to_cpu_16(desc->status_error0);
 145         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 146                 mb->ol_flags |= PKT_RX_RSS_HASH;
 147                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 148         }
 149
 150 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 151         if (desc->flow_id != 0xFFFFFFFF) {
 152                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 153                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 154         }
 155
 156         if (rxq->xtr_ol_flag) {
 157                 uint32_t metadata = 0;
 158
 159                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 160                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 161                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 162                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 163
 164                 if (metadata) {
 165                         mb->ol_flags |= rxq->xtr_ol_flag;
 166
 167                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 168                 }
 169         }
 170 #endif
 171 }
 172
 173 void
 174 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 175 {
 176         switch (rxdid) {
 177         case ICE_RXDID_COMMS_AUX_VLAN:
 178                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 179                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 180                 break;
 181
 182         case ICE_RXDID_COMMS_AUX_IPV4:
 183                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 184                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 185                 break;
 186
 187         case ICE_RXDID_COMMS_AUX_IPV6:
 188                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 189                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 190                 break;
 191
 192         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 193                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 194                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 195                 break;
 196
 197         case ICE_RXDID_COMMS_AUX_TCP:
 198                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 199                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 200                 break;
 201
 202         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 203                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 204                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
 205                 break;
 206
 207         case ICE_RXDID_COMMS_GENERIC:
 208                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
 209                 break;
 210
 211         case ICE_RXDID_COMMS_OVS:
 212                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 213                 break;
 214
 215         default:
 216                 /* update this according to the RXDID for PROTO_XTR_NONE */
 217                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 218                 break;
 219         }
 220
 221         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 222                 rxq->xtr_ol_flag = 0;
 223 }
 224
 225 static enum ice_status
 226 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 227 {
 228         struct ice_vsi *vsi = rxq->vsi;
 229         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 230         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 231         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
 232         struct ice_rlan_ctx rx_ctx;
 233         enum ice_status err;
 234         uint16_t buf_size, len;
 235         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 236         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 237         uint32_t regval;
 238
 239         /* Set buffer size as the head split is disabled. */
 240         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 241                               RTE_PKTMBUF_HEADROOM);
 242         rxq->rx_hdr_len = 0;
 243         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 244         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
 245         rxq->max_pkt_len = RTE_MIN(len,
 246                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
 247
 248         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 249                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
 250                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 251                         PMD_DRV_LOG(ERR, "maximum packet length must "
 252                                     "be larger than %u and smaller than %u,"
 253                                     "as jumbo frame is enabled",
 254                                     (uint32_t)RTE_ETHER_MAX_LEN,
 255                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 256                         return -EINVAL;
 257                 }
 258         } else {
 259                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 260                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 261                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 262                                     "larger than %u and smaller than %u, "
 263                                     "as jumbo frame is disabled",
 264                                     (uint32_t)RTE_ETHER_MIN_LEN,
 265                                     (uint32_t)RTE_ETHER_MAX_LEN);
 266                         return -EINVAL;
 267                 }
 268         }
 269
 270         memset(&rx_ctx, 0, sizeof(rx_ctx));
 271
 272         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 273         rx_ctx.qlen = rxq->nb_rx_desc;
 274         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 275         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 276         rx_ctx.dtype = 0; /* No Header Split mode */
 277 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 278         rx_ctx.dsize = 1; /* 32B descriptors */
 279 #endif
 280         rx_ctx.rxmax = rxq->max_pkt_len;
 281         /* TPH: Transaction Layer Packet (TLP) processing hints */
 282         rx_ctx.tphrdesc_ena = 1;
 283         rx_ctx.tphwdesc_ena = 1;
 284         rx_ctx.tphdata_ena = 1;
 285         rx_ctx.tphhead_ena = 1;
 286         /* Low Receive Queue Threshold defined in 64 descriptors units.
 287          * When the number of free descriptors goes below the lrxqthresh,
 288          * an immediate interrupt is triggered.
 289          */
 290         rx_ctx.lrxqthresh = 2;
 291         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 292         rx_ctx.l2tsel = 1;
 293         rx_ctx.showiv = 0;
 294         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 295
 296         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 297
 298         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 299                     rxq->port_id, rxq->queue_id, rxdid);
 300
 301         if (!(pf->supported_rxdid & BIT(rxdid))) {
 302                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 303                             rxdid);
 304                 return -EINVAL;
 305         }
 306
 307         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 308
 309         /* Enable Flexible Descriptors in the queue context which
 310          * allows this driver to select a specific receive descriptor format
 311          */
 312         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 313                 QRXFLXP_CNTXT_RXDID_IDX_M;
 314
 315         /* increasing context priority to pick up profile ID;
 316          * default is 0x01; setting to 0x03 to ensure profile
 317          * is programming if prev context is of same priority
 318          */
 319         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 320                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 321
 322         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 323
 324         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 325         if (err) {
 326                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 327                             rxq->queue_id);
 328                 return -EINVAL;
 329         }
 330         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 331         if (err) {
 332                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 333                             rxq->queue_id);
 334                 return -EINVAL;
 335         }
 336
 337         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 338                               RTE_PKTMBUF_HEADROOM);
 339
 340         /* Check if scattered RX needs to be used. */
 341         if (rxq->max_pkt_len > buf_size)
 342                 dev->data->scattered_rx = 1;
 343
 344         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 345
 346         /* Init the Rx tail register*/
 347         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 348
 349         return 0;
 350 }
 351
 352 /* Allocate mbufs for all descriptors in rx queue */
 353 static int
 354 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 355 {
 356         struct ice_rx_entry *rxe = rxq->sw_ring;
 357         uint64_t dma_addr;
 358         uint16_t i;
 359
 360         for (i = 0; i < rxq->nb_rx_desc; i++) {
 361                 volatile union ice_rx_flex_desc *rxd;
 362                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 363
 364                 if (unlikely(!mbuf)) {
 365                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 366                         return -ENOMEM;
 367                 }
 368
 369                 rte_mbuf_refcnt_set(mbuf, 1);
 370                 mbuf->next = NULL;
 371                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 372                 mbuf->nb_segs = 1;
 373                 mbuf->port = rxq->port_id;
 374
 375                 dma_addr =
 376                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 377
 378                 rxd = &rxq->rx_ring[i];
 379                 rxd->read.pkt_addr = dma_addr;
 380                 rxd->read.hdr_addr = 0;
 381 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 382                 rxd->read.rsvd1 = 0;
 383                 rxd->read.rsvd2 = 0;
 384 #endif
 385                 rxe[i].mbuf = mbuf;
 386         }
 387
 388         return 0;
 389 }
 390
 391 /* Free all mbufs for descriptors in rx queue */
 392 static void
 393 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 394 {
 395         uint16_t i;
 396
 397         if (!rxq || !rxq->sw_ring) {
 398                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 399                 return;
 400         }
 401
 402         for (i = 0; i < rxq->nb_rx_desc; i++) {
 403                 if (rxq->sw_ring[i].mbuf) {
 404                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 405                         rxq->sw_ring[i].mbuf = NULL;
 406                 }
 407         }
 408         if (rxq->rx_nb_avail == 0)
 409                 return;
 410         for (i = 0; i < rxq->rx_nb_avail; i++)
 411                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 412
 413         rxq->rx_nb_avail = 0;
 414 }
 415
 416 /* turn on or off rx queue
 417  * @q_idx: queue index in pf scope
 418  * @on: turn on or off the queue
 419  */
 420 static int
 421 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 422 {
 423         uint32_t reg;
 424         uint16_t j;
 425
 426         /* QRX_CTRL = QRX_ENA */
 427         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 428
 429         if (on) {
 430                 if (reg & QRX_CTRL_QENA_STAT_M)
 431                         return 0; /* Already on, skip */
 432                 reg |= QRX_CTRL_QENA_REQ_M;
 433         } else {
 434                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 435                         return 0; /* Already off, skip */
 436                 reg &= ~QRX_CTRL_QENA_REQ_M;
 437         }
 438
 439         /* Write the register */
 440         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 441         /* Check the result. It is said that QENA_STAT
 442          * follows the QENA_REQ not more than 10 use.
 443          * TODO: need to change the wait counter later
 444          */
 445         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 446                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 447                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 448                 if (on) {
 449                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 450                             (reg & QRX_CTRL_QENA_STAT_M))
 451                                 break;
 452                 } else {
 453                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 454                             !(reg & QRX_CTRL_QENA_STAT_M))
 455                                 break;
 456                 }
 457         }
 458
 459         /* Check if it is timeout */
 460         if (j >= ICE_CHK_Q_ENA_COUNT) {
 461                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 462                             (on ? "enable" : "disable"), q_idx);
 463                 return -ETIMEDOUT;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static inline int
 470 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 471 {
 472         int ret = 0;
 473
 474         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 475                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 476                              "rxq->rx_free_thresh=%d, "
 477                              "ICE_RX_MAX_BURST=%d",
 478                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 479                 ret = -EINVAL;
 480         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 481                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 482                              "rxq->rx_free_thresh=%d, "
 483                              "rxq->nb_rx_desc=%d",
 484                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 485                 ret = -EINVAL;
 486         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 487                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 488                              "rxq->nb_rx_desc=%d, "
 489                              "rxq->rx_free_thresh=%d",
 490                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 491                 ret = -EINVAL;
 492         }
 493
 494         return ret;
 495 }
 496
 497 /* reset fields in ice_rx_queue back to default */
 498 static void
 499 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 500 {
 501         unsigned int i;
 502         uint16_t len;
 503
 504         if (!rxq) {
 505                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 506                 return;
 507         }
 508
 509         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 510
 511         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 512                 ((volatile char *)rxq->rx_ring)[i] = 0;
 513
 514         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 515         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 516                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 517
 518         rxq->rx_nb_avail = 0;
 519         rxq->rx_next_avail = 0;
 520         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 521
 522         rxq->rx_tail = 0;
 523         rxq->nb_rx_hold = 0;
 524         rxq->pkt_first_seg = NULL;
 525         rxq->pkt_last_seg = NULL;
 526
 527         rxq->rxrearm_start = 0;
 528         rxq->rxrearm_nb = 0;
 529 }
 530
 531 int
 532 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 533 {
 534         struct ice_rx_queue *rxq;
 535         int err;
 536         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 537
 538         PMD_INIT_FUNC_TRACE();
 539
 540         if (rx_queue_id >= dev->data->nb_rx_queues) {
 541                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 542                             rx_queue_id, dev->data->nb_rx_queues);
 543                 return -EINVAL;
 544         }
 545
 546         rxq = dev->data->rx_queues[rx_queue_id];
 547         if (!rxq || !rxq->q_set) {
 548                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 549                             rx_queue_id);
 550                 return -EINVAL;
 551         }
 552
 553         err = ice_program_hw_rx_queue(rxq);
 554         if (err) {
 555                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 556                             rx_queue_id);
 557                 return -EIO;
 558         }
 559
 560         err = ice_alloc_rx_queue_mbufs(rxq);
 561         if (err) {
 562                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 563                 return -ENOMEM;
 564         }
 565
 566         /* Init the RX tail register. */
 567         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 568
 569         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 570         if (err) {
 571                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 572                             rx_queue_id);
 573
 574                 rxq->rx_rel_mbufs(rxq);
 575                 ice_reset_rx_queue(rxq);
 576                 return -EINVAL;
 577         }
 578
 579         dev->data->rx_queue_state[rx_queue_id] =
 580                 RTE_ETH_QUEUE_STATE_STARTED;
 581
 582         return 0;
 583 }
 584
 585 int
 586 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 587 {
 588         struct ice_rx_queue *rxq;
 589         int err;
 590         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 591
 592         if (rx_queue_id < dev->data->nb_rx_queues) {
 593                 rxq = dev->data->rx_queues[rx_queue_id];
 594
 595                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 596                 if (err) {
 597                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 598                                     rx_queue_id);
 599                         return -EINVAL;
 600                 }
 601                 rxq->rx_rel_mbufs(rxq);
 602                 ice_reset_rx_queue(rxq);
 603                 dev->data->rx_queue_state[rx_queue_id] =
 604                         RTE_ETH_QUEUE_STATE_STOPPED;
 605         }
 606
 607         return 0;
 608 }
 609
 610 int
 611 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 612 {
 613         struct ice_tx_queue *txq;
 614         int err;
 615         struct ice_vsi *vsi;
 616         struct ice_hw *hw;
 617         struct ice_aqc_add_tx_qgrp *txq_elem;
 618         struct ice_tlan_ctx tx_ctx;
 619         int buf_len;
 620
 621         PMD_INIT_FUNC_TRACE();
 622
 623         if (tx_queue_id >= dev->data->nb_tx_queues) {
 624                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 625                             tx_queue_id, dev->data->nb_tx_queues);
 626                 return -EINVAL;
 627         }
 628
 629         txq = dev->data->tx_queues[tx_queue_id];
 630         if (!txq || !txq->q_set) {
 631                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 632                             tx_queue_id);
 633                 return -EINVAL;
 634         }
 635
 636         buf_len = ice_struct_size(txq_elem, txqs, 1);
 637         txq_elem = ice_malloc(hw, buf_len);
 638         if (!txq_elem)
 639                 return -ENOMEM;
 640
 641         vsi = txq->vsi;
 642         hw = ICE_VSI_TO_HW(vsi);
 643
 644         memset(&tx_ctx, 0, sizeof(tx_ctx));
 645         txq_elem->num_txqs = 1;
 646         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 647
 648         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 649         tx_ctx.qlen = txq->nb_tx_desc;
 650         tx_ctx.pf_num = hw->pf_id;
 651         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 652         tx_ctx.src_vsi = vsi->vsi_id;
 653         tx_ctx.port_num = hw->port_info->lport;
 654         tx_ctx.tso_ena = 1; /* tso enable */
 655         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 656         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 657
 658         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 659                     ice_tlan_ctx_info);
 660
 661         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 662
 663         /* Init the Tx tail register*/
 664         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 665
 666         /* Fix me, we assume TC always 0 here */
 667         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 668                         txq_elem, buf_len, NULL);
 669         if (err) {
 670                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 671                 rte_free(txq_elem);
 672                 return -EIO;
 673         }
 674         /* store the schedule node id */
 675         txq->q_teid = txq_elem->txqs[0].q_teid;
 676
 677         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 678
 679         rte_free(txq_elem);
 680         return 0;
 681 }
 682
 683 static enum ice_status
 684 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 685 {
 686         struct ice_vsi *vsi = rxq->vsi;
 687         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 688         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 689         struct ice_rlan_ctx rx_ctx;
 690         enum ice_status err;
 691         uint32_t regval;
 692
 693         rxq->rx_hdr_len = 0;
 694         rxq->rx_buf_len = 1024;
 695
 696         memset(&rx_ctx, 0, sizeof(rx_ctx));
 697
 698         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 699         rx_ctx.qlen = rxq->nb_rx_desc;
 700         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 701         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 702         rx_ctx.dtype = 0; /* No Header Split mode */
 703         rx_ctx.dsize = 1; /* 32B descriptors */
 704         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 705         /* TPH: Transaction Layer Packet (TLP) processing hints */
 706         rx_ctx.tphrdesc_ena = 1;
 707         rx_ctx.tphwdesc_ena = 1;
 708         rx_ctx.tphdata_ena = 1;
 709         rx_ctx.tphhead_ena = 1;
 710         /* Low Receive Queue Threshold defined in 64 descriptors units.
 711          * When the number of free descriptors goes below the lrxqthresh,
 712          * an immediate interrupt is triggered.
 713          */
 714         rx_ctx.lrxqthresh = 2;
 715         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 716         rx_ctx.l2tsel = 1;
 717         rx_ctx.showiv = 0;
 718         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 719
 720         /* Enable Flexible Descriptors in the queue context which
 721          * allows this driver to select a specific receive descriptor format
 722          */
 723         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 724                 QRXFLXP_CNTXT_RXDID_IDX_M;
 725
 726         /* increasing context priority to pick up profile ID;
 727          * default is 0x01; setting to 0x03 to ensure profile
 728          * is programming if prev context is of same priority
 729          */
 730         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 731                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 732
 733         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 734
 735         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 736         if (err) {
 737                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 738                             rxq->queue_id);
 739                 return -EINVAL;
 740         }
 741         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 742         if (err) {
 743                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 744                             rxq->queue_id);
 745                 return -EINVAL;
 746         }
 747
 748         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 749
 750         /* Init the Rx tail register*/
 751         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 752
 753         return 0;
 754 }
 755
 756 int
 757 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 758 {
 759         struct ice_rx_queue *rxq;
 760         int err;
 761         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 762         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 763
 764         PMD_INIT_FUNC_TRACE();
 765
 766         rxq = pf->fdir.rxq;
 767         if (!rxq || !rxq->q_set) {
 768                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 769                             rx_queue_id);
 770                 return -EINVAL;
 771         }
 772
 773         err = ice_fdir_program_hw_rx_queue(rxq);
 774         if (err) {
 775                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 776                             rx_queue_id);
 777                 return -EIO;
 778         }
 779
 780         /* Init the RX tail register. */
 781         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 782
 783         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 784         if (err) {
 785                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 786                             rx_queue_id);
 787
 788                 ice_reset_rx_queue(rxq);
 789                 return -EINVAL;
 790         }
 791
 792         return 0;
 793 }
 794
 795 int
 796 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 797 {
 798         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 799         struct ice_tx_queue *txq;
 800         int err;
 801         struct ice_vsi *vsi;
 802         struct ice_hw *hw;
 803         struct ice_aqc_add_tx_qgrp *txq_elem;
 804         struct ice_tlan_ctx tx_ctx;
 805         int buf_len;
 806
 807         PMD_INIT_FUNC_TRACE();
 808
 809         txq = pf->fdir.txq;
 810         if (!txq || !txq->q_set) {
 811                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 812                             tx_queue_id);
 813                 return -EINVAL;
 814         }
 815
 816         buf_len = ice_struct_size(txq_elem, txqs, 1);
 817         txq_elem = ice_malloc(hw, buf_len);
 818         if (!txq_elem)
 819                 return -ENOMEM;
 820
 821         vsi = txq->vsi;
 822         hw = ICE_VSI_TO_HW(vsi);
 823
 824         memset(&tx_ctx, 0, sizeof(tx_ctx));
 825         txq_elem->num_txqs = 1;
 826         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 827
 828         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 829         tx_ctx.qlen = txq->nb_tx_desc;
 830         tx_ctx.pf_num = hw->pf_id;
 831         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 832         tx_ctx.src_vsi = vsi->vsi_id;
 833         tx_ctx.port_num = hw->port_info->lport;
 834         tx_ctx.tso_ena = 1; /* tso enable */
 835         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 836         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 837
 838         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 839                     ice_tlan_ctx_info);
 840
 841         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 842
 843         /* Init the Tx tail register*/
 844         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 845
 846         /* Fix me, we assume TC always 0 here */
 847         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 848                               txq_elem, buf_len, NULL);
 849         if (err) {
 850                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 851                 rte_free(txq_elem);
 852                 return -EIO;
 853         }
 854         /* store the schedule node id */
 855         txq->q_teid = txq_elem->txqs[0].q_teid;
 856
 857         rte_free(txq_elem);
 858         return 0;
 859 }
 860
 861 /* Free all mbufs for descriptors in tx queue */
 862 static void
 863 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 864 {
 865         uint16_t i;
 866
 867         if (!txq || !txq->sw_ring) {
 868                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 869                 return;
 870         }
 871
 872         for (i = 0; i < txq->nb_tx_desc; i++) {
 873                 if (txq->sw_ring[i].mbuf) {
 874                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 875                         txq->sw_ring[i].mbuf = NULL;
 876                 }
 877         }
 878 }
 879
 880 static void
 881 ice_reset_tx_queue(struct ice_tx_queue *txq)
 882 {
 883         struct ice_tx_entry *txe;
 884         uint16_t i, prev, size;
 885
 886         if (!txq) {
 887                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 888                 return;
 889         }
 890
 891         txe = txq->sw_ring;
 892         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 893         for (i = 0; i < size; i++)
 894                 ((volatile char *)txq->tx_ring)[i] = 0;
 895
 896         prev = (uint16_t)(txq->nb_tx_desc - 1);
 897         for (i = 0; i < txq->nb_tx_desc; i++) {
 898                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 899
 900                 txd->cmd_type_offset_bsz =
 901                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 902                 txe[i].mbuf =  NULL;
 903                 txe[i].last_id = i;
 904                 txe[prev].next_id = i;
 905                 prev = i;
 906         }
 907
 908         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 909         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 910
 911         txq->tx_tail = 0;
 912         txq->nb_tx_used = 0;
 913
 914         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 915         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 916 }
 917
 918 int
 919 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 920 {
 921         struct ice_tx_queue *txq;
 922         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 924         struct ice_vsi *vsi = pf->main_vsi;
 925         enum ice_status status;
 926         uint16_t q_ids[1];
 927         uint32_t q_teids[1];
 928         uint16_t q_handle = tx_queue_id;
 929
 930         if (tx_queue_id >= dev->data->nb_tx_queues) {
 931                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 932                             tx_queue_id, dev->data->nb_tx_queues);
 933                 return -EINVAL;
 934         }
 935
 936         txq = dev->data->tx_queues[tx_queue_id];
 937         if (!txq) {
 938                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 939                             tx_queue_id);
 940                 return -EINVAL;
 941         }
 942
 943         q_ids[0] = txq->reg_idx;
 944         q_teids[0] = txq->q_teid;
 945
 946         /* Fix me, we assume TC always 0 here */
 947         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 948                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 949         if (status != ICE_SUCCESS) {
 950                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 951                 return -EINVAL;
 952         }
 953
 954         txq->tx_rel_mbufs(txq);
 955         ice_reset_tx_queue(txq);
 956         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 957
 958         return 0;
 959 }
 960
 961 int
 962 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 963 {
 964         struct ice_rx_queue *rxq;
 965         int err;
 966         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 967         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 968
 969         rxq = pf->fdir.rxq;
 970
 971         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 972         if (err) {
 973                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 974                             rx_queue_id);
 975                 return -EINVAL;
 976         }
 977         rxq->rx_rel_mbufs(rxq);
 978
 979         return 0;
 980 }
 981
 982 int
 983 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 984 {
 985         struct ice_tx_queue *txq;
 986         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 988         struct ice_vsi *vsi = pf->main_vsi;
 989         enum ice_status status;
 990         uint16_t q_ids[1];
 991         uint32_t q_teids[1];
 992         uint16_t q_handle = tx_queue_id;
 993
 994         txq = pf->fdir.txq;
 995         if (!txq) {
 996                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 997                             tx_queue_id);
 998                 return -EINVAL;
 999         }
1000         vsi = txq->vsi;
1001
1002         q_ids[0] = txq->reg_idx;
1003         q_teids[0] = txq->q_teid;
1004
1005         /* Fix me, we assume TC always 0 here */
1006         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1007                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1008         if (status != ICE_SUCCESS) {
1009                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1010                 return -EINVAL;
1011         }
1012
1013         txq->tx_rel_mbufs(txq);
1014
1015         return 0;
1016 }
1017
1018 int
1019 ice_rx_queue_setup(struct rte_eth_dev *dev,
1020                    uint16_t queue_idx,
1021                    uint16_t nb_desc,
1022                    unsigned int socket_id,
1023                    const struct rte_eth_rxconf *rx_conf,
1024                    struct rte_mempool *mp)
1025 {
1026         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1027         struct ice_adapter *ad =
1028                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1029         struct ice_vsi *vsi = pf->main_vsi;
1030         struct ice_rx_queue *rxq;
1031         const struct rte_memzone *rz;
1032         uint32_t ring_size;
1033         uint16_t len;
1034         int use_def_burst_func = 1;
1035
1036         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1037             nb_desc > ICE_MAX_RING_DESC ||
1038             nb_desc < ICE_MIN_RING_DESC) {
1039                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1040                              "invalid", nb_desc);
1041                 return -EINVAL;
1042         }
1043
1044         /* Free memory if needed */
1045         if (dev->data->rx_queues[queue_idx]) {
1046                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1047                 dev->data->rx_queues[queue_idx] = NULL;
1048         }
1049
1050         /* Allocate the rx queue data structure */
1051         rxq = rte_zmalloc_socket(NULL,
1052                                  sizeof(struct ice_rx_queue),
1053                                  RTE_CACHE_LINE_SIZE,
1054                                  socket_id);
1055         if (!rxq) {
1056                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1057                              "rx queue data structure");
1058                 return -ENOMEM;
1059         }
1060         rxq->mp = mp;
1061         rxq->nb_rx_desc = nb_desc;
1062         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1063         rxq->queue_id = queue_idx;
1064
1065         rxq->reg_idx = vsi->base_queue + queue_idx;
1066         rxq->port_id = dev->data->port_id;
1067         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1068                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1069         else
1070                 rxq->crc_len = 0;
1071
1072         rxq->drop_en = rx_conf->rx_drop_en;
1073         rxq->vsi = vsi;
1074         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1075         rxq->proto_xtr = pf->proto_xtr != NULL ?
1076                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1077
1078         /* Allocate the maximun number of RX ring hardware descriptor. */
1079         len = ICE_MAX_RING_DESC;
1080
1081         /**
1082          * Allocating a little more memory because vectorized/bulk_alloc Rx
1083          * functions doesn't check boundaries each time.
1084          */
1085         len += ICE_RX_MAX_BURST;
1086
1087         /* Allocate the maximum number of RX ring hardware descriptor. */
1088         ring_size = sizeof(union ice_rx_flex_desc) * len;
1089         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1090         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1091                                       ring_size, ICE_RING_BASE_ALIGN,
1092                                       socket_id);
1093         if (!rz) {
1094                 ice_rx_queue_release(rxq);
1095                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1096                 return -ENOMEM;
1097         }
1098
1099         /* Zero all the descriptors in the ring. */
1100         memset(rz->addr, 0, ring_size);
1101
1102         rxq->rx_ring_dma = rz->iova;
1103         rxq->rx_ring = rz->addr;
1104
1105         /* always reserve more for bulk alloc */
1106         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1107
1108         /* Allocate the software ring. */
1109         rxq->sw_ring = rte_zmalloc_socket(NULL,
1110                                           sizeof(struct ice_rx_entry) * len,
1111                                           RTE_CACHE_LINE_SIZE,
1112                                           socket_id);
1113         if (!rxq->sw_ring) {
1114                 ice_rx_queue_release(rxq);
1115                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1116                 return -ENOMEM;
1117         }
1118
1119         ice_reset_rx_queue(rxq);
1120         rxq->q_set = true;
1121         dev->data->rx_queues[queue_idx] = rxq;
1122         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1123
1124         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1125
1126         if (!use_def_burst_func) {
1127                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1128                              "satisfied. Rx Burst Bulk Alloc function will be "
1129                              "used on port=%d, queue=%d.",
1130                              rxq->port_id, rxq->queue_id);
1131         } else {
1132                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1133                              "not satisfied, Scattered Rx is requested. "
1134                              "on port=%d, queue=%d.",
1135                              rxq->port_id, rxq->queue_id);
1136                 ad->rx_bulk_alloc_allowed = false;
1137         }
1138
1139         return 0;
1140 }
1141
1142 void
1143 ice_rx_queue_release(void *rxq)
1144 {
1145         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1146
1147         if (!q) {
1148                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1149                 return;
1150         }
1151
1152         q->rx_rel_mbufs(q);
1153         rte_free(q->sw_ring);
1154         rte_free(q);
1155 }
1156
1157 int
1158 ice_tx_queue_setup(struct rte_eth_dev *dev,
1159                    uint16_t queue_idx,
1160                    uint16_t nb_desc,
1161                    unsigned int socket_id,
1162                    const struct rte_eth_txconf *tx_conf)
1163 {
1164         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1165         struct ice_vsi *vsi = pf->main_vsi;
1166         struct ice_tx_queue *txq;
1167         const struct rte_memzone *tz;
1168         uint32_t ring_size;
1169         uint16_t tx_rs_thresh, tx_free_thresh;
1170         uint64_t offloads;
1171
1172         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1173
1174         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1175             nb_desc > ICE_MAX_RING_DESC ||
1176             nb_desc < ICE_MIN_RING_DESC) {
1177                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1178                              "invalid", nb_desc);
1179                 return -EINVAL;
1180         }
1181
1182         /**
1183          * The following two parameters control the setting of the RS bit on
1184          * transmit descriptors. TX descriptors will have their RS bit set
1185          * after txq->tx_rs_thresh descriptors have been used. The TX
1186          * descriptor ring will be cleaned after txq->tx_free_thresh
1187          * descriptors are used or if the number of descriptors required to
1188          * transmit a packet is greater than the number of free TX descriptors.
1189          *
1190          * The following constraints must be satisfied:
1191          *  - tx_rs_thresh must be greater than 0.
1192          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1193          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1194          *  - tx_rs_thresh must be a divisor of the ring size.
1195          *  - tx_free_thresh must be greater than 0.
1196          *  - tx_free_thresh must be less than the size of the ring minus 3.
1197          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1198          *
1199          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1200          * race condition, hence the maximum threshold constraints. When set
1201          * to zero use default values.
1202          */
1203         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1204                                     tx_conf->tx_free_thresh :
1205                                     ICE_DEFAULT_TX_FREE_THRESH);
1206         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1207         tx_rs_thresh =
1208                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1209                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1210         if (tx_conf->tx_rs_thresh)
1211                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1212         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1213                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1214                                 "exceed nb_desc. (tx_rs_thresh=%u "
1215                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1216                                 (unsigned int)tx_rs_thresh,
1217                                 (unsigned int)tx_free_thresh,
1218                                 (unsigned int)nb_desc,
1219                                 (int)dev->data->port_id,
1220                                 (int)queue_idx);
1221                 return -EINVAL;
1222         }
1223         if (tx_rs_thresh >= (nb_desc - 2)) {
1224                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1225                              "number of TX descriptors minus 2. "
1226                              "(tx_rs_thresh=%u port=%d queue=%d)",
1227                              (unsigned int)tx_rs_thresh,
1228                              (int)dev->data->port_id,
1229                              (int)queue_idx);
1230                 return -EINVAL;
1231         }
1232         if (tx_free_thresh >= (nb_desc - 3)) {
1233                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1234                              "tx_free_thresh must be less than the "
1235                              "number of TX descriptors minus 3. "
1236                              "(tx_free_thresh=%u port=%d queue=%d)",
1237                              (unsigned int)tx_free_thresh,
1238                              (int)dev->data->port_id,
1239                              (int)queue_idx);
1240                 return -EINVAL;
1241         }
1242         if (tx_rs_thresh > tx_free_thresh) {
1243                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1244                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1245                              " tx_rs_thresh=%u port=%d queue=%d)",
1246                              (unsigned int)tx_free_thresh,
1247                              (unsigned int)tx_rs_thresh,
1248                              (int)dev->data->port_id,
1249                              (int)queue_idx);
1250                 return -EINVAL;
1251         }
1252         if ((nb_desc % tx_rs_thresh) != 0) {
1253                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1254                              "number of TX descriptors. (tx_rs_thresh=%u"
1255                              " port=%d queue=%d)",
1256                              (unsigned int)tx_rs_thresh,
1257                              (int)dev->data->port_id,
1258                              (int)queue_idx);
1259                 return -EINVAL;
1260         }
1261         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1262                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1263                              "tx_rs_thresh is greater than 1. "
1264                              "(tx_rs_thresh=%u port=%d queue=%d)",
1265                              (unsigned int)tx_rs_thresh,
1266                              (int)dev->data->port_id,
1267                              (int)queue_idx);
1268                 return -EINVAL;
1269         }
1270
1271         /* Free memory if needed. */
1272         if (dev->data->tx_queues[queue_idx]) {
1273                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1274                 dev->data->tx_queues[queue_idx] = NULL;
1275         }
1276
1277         /* Allocate the TX queue data structure. */
1278         txq = rte_zmalloc_socket(NULL,
1279                                  sizeof(struct ice_tx_queue),
1280                                  RTE_CACHE_LINE_SIZE,
1281                                  socket_id);
1282         if (!txq) {
1283                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1284                              "tx queue structure");
1285                 return -ENOMEM;
1286         }
1287
1288         /* Allocate TX hardware ring descriptors. */
1289         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1290         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1291         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1292                                       ring_size, ICE_RING_BASE_ALIGN,
1293                                       socket_id);
1294         if (!tz) {
1295                 ice_tx_queue_release(txq);
1296                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1297                 return -ENOMEM;
1298         }
1299
1300         txq->nb_tx_desc = nb_desc;
1301         txq->tx_rs_thresh = tx_rs_thresh;
1302         txq->tx_free_thresh = tx_free_thresh;
1303         txq->pthresh = tx_conf->tx_thresh.pthresh;
1304         txq->hthresh = tx_conf->tx_thresh.hthresh;
1305         txq->wthresh = tx_conf->tx_thresh.wthresh;
1306         txq->queue_id = queue_idx;
1307
1308         txq->reg_idx = vsi->base_queue + queue_idx;
1309         txq->port_id = dev->data->port_id;
1310         txq->offloads = offloads;
1311         txq->vsi = vsi;
1312         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1313
1314         txq->tx_ring_dma = tz->iova;
1315         txq->tx_ring = tz->addr;
1316
1317         /* Allocate software ring */
1318         txq->sw_ring =
1319                 rte_zmalloc_socket(NULL,
1320                                    sizeof(struct ice_tx_entry) * nb_desc,
1321                                    RTE_CACHE_LINE_SIZE,
1322                                    socket_id);
1323         if (!txq->sw_ring) {
1324                 ice_tx_queue_release(txq);
1325                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1326                 return -ENOMEM;
1327         }
1328
1329         ice_reset_tx_queue(txq);
1330         txq->q_set = true;
1331         dev->data->tx_queues[queue_idx] = txq;
1332         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1333         ice_set_tx_function_flag(dev, txq);
1334
1335         return 0;
1336 }
1337
1338 void
1339 ice_tx_queue_release(void *txq)
1340 {
1341         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1342
1343         if (!q) {
1344                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1345                 return;
1346         }
1347
1348         q->tx_rel_mbufs(q);
1349         rte_free(q->sw_ring);
1350         rte_free(q);
1351 }
1352
1353 void
1354 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1355                  struct rte_eth_rxq_info *qinfo)
1356 {
1357         struct ice_rx_queue *rxq;
1358
1359         rxq = dev->data->rx_queues[queue_id];
1360
1361         qinfo->mp = rxq->mp;
1362         qinfo->scattered_rx = dev->data->scattered_rx;
1363         qinfo->nb_desc = rxq->nb_rx_desc;
1364
1365         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1366         qinfo->conf.rx_drop_en = rxq->drop_en;
1367         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1368 }
1369
1370 void
1371 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1372                  struct rte_eth_txq_info *qinfo)
1373 {
1374         struct ice_tx_queue *txq;
1375
1376         txq = dev->data->tx_queues[queue_id];
1377
1378         qinfo->nb_desc = txq->nb_tx_desc;
1379
1380         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1381         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1382         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1383
1384         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1385         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1386         qinfo->conf.offloads = txq->offloads;
1387         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1388 }
1389
1390 uint32_t
1391 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1392 {
1393 #define ICE_RXQ_SCAN_INTERVAL 4
1394         volatile union ice_rx_flex_desc *rxdp;
1395         struct ice_rx_queue *rxq;
1396         uint16_t desc = 0;
1397
1398         rxq = dev->data->rx_queues[rx_queue_id];
1399         rxdp = &rxq->rx_ring[rxq->rx_tail];
1400         while ((desc < rxq->nb_rx_desc) &&
1401                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1402                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1403                 /**
1404                  * Check the DD bit of a rx descriptor of each 4 in a group,
1405                  * to avoid checking too frequently and downgrading performance
1406                  * too much.
1407                  */
1408                 desc += ICE_RXQ_SCAN_INTERVAL;
1409                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1410                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1411                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1412                                  desc - rxq->nb_rx_desc]);
1413         }
1414
1415         return desc;
1416 }
1417
1418 #define ICE_RX_FLEX_ERR0_BITS   \
1419         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1420          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1421          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1422          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1423          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1424          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1425
1426 /* Rx L3/L4 checksum */
1427 static inline uint64_t
1428 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1429 {
1430         uint64_t flags = 0;
1431
1432         /* check if HW has decoded the packet and checksum */
1433         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1434                 return 0;
1435
1436         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1437                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1438                 return flags;
1439         }
1440
1441         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1442                 flags |= PKT_RX_IP_CKSUM_BAD;
1443         else
1444                 flags |= PKT_RX_IP_CKSUM_GOOD;
1445
1446         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1447                 flags |= PKT_RX_L4_CKSUM_BAD;
1448         else
1449                 flags |= PKT_RX_L4_CKSUM_GOOD;
1450
1451         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1452                 flags |= PKT_RX_EIP_CKSUM_BAD;
1453
1454         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1455                 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1456         else
1457                 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1458
1459         return flags;
1460 }
1461
1462 static inline void
1463 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1464 {
1465         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1466             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1467                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1468                 mb->vlan_tci =
1469                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1470                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1471                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1472         } else {
1473                 mb->vlan_tci = 0;
1474         }
1475
1476 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1477         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1478             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1479                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1480                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1481                 mb->vlan_tci_outer = mb->vlan_tci;
1482                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1483                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1484                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1485                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1486         } else {
1487                 mb->vlan_tci_outer = 0;
1488         }
1489 #endif
1490         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1491                    mb->vlan_tci, mb->vlan_tci_outer);
1492 }
1493
1494 #define ICE_LOOK_AHEAD 8
1495 #if (ICE_LOOK_AHEAD != 8)
1496 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1497 #endif
1498 static inline int
1499 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1500 {
1501         volatile union ice_rx_flex_desc *rxdp;
1502         struct ice_rx_entry *rxep;
1503         struct rte_mbuf *mb;
1504         uint16_t stat_err0;
1505         uint16_t pkt_len;
1506         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1507         int32_t i, j, nb_rx = 0;
1508         uint64_t pkt_flags = 0;
1509         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1510
1511         rxdp = &rxq->rx_ring[rxq->rx_tail];
1512         rxep = &rxq->sw_ring[rxq->rx_tail];
1513
1514         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1515
1516         /* Make sure there is at least 1 packet to receive */
1517         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1518                 return 0;
1519
1520         /**
1521          * Scan LOOK_AHEAD descriptors at a time to determine which
1522          * descriptors reference packets that are ready to be received.
1523          */
1524         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1525              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1526                 /* Read desc statuses backwards to avoid race condition */
1527                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1528                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1529
1530                 rte_smp_rmb();
1531
1532                 /* Compute how many status bits were set */
1533                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1534                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1535
1536                 nb_rx += nb_dd;
1537
1538                 /* Translate descriptor info to mbuf parameters */
1539                 for (j = 0; j < nb_dd; j++) {
1540                         mb = rxep[j].mbuf;
1541                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1542                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1543                         mb->data_len = pkt_len;
1544                         mb->pkt_len = pkt_len;
1545                         mb->ol_flags = 0;
1546                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1547                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1548                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1549                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1550                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1551                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1552
1553                         mb->ol_flags |= pkt_flags;
1554                 }
1555
1556                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1557                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1558
1559                 if (nb_dd != ICE_LOOK_AHEAD)
1560                         break;
1561         }
1562
1563         /* Clear software ring entries */
1564         for (i = 0; i < nb_rx; i++)
1565                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1566
1567         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1568                    "port_id=%u, queue_id=%u, nb_rx=%d",
1569                    rxq->port_id, rxq->queue_id, nb_rx);
1570
1571         return nb_rx;
1572 }
1573
1574 static inline uint16_t
1575 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1576                        struct rte_mbuf **rx_pkts,
1577                        uint16_t nb_pkts)
1578 {
1579         uint16_t i;
1580         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1581
1582         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1583
1584         for (i = 0; i < nb_pkts; i++)
1585                 rx_pkts[i] = stage[i];
1586
1587         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1588         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1589
1590         return nb_pkts;
1591 }
1592
1593 static inline int
1594 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1595 {
1596         volatile union ice_rx_flex_desc *rxdp;
1597         struct ice_rx_entry *rxep;
1598         struct rte_mbuf *mb;
1599         uint16_t alloc_idx, i;
1600         uint64_t dma_addr;
1601         int diag;
1602
1603         /* Allocate buffers in bulk */
1604         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1605                                (rxq->rx_free_thresh - 1));
1606         rxep = &rxq->sw_ring[alloc_idx];
1607         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1608                                     rxq->rx_free_thresh);
1609         if (unlikely(diag != 0)) {
1610                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1611                 return -ENOMEM;
1612         }
1613
1614         rxdp = &rxq->rx_ring[alloc_idx];
1615         for (i = 0; i < rxq->rx_free_thresh; i++) {
1616                 if (likely(i < (rxq->rx_free_thresh - 1)))
1617                         /* Prefetch next mbuf */
1618                         rte_prefetch0(rxep[i + 1].mbuf);
1619
1620                 mb = rxep[i].mbuf;
1621                 rte_mbuf_refcnt_set(mb, 1);
1622                 mb->next = NULL;
1623                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1624                 mb->nb_segs = 1;
1625                 mb->port = rxq->port_id;
1626                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1627                 rxdp[i].read.hdr_addr = 0;
1628                 rxdp[i].read.pkt_addr = dma_addr;
1629         }
1630
1631         /* Update rx tail regsiter */
1632         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1633
1634         rxq->rx_free_trigger =
1635                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1636         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1637                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1638
1639         return 0;
1640 }
1641
1642 static inline uint16_t
1643 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1644 {
1645         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1646         uint16_t nb_rx = 0;
1647         struct rte_eth_dev *dev;
1648
1649         if (!nb_pkts)
1650                 return 0;
1651
1652         if (rxq->rx_nb_avail)
1653                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1654
1655         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1656         rxq->rx_next_avail = 0;
1657         rxq->rx_nb_avail = nb_rx;
1658         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1659
1660         if (rxq->rx_tail > rxq->rx_free_trigger) {
1661                 if (ice_rx_alloc_bufs(rxq) != 0) {
1662                         uint16_t i, j;
1663
1664                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1665                         dev->data->rx_mbuf_alloc_failed +=
1666                                 rxq->rx_free_thresh;
1667                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1668                                    "port_id=%u, queue_id=%u",
1669                                    rxq->port_id, rxq->queue_id);
1670                         rxq->rx_nb_avail = 0;
1671                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1672                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1673                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1674
1675                         return 0;
1676                 }
1677         }
1678
1679         if (rxq->rx_tail >= rxq->nb_rx_desc)
1680                 rxq->rx_tail = 0;
1681
1682         if (rxq->rx_nb_avail)
1683                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1684
1685         return 0;
1686 }
1687
1688 static uint16_t
1689 ice_recv_pkts_bulk_alloc(void *rx_queue,
1690                          struct rte_mbuf **rx_pkts,
1691                          uint16_t nb_pkts)
1692 {
1693         uint16_t nb_rx = 0;
1694         uint16_t n;
1695         uint16_t count;
1696
1697         if (unlikely(nb_pkts == 0))
1698                 return nb_rx;
1699
1700         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1701                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1702
1703         while (nb_pkts) {
1704                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1705                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1706                 nb_rx = (uint16_t)(nb_rx + count);
1707                 nb_pkts = (uint16_t)(nb_pkts - count);
1708                 if (count < n)
1709                         break;
1710         }
1711
1712         return nb_rx;
1713 }
1714
1715 static uint16_t
1716 ice_recv_scattered_pkts(void *rx_queue,
1717                         struct rte_mbuf **rx_pkts,
1718                         uint16_t nb_pkts)
1719 {
1720         struct ice_rx_queue *rxq = rx_queue;
1721         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1722         volatile union ice_rx_flex_desc *rxdp;
1723         union ice_rx_flex_desc rxd;
1724         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1725         struct ice_rx_entry *rxe;
1726         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1727         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1728         struct rte_mbuf *nmb; /* new allocated mbuf */
1729         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1730         uint16_t rx_id = rxq->rx_tail;
1731         uint16_t nb_rx = 0;
1732         uint16_t nb_hold = 0;
1733         uint16_t rx_packet_len;
1734         uint16_t rx_stat_err0;
1735         uint64_t dma_addr;
1736         uint64_t pkt_flags;
1737         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1738         struct rte_eth_dev *dev;
1739
1740         while (nb_rx < nb_pkts) {
1741                 rxdp = &rx_ring[rx_id];
1742                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1743
1744                 /* Check the DD bit first */
1745                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1746                         break;
1747
1748                 /* allocate mbuf */
1749                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1750                 if (unlikely(!nmb)) {
1751                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1752                         dev->data->rx_mbuf_alloc_failed++;
1753                         break;
1754                 }
1755                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1756
1757                 nb_hold++;
1758                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1759                 rx_id++;
1760                 if (unlikely(rx_id == rxq->nb_rx_desc))
1761                         rx_id = 0;
1762
1763                 /* Prefetch next mbuf */
1764                 rte_prefetch0(sw_ring[rx_id].mbuf);
1765
1766                 /**
1767                  * When next RX descriptor is on a cache line boundary,
1768                  * prefetch the next 4 RX descriptors and next 8 pointers
1769                  * to mbufs.
1770                  */
1771                 if ((rx_id & 0x3) == 0) {
1772                         rte_prefetch0(&rx_ring[rx_id]);
1773                         rte_prefetch0(&sw_ring[rx_id]);
1774                 }
1775
1776                 rxm = rxe->mbuf;
1777                 rxe->mbuf = nmb;
1778                 dma_addr =
1779                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1780
1781                 /* Set data buffer address and data length of the mbuf */
1782                 rxdp->read.hdr_addr = 0;
1783                 rxdp->read.pkt_addr = dma_addr;
1784                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1785                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1786                 rxm->data_len = rx_packet_len;
1787                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1788
1789                 /**
1790                  * If this is the first buffer of the received packet, set the
1791                  * pointer to the first mbuf of the packet and initialize its
1792                  * context. Otherwise, update the total length and the number
1793                  * of segments of the current scattered packet, and update the
1794                  * pointer to the last mbuf of the current packet.
1795                  */
1796                 if (!first_seg) {
1797                         first_seg = rxm;
1798                         first_seg->nb_segs = 1;
1799                         first_seg->pkt_len = rx_packet_len;
1800                 } else {
1801                         first_seg->pkt_len =
1802                                 (uint16_t)(first_seg->pkt_len +
1803                                            rx_packet_len);
1804                         first_seg->nb_segs++;
1805                         last_seg->next = rxm;
1806                 }
1807
1808                 /**
1809                  * If this is not the last buffer of the received packet,
1810                  * update the pointer to the last mbuf of the current scattered
1811                  * packet and continue to parse the RX ring.
1812                  */
1813                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1814                         last_seg = rxm;
1815                         continue;
1816                 }
1817
1818                 /**
1819                  * This is the last buffer of the received packet. If the CRC
1820                  * is not stripped by the hardware:
1821                  *  - Subtract the CRC length from the total packet length.
1822                  *  - If the last buffer only contains the whole CRC or a part
1823                  *  of it, free the mbuf associated to the last buffer. If part
1824                  *  of the CRC is also contained in the previous mbuf, subtract
1825                  *  the length of that CRC part from the data length of the
1826                  *  previous mbuf.
1827                  */
1828                 rxm->next = NULL;
1829                 if (unlikely(rxq->crc_len > 0)) {
1830                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1831                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1832                                 rte_pktmbuf_free_seg(rxm);
1833                                 first_seg->nb_segs--;
1834                                 last_seg->data_len =
1835                                         (uint16_t)(last_seg->data_len -
1836                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1837                                 last_seg->next = NULL;
1838                         } else
1839                                 rxm->data_len = (uint16_t)(rx_packet_len -
1840                                                            RTE_ETHER_CRC_LEN);
1841                 }
1842
1843                 first_seg->port = rxq->port_id;
1844                 first_seg->ol_flags = 0;
1845                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1846                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1847                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1848                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1849                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1850                 first_seg->ol_flags |= pkt_flags;
1851                 /* Prefetch data of first segment, if configured to do so. */
1852                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1853                                           first_seg->data_off));
1854                 rx_pkts[nb_rx++] = first_seg;
1855                 first_seg = NULL;
1856         }
1857
1858         /* Record index of the next RX descriptor to probe. */
1859         rxq->rx_tail = rx_id;
1860         rxq->pkt_first_seg = first_seg;
1861         rxq->pkt_last_seg = last_seg;
1862
1863         /**
1864          * If the number of free RX descriptors is greater than the RX free
1865          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1866          * register. Update the RDT with the value of the last processed RX
1867          * descriptor minus 1, to guarantee that the RDT register is never
1868          * equal to the RDH register, which creates a "full" ring situtation
1869          * from the hardware point of view.
1870          */
1871         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1872         if (nb_hold > rxq->rx_free_thresh) {
1873                 rx_id = (uint16_t)(rx_id == 0 ?
1874                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1875                 /* write TAIL register */
1876                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1877                 nb_hold = 0;
1878         }
1879         rxq->nb_rx_hold = nb_hold;
1880
1881         /* return received packet in the burst */
1882         return nb_rx;
1883 }
1884
1885 const uint32_t *
1886 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1887 {
1888         struct ice_adapter *ad =
1889                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1890         const uint32_t *ptypes;
1891
1892         static const uint32_t ptypes_os[] = {
1893                 /* refers to ice_get_default_pkt_type() */
1894                 RTE_PTYPE_L2_ETHER,
1895                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1896                 RTE_PTYPE_L2_ETHER_LLDP,
1897                 RTE_PTYPE_L2_ETHER_ARP,
1898                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1899                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1900                 RTE_PTYPE_L4_FRAG,
1901                 RTE_PTYPE_L4_ICMP,
1902                 RTE_PTYPE_L4_NONFRAG,
1903                 RTE_PTYPE_L4_SCTP,
1904                 RTE_PTYPE_L4_TCP,
1905                 RTE_PTYPE_L4_UDP,
1906                 RTE_PTYPE_TUNNEL_GRENAT,
1907                 RTE_PTYPE_TUNNEL_IP,
1908                 RTE_PTYPE_INNER_L2_ETHER,
1909                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1910                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1911                 RTE_PTYPE_INNER_L4_FRAG,
1912                 RTE_PTYPE_INNER_L4_ICMP,
1913                 RTE_PTYPE_INNER_L4_NONFRAG,
1914                 RTE_PTYPE_INNER_L4_SCTP,
1915                 RTE_PTYPE_INNER_L4_TCP,
1916                 RTE_PTYPE_INNER_L4_UDP,
1917                 RTE_PTYPE_UNKNOWN
1918         };
1919
1920         static const uint32_t ptypes_comms[] = {
1921                 /* refers to ice_get_default_pkt_type() */
1922                 RTE_PTYPE_L2_ETHER,
1923                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1924                 RTE_PTYPE_L2_ETHER_LLDP,
1925                 RTE_PTYPE_L2_ETHER_ARP,
1926                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1927                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1928                 RTE_PTYPE_L4_FRAG,
1929                 RTE_PTYPE_L4_ICMP,
1930                 RTE_PTYPE_L4_NONFRAG,
1931                 RTE_PTYPE_L4_SCTP,
1932                 RTE_PTYPE_L4_TCP,
1933                 RTE_PTYPE_L4_UDP,
1934                 RTE_PTYPE_TUNNEL_GRENAT,
1935                 RTE_PTYPE_TUNNEL_IP,
1936                 RTE_PTYPE_INNER_L2_ETHER,
1937                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1938                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1939                 RTE_PTYPE_INNER_L4_FRAG,
1940                 RTE_PTYPE_INNER_L4_ICMP,
1941                 RTE_PTYPE_INNER_L4_NONFRAG,
1942                 RTE_PTYPE_INNER_L4_SCTP,
1943                 RTE_PTYPE_INNER_L4_TCP,
1944                 RTE_PTYPE_INNER_L4_UDP,
1945                 RTE_PTYPE_TUNNEL_GTPC,
1946                 RTE_PTYPE_TUNNEL_GTPU,
1947                 RTE_PTYPE_L2_ETHER_PPPOE,
1948                 RTE_PTYPE_UNKNOWN
1949         };
1950
1951         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1952                 ptypes = ptypes_comms;
1953         else
1954                 ptypes = ptypes_os;
1955
1956         if (dev->rx_pkt_burst == ice_recv_pkts ||
1957             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1958             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1959                 return ptypes;
1960
1961 #ifdef RTE_ARCH_X86
1962         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1963             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1964 #ifdef CC_AVX512_SUPPORT
1965             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
1966             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
1967 #endif
1968             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1969             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1970                 return ptypes;
1971 #endif
1972
1973         return NULL;
1974 }
1975
1976 int
1977 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1978 {
1979         volatile union ice_rx_flex_desc *rxdp;
1980         struct ice_rx_queue *rxq = rx_queue;
1981         uint32_t desc;
1982
1983         if (unlikely(offset >= rxq->nb_rx_desc))
1984                 return -EINVAL;
1985
1986         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1987                 return RTE_ETH_RX_DESC_UNAVAIL;
1988
1989         desc = rxq->rx_tail + offset;
1990         if (desc >= rxq->nb_rx_desc)
1991                 desc -= rxq->nb_rx_desc;
1992
1993         rxdp = &rxq->rx_ring[desc];
1994         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1995             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1996                 return RTE_ETH_RX_DESC_DONE;
1997
1998         return RTE_ETH_RX_DESC_AVAIL;
1999 }
2000
2001 int
2002 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2003 {
2004         struct ice_tx_queue *txq = tx_queue;
2005         volatile uint64_t *status;
2006         uint64_t mask, expect;
2007         uint32_t desc;
2008
2009         if (unlikely(offset >= txq->nb_tx_desc))
2010                 return -EINVAL;
2011
2012         desc = txq->tx_tail + offset;
2013         /* go to next desc that has the RS bit */
2014         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2015                 txq->tx_rs_thresh;
2016         if (desc >= txq->nb_tx_desc) {
2017                 desc -= txq->nb_tx_desc;
2018                 if (desc >= txq->nb_tx_desc)
2019                         desc -= txq->nb_tx_desc;
2020         }
2021
2022         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2023         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2024         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2025                                   ICE_TXD_QW1_DTYPE_S);
2026         if ((*status & mask) == expect)
2027                 return RTE_ETH_TX_DESC_DONE;
2028
2029         return RTE_ETH_TX_DESC_FULL;
2030 }
2031
2032 void
2033 ice_free_queues(struct rte_eth_dev *dev)
2034 {
2035         uint16_t i;
2036
2037         PMD_INIT_FUNC_TRACE();
2038
2039         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2040                 if (!dev->data->rx_queues[i])
2041                         continue;
2042                 ice_rx_queue_release(dev->data->rx_queues[i]);
2043                 dev->data->rx_queues[i] = NULL;
2044                 rte_eth_dma_zone_free(dev, "rx_ring", i);
2045         }
2046         dev->data->nb_rx_queues = 0;
2047
2048         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2049                 if (!dev->data->tx_queues[i])
2050                         continue;
2051                 ice_tx_queue_release(dev->data->tx_queues[i]);
2052                 dev->data->tx_queues[i] = NULL;
2053                 rte_eth_dma_zone_free(dev, "tx_ring", i);
2054         }
2055         dev->data->nb_tx_queues = 0;
2056 }
2057
2058 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2059 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2060
2061 int
2062 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2063 {
2064         struct ice_tx_queue *txq;
2065         const struct rte_memzone *tz = NULL;
2066         uint32_t ring_size;
2067         struct rte_eth_dev *dev;
2068
2069         if (!pf) {
2070                 PMD_DRV_LOG(ERR, "PF is not available");
2071                 return -EINVAL;
2072         }
2073
2074         dev = pf->adapter->eth_dev;
2075
2076         /* Allocate the TX queue data structure. */
2077         txq = rte_zmalloc_socket("ice fdir tx queue",
2078                                  sizeof(struct ice_tx_queue),
2079                                  RTE_CACHE_LINE_SIZE,
2080                                  SOCKET_ID_ANY);
2081         if (!txq) {
2082                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2083                             "tx queue structure.");
2084                 return -ENOMEM;
2085         }
2086
2087         /* Allocate TX hardware ring descriptors. */
2088         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2089         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2090
2091         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2092                                       ICE_FDIR_QUEUE_ID, ring_size,
2093                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2094         if (!tz) {
2095                 ice_tx_queue_release(txq);
2096                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2097                 return -ENOMEM;
2098         }
2099
2100         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2101         txq->queue_id = ICE_FDIR_QUEUE_ID;
2102         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2103         txq->vsi = pf->fdir.fdir_vsi;
2104
2105         txq->tx_ring_dma = tz->iova;
2106         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2107         /*
2108          * don't need to allocate software ring and reset for the fdir
2109          * program queue just set the queue has been configured.
2110          */
2111         txq->q_set = true;
2112         pf->fdir.txq = txq;
2113
2114         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2115
2116         return ICE_SUCCESS;
2117 }
2118
2119 int
2120 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2121 {
2122         struct ice_rx_queue *rxq;
2123         const struct rte_memzone *rz = NULL;
2124         uint32_t ring_size;
2125         struct rte_eth_dev *dev;
2126
2127         if (!pf) {
2128                 PMD_DRV_LOG(ERR, "PF is not available");
2129                 return -EINVAL;
2130         }
2131
2132         dev = pf->adapter->eth_dev;
2133
2134         /* Allocate the RX queue data structure. */
2135         rxq = rte_zmalloc_socket("ice fdir rx queue",
2136                                  sizeof(struct ice_rx_queue),
2137                                  RTE_CACHE_LINE_SIZE,
2138                                  SOCKET_ID_ANY);
2139         if (!rxq) {
2140                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2141                             "rx queue structure.");
2142                 return -ENOMEM;
2143         }
2144
2145         /* Allocate RX hardware ring descriptors. */
2146         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2147         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2148
2149         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2150                                       ICE_FDIR_QUEUE_ID, ring_size,
2151                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2152         if (!rz) {
2153                 ice_rx_queue_release(rxq);
2154                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2155                 return -ENOMEM;
2156         }
2157
2158         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2159         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2160         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2161         rxq->vsi = pf->fdir.fdir_vsi;
2162
2163         rxq->rx_ring_dma = rz->iova;
2164         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2165                sizeof(union ice_32byte_rx_desc));
2166         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2167
2168         /*
2169          * Don't need to allocate software ring and reset for the fdir
2170          * rx queue, just set the queue has been configured.
2171          */
2172         rxq->q_set = true;
2173         pf->fdir.rxq = rxq;
2174
2175         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2176
2177         return ICE_SUCCESS;
2178 }
2179
2180 uint16_t
2181 ice_recv_pkts(void *rx_queue,
2182               struct rte_mbuf **rx_pkts,
2183               uint16_t nb_pkts)
2184 {
2185         struct ice_rx_queue *rxq = rx_queue;
2186         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2187         volatile union ice_rx_flex_desc *rxdp;
2188         union ice_rx_flex_desc rxd;
2189         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2190         struct ice_rx_entry *rxe;
2191         struct rte_mbuf *nmb; /* new allocated mbuf */
2192         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2193         uint16_t rx_id = rxq->rx_tail;
2194         uint16_t nb_rx = 0;
2195         uint16_t nb_hold = 0;
2196         uint16_t rx_packet_len;
2197         uint16_t rx_stat_err0;
2198         uint64_t dma_addr;
2199         uint64_t pkt_flags;
2200         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2201         struct rte_eth_dev *dev;
2202
2203         while (nb_rx < nb_pkts) {
2204                 rxdp = &rx_ring[rx_id];
2205                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2206
2207                 /* Check the DD bit first */
2208                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2209                         break;
2210
2211                 /* allocate mbuf */
2212                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2213                 if (unlikely(!nmb)) {
2214                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2215                         dev->data->rx_mbuf_alloc_failed++;
2216                         break;
2217                 }
2218                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2219
2220                 nb_hold++;
2221                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2222                 rx_id++;
2223                 if (unlikely(rx_id == rxq->nb_rx_desc))
2224                         rx_id = 0;
2225                 rxm = rxe->mbuf;
2226                 rxe->mbuf = nmb;
2227                 dma_addr =
2228                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2229
2230                 /**
2231                  * fill the read format of descriptor with physic address in
2232                  * new allocated mbuf: nmb
2233                  */
2234                 rxdp->read.hdr_addr = 0;
2235                 rxdp->read.pkt_addr = dma_addr;
2236
2237                 /* calculate rx_packet_len of the received pkt */
2238                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2239                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2240
2241                 /* fill old mbuf with received descriptor: rxd */
2242                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2243                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2244                 rxm->nb_segs = 1;
2245                 rxm->next = NULL;
2246                 rxm->pkt_len = rx_packet_len;
2247                 rxm->data_len = rx_packet_len;
2248                 rxm->port = rxq->port_id;
2249                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2250                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2251                 ice_rxd_to_vlan_tci(rxm, &rxd);
2252                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2253                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2254                 rxm->ol_flags |= pkt_flags;
2255                 /* copy old mbuf to rx_pkts */
2256                 rx_pkts[nb_rx++] = rxm;
2257         }
2258         rxq->rx_tail = rx_id;
2259         /**
2260          * If the number of free RX descriptors is greater than the RX free
2261          * threshold of the queue, advance the receive tail register of queue.
2262          * Update that register with the value of the last processed RX
2263          * descriptor minus 1.
2264          */
2265         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2266         if (nb_hold > rxq->rx_free_thresh) {
2267                 rx_id = (uint16_t)(rx_id == 0 ?
2268                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2269                 /* write TAIL register */
2270                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2271                 nb_hold = 0;
2272         }
2273         rxq->nb_rx_hold = nb_hold;
2274
2275         /* return received packet in the burst */
2276         return nb_rx;
2277 }
2278
2279 static inline void
2280 ice_parse_tunneling_params(uint64_t ol_flags,
2281                             union ice_tx_offload tx_offload,
2282                             uint32_t *cd_tunneling)
2283 {
2284         /* EIPT: External (outer) IP header type */
2285         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2286                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2287         else if (ol_flags & PKT_TX_OUTER_IPV4)
2288                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2289         else if (ol_flags & PKT_TX_OUTER_IPV6)
2290                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2291
2292         /* EIPLEN: External (outer) IP header length, in DWords */
2293         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2294                 ICE_TXD_CTX_QW0_EIPLEN_S;
2295
2296         /* L4TUNT: L4 Tunneling Type */
2297         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2298         case PKT_TX_TUNNEL_IPIP:
2299                 /* for non UDP / GRE tunneling, set to 00b */
2300                 break;
2301         case PKT_TX_TUNNEL_VXLAN:
2302         case PKT_TX_TUNNEL_GTP:
2303         case PKT_TX_TUNNEL_GENEVE:
2304                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2305                 break;
2306         case PKT_TX_TUNNEL_GRE:
2307                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2308                 break;
2309         default:
2310                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2311                 return;
2312         }
2313
2314         /* L4TUNLEN: L4 Tunneling Length, in Words
2315          *
2316          * We depend on app to set rte_mbuf.l2_len correctly.
2317          * For IP in GRE it should be set to the length of the GRE
2318          * header;
2319          * For MAC in GRE or MAC in UDP it should be set to the length
2320          * of the GRE or UDP headers plus the inner MAC up to including
2321          * its last Ethertype.
2322          * If MPLS labels exists, it should include them as well.
2323          */
2324         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2325                 ICE_TXD_CTX_QW0_NATLEN_S;
2326
2327         /**
2328          * Calculate the tunneling UDP checksum.
2329          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2330          */
2331         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2332             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2333                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2334 }
2335
2336 static inline void
2337 ice_txd_enable_checksum(uint64_t ol_flags,
2338                         uint32_t *td_cmd,
2339                         uint32_t *td_offset,
2340                         union ice_tx_offload tx_offload)
2341 {
2342         /* Set MACLEN */
2343         if (ol_flags & PKT_TX_TUNNEL_MASK)
2344                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2345                         << ICE_TX_DESC_LEN_MACLEN_S;
2346         else
2347                 *td_offset |= (tx_offload.l2_len >> 1)
2348                         << ICE_TX_DESC_LEN_MACLEN_S;
2349
2350         /* Enable L3 checksum offloads */
2351         if (ol_flags & PKT_TX_IP_CKSUM) {
2352                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2353                 *td_offset |= (tx_offload.l3_len >> 2) <<
2354                               ICE_TX_DESC_LEN_IPLEN_S;
2355         } else if (ol_flags & PKT_TX_IPV4) {
2356                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2357                 *td_offset |= (tx_offload.l3_len >> 2) <<
2358                               ICE_TX_DESC_LEN_IPLEN_S;
2359         } else if (ol_flags & PKT_TX_IPV6) {
2360                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2361                 *td_offset |= (tx_offload.l3_len >> 2) <<
2362                               ICE_TX_DESC_LEN_IPLEN_S;
2363         }
2364
2365         if (ol_flags & PKT_TX_TCP_SEG) {
2366                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2367                 *td_offset |= (tx_offload.l4_len >> 2) <<
2368                               ICE_TX_DESC_LEN_L4_LEN_S;
2369                 return;
2370         }
2371
2372         /* Enable L4 checksum offloads */
2373         switch (ol_flags & PKT_TX_L4_MASK) {
2374         case PKT_TX_TCP_CKSUM:
2375                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2376                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2377                               ICE_TX_DESC_LEN_L4_LEN_S;
2378                 break;
2379         case PKT_TX_SCTP_CKSUM:
2380                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2381                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2382                               ICE_TX_DESC_LEN_L4_LEN_S;
2383                 break;
2384         case PKT_TX_UDP_CKSUM:
2385                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2386                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2387                               ICE_TX_DESC_LEN_L4_LEN_S;
2388                 break;
2389         default:
2390                 break;
2391         }
2392 }
2393
2394 static inline int
2395 ice_xmit_cleanup(struct ice_tx_queue *txq)
2396 {
2397         struct ice_tx_entry *sw_ring = txq->sw_ring;
2398         volatile struct ice_tx_desc *txd = txq->tx_ring;
2399         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2400         uint16_t nb_tx_desc = txq->nb_tx_desc;
2401         uint16_t desc_to_clean_to;
2402         uint16_t nb_tx_to_clean;
2403
2404         /* Determine the last descriptor needing to be cleaned */
2405         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2406         if (desc_to_clean_to >= nb_tx_desc)
2407                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2408
2409         /* Check to make sure the last descriptor to clean is done */
2410         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2411         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2412             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2413                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2414                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2415                                 desc_to_clean_to,
2416                                 txq->port_id, txq->queue_id,
2417                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2418                 /* Failed to clean any descriptors */
2419                 return -1;
2420         }
2421
2422         /* Figure out how many descriptors will be cleaned */
2423         if (last_desc_cleaned > desc_to_clean_to)
2424                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2425                                             desc_to_clean_to);
2426         else
2427                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2428                                             last_desc_cleaned);
2429
2430         /* The last descriptor to clean is done, so that means all the
2431          * descriptors from the last descriptor that was cleaned
2432          * up to the last descriptor with the RS bit set
2433          * are done. Only reset the threshold descriptor.
2434          */
2435         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2436
2437         /* Update the txq to reflect the last descriptor that was cleaned */
2438         txq->last_desc_cleaned = desc_to_clean_to;
2439         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2440
2441         return 0;
2442 }
2443
2444 /* Construct the tx flags */
2445 static inline uint64_t
2446 ice_build_ctob(uint32_t td_cmd,
2447                uint32_t td_offset,
2448                uint16_t size,
2449                uint32_t td_tag)
2450 {
2451         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2452                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2453                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2454                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2455                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2456 }
2457
2458 /* Check if the context descriptor is needed for TX offloading */
2459 static inline uint16_t
2460 ice_calc_context_desc(uint64_t flags)
2461 {
2462         static uint64_t mask = PKT_TX_TCP_SEG |
2463                 PKT_TX_QINQ |
2464                 PKT_TX_OUTER_IP_CKSUM |
2465                 PKT_TX_TUNNEL_MASK;
2466
2467         return (flags & mask) ? 1 : 0;
2468 }
2469
2470 /* set ice TSO context descriptor */
2471 static inline uint64_t
2472 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2473 {
2474         uint64_t ctx_desc = 0;
2475         uint32_t cd_cmd, hdr_len, cd_tso_len;
2476
2477         if (!tx_offload.l4_len) {
2478                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2479                 return ctx_desc;
2480         }
2481
2482         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2483         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2484                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2485
2486         cd_cmd = ICE_TX_CTX_DESC_TSO;
2487         cd_tso_len = mbuf->pkt_len - hdr_len;
2488         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2489                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2490                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2491
2492         return ctx_desc;
2493 }
2494
2495 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2496 #define ICE_MAX_DATA_PER_TXD \
2497         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2498 /* Calculate the number of TX descriptors needed for each pkt */
2499 static inline uint16_t
2500 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2501 {
2502         struct rte_mbuf *txd = tx_pkt;
2503         uint16_t count = 0;
2504
2505         while (txd != NULL) {
2506                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2507                 txd = txd->next;
2508         }
2509
2510         return count;
2511 }
2512
2513 uint16_t
2514 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2515 {
2516         struct ice_tx_queue *txq;
2517         volatile struct ice_tx_desc *tx_ring;
2518         volatile struct ice_tx_desc *txd;
2519         struct ice_tx_entry *sw_ring;
2520         struct ice_tx_entry *txe, *txn;
2521         struct rte_mbuf *tx_pkt;
2522         struct rte_mbuf *m_seg;
2523         uint32_t cd_tunneling_params;
2524         uint16_t tx_id;
2525         uint16_t nb_tx;
2526         uint16_t nb_used;
2527         uint16_t nb_ctx;
2528         uint32_t td_cmd = 0;
2529         uint32_t td_offset = 0;
2530         uint32_t td_tag = 0;
2531         uint16_t tx_last;
2532         uint16_t slen;
2533         uint64_t buf_dma_addr;
2534         uint64_t ol_flags;
2535         union ice_tx_offload tx_offload = {0};
2536
2537         txq = tx_queue;
2538         sw_ring = txq->sw_ring;
2539         tx_ring = txq->tx_ring;
2540         tx_id = txq->tx_tail;
2541         txe = &sw_ring[tx_id];
2542
2543         /* Check if the descriptor ring needs to be cleaned. */
2544         if (txq->nb_tx_free < txq->tx_free_thresh)
2545                 (void)ice_xmit_cleanup(txq);
2546
2547         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2548                 tx_pkt = *tx_pkts++;
2549
2550                 td_cmd = 0;
2551                 td_tag = 0;
2552                 td_offset = 0;
2553                 ol_flags = tx_pkt->ol_flags;
2554                 tx_offload.l2_len = tx_pkt->l2_len;
2555                 tx_offload.l3_len = tx_pkt->l3_len;
2556                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2557                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2558                 tx_offload.l4_len = tx_pkt->l4_len;
2559                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2560                 /* Calculate the number of context descriptors needed. */
2561                 nb_ctx = ice_calc_context_desc(ol_flags);
2562
2563                 /* The number of descriptors that must be allocated for
2564                  * a packet equals to the number of the segments of that
2565                  * packet plus the number of context descriptor if needed.
2566                  * Recalculate the needed tx descs when TSO enabled in case
2567                  * the mbuf data size exceeds max data size that hw allows
2568                  * per tx desc.
2569                  */
2570                 if (ol_flags & PKT_TX_TCP_SEG)
2571                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2572                                              nb_ctx);
2573                 else
2574                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2575                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2576
2577                 /* Circular ring */
2578                 if (tx_last >= txq->nb_tx_desc)
2579                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2580
2581                 if (nb_used > txq->nb_tx_free) {
2582                         if (ice_xmit_cleanup(txq) != 0) {
2583                                 if (nb_tx == 0)
2584                                         return 0;
2585                                 goto end_of_tx;
2586                         }
2587                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2588                                 while (nb_used > txq->nb_tx_free) {
2589                                         if (ice_xmit_cleanup(txq) != 0) {
2590                                                 if (nb_tx == 0)
2591                                                         return 0;
2592                                                 goto end_of_tx;
2593                                         }
2594                                 }
2595                         }
2596                 }
2597
2598                 /* Descriptor based VLAN insertion */
2599                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2600                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2601                         td_tag = tx_pkt->vlan_tci;
2602                 }
2603
2604                 /* Fill in tunneling parameters if necessary */
2605                 cd_tunneling_params = 0;
2606                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2607                         ice_parse_tunneling_params(ol_flags, tx_offload,
2608                                                    &cd_tunneling_params);
2609
2610                 /* Enable checksum offloading */
2611                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2612                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2613                                                 &td_offset, tx_offload);
2614
2615                 if (nb_ctx) {
2616                         /* Setup TX context descriptor if required */
2617                         volatile struct ice_tx_ctx_desc *ctx_txd =
2618                                 (volatile struct ice_tx_ctx_desc *)
2619                                         &tx_ring[tx_id];
2620                         uint16_t cd_l2tag2 = 0;
2621                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2622
2623                         txn = &sw_ring[txe->next_id];
2624                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2625                         if (txe->mbuf) {
2626                                 rte_pktmbuf_free_seg(txe->mbuf);
2627                                 txe->mbuf = NULL;
2628                         }
2629
2630                         if (ol_flags & PKT_TX_TCP_SEG)
2631                                 cd_type_cmd_tso_mss |=
2632                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2633
2634                         ctx_txd->tunneling_params =
2635                                 rte_cpu_to_le_32(cd_tunneling_params);
2636
2637                         /* TX context descriptor based double VLAN insert */
2638                         if (ol_flags & PKT_TX_QINQ) {
2639                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2640                                 cd_type_cmd_tso_mss |=
2641                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2642                                          ICE_TXD_CTX_QW1_CMD_S);
2643                         }
2644                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2645                         ctx_txd->qw1 =
2646                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2647
2648                         txe->last_id = tx_last;
2649                         tx_id = txe->next_id;
2650                         txe = txn;
2651                 }
2652                 m_seg = tx_pkt;
2653
2654                 do {
2655                         txd = &tx_ring[tx_id];
2656                         txn = &sw_ring[txe->next_id];
2657
2658                         if (txe->mbuf)
2659                                 rte_pktmbuf_free_seg(txe->mbuf);
2660                         txe->mbuf = m_seg;
2661
2662                         /* Setup TX Descriptor */
2663                         slen = m_seg->data_len;
2664                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2665
2666                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2667                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2668                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2669                                 txd->cmd_type_offset_bsz =
2670                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2671                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2672                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2673                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2674                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2675                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2676
2677                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2678                                 slen -= ICE_MAX_DATA_PER_TXD;
2679
2680                                 txe->last_id = tx_last;
2681                                 tx_id = txe->next_id;
2682                                 txe = txn;
2683                                 txd = &tx_ring[tx_id];
2684                                 txn = &sw_ring[txe->next_id];
2685                         }
2686
2687                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2688                         txd->cmd_type_offset_bsz =
2689                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2690                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2691                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2692                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2693                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2694
2695                         txe->last_id = tx_last;
2696                         tx_id = txe->next_id;
2697                         txe = txn;
2698                         m_seg = m_seg->next;
2699                 } while (m_seg);
2700
2701                 /* fill the last descriptor with End of Packet (EOP) bit */
2702                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2703                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2704                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2705
2706                 /* set RS bit on the last descriptor of one packet */
2707                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2708                         PMD_TX_FREE_LOG(DEBUG,
2709                                         "Setting RS bit on TXD id="
2710                                         "%4u (port=%d queue=%d)",
2711                                         tx_last, txq->port_id, txq->queue_id);
2712
2713                         td_cmd |= ICE_TX_DESC_CMD_RS;
2714
2715                         /* Update txq RS bit counters */
2716                         txq->nb_tx_used = 0;
2717                 }
2718                 txd->cmd_type_offset_bsz |=
2719                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2720                                          ICE_TXD_QW1_CMD_S);
2721         }
2722 end_of_tx:
2723         /* update Tail register */
2724         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2725         txq->tx_tail = tx_id;
2726
2727         return nb_tx;
2728 }
2729
2730 static __rte_always_inline int
2731 ice_tx_free_bufs(struct ice_tx_queue *txq)
2732 {
2733         struct ice_tx_entry *txep;
2734         uint16_t i;
2735
2736         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2737              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2738             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2739                 return 0;
2740
2741         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2742
2743         for (i = 0; i < txq->tx_rs_thresh; i++)
2744                 rte_prefetch0((txep + i)->mbuf);
2745
2746         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2747                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2748                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2749                         txep->mbuf = NULL;
2750                 }
2751         } else {
2752                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2753                         rte_pktmbuf_free_seg(txep->mbuf);
2754                         txep->mbuf = NULL;
2755                 }
2756         }
2757
2758         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2759         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2760         if (txq->tx_next_dd >= txq->nb_tx_desc)
2761                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2762
2763         return txq->tx_rs_thresh;
2764 }
2765
2766 static int
2767 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2768                         uint32_t free_cnt)
2769 {
2770         struct ice_tx_entry *swr_ring = txq->sw_ring;
2771         uint16_t i, tx_last, tx_id;
2772         uint16_t nb_tx_free_last;
2773         uint16_t nb_tx_to_clean;
2774         uint32_t pkt_cnt;
2775
2776         /* Start free mbuf from the next of tx_tail */
2777         tx_last = txq->tx_tail;
2778         tx_id  = swr_ring[tx_last].next_id;
2779
2780         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2781                 return 0;
2782
2783         nb_tx_to_clean = txq->nb_tx_free;
2784         nb_tx_free_last = txq->nb_tx_free;
2785         if (!free_cnt)
2786                 free_cnt = txq->nb_tx_desc;
2787
2788         /* Loop through swr_ring to count the amount of
2789          * freeable mubfs and packets.
2790          */
2791         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2792                 for (i = 0; i < nb_tx_to_clean &&
2793                         pkt_cnt < free_cnt &&
2794                         tx_id != tx_last; i++) {
2795                         if (swr_ring[tx_id].mbuf != NULL) {
2796                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2797                                 swr_ring[tx_id].mbuf = NULL;
2798
2799                                 /*
2800                                  * last segment in the packet,
2801                                  * increment packet count
2802                                  */
2803                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2804                         }
2805
2806                         tx_id = swr_ring[tx_id].next_id;
2807                 }
2808
2809                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2810                         txq->nb_tx_free || tx_id == tx_last)
2811                         break;
2812
2813                 if (pkt_cnt < free_cnt) {
2814                         if (ice_xmit_cleanup(txq))
2815                                 break;
2816
2817                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2818                         nb_tx_free_last = txq->nb_tx_free;
2819                 }
2820         }
2821
2822         return (int)pkt_cnt;
2823 }
2824
2825 #ifdef RTE_ARCH_X86
2826 static int
2827 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2828                         uint32_t free_cnt __rte_unused)
2829 {
2830         return -ENOTSUP;
2831 }
2832 #endif
2833
2834 static int
2835 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2836                         uint32_t free_cnt)
2837 {
2838         int i, n, cnt;
2839
2840         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2841                 free_cnt = txq->nb_tx_desc;
2842
2843         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2844
2845         for (i = 0; i < cnt; i += n) {
2846                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2847                         break;
2848
2849                 n = ice_tx_free_bufs(txq);
2850
2851                 if (n == 0)
2852                         break;
2853         }
2854
2855         return i;
2856 }
2857
2858 int
2859 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2860 {
2861         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2862         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2863         struct ice_adapter *ad =
2864                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2865
2866 #ifdef RTE_ARCH_X86
2867         if (ad->tx_vec_allowed)
2868                 return ice_tx_done_cleanup_vec(q, free_cnt);
2869 #endif
2870         if (ad->tx_simple_allowed)
2871                 return ice_tx_done_cleanup_simple(q, free_cnt);
2872         else
2873                 return ice_tx_done_cleanup_full(q, free_cnt);
2874 }
2875
2876 /* Populate 4 descriptors with data from 4 mbufs */
2877 static inline void
2878 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2879 {
2880         uint64_t dma_addr;
2881         uint32_t i;
2882
2883         for (i = 0; i < 4; i++, txdp++, pkts++) {
2884                 dma_addr = rte_mbuf_data_iova(*pkts);
2885                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2886                 txdp->cmd_type_offset_bsz =
2887                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2888                                        (*pkts)->data_len, 0);
2889         }
2890 }
2891
2892 /* Populate 1 descriptor with data from 1 mbuf */
2893 static inline void
2894 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2895 {
2896         uint64_t dma_addr;
2897
2898         dma_addr = rte_mbuf_data_iova(*pkts);
2899         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2900         txdp->cmd_type_offset_bsz =
2901                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2902                                (*pkts)->data_len, 0);
2903 }
2904
2905 static inline void
2906 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2907                     uint16_t nb_pkts)
2908 {
2909         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2910         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2911         const int N_PER_LOOP = 4;
2912         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2913         int mainpart, leftover;
2914         int i, j;
2915
2916         /**
2917          * Process most of the packets in chunks of N pkts.  Any
2918          * leftover packets will get processed one at a time.
2919          */
2920         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2921         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2922         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2923                 /* Copy N mbuf pointers to the S/W ring */
2924                 for (j = 0; j < N_PER_LOOP; ++j)
2925                         (txep + i + j)->mbuf = *(pkts + i + j);
2926                 tx4(txdp + i, pkts + i);
2927         }
2928
2929         if (unlikely(leftover > 0)) {
2930                 for (i = 0; i < leftover; ++i) {
2931                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2932                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2933                 }
2934         }
2935 }
2936
2937 static inline uint16_t
2938 tx_xmit_pkts(struct ice_tx_queue *txq,
2939              struct rte_mbuf **tx_pkts,
2940              uint16_t nb_pkts)
2941 {
2942         volatile struct ice_tx_desc *txr = txq->tx_ring;
2943         uint16_t n = 0;
2944
2945         /**
2946          * Begin scanning the H/W ring for done descriptors when the number
2947          * of available descriptors drops below tx_free_thresh. For each done
2948          * descriptor, free the associated buffer.
2949          */
2950         if (txq->nb_tx_free < txq->tx_free_thresh)
2951                 ice_tx_free_bufs(txq);
2952
2953         /* Use available descriptor only */
2954         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2955         if (unlikely(!nb_pkts))
2956                 return 0;
2957
2958         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2959         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2960                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2961                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2962                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2963                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2964                                          ICE_TXD_QW1_CMD_S);
2965                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2966                 txq->tx_tail = 0;
2967         }
2968
2969         /* Fill hardware descriptor ring with mbuf data */
2970         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2971         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2972
2973         /* Determin if RS bit needs to be set */
2974         if (txq->tx_tail > txq->tx_next_rs) {
2975                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2976                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2977                                          ICE_TXD_QW1_CMD_S);
2978                 txq->tx_next_rs =
2979                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2980                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2981                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2982         }
2983
2984         if (txq->tx_tail >= txq->nb_tx_desc)
2985                 txq->tx_tail = 0;
2986
2987         /* Update the tx tail register */
2988         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
2989
2990         return nb_pkts;
2991 }
2992
2993 static uint16_t
2994 ice_xmit_pkts_simple(void *tx_queue,
2995                      struct rte_mbuf **tx_pkts,
2996                      uint16_t nb_pkts)
2997 {
2998         uint16_t nb_tx = 0;
2999
3000         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3001                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3002                                     tx_pkts, nb_pkts);
3003
3004         while (nb_pkts) {
3005                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3006                                                       ICE_TX_MAX_BURST);
3007
3008                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3009                                    &tx_pkts[nb_tx], num);
3010                 nb_tx = (uint16_t)(nb_tx + ret);
3011                 nb_pkts = (uint16_t)(nb_pkts - ret);
3012                 if (ret < num)
3013                         break;
3014         }
3015
3016         return nb_tx;
3017 }
3018
3019 void __rte_cold
3020 ice_set_rx_function(struct rte_eth_dev *dev)
3021 {
3022         PMD_INIT_FUNC_TRACE();
3023         struct ice_adapter *ad =
3024                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3025 #ifdef RTE_ARCH_X86
3026         struct ice_rx_queue *rxq;
3027         int i;
3028         bool use_avx512 = false;
3029         bool use_avx2 = false;
3030
3031         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3032                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
3033                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3034                         ad->rx_vec_allowed = true;
3035                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3036                                 rxq = dev->data->rx_queues[i];
3037                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3038                                         ad->rx_vec_allowed = false;
3039                                         break;
3040                                 }
3041                         }
3042
3043                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3044                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3045                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3046 #ifdef CC_AVX512_SUPPORT
3047                                 use_avx512 = true;
3048 #else
3049                         PMD_DRV_LOG(NOTICE,
3050                                 "AVX512 is not supported in build env");
3051 #endif
3052                         if (!use_avx512 &&
3053                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3054                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3055                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3056                                 use_avx2 = true;
3057
3058                 } else {
3059                         ad->rx_vec_allowed = false;
3060                 }
3061         }
3062
3063         if (ad->rx_vec_allowed) {
3064                 if (dev->data->scattered_rx) {
3065                         if (use_avx512) {
3066 #ifdef CC_AVX512_SUPPORT
3067                                 PMD_DRV_LOG(NOTICE,
3068                                         "Using AVX512 Vector Scattered Rx (port %d).",
3069                                         dev->data->port_id);
3070                                 dev->rx_pkt_burst =
3071                                         ice_recv_scattered_pkts_vec_avx512;
3072 #endif
3073                         } else {
3074                                 PMD_DRV_LOG(DEBUG,
3075                                         "Using %sVector Scattered Rx (port %d).",
3076                                         use_avx2 ? "avx2 " : "",
3077                                         dev->data->port_id);
3078                                 dev->rx_pkt_burst = use_avx2 ?
3079                                         ice_recv_scattered_pkts_vec_avx2 :
3080                                         ice_recv_scattered_pkts_vec;
3081                         }
3082                 } else {
3083                         if (use_avx512) {
3084 #ifdef CC_AVX512_SUPPORT
3085                                 PMD_DRV_LOG(NOTICE,
3086                                         "Using AVX512 Vector Rx (port %d).",
3087                                         dev->data->port_id);
3088                                 dev->rx_pkt_burst =
3089                                         ice_recv_pkts_vec_avx512;
3090 #endif
3091                         } else {
3092                                 PMD_DRV_LOG(DEBUG,
3093                                         "Using %sVector Rx (port %d).",
3094                                         use_avx2 ? "avx2 " : "",
3095                                         dev->data->port_id);
3096                                 dev->rx_pkt_burst = use_avx2 ?
3097                                         ice_recv_pkts_vec_avx2 :
3098                                         ice_recv_pkts_vec;
3099                         }
3100                 }
3101                 return;
3102         }
3103
3104 #endif
3105
3106         if (dev->data->scattered_rx) {
3107                 /* Set the non-LRO scattered function */
3108                 PMD_INIT_LOG(DEBUG,
3109                              "Using a Scattered function on port %d.",
3110                              dev->data->port_id);
3111                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3112         } else if (ad->rx_bulk_alloc_allowed) {
3113                 PMD_INIT_LOG(DEBUG,
3114                              "Rx Burst Bulk Alloc Preconditions are "
3115                              "satisfied. Rx Burst Bulk Alloc function "
3116                              "will be used on port %d.",
3117                              dev->data->port_id);
3118                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3119         } else {
3120                 PMD_INIT_LOG(DEBUG,
3121                              "Rx Burst Bulk Alloc Preconditions are not "
3122                              "satisfied, Normal Rx will be used on port %d.",
3123                              dev->data->port_id);
3124                 dev->rx_pkt_burst = ice_recv_pkts;
3125         }
3126 }
3127
3128 static const struct {
3129         eth_rx_burst_t pkt_burst;
3130         const char *info;
3131 } ice_rx_burst_infos[] = {
3132         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3133         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3134         { ice_recv_pkts,                    "Scalar" },
3135 #ifdef RTE_ARCH_X86
3136 #ifdef CC_AVX512_SUPPORT
3137         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3138         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3139 #endif
3140         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3141         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3142         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3143         { ice_recv_pkts_vec,                "Vector SSE" },
3144 #endif
3145 };
3146
3147 int
3148 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3149                       struct rte_eth_burst_mode *mode)
3150 {
3151         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3152         int ret = -EINVAL;
3153         unsigned int i;
3154
3155         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3156                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3157                         snprintf(mode->info, sizeof(mode->info), "%s",
3158                                  ice_rx_burst_infos[i].info);
3159                         ret = 0;
3160                         break;
3161                 }
3162         }
3163
3164         return ret;
3165 }
3166
3167 void __rte_cold
3168 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3169 {
3170         struct ice_adapter *ad =
3171                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3172
3173         /* Use a simple Tx queue if possible (only fast free is allowed) */
3174         ad->tx_simple_allowed =
3175                 (txq->offloads ==
3176                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3177                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3178
3179         if (ad->tx_simple_allowed)
3180                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3181                              txq->queue_id);
3182         else
3183                 PMD_INIT_LOG(DEBUG,
3184                              "Simple Tx can NOT be enabled on Tx queue %u.",
3185                              txq->queue_id);
3186 }
3187
3188 /*********************************************************************
3189  *
3190  *  TX prep functions
3191  *
3192  **********************************************************************/
3193 /* The default values of TSO MSS */
3194 #define ICE_MIN_TSO_MSS            64
3195 #define ICE_MAX_TSO_MSS            9728
3196 #define ICE_MAX_TSO_FRAME_SIZE     262144
3197 uint16_t
3198 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3199               uint16_t nb_pkts)
3200 {
3201         int i, ret;
3202         uint64_t ol_flags;
3203         struct rte_mbuf *m;
3204
3205         for (i = 0; i < nb_pkts; i++) {
3206                 m = tx_pkts[i];
3207                 ol_flags = m->ol_flags;
3208
3209                 if (ol_flags & PKT_TX_TCP_SEG &&
3210                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3211                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3212                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3213                         /**
3214                          * MSS outside the range are considered malicious
3215                          */
3216                         rte_errno = EINVAL;
3217                         return i;
3218                 }
3219
3220 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3221                 ret = rte_validate_tx_offload(m);
3222                 if (ret != 0) {
3223                         rte_errno = -ret;
3224                         return i;
3225                 }
3226 #endif
3227                 ret = rte_net_intel_cksum_prepare(m);
3228                 if (ret != 0) {
3229                         rte_errno = -ret;
3230                         return i;
3231                 }
3232         }
3233         return i;
3234 }
3235
3236 void __rte_cold
3237 ice_set_tx_function(struct rte_eth_dev *dev)
3238 {
3239         struct ice_adapter *ad =
3240                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3241 #ifdef RTE_ARCH_X86
3242         struct ice_tx_queue *txq;
3243         int i;
3244         bool use_avx512 = false;
3245         bool use_avx2 = false;
3246
3247         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3248                 if (!ice_tx_vec_dev_check(dev) &&
3249                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3250                         ad->tx_vec_allowed = true;
3251                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3252                                 txq = dev->data->tx_queues[i];
3253                                 if (txq && ice_txq_vec_setup(txq)) {
3254                                         ad->tx_vec_allowed = false;
3255                                         break;
3256                                 }
3257                         }
3258
3259                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3260                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3261                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3262 #ifdef CC_AVX512_SUPPORT
3263                                 use_avx512 = true;
3264 #else
3265                         PMD_DRV_LOG(NOTICE,
3266                                 "AVX512 is not supported in build env");
3267 #endif
3268                         if (!use_avx512 &&
3269                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3270                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3271                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3272                                 use_avx2 = true;
3273
3274                 } else {
3275                         ad->tx_vec_allowed = false;
3276                 }
3277         }
3278
3279         if (ad->tx_vec_allowed) {
3280                 if (use_avx512) {
3281 #ifdef CC_AVX512_SUPPORT
3282                         PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3283                                     dev->data->port_id);
3284                         dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3285 #endif
3286                 } else {
3287                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3288                                     use_avx2 ? "avx2 " : "",
3289                                     dev->data->port_id);
3290                         dev->tx_pkt_burst = use_avx2 ?
3291                                             ice_xmit_pkts_vec_avx2 :
3292                                             ice_xmit_pkts_vec;
3293                 }
3294                 dev->tx_pkt_prepare = NULL;
3295
3296                 return;
3297         }
3298 #endif
3299
3300         if (ad->tx_simple_allowed) {
3301                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3302                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3303                 dev->tx_pkt_prepare = NULL;
3304         } else {
3305                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3306                 dev->tx_pkt_burst = ice_xmit_pkts;
3307                 dev->tx_pkt_prepare = ice_prep_pkts;
3308         }
3309 }
3310
3311 static const struct {
3312         eth_tx_burst_t pkt_burst;
3313         const char *info;
3314 } ice_tx_burst_infos[] = {
3315         { ice_xmit_pkts_simple,   "Scalar Simple" },
3316         { ice_xmit_pkts,          "Scalar" },
3317 #ifdef RTE_ARCH_X86
3318 #ifdef CC_AVX512_SUPPORT
3319         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3320 #endif
3321         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3322         { ice_xmit_pkts_vec,      "Vector SSE" },
3323 #endif
3324 };
3325
3326 int
3327 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3328                       struct rte_eth_burst_mode *mode)
3329 {
3330         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3331         int ret = -EINVAL;
3332         unsigned int i;
3333
3334         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3335                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3336                         snprintf(mode->info, sizeof(mode->info), "%s",
3337                                  ice_tx_burst_infos[i].info);
3338                         ret = 0;
3339                         break;
3340                 }
3341         }
3342
3343         return ret;
3344 }
3345
3346 /* For each value it means, datasheet of hardware can tell more details
3347  *
3348  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3349  */
3350 static inline uint32_t
3351 ice_get_default_pkt_type(uint16_t ptype)
3352 {
3353         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3354                 __rte_cache_aligned = {
3355                 /* L2 types */
3356                 /* [0] reserved */
3357                 [1] = RTE_PTYPE_L2_ETHER,
3358                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3359                 /* [3] - [5] reserved */
3360                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3361                 /* [7] - [10] reserved */
3362                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3363                 /* [12] - [21] reserved */
3364
3365                 /* Non tunneled IPv4 */
3366                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3367                        RTE_PTYPE_L4_FRAG,
3368                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3369                        RTE_PTYPE_L4_NONFRAG,
3370                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3371                        RTE_PTYPE_L4_UDP,
3372                 /* [25] reserved */
3373                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3374                        RTE_PTYPE_L4_TCP,
3375                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3376                        RTE_PTYPE_L4_SCTP,
3377                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3378                        RTE_PTYPE_L4_ICMP,
3379
3380                 /* IPv4 --> IPv4 */
3381                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3382                        RTE_PTYPE_TUNNEL_IP |
3383                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3384                        RTE_PTYPE_INNER_L4_FRAG,
3385                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3386                        RTE_PTYPE_TUNNEL_IP |
3387                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3388                        RTE_PTYPE_INNER_L4_NONFRAG,
3389                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3390                        RTE_PTYPE_TUNNEL_IP |
3391                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3392                        RTE_PTYPE_INNER_L4_UDP,
3393                 /* [32] reserved */
3394                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3395                        RTE_PTYPE_TUNNEL_IP |
3396                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3397                        RTE_PTYPE_INNER_L4_TCP,
3398                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3399                        RTE_PTYPE_TUNNEL_IP |
3400                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3401                        RTE_PTYPE_INNER_L4_SCTP,
3402                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3403                        RTE_PTYPE_TUNNEL_IP |
3404                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3405                        RTE_PTYPE_INNER_L4_ICMP,
3406
3407                 /* IPv4 --> IPv6 */
3408                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3409                        RTE_PTYPE_TUNNEL_IP |
3410                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3411                        RTE_PTYPE_INNER_L4_FRAG,
3412                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3413                        RTE_PTYPE_TUNNEL_IP |
3414                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3415                        RTE_PTYPE_INNER_L4_NONFRAG,
3416                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3417                        RTE_PTYPE_TUNNEL_IP |
3418                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3419                        RTE_PTYPE_INNER_L4_UDP,
3420                 /* [39] reserved */
3421                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3422                        RTE_PTYPE_TUNNEL_IP |
3423                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3424                        RTE_PTYPE_INNER_L4_TCP,
3425                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3426                        RTE_PTYPE_TUNNEL_IP |
3427                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3428                        RTE_PTYPE_INNER_L4_SCTP,
3429                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3430                        RTE_PTYPE_TUNNEL_IP |
3431                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3432                        RTE_PTYPE_INNER_L4_ICMP,
3433
3434                 /* IPv4 --> GRE/Teredo/VXLAN */
3435                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3436                        RTE_PTYPE_TUNNEL_GRENAT,
3437
3438                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3439                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3440                        RTE_PTYPE_TUNNEL_GRENAT |
3441                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3442                        RTE_PTYPE_INNER_L4_FRAG,
3443                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3444                        RTE_PTYPE_TUNNEL_GRENAT |
3445                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3446                        RTE_PTYPE_INNER_L4_NONFRAG,
3447                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3448                        RTE_PTYPE_TUNNEL_GRENAT |
3449                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3450                        RTE_PTYPE_INNER_L4_UDP,
3451                 /* [47] reserved */
3452                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3453                        RTE_PTYPE_TUNNEL_GRENAT |
3454                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3455                        RTE_PTYPE_INNER_L4_TCP,
3456                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3457                        RTE_PTYPE_TUNNEL_GRENAT |
3458                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3459                        RTE_PTYPE_INNER_L4_SCTP,
3460                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3461                        RTE_PTYPE_TUNNEL_GRENAT |
3462                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3463                        RTE_PTYPE_INNER_L4_ICMP,
3464
3465                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3466                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3467                        RTE_PTYPE_TUNNEL_GRENAT |
3468                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3469                        RTE_PTYPE_INNER_L4_FRAG,
3470                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3471                        RTE_PTYPE_TUNNEL_GRENAT |
3472                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3473                        RTE_PTYPE_INNER_L4_NONFRAG,
3474                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3475                        RTE_PTYPE_TUNNEL_GRENAT |
3476                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3477                        RTE_PTYPE_INNER_L4_UDP,
3478                 /* [54] reserved */
3479                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3480                        RTE_PTYPE_TUNNEL_GRENAT |
3481                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3482                        RTE_PTYPE_INNER_L4_TCP,
3483                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3484                        RTE_PTYPE_TUNNEL_GRENAT |
3485                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3486                        RTE_PTYPE_INNER_L4_SCTP,
3487                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3488                        RTE_PTYPE_TUNNEL_GRENAT |
3489                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3490                        RTE_PTYPE_INNER_L4_ICMP,
3491
3492                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3493                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3494                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3495
3496                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3497                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3498                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3499                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3500                        RTE_PTYPE_INNER_L4_FRAG,
3501                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3502                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3503                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3504                        RTE_PTYPE_INNER_L4_NONFRAG,
3505                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3506                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3507                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3508                        RTE_PTYPE_INNER_L4_UDP,
3509                 /* [62] reserved */
3510                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3511                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3512                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3513                        RTE_PTYPE_INNER_L4_TCP,
3514                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3515                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3516                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3517                        RTE_PTYPE_INNER_L4_SCTP,
3518                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3519                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3520                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3521                        RTE_PTYPE_INNER_L4_ICMP,
3522
3523                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3524                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3525                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3526                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3527                        RTE_PTYPE_INNER_L4_FRAG,
3528                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3529                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3530                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3531                        RTE_PTYPE_INNER_L4_NONFRAG,
3532                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3533                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3534                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3535                        RTE_PTYPE_INNER_L4_UDP,
3536                 /* [69] reserved */
3537                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3538                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3539                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3540                        RTE_PTYPE_INNER_L4_TCP,
3541                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3542                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3543                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3544                        RTE_PTYPE_INNER_L4_SCTP,
3545                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3546                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3547                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3548                        RTE_PTYPE_INNER_L4_ICMP,
3549                 /* [73] - [87] reserved */
3550
3551                 /* Non tunneled IPv6 */
3552                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3553                        RTE_PTYPE_L4_FRAG,
3554                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3555                        RTE_PTYPE_L4_NONFRAG,
3556                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3557                        RTE_PTYPE_L4_UDP,
3558                 /* [91] reserved */
3559                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3560                        RTE_PTYPE_L4_TCP,
3561                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3562                        RTE_PTYPE_L4_SCTP,
3563                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3564                        RTE_PTYPE_L4_ICMP,
3565
3566                 /* IPv6 --> IPv4 */
3567                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3568                        RTE_PTYPE_TUNNEL_IP |
3569                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3570                        RTE_PTYPE_INNER_L4_FRAG,
3571                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3572                        RTE_PTYPE_TUNNEL_IP |
3573                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3574                        RTE_PTYPE_INNER_L4_NONFRAG,
3575                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3576                        RTE_PTYPE_TUNNEL_IP |
3577                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3578                        RTE_PTYPE_INNER_L4_UDP,
3579                 /* [98] reserved */
3580                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3581                        RTE_PTYPE_TUNNEL_IP |
3582                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3583                        RTE_PTYPE_INNER_L4_TCP,
3584                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3585                         RTE_PTYPE_TUNNEL_IP |
3586                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3587                         RTE_PTYPE_INNER_L4_SCTP,
3588                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3589                         RTE_PTYPE_TUNNEL_IP |
3590                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3591                         RTE_PTYPE_INNER_L4_ICMP,
3592
3593                 /* IPv6 --> IPv6 */
3594                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3595                         RTE_PTYPE_TUNNEL_IP |
3596                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3597                         RTE_PTYPE_INNER_L4_FRAG,
3598                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3599                         RTE_PTYPE_TUNNEL_IP |
3600                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3601                         RTE_PTYPE_INNER_L4_NONFRAG,
3602                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3603                         RTE_PTYPE_TUNNEL_IP |
3604                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3605                         RTE_PTYPE_INNER_L4_UDP,
3606                 /* [105] reserved */
3607                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3608                         RTE_PTYPE_TUNNEL_IP |
3609                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3610                         RTE_PTYPE_INNER_L4_TCP,
3611                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3612                         RTE_PTYPE_TUNNEL_IP |
3613                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3614                         RTE_PTYPE_INNER_L4_SCTP,
3615                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3616                         RTE_PTYPE_TUNNEL_IP |
3617                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3618                         RTE_PTYPE_INNER_L4_ICMP,
3619
3620                 /* IPv6 --> GRE/Teredo/VXLAN */
3621                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3622                         RTE_PTYPE_TUNNEL_GRENAT,
3623
3624                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3625                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3626                         RTE_PTYPE_TUNNEL_GRENAT |
3627                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3628                         RTE_PTYPE_INNER_L4_FRAG,
3629                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3630                         RTE_PTYPE_TUNNEL_GRENAT |
3631                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3632                         RTE_PTYPE_INNER_L4_NONFRAG,
3633                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3634                         RTE_PTYPE_TUNNEL_GRENAT |
3635                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3636                         RTE_PTYPE_INNER_L4_UDP,
3637                 /* [113] reserved */
3638                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3639                         RTE_PTYPE_TUNNEL_GRENAT |
3640                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3641                         RTE_PTYPE_INNER_L4_TCP,
3642                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3643                         RTE_PTYPE_TUNNEL_GRENAT |
3644                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3645                         RTE_PTYPE_INNER_L4_SCTP,
3646                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3647                         RTE_PTYPE_TUNNEL_GRENAT |
3648                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3649                         RTE_PTYPE_INNER_L4_ICMP,
3650
3651                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3652                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3653                         RTE_PTYPE_TUNNEL_GRENAT |
3654                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3655                         RTE_PTYPE_INNER_L4_FRAG,
3656                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3657                         RTE_PTYPE_TUNNEL_GRENAT |
3658                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3659                         RTE_PTYPE_INNER_L4_NONFRAG,
3660                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3661                         RTE_PTYPE_TUNNEL_GRENAT |
3662                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3663                         RTE_PTYPE_INNER_L4_UDP,
3664                 /* [120] reserved */
3665                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3666                         RTE_PTYPE_TUNNEL_GRENAT |
3667                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3668                         RTE_PTYPE_INNER_L4_TCP,
3669                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3670                         RTE_PTYPE_TUNNEL_GRENAT |
3671                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3672                         RTE_PTYPE_INNER_L4_SCTP,
3673                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3674                         RTE_PTYPE_TUNNEL_GRENAT |
3675                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3676                         RTE_PTYPE_INNER_L4_ICMP,
3677
3678                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3679                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3680                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3681
3682                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3683                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3684                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3685                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3686                         RTE_PTYPE_INNER_L4_FRAG,
3687                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3688                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3689                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3690                         RTE_PTYPE_INNER_L4_NONFRAG,
3691                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3692                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3693                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3694                         RTE_PTYPE_INNER_L4_UDP,
3695                 /* [128] reserved */
3696                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3697                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3698                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3699                         RTE_PTYPE_INNER_L4_TCP,
3700                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3701                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3702                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3703                         RTE_PTYPE_INNER_L4_SCTP,
3704                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3705                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3706                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3707                         RTE_PTYPE_INNER_L4_ICMP,
3708
3709                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3710                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3711                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3712                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3713                         RTE_PTYPE_INNER_L4_FRAG,
3714                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3715                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3716                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3717                         RTE_PTYPE_INNER_L4_NONFRAG,
3718                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3719                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3720                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3721                         RTE_PTYPE_INNER_L4_UDP,
3722                 /* [135] reserved */
3723                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3724                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3725                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3726                         RTE_PTYPE_INNER_L4_TCP,
3727                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3728                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3729                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_INNER_L4_SCTP,
3731                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3732                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3733                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3734                         RTE_PTYPE_INNER_L4_ICMP,
3735                 /* [139] - [299] reserved */
3736
3737                 /* PPPoE */
3738                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3739                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3740
3741                 /* PPPoE --> IPv4 */
3742                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3743                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3744                         RTE_PTYPE_L4_FRAG,
3745                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3746                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3747                         RTE_PTYPE_L4_NONFRAG,
3748                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3749                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3750                         RTE_PTYPE_L4_UDP,
3751                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3752                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3753                         RTE_PTYPE_L4_TCP,
3754                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3755                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3756                         RTE_PTYPE_L4_SCTP,
3757                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3758                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3759                         RTE_PTYPE_L4_ICMP,
3760
3761                 /* PPPoE --> IPv6 */
3762                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3763                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3764                         RTE_PTYPE_L4_FRAG,
3765                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3766                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3767                         RTE_PTYPE_L4_NONFRAG,
3768                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3769                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3770                         RTE_PTYPE_L4_UDP,
3771                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3772                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3773                         RTE_PTYPE_L4_TCP,
3774                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3775                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3776                         RTE_PTYPE_L4_SCTP,
3777                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3778                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3779                         RTE_PTYPE_L4_ICMP,
3780                 /* [314] - [324] reserved */
3781
3782                 /* IPv4/IPv6 --> GTPC/GTPU */
3783                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3784                         RTE_PTYPE_TUNNEL_GTPC,
3785                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3786                         RTE_PTYPE_TUNNEL_GTPC,
3787                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3788                         RTE_PTYPE_TUNNEL_GTPC,
3789                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3790                         RTE_PTYPE_TUNNEL_GTPC,
3791                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3792                         RTE_PTYPE_TUNNEL_GTPU,
3793                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3794                         RTE_PTYPE_TUNNEL_GTPU,
3795
3796                 /* IPv4 --> GTPU --> IPv4 */
3797                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3798                         RTE_PTYPE_TUNNEL_GTPU |
3799                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3800                         RTE_PTYPE_INNER_L4_FRAG,
3801                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3802                         RTE_PTYPE_TUNNEL_GTPU |
3803                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3804                         RTE_PTYPE_INNER_L4_NONFRAG,
3805                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3806                         RTE_PTYPE_TUNNEL_GTPU |
3807                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3808                         RTE_PTYPE_INNER_L4_UDP,
3809                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3810                         RTE_PTYPE_TUNNEL_GTPU |
3811                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3812                         RTE_PTYPE_INNER_L4_TCP,
3813                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3814                         RTE_PTYPE_TUNNEL_GTPU |
3815                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3816                         RTE_PTYPE_INNER_L4_ICMP,
3817
3818                 /* IPv6 --> GTPU --> IPv4 */
3819                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3820                         RTE_PTYPE_TUNNEL_GTPU |
3821                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3822                         RTE_PTYPE_INNER_L4_FRAG,
3823                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3824                         RTE_PTYPE_TUNNEL_GTPU |
3825                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3826                         RTE_PTYPE_INNER_L4_NONFRAG,
3827                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828                         RTE_PTYPE_TUNNEL_GTPU |
3829                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3830                         RTE_PTYPE_INNER_L4_UDP,
3831                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3832                         RTE_PTYPE_TUNNEL_GTPU |
3833                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3834                         RTE_PTYPE_INNER_L4_TCP,
3835                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3836                         RTE_PTYPE_TUNNEL_GTPU |
3837                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3838                         RTE_PTYPE_INNER_L4_ICMP,
3839
3840                 /* IPv4 --> GTPU --> IPv6 */
3841                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3842                         RTE_PTYPE_TUNNEL_GTPU |
3843                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3844                         RTE_PTYPE_INNER_L4_FRAG,
3845                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3846                         RTE_PTYPE_TUNNEL_GTPU |
3847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_INNER_L4_NONFRAG,
3849                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3850                         RTE_PTYPE_TUNNEL_GTPU |
3851                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3852                         RTE_PTYPE_INNER_L4_UDP,
3853                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3854                         RTE_PTYPE_TUNNEL_GTPU |
3855                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3856                         RTE_PTYPE_INNER_L4_TCP,
3857                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3858                         RTE_PTYPE_TUNNEL_GTPU |
3859                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3860                         RTE_PTYPE_INNER_L4_ICMP,
3861
3862                 /* IPv6 --> GTPU --> IPv6 */
3863                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3864                         RTE_PTYPE_TUNNEL_GTPU |
3865                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3866                         RTE_PTYPE_INNER_L4_FRAG,
3867                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3868                         RTE_PTYPE_TUNNEL_GTPU |
3869                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3870                         RTE_PTYPE_INNER_L4_NONFRAG,
3871                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3872                         RTE_PTYPE_TUNNEL_GTPU |
3873                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3874                         RTE_PTYPE_INNER_L4_UDP,
3875                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3876                         RTE_PTYPE_TUNNEL_GTPU |
3877                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3878                         RTE_PTYPE_INNER_L4_TCP,
3879                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3880                         RTE_PTYPE_TUNNEL_GTPU |
3881                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3882                         RTE_PTYPE_INNER_L4_ICMP,
3883                 /* All others reserved */
3884         };
3885
3886         return type_table[ptype];
3887 }
3888
3889 void __rte_cold
3890 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3891 {
3892         struct ice_adapter *ad =
3893                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3894         int i;
3895
3896         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3897                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3898 }
3899
3900 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3901 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3902                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3903 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3904 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3905
3906 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3907 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3908         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3909 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3910 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3911         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3912
3913 /*
3914  * check the programming status descriptor in rx queue.
3915  * done after Programming Flow Director is programmed on
3916  * tx queue
3917  */
3918 static inline int
3919 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3920 {
3921         volatile union ice_32byte_rx_desc *rxdp;
3922         uint64_t qword1;
3923         uint32_t rx_status;
3924         uint32_t error;
3925         uint32_t id;
3926         int ret = -EAGAIN;
3927
3928         rxdp = (volatile union ice_32byte_rx_desc *)
3929                 (&rxq->rx_ring[rxq->rx_tail]);
3930         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3931         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3932                         >> ICE_RXD_QW1_STATUS_S;
3933
3934         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3935                 ret = 0;
3936                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3937                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3938                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3939                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3940                 if (error) {
3941                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3942                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3943                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3944                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3945                         ret = -EINVAL;
3946                         goto err;
3947                 }
3948                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3949                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3950                 if (error) {
3951                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3952                         ret = -EINVAL;
3953                 }
3954 err:
3955                 rxdp->wb.qword1.status_error_len = 0;
3956                 rxq->rx_tail++;
3957                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3958                         rxq->rx_tail = 0;
3959                 if (rxq->rx_tail == 0)
3960                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3961                 else
3962                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3963         }
3964
3965         return ret;
3966 }
3967
3968 #define ICE_FDIR_MAX_WAIT_US 10000
3969
3970 int
3971 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3972 {
3973         struct ice_tx_queue *txq = pf->fdir.txq;
3974         struct ice_rx_queue *rxq = pf->fdir.rxq;
3975         volatile struct ice_fltr_desc *fdirdp;
3976         volatile struct ice_tx_desc *txdp;
3977         uint32_t td_cmd;
3978         uint16_t i;
3979
3980         fdirdp = (volatile struct ice_fltr_desc *)
3981                 (&txq->tx_ring[txq->tx_tail]);
3982         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3983         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3984
3985         txdp = &txq->tx_ring[txq->tx_tail + 1];
3986         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3987         td_cmd = ICE_TX_DESC_CMD_EOP |
3988                 ICE_TX_DESC_CMD_RS  |
3989                 ICE_TX_DESC_CMD_DUMMY;
3990
3991         txdp->cmd_type_offset_bsz =
3992                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3993
3994         txq->tx_tail += 2;
3995         if (txq->tx_tail >= txq->nb_tx_desc)
3996                 txq->tx_tail = 0;
3997         /* Update the tx tail register */
3998         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3999         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4000                 if ((txdp->cmd_type_offset_bsz &
4001                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4002                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4003                         break;
4004                 rte_delay_us(1);
4005         }
4006         if (i >= ICE_FDIR_MAX_WAIT_US) {
4007                 PMD_DRV_LOG(ERR,
4008                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4009                 return -ETIMEDOUT;
4010         }
4011
4012         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4013                 int ret;
4014
4015                 ret = ice_check_fdir_programming_status(rxq);
4016                 if (ret == -EAGAIN)
4017                         rte_delay_us(1);
4018                 else
4019                         return ret;
4020         }
4021
4022         PMD_DRV_LOG(ERR,
4023                     "Failed to program FDIR filter: programming status reported.");
4024         return -ETIMEDOUT;
4025
4026
4027 }