1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include "ice_ethdev.h"
10 #define ICE_ALIGN_RING_DESC 32
11 #define ICE_MIN_RING_DESC 64
12 #define ICE_MAX_RING_DESC 4096
13 #define ICE_DMA_MEM_ALIGN 4096
14 #define ICE_RING_BASE_ALIGN 128
16 #define ICE_RX_MAX_BURST 32
17 #define ICE_TX_MAX_BURST 32
19 #define ICE_CHK_Q_ENA_COUNT 100
20 #define ICE_CHK_Q_ENA_INTERVAL_US 100
22 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
23 #define ice_rx_desc ice_16byte_rx_desc
25 #define ice_rx_desc ice_32byte_rx_desc
28 #define ICE_SUPPORT_CHAIN_NUM 5
31 struct rte_mbuf *mbuf;
35 struct rte_mempool *mp; /* mbuf pool to populate RX ring */
36 volatile union ice_rx_desc *rx_ring;/* RX ring virtual address */
37 uint64_t rx_ring_phys_addr; /* RX ring DMA address */
38 struct ice_rx_entry *sw_ring; /* address of RX soft ring */
39 uint16_t nb_rx_desc; /* number of RX descriptors */
40 uint16_t rx_free_thresh; /* max free RX desc to hold */
41 uint16_t rx_tail; /* current value of tail */
42 uint16_t nb_rx_hold; /* number of held free RX desc */
43 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
44 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
45 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
46 uint16_t rx_nb_avail; /**< number of staged packets ready */
47 uint16_t rx_next_avail; /**< index of next staged packets */
48 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
49 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
50 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];
52 uint8_t port_id; /* device port ID */
53 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
54 uint16_t queue_id; /* RX queue index */
55 uint16_t reg_idx; /* RX queue register index */
56 uint8_t drop_en; /* if not 0, set register bit */
57 volatile uint8_t *qrx_tail; /* register address of tail */
58 struct ice_vsi *vsi; /* the VSI this queue belongs to */
59 uint16_t rx_buf_len; /* The packet buffer size */
60 uint16_t rx_hdr_len; /* The header buffer size */
61 uint16_t max_pkt_len; /* Maximum packet length */
62 bool q_set; /* indicate if rx queue has been configured */
63 bool rx_deferred_start; /* don't start this queue in dev start */
67 struct rte_mbuf *mbuf;
73 uint16_t nb_tx_desc; /* number of TX descriptors */
74 uint64_t tx_ring_phys_addr; /* TX ring DMA address */
75 volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */
76 struct ice_tx_entry *sw_ring; /* virtual address of SW ring */
77 uint16_t tx_tail; /* current value of tail register */
78 volatile uint8_t *qtx_tail; /* register address of tail */
79 uint16_t nb_tx_used; /* number of TX desc used since RS bit set */
80 /* index to last TX descriptor to have been cleaned */
81 uint16_t last_desc_cleaned;
82 /* Total number of TX descriptors ready to be allocated. */
84 /* Start freeing TX buffers if there are less free descriptors than
87 uint16_t tx_free_thresh;
88 /* Number of TX descriptors to use before RS bit is set. */
89 uint16_t tx_rs_thresh;
90 uint8_t pthresh; /**< Prefetch threshold register. */
91 uint8_t hthresh; /**< Host threshold register. */
92 uint8_t wthresh; /**< Write-back threshold reg. */
93 uint8_t port_id; /* Device port identifier. */
94 uint16_t queue_id; /* TX queue index. */
95 uint32_t q_teid; /* TX schedule node id. */
98 struct ice_vsi *vsi; /* the VSI this queue belongs to */
101 bool tx_deferred_start; /* don't start this queue in dev start */
102 bool q_set; /* indicate if tx queue has been configured */
105 /* Offload features */
106 union ice_tx_offload {
109 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
110 uint64_t l3_len:9; /* L3 (IP) Header Length. */
111 uint64_t l4_len:8; /* L4 Header Length. */
112 uint64_t tso_segsz:16; /* TCP TSO segment size */
113 uint64_t outer_l2_len:8; /* outer L2 Header Length */
114 uint64_t outer_l3_len:16; /* outer L3 Header Length */
118 int ice_rx_queue_setup(struct rte_eth_dev *dev,
121 unsigned int socket_id,
122 const struct rte_eth_rxconf *rx_conf,
123 struct rte_mempool *mp);
124 int ice_tx_queue_setup(struct rte_eth_dev *dev,
127 unsigned int socket_id,
128 const struct rte_eth_txconf *tx_conf);
129 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
130 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
131 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
132 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
133 void ice_rx_queue_release(void *rxq);
134 void ice_tx_queue_release(void *txq);
135 void ice_clear_queues(struct rte_eth_dev *dev);
136 void ice_free_queues(struct rte_eth_dev *dev);
137 uint32_t ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
138 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
139 struct rte_eth_rxq_info *qinfo);
140 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
141 struct rte_eth_txq_info *qinfo);
142 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
143 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
144 #endif /* _ICE_RXTX_H_ */