drivers/net/ice/ice_rxtx_vec_avx2.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 static inline void
  14 ice_rxq_rearm(struct ice_rx_queue *rxq)
  15 {
  16         int i;
  17         uint16_t rx_id;
  18         volatile union ice_rx_flex_desc *rxdp;
  19         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  20
  21         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  22
  23         /* Pull 'n' more MBUFs into the software ring */
  24         if (rte_mempool_get_bulk(rxq->mp,
  25                                  (void *)rxep,
  26                                  ICE_RXQ_REARM_THRESH) < 0) {
  27                 if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  28                     rxq->nb_rx_desc) {
  29                         __m128i dma_addr0;
  30
  31                         dma_addr0 = _mm_setzero_si128();
  32                         for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  33                                 rxep[i].mbuf = &rxq->fake_mbuf;
  34                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  35                                                 dma_addr0);
  36                         }
  37                 }
  38                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  39                         ICE_RXQ_REARM_THRESH;
  40                 return;
  41         }
  42
  43 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  44         struct rte_mbuf *mb0, *mb1;
  45         __m128i dma_addr0, dma_addr1;
  46         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  47                         RTE_PKTMBUF_HEADROOM);
  48         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  49         for (i = 0; i < ICE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  50                 __m128i vaddr0, vaddr1;
  51
  52                 mb0 = rxep[0].mbuf;
  53                 mb1 = rxep[1].mbuf;
  54
  55                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  56                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  57                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  58                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  59                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  60
  61                 /* convert pa to dma_addr hdr/data */
  62                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  63                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  64
  65                 /* add headroom to pa values */
  66                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  67                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  68
  69                 /* flush desc with pa dma_addr */
  70                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  71                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  72         }
  73 #else
  74         struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
  75         __m256i dma_addr0_1, dma_addr2_3;
  76         __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
  77         /* Initialize the mbufs in vector, process 4 mbufs in one loop */
  78         for (i = 0; i < ICE_RXQ_REARM_THRESH;
  79                         i += 4, rxep += 4, rxdp += 4) {
  80                 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
  81                 __m256i vaddr0_1, vaddr2_3;
  82
  83                 mb0 = rxep[0].mbuf;
  84                 mb1 = rxep[1].mbuf;
  85                 mb2 = rxep[2].mbuf;
  86                 mb3 = rxep[3].mbuf;
  87
  88                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  89                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  90                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  91                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  92                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  93                 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
  94                 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
  95
  96                 /**
  97                  * merge 0 & 1, by casting 0 to 256-bit and inserting 1
  98                  * into the high lanes. Similarly for 2 & 3
  99                  */
 100                 vaddr0_1 =
 101                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 102                                                 vaddr1, 1);
 103                 vaddr2_3 =
 104                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 105                                                 vaddr3, 1);
 106
 107                 /* convert pa to dma_addr hdr/data */
 108                 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
 109                 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
 110
 111                 /* add headroom to pa values */
 112                 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
 113                 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
 114
 115                 /* flush desc with pa dma_addr */
 116                 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
 117                 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
 118         }
 119
 120 #endif
 121
 122         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
 123         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 124                 rxq->rxrearm_start = 0;
 125
 126         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
 127
 128         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 129                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 130
 131         /* Update the tail pointer on the NIC */
 132         ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 133 }
 134
 135 static inline __m256i
 136 ice_flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)
 137 {
 138 #define FDID_MIS_MAGIC 0xFFFFFFFF
 139         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
 140         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
 141         const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
 142                         PKT_RX_FDIR_ID);
 143         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 144         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 145         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 146                         fdir_mis_mask);
 147         /* this XOR op results to bit-reverse the fdir_mask */
 148         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 149         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 150
 151         return fdir_flags;
 152 }
 153
 154 static inline uint16_t
 155 _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 156                             uint16_t nb_pkts, uint8_t *split_packet)
 157 {
 158 #define ICE_DESCS_PER_LOOP_AVX 8
 159
 160         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 161         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 162                         0, rxq->mbuf_initializer);
 163         struct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
 164         volatile union ice_rx_flex_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 165         const int avx_aligned = ((rxq->rx_tail & 1) == 0);
 166
 167         rte_prefetch0(rxdp);
 168
 169         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */
 170         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);
 171
 172         /* See if we need to rearm the RX queue - gives the prefetch a bit
 173          * of time to act
 174          */
 175         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 176                 ice_rxq_rearm(rxq);
 177
 178         /* Before we start moving massive data around, check to see if
 179          * there is actually a packet available
 180          */
 181         if (!(rxdp->wb.status_error0 &
 182                         rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 183                 return 0;
 184
 185         /* constants used in processing loop */
 186         const __m256i crc_adjust =
 187                 _mm256_set_epi16
 188                         (/* first descriptor */
 189                          0, 0, 0,       /* ignore non-length fields */
 190                          -rxq->crc_len, /* sub crc on data_len */
 191                          0,             /* ignore high-16bits of pkt_len */
 192                          -rxq->crc_len, /* sub crc on pkt_len */
 193                          0, 0,          /* ignore pkt_type field */
 194                          /* second descriptor */
 195                          0, 0, 0,       /* ignore non-length fields */
 196                          -rxq->crc_len, /* sub crc on data_len */
 197                          0,             /* ignore high-16bits of pkt_len */
 198                          -rxq->crc_len, /* sub crc on pkt_len */
 199                          0, 0           /* ignore pkt_type field */
 200                         );
 201
 202         /* 8 packets DD mask, LSB in each 32-bit value */
 203         const __m256i dd_check = _mm256_set1_epi32(1);
 204
 205         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 206         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 207                         ICE_RX_DESC_STATUS_EOF_S);
 208
 209         /* mask to shuffle from desc. to mbuf (2 descriptors)*/
 210         const __m256i shuf_msk =
 211                 _mm256_set_epi8
 212                         (/* first descriptor */
 213                          0xFF, 0xFF,
 214                          0xFF, 0xFF,    /* rss hash parsed separately */
 215                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 216                          5, 4,          /* octet 4~5, 16 bits data_len */
 217                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 218                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 219                          0xFF, 0xFF,    /* pkt_type set as unknown */
 220                          0xFF, 0xFF,    /*pkt_type set as unknown */
 221                          /* second descriptor */
 222                          0xFF, 0xFF,
 223                          0xFF, 0xFF,    /* rss hash parsed separately */
 224                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 225                          5, 4,          /* octet 4~5, 16 bits data_len */
 226                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 227                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 228                          0xFF, 0xFF,    /* pkt_type set as unknown */
 229                          0xFF, 0xFF     /*pkt_type set as unknown */
 230                         );
 231         /**
 232          * compile-time check the above crc and shuffle layout is correct.
 233          * NOTE: the first field (lowest address) is given last in set_epi
 234          * calls above.
 235          */
 236         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 237                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 238         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 239                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 240         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 241                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 242         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 243                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 244
 245         /* Status/Error flag masks */
 246         /**
 247          * mask everything except Checksum Reports, RSS indication
 248          * and VLAN indication.
 249          * bit6:4 for IP/L4 checksum errors.
 250          * bit12 is for RSS indication.
 251          * bit13 is for VLAN indication.
 252          */
 253         const __m256i flags_mask =
 254                  _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 255         /**
 256          * data to be shuffled by the result of the flags mask shifted by 4
 257          * bits.  This gives use the l3_l4 flags.
 258          */
 259         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 260                         /* shift right 1 bit to make sure it not exceed 255 */
 261                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 262                          PKT_RX_IP_CKSUM_BAD) >> 1,
 263                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 264                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 265                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 266                          PKT_RX_IP_CKSUM_BAD) >> 1,
 267                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 268                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 269                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 270                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 271                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 272                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 273                         /* second 128-bits */
 274                         0, 0, 0, 0, 0, 0, 0, 0,
 275                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 276                          PKT_RX_IP_CKSUM_BAD) >> 1,
 277                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 278                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 279                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 280                          PKT_RX_IP_CKSUM_BAD) >> 1,
 281                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 282                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 283                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 284                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 285                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 286                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 287         const __m256i cksum_mask =
 288                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 289                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 290                                    PKT_RX_EIP_CKSUM_BAD);
 291         /**
 292          * data to be shuffled by result of flag mask, shifted down 12.
 293          * If RSS(bit12)/VLAN(bit13) are set,
 294          * shuffle moves appropriate flags in place.
 295          */
 296         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 297                         0, 0, 0, 0,
 298                         0, 0, 0, 0,
 299                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 300                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 301                         PKT_RX_RSS_HASH, 0,
 302                         /* end up 128-bits */
 303                         0, 0, 0, 0,
 304                         0, 0, 0, 0,
 305                         0, 0, 0, 0,
 306                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 307                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 308                         PKT_RX_RSS_HASH, 0);
 309
 310         RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
 311
 312         uint16_t i, received;
 313
 314         for (i = 0, received = 0; i < nb_pkts;
 315              i += ICE_DESCS_PER_LOOP_AVX,
 316              rxdp += ICE_DESCS_PER_LOOP_AVX) {
 317                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 318                 _mm256_storeu_si256((void *)&rx_pkts[i],
 319                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 320 #ifdef RTE_ARCH_X86_64
 321                 _mm256_storeu_si256
 322                         ((void *)&rx_pkts[i + 4],
 323                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 324 #endif
 325
 326                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 327 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 328                 /* for AVX we need alignment otherwise loads are not atomic */
 329                 if (avx_aligned) {
 330                         /* load in descriptors, 2 at a time, in reverse order */
 331                         raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
 332                         rte_compiler_barrier();
 333                         raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
 334                         rte_compiler_barrier();
 335                         raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
 336                         rte_compiler_barrier();
 337                         raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
 338                 } else
 339 #endif
 340                 {
 341                         const __m128i raw_desc7 =
 342                                 _mm_load_si128((void *)(rxdp + 7));
 343                         rte_compiler_barrier();
 344                         const __m128i raw_desc6 =
 345                                 _mm_load_si128((void *)(rxdp + 6));
 346                         rte_compiler_barrier();
 347                         const __m128i raw_desc5 =
 348                                 _mm_load_si128((void *)(rxdp + 5));
 349                         rte_compiler_barrier();
 350                         const __m128i raw_desc4 =
 351                                 _mm_load_si128((void *)(rxdp + 4));
 352                         rte_compiler_barrier();
 353                         const __m128i raw_desc3 =
 354                                 _mm_load_si128((void *)(rxdp + 3));
 355                         rte_compiler_barrier();
 356                         const __m128i raw_desc2 =
 357                                 _mm_load_si128((void *)(rxdp + 2));
 358                         rte_compiler_barrier();
 359                         const __m128i raw_desc1 =
 360                                 _mm_load_si128((void *)(rxdp + 1));
 361                         rte_compiler_barrier();
 362                         const __m128i raw_desc0 =
 363                                 _mm_load_si128((void *)(rxdp + 0));
 364
 365                         raw_desc6_7 =
 366                                 _mm256_inserti128_si256
 367                                         (_mm256_castsi128_si256(raw_desc6),
 368                                          raw_desc7, 1);
 369                         raw_desc4_5 =
 370                                 _mm256_inserti128_si256
 371                                         (_mm256_castsi128_si256(raw_desc4),
 372                                          raw_desc5, 1);
 373                         raw_desc2_3 =
 374                                 _mm256_inserti128_si256
 375                                         (_mm256_castsi128_si256(raw_desc2),
 376                                          raw_desc3, 1);
 377                         raw_desc0_1 =
 378                                 _mm256_inserti128_si256
 379                                         (_mm256_castsi128_si256(raw_desc0),
 380                                          raw_desc1, 1);
 381                 }
 382
 383                 if (split_packet) {
 384                         int j;
 385
 386                         for (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)
 387                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 388                 }
 389
 390                 /**
 391                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 392                  * Then write into the mbuf.
 393                  */
 394                 __m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);
 395                 __m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);
 396
 397                 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
 398                 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
 399                 /**
 400                  * to get packet types, ptype is located in bit16-25
 401                  * of each 128bits
 402                  */
 403                 const __m256i ptype_mask =
 404                         _mm256_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);
 405                 const __m256i ptypes6_7 =
 406                         _mm256_and_si256(raw_desc6_7, ptype_mask);
 407                 const __m256i ptypes4_5 =
 408                         _mm256_and_si256(raw_desc4_5, ptype_mask);
 409                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 410                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 411                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 412                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 413
 414                 mb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype7], 4);
 415                 mb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype6], 0);
 416                 mb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype5], 4);
 417                 mb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype4], 0);
 418                 /* merge the status bits into one register */
 419                 const __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,
 420                                 raw_desc4_5);
 421
 422                 /**
 423                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 424                  * Then write into the mbuf.
 425                  */
 426                 __m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);
 427                 __m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);
 428
 429                 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
 430                 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
 431                 /**
 432                  * to get packet types, ptype is located in bit16-25
 433                  * of each 128bits
 434                  */
 435                 const __m256i ptypes2_3 =
 436                         _mm256_and_si256(raw_desc2_3, ptype_mask);
 437                 const __m256i ptypes0_1 =
 438                         _mm256_and_si256(raw_desc0_1, ptype_mask);
 439                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 440                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 441                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 442                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 443
 444                 mb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype3], 4);
 445                 mb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype2], 0);
 446                 mb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype1], 4);
 447                 mb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype0], 0);
 448                 /* merge the status bits into one register */
 449                 const __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,
 450                                                                 raw_desc0_1);
 451
 452                 /**
 453                  * take the two sets of status bits and merge to one
 454                  * After merge, the packets status flags are in the
 455                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 456                  */
 457                 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
 458                                                           status0_3);
 459
 460                 /* now do flag manipulation */
 461
 462                 /* get only flag/error bits we want */
 463                 const __m256i flag_bits =
 464                         _mm256_and_si256(status0_7, flags_mask);
 465                 /**
 466                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 467                  * of flags in flags_shuf, and finally mask out extra bits
 468                  */
 469                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 470                                 _mm256_srli_epi32(flag_bits, 4));
 471                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 472                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 473                 /* set rss and vlan flags */
 474                 const __m256i rss_vlan_flag_bits =
 475                         _mm256_srli_epi32(flag_bits, 12);
 476                 const __m256i rss_vlan_flags =
 477                         _mm256_shuffle_epi8(rss_vlan_flags_shuf,
 478                                             rss_vlan_flag_bits);
 479
 480                 /* merge flags */
 481                 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 482                                 rss_vlan_flags);
 483
 484                 if (rxq->fdir_enabled) {
 485                         const __m256i fdir_id4_7 =
 486                                 _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);
 487
 488                         const __m256i fdir_id0_3 =
 489                                 _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);
 490
 491                         const __m256i fdir_id0_7 =
 492                                 _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);
 493
 494                         const __m256i fdir_flags =
 495                                 ice_flex_rxd_to_fdir_flags_vec_avx2(fdir_id0_7);
 496
 497                         /* merge with fdir_flags */
 498                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
 499
 500                         /* write to mbuf: have to use scalar store here */
 501                         rx_pkts[i + 0]->hash.fdir.hi =
 502                                 _mm256_extract_epi32(fdir_id0_7, 3);
 503
 504                         rx_pkts[i + 1]->hash.fdir.hi =
 505                                 _mm256_extract_epi32(fdir_id0_7, 7);
 506
 507                         rx_pkts[i + 2]->hash.fdir.hi =
 508                                 _mm256_extract_epi32(fdir_id0_7, 2);
 509
 510                         rx_pkts[i + 3]->hash.fdir.hi =
 511                                 _mm256_extract_epi32(fdir_id0_7, 6);
 512
 513                         rx_pkts[i + 4]->hash.fdir.hi =
 514                                 _mm256_extract_epi32(fdir_id0_7, 1);
 515
 516                         rx_pkts[i + 5]->hash.fdir.hi =
 517                                 _mm256_extract_epi32(fdir_id0_7, 5);
 518
 519                         rx_pkts[i + 6]->hash.fdir.hi =
 520                                 _mm256_extract_epi32(fdir_id0_7, 0);
 521
 522                         rx_pkts[i + 7]->hash.fdir.hi =
 523                                 _mm256_extract_epi32(fdir_id0_7, 4);
 524                 } /* if() on fdir_enabled */
 525
 526 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 527                 /**
 528                  * needs to load 2nd 16B of each desc for RSS hash parsing,
 529                  * will cause performance drop to get into this context.
 530                  */
 531                 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
 532                                 DEV_RX_OFFLOAD_RSS_HASH) {
 533                         /* load bottom half of every 32B desc */
 534                         const __m128i raw_desc_bh7 =
 535                                 _mm_load_si128
 536                                         ((void *)(&rxdp[7].wb.status_error1));
 537                         rte_compiler_barrier();
 538                         const __m128i raw_desc_bh6 =
 539                                 _mm_load_si128
 540                                         ((void *)(&rxdp[6].wb.status_error1));
 541                         rte_compiler_barrier();
 542                         const __m128i raw_desc_bh5 =
 543                                 _mm_load_si128
 544                                         ((void *)(&rxdp[5].wb.status_error1));
 545                         rte_compiler_barrier();
 546                         const __m128i raw_desc_bh4 =
 547                                 _mm_load_si128
 548                                         ((void *)(&rxdp[4].wb.status_error1));
 549                         rte_compiler_barrier();
 550                         const __m128i raw_desc_bh3 =
 551                                 _mm_load_si128
 552                                         ((void *)(&rxdp[3].wb.status_error1));
 553                         rte_compiler_barrier();
 554                         const __m128i raw_desc_bh2 =
 555                                 _mm_load_si128
 556                                         ((void *)(&rxdp[2].wb.status_error1));
 557                         rte_compiler_barrier();
 558                         const __m128i raw_desc_bh1 =
 559                                 _mm_load_si128
 560                                         ((void *)(&rxdp[1].wb.status_error1));
 561                         rte_compiler_barrier();
 562                         const __m128i raw_desc_bh0 =
 563                                 _mm_load_si128
 564                                         ((void *)(&rxdp[0].wb.status_error1));
 565
 566                         __m256i raw_desc_bh6_7 =
 567                                 _mm256_inserti128_si256
 568                                         (_mm256_castsi128_si256(raw_desc_bh6),
 569                                         raw_desc_bh7, 1);
 570                         __m256i raw_desc_bh4_5 =
 571                                 _mm256_inserti128_si256
 572                                         (_mm256_castsi128_si256(raw_desc_bh4),
 573                                         raw_desc_bh5, 1);
 574                         __m256i raw_desc_bh2_3 =
 575                                 _mm256_inserti128_si256
 576                                         (_mm256_castsi128_si256(raw_desc_bh2),
 577                                         raw_desc_bh3, 1);
 578                         __m256i raw_desc_bh0_1 =
 579                                 _mm256_inserti128_si256
 580                                         (_mm256_castsi128_si256(raw_desc_bh0),
 581                                         raw_desc_bh1, 1);
 582
 583                         /**
 584                          * to shift the 32b RSS hash value to the
 585                          * highest 32b of each 128b before mask
 586                          */
 587                         __m256i rss_hash6_7 =
 588                                 _mm256_slli_epi64(raw_desc_bh6_7, 32);
 589                         __m256i rss_hash4_5 =
 590                                 _mm256_slli_epi64(raw_desc_bh4_5, 32);
 591                         __m256i rss_hash2_3 =
 592                                 _mm256_slli_epi64(raw_desc_bh2_3, 32);
 593                         __m256i rss_hash0_1 =
 594                                 _mm256_slli_epi64(raw_desc_bh0_1, 32);
 595
 596                         __m256i rss_hash_msk =
 597                                 _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
 598                                                  0xFFFFFFFF, 0, 0, 0);
 599
 600                         rss_hash6_7 = _mm256_and_si256
 601                                         (rss_hash6_7, rss_hash_msk);
 602                         rss_hash4_5 = _mm256_and_si256
 603                                         (rss_hash4_5, rss_hash_msk);
 604                         rss_hash2_3 = _mm256_and_si256
 605                                         (rss_hash2_3, rss_hash_msk);
 606                         rss_hash0_1 = _mm256_and_si256
 607                                         (rss_hash0_1, rss_hash_msk);
 608
 609                         mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
 610                         mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
 611                         mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
 612                         mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
 613                 } /* if() on RSS hash parsing */
 614 #endif
 615
 616                 /**
 617                  * At this point, we have the 8 sets of flags in the low 16-bits
 618                  * of each 32-bit value in vlan0.
 619                  * We want to extract these, and merge them with the mbuf init
 620                  * data so we can do a single write to the mbuf to set the flags
 621                  * and all the other initialization fields. Extracting the
 622                  * appropriate flags means that we have to do a shift and blend
 623                  * for each mbuf before we do the write. However, we can also
 624                  * add in the previously computed rx_descriptor fields to
 625                  * make a single 256-bit write per mbuf
 626                  */
 627                 /* check the structure matches expectations */
 628                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 629                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 630                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 631                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 632                                                     rearm_data),
 633                                            16));
 634                 /* build up data and do writes */
 635                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 636                         rearm6, rearm7;
 637                 rearm6 = _mm256_blend_epi32(mbuf_init,
 638                                             _mm256_slli_si256(mbuf_flags, 8),
 639                                             0x04);
 640                 rearm4 = _mm256_blend_epi32(mbuf_init,
 641                                             _mm256_slli_si256(mbuf_flags, 4),
 642                                             0x04);
 643                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 644                 rearm0 = _mm256_blend_epi32(mbuf_init,
 645                                             _mm256_srli_si256(mbuf_flags, 4),
 646                                             0x04);
 647                 /* permute to add in the rx_descriptor e.g. rss fields */
 648                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 649                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 650                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 651                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 652                 /* write to mbuf */
 653                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 654                                     rearm6);
 655                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 656                                     rearm4);
 657                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 658                                     rearm2);
 659                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 660                                     rearm0);
 661
 662                 /* repeat for the odd mbufs */
 663                 const __m256i odd_flags =
 664                         _mm256_castsi128_si256
 665                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 666                 rearm7 = _mm256_blend_epi32(mbuf_init,
 667                                             _mm256_slli_si256(odd_flags, 8),
 668                                             0x04);
 669                 rearm5 = _mm256_blend_epi32(mbuf_init,
 670                                             _mm256_slli_si256(odd_flags, 4),
 671                                             0x04);
 672                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 673                 rearm1 = _mm256_blend_epi32(mbuf_init,
 674                                             _mm256_srli_si256(odd_flags, 4),
 675                                             0x04);
 676                 /* since odd mbufs are already in hi 128-bits use blend */
 677                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 678                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 679                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 680                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 681                 /* again write to mbufs */
 682                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 683                                     rearm7);
 684                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 685                                     rearm5);
 686                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 687                                     rearm3);
 688                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 689                                     rearm1);
 690
 691                 /* extract and record EOP bit */
 692                 if (split_packet) {
 693                         const __m128i eop_mask =
 694                                 _mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);
 695                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 696                                                                      eop_check);
 697                         /* pack status bits into a single 128-bit register */
 698                         const __m128i eop_bits =
 699                                 _mm_packus_epi32
 700                                         (_mm256_castsi256_si128(eop_bits256),
 701                                          _mm256_extractf128_si256(eop_bits256,
 702                                                                   1));
 703                         /**
 704                          * flip bits, and mask out the EOP bit, which is now
 705                          * a split-packet bit i.e. !EOP, rather than EOP one.
 706                          */
 707                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 708                                         eop_mask);
 709                         /**
 710                          * eop bits are out of order, so we need to shuffle them
 711                          * back into order again. In doing so, only use low 8
 712                          * bits, which acts like another pack instruction
 713                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 714                          * [Since we use epi8, the 16-bit positions are
 715                          * multiplied by 2 in the eop_shuffle value.]
 716                          */
 717                         __m128i eop_shuffle =
 718                                 _mm_set_epi8(/* zero hi 64b */
 719                                              0xFF, 0xFF, 0xFF, 0xFF,
 720                                              0xFF, 0xFF, 0xFF, 0xFF,
 721                                              /* move values to lo 64b */
 722                                              8, 0, 10, 2,
 723                                              12, 4, 14, 6);
 724                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 725                         *(uint64_t *)split_packet =
 726                                 _mm_cvtsi128_si64(split_bits);
 727                         split_packet += ICE_DESCS_PER_LOOP_AVX;
 728                 }
 729
 730                 /* perform dd_check */
 731                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 732                 status0_7 = _mm256_packs_epi32(status0_7,
 733                                                _mm256_setzero_si256());
 734
 735                 uint64_t burst = __builtin_popcountll
 736                                         (_mm_cvtsi128_si64
 737                                                 (_mm256_extracti128_si256
 738                                                         (status0_7, 1)));
 739                 burst += __builtin_popcountll
 740                                 (_mm_cvtsi128_si64
 741                                         (_mm256_castsi256_si128(status0_7)));
 742                 received += burst;
 743                 if (burst != ICE_DESCS_PER_LOOP_AVX)
 744                         break;
 745         }
 746
 747         /* update tail pointers */
 748         rxq->rx_tail += received;
 749         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 750         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 751                 rxq->rx_tail--;
 752                 received--;
 753         }
 754         rxq->rxrearm_nb += received;
 755         return received;
 756 }
 757
 758 /**
 759  * Notice:
 760  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 761  */
 762 uint16_t
 763 ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 764                        uint16_t nb_pkts)
 765 {
 766         return _ice_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
 767 }
 768
 769 /**
 770  * vPMD receive routine that reassembles single burst of 32 scattered packets
 771  * Notice:
 772  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 773  */
 774 static uint16_t
 775 ice_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 776                                   uint16_t nb_pkts)
 777 {
 778         struct ice_rx_queue *rxq = rx_queue;
 779         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 780
 781         /* get some new buffers */
 782         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
 783                                                        split_flags);
 784         if (nb_bufs == 0)
 785                 return 0;
 786
 787         /* happy day case, full burst + no packets to be joined */
 788         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 789
 790         if (!rxq->pkt_first_seg &&
 791             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 792             split_fl64[2] == 0 && split_fl64[3] == 0)
 793                 return nb_bufs;
 794
 795         /* reassemble any packets that need reassembly*/
 796         unsigned int i = 0;
 797
 798         if (!rxq->pkt_first_seg) {
 799                 /* find the first split flag, and only reassemble then*/
 800                 while (i < nb_bufs && !split_flags[i])
 801                         i++;
 802                 if (i == nb_bufs)
 803                         return nb_bufs;
 804                 rxq->pkt_first_seg = rx_pkts[i];
 805         }
 806         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 807                                              &split_flags[i]);
 808 }
 809
 810 /**
 811  * vPMD receive routine that reassembles scattered packets.
 812  * Main receive routine that can handle arbitrary burst sizes
 813  * Notice:
 814  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 815  */
 816 uint16_t
 817 ice_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 818                                  uint16_t nb_pkts)
 819 {
 820         uint16_t retval = 0;
 821
 822         while (nb_pkts > ICE_VPMD_RX_BURST) {
 823                 uint16_t burst = ice_recv_scattered_burst_vec_avx2(rx_queue,
 824                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 825                 retval += burst;
 826                 nb_pkts -= burst;
 827                 if (burst < ICE_VPMD_RX_BURST)
 828                         return retval;
 829         }
 830         return retval + ice_recv_scattered_burst_vec_avx2(rx_queue,
 831                                 rx_pkts + retval, nb_pkts);
 832 }
 833
 834 static inline void
 835 ice_vtx1(volatile struct ice_tx_desc *txdp,
 836          struct rte_mbuf *pkt, uint64_t flags)
 837 {
 838         uint64_t high_qw =
 839                 (ICE_TX_DESC_DTYPE_DATA |
 840                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
 841                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
 842
 843         __m128i descriptor = _mm_set_epi64x(high_qw,
 844                                 pkt->buf_iova + pkt->data_off);
 845         _mm_store_si128((__m128i *)txdp, descriptor);
 846 }
 847
 848 static inline void
 849 ice_vtx(volatile struct ice_tx_desc *txdp,
 850         struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 851 {
 852         const uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |
 853                         ((uint64_t)flags  << ICE_TXD_QW1_CMD_S));
 854
 855         /* if unaligned on 32-bit boundary, do one to align */
 856         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
 857                 ice_vtx1(txdp, *pkt, flags);
 858                 nb_pkts--, txdp++, pkt++;
 859         }
 860
 861         /* do two at a time while possible, in bursts */
 862         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
 863                 uint64_t hi_qw3 =
 864                         hi_qw_tmpl |
 865                         ((uint64_t)pkt[3]->data_len <<
 866                          ICE_TXD_QW1_TX_BUF_SZ_S);
 867                 uint64_t hi_qw2 =
 868                         hi_qw_tmpl |
 869                         ((uint64_t)pkt[2]->data_len <<
 870                          ICE_TXD_QW1_TX_BUF_SZ_S);
 871                 uint64_t hi_qw1 =
 872                         hi_qw_tmpl |
 873                         ((uint64_t)pkt[1]->data_len <<
 874                          ICE_TXD_QW1_TX_BUF_SZ_S);
 875                 uint64_t hi_qw0 =
 876                         hi_qw_tmpl |
 877                         ((uint64_t)pkt[0]->data_len <<
 878                          ICE_TXD_QW1_TX_BUF_SZ_S);
 879
 880                 __m256i desc2_3 =
 881                         _mm256_set_epi64x
 882                                 (hi_qw3,
 883                                  pkt[3]->buf_iova + pkt[3]->data_off,
 884                                  hi_qw2,
 885                                  pkt[2]->buf_iova + pkt[2]->data_off);
 886                 __m256i desc0_1 =
 887                         _mm256_set_epi64x
 888                                 (hi_qw1,
 889                                  pkt[1]->buf_iova + pkt[1]->data_off,
 890                                  hi_qw0,
 891                                  pkt[0]->buf_iova + pkt[0]->data_off);
 892                 _mm256_store_si256((void *)(txdp + 2), desc2_3);
 893                 _mm256_store_si256((void *)txdp, desc0_1);
 894         }
 895
 896         /* do any last ones */
 897         while (nb_pkts) {
 898                 ice_vtx1(txdp, *pkt, flags);
 899                 txdp++, pkt++, nb_pkts--;
 900         }
 901 }
 902
 903 static inline uint16_t
 904 ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 905                               uint16_t nb_pkts)
 906 {
 907         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 908         volatile struct ice_tx_desc *txdp;
 909         struct ice_tx_entry *txep;
 910         uint16_t n, nb_commit, tx_id;
 911         uint64_t flags = ICE_TD_CMD;
 912         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
 913
 914         /* cross rx_thresh boundary is not allowed */
 915         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 916
 917         if (txq->nb_tx_free < txq->tx_free_thresh)
 918                 ice_tx_free_bufs(txq);
 919
 920         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 921         if (unlikely(nb_pkts == 0))
 922                 return 0;
 923
 924         tx_id = txq->tx_tail;
 925         txdp = &txq->tx_ring[tx_id];
 926         txep = &txq->sw_ring[tx_id];
 927
 928         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 929
 930         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 931         if (nb_commit >= n) {
 932                 ice_tx_backlog_entry(txep, tx_pkts, n);
 933
 934                 ice_vtx(txdp, tx_pkts, n - 1, flags);
 935                 tx_pkts += (n - 1);
 936                 txdp += (n - 1);
 937
 938                 ice_vtx1(txdp, *tx_pkts++, rs);
 939
 940                 nb_commit = (uint16_t)(nb_commit - n);
 941
 942                 tx_id = 0;
 943                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 944
 945                 /* avoid reach the end of ring */
 946                 txdp = &txq->tx_ring[tx_id];
 947                 txep = &txq->sw_ring[tx_id];
 948         }
 949
 950         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
 951
 952         ice_vtx(txdp, tx_pkts, nb_commit, flags);
 953
 954         tx_id = (uint16_t)(tx_id + nb_commit);
 955         if (tx_id > txq->tx_next_rs) {
 956                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 957                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
 958                                          ICE_TXD_QW1_CMD_S);
 959                 txq->tx_next_rs =
 960                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 961         }
 962
 963         txq->tx_tail = tx_id;
 964
 965         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
 966
 967         return nb_pkts;
 968 }
 969
 970 uint16_t
 971 ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 972                        uint16_t nb_pkts)
 973 {
 974         uint16_t nb_tx = 0;
 975         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 976
 977         while (nb_pkts) {
 978                 uint16_t ret, num;
 979
 980                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 981                 ret = ice_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
 982                                                     num);
 983                 nb_tx += ret;
 984                 nb_pkts -= ret;
 985                 if (ret < num)
 986                         break;
 987         }
 988
 989         return nb_tx;
 990 }