drivers/net/ice/ice_rxtx_vec_avx2.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 static inline void
  14 ice_rxq_rearm(struct ice_rx_queue *rxq)
  15 {
  16         int i;
  17         uint16_t rx_id;
  18         volatile union ice_rx_flex_desc *rxdp;
  19         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  20
  21         rxdp = (union ice_rx_flex_desc *)rxq->rx_ring + rxq->rxrearm_start;
  22
  23         /* Pull 'n' more MBUFs into the software ring */
  24         if (rte_mempool_get_bulk(rxq->mp,
  25                                  (void *)rxep,
  26                                  ICE_RXQ_REARM_THRESH) < 0) {
  27                 if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  28                     rxq->nb_rx_desc) {
  29                         __m128i dma_addr0;
  30
  31                         dma_addr0 = _mm_setzero_si128();
  32                         for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  33                                 rxep[i].mbuf = &rxq->fake_mbuf;
  34                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  35                                                 dma_addr0);
  36                         }
  37                 }
  38                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  39                         ICE_RXQ_REARM_THRESH;
  40                 return;
  41         }
  42
  43 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  44         struct rte_mbuf *mb0, *mb1;
  45         __m128i dma_addr0, dma_addr1;
  46         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  47                         RTE_PKTMBUF_HEADROOM);
  48         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  49         for (i = 0; i < ICE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  50                 __m128i vaddr0, vaddr1;
  51
  52                 mb0 = rxep[0].mbuf;
  53                 mb1 = rxep[1].mbuf;
  54
  55                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  56                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  57                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  58                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  59                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  60
  61                 /* convert pa to dma_addr hdr/data */
  62                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  63                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  64
  65                 /* add headroom to pa values */
  66                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  67                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  68
  69                 /* flush desc with pa dma_addr */
  70                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  71                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  72         }
  73 #else
  74         struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
  75         __m256i dma_addr0_1, dma_addr2_3;
  76         __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
  77         /* Initialize the mbufs in vector, process 4 mbufs in one loop */
  78         for (i = 0; i < ICE_RXQ_REARM_THRESH;
  79                         i += 4, rxep += 4, rxdp += 4) {
  80                 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
  81                 __m256i vaddr0_1, vaddr2_3;
  82
  83                 mb0 = rxep[0].mbuf;
  84                 mb1 = rxep[1].mbuf;
  85                 mb2 = rxep[2].mbuf;
  86                 mb3 = rxep[3].mbuf;
  87
  88                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  89                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  90                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  91                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  92                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  93                 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
  94                 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
  95
  96                 /**
  97                  * merge 0 & 1, by casting 0 to 256-bit and inserting 1
  98                  * into the high lanes. Similarly for 2 & 3
  99                  */
 100                 vaddr0_1 =
 101                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 102                                                 vaddr1, 1);
 103                 vaddr2_3 =
 104                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 105                                                 vaddr3, 1);
 106
 107                 /* convert pa to dma_addr hdr/data */
 108                 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
 109                 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
 110
 111                 /* add headroom to pa values */
 112                 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
 113                 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
 114
 115                 /* flush desc with pa dma_addr */
 116                 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
 117                 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
 118         }
 119
 120 #endif
 121
 122         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
 123         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 124                 rxq->rxrearm_start = 0;
 125
 126         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
 127
 128         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 129                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 130
 131         /* Update the tail pointer on the NIC */
 132         ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 133 }
 134
 135 static inline uint16_t
 136 _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 137                             uint16_t nb_pkts, uint8_t *split_packet)
 138 {
 139 #define ICE_DESCS_PER_LOOP_AVX 8
 140
 141         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 142         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 143                         0, rxq->mbuf_initializer);
 144         struct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
 145         volatile union ice_rx_flex_desc *rxdp =
 146                 (union ice_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 147         const int avx_aligned = ((rxq->rx_tail & 1) == 0);
 148
 149         rte_prefetch0(rxdp);
 150
 151         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */
 152         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);
 153
 154         /* See if we need to rearm the RX queue - gives the prefetch a bit
 155          * of time to act
 156          */
 157         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 158                 ice_rxq_rearm(rxq);
 159
 160         /* Before we start moving massive data around, check to see if
 161          * there is actually a packet available
 162          */
 163         if (!(rxdp->wb.status_error0 &
 164                         rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 165                 return 0;
 166
 167         /* constants used in processing loop */
 168         const __m256i crc_adjust =
 169                 _mm256_set_epi16
 170                         (/* first descriptor */
 171                          0, 0, 0,       /* ignore non-length fields */
 172                          -rxq->crc_len, /* sub crc on data_len */
 173                          0,             /* ignore high-16bits of pkt_len */
 174                          -rxq->crc_len, /* sub crc on pkt_len */
 175                          0, 0,          /* ignore pkt_type field */
 176                          /* second descriptor */
 177                          0, 0, 0,       /* ignore non-length fields */
 178                          -rxq->crc_len, /* sub crc on data_len */
 179                          0,             /* ignore high-16bits of pkt_len */
 180                          -rxq->crc_len, /* sub crc on pkt_len */
 181                          0, 0           /* ignore pkt_type field */
 182                         );
 183
 184         /* 8 packets DD mask, LSB in each 32-bit value */
 185         const __m256i dd_check = _mm256_set1_epi32(1);
 186
 187         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 188         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 189                         ICE_RX_DESC_STATUS_EOF_S);
 190
 191         /* mask to shuffle from desc. to mbuf (2 descriptors)*/
 192         const __m256i shuf_msk =
 193                 _mm256_set_epi8
 194                         (/* first descriptor */
 195                          0xFF, 0xFF,
 196                          0xFF, 0xFF,    /* rss not supported */
 197                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 198                          5, 4,          /* octet 4~5, 16 bits data_len */
 199                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 200                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 201                          0xFF, 0xFF,    /* pkt_type set as unknown */
 202                          0xFF, 0xFF,    /*pkt_type set as unknown */
 203                          /* second descriptor */
 204                          0xFF, 0xFF,
 205                          0xFF, 0xFF,    /* rss not supported */
 206                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
 207                          5, 4,          /* octet 4~5, 16 bits data_len */
 208                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
 209                          5, 4,          /* octet 4~5, 16 bits pkt_len */
 210                          0xFF, 0xFF,    /* pkt_type set as unknown */
 211                          0xFF, 0xFF     /*pkt_type set as unknown */
 212                         );
 213         /**
 214          * compile-time check the above crc and shuffle layout is correct.
 215          * NOTE: the first field (lowest address) is given last in set_epi
 216          * calls above.
 217          */
 218         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 219                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 220         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 221                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 222         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 223                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 224         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 225                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 226
 227         /* Status/Error flag masks */
 228         /**
 229          * mask everything except Checksum Reports, RSS indication
 230          * and VLAN indication.
 231          * bit6:4 for IP/L4 checksum errors.
 232          * bit12 is for RSS indication.
 233          * bit13 is for VLAN indication.
 234          */
 235         const __m256i flags_mask =
 236                  _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 237         /**
 238          * data to be shuffled by the result of the flags mask shifted by 4
 239          * bits.  This gives use the l3_l4 flags.
 240          */
 241         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 242                         /* shift right 1 bit to make sure it not exceed 255 */
 243                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 244                          PKT_RX_IP_CKSUM_BAD) >> 1,
 245                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 246                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 247                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 248                          PKT_RX_IP_CKSUM_BAD) >> 1,
 249                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 250                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 251                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 252                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 253                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 254                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 255                         /* second 128-bits */
 256                         0, 0, 0, 0, 0, 0, 0, 0,
 257                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 258                          PKT_RX_IP_CKSUM_BAD) >> 1,
 259                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 260                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 261                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 262                          PKT_RX_IP_CKSUM_BAD) >> 1,
 263                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 264                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 265                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 266                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 267                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 268                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 269         const __m256i cksum_mask =
 270                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 271                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 272                                    PKT_RX_EIP_CKSUM_BAD);
 273         /**
 274          * data to be shuffled by result of flag mask, shifted down 12.
 275          * If RSS(bit12)/VLAN(bit13) are set,
 276          * shuffle moves appropriate flags in place.
 277          */
 278         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 279                         0, 0, 0, 0,
 280                         0, 0, 0, 0,
 281                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 282                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 283                         PKT_RX_RSS_HASH, 0,
 284                         /* end up 128-bits */
 285                         0, 0, 0, 0,
 286                         0, 0, 0, 0,
 287                         0, 0, 0, 0,
 288                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 289                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 290                         PKT_RX_RSS_HASH, 0);
 291
 292         RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
 293
 294         uint16_t i, received;
 295
 296         for (i = 0, received = 0; i < nb_pkts;
 297              i += ICE_DESCS_PER_LOOP_AVX,
 298              rxdp += ICE_DESCS_PER_LOOP_AVX) {
 299                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 300                 _mm256_storeu_si256((void *)&rx_pkts[i],
 301                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 302 #ifdef RTE_ARCH_X86_64
 303                 _mm256_storeu_si256
 304                         ((void *)&rx_pkts[i + 4],
 305                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 306 #endif
 307
 308                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 309 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 310                 /* for AVX we need alignment otherwise loads are not atomic */
 311                 if (avx_aligned) {
 312                         /* load in descriptors, 2 at a time, in reverse order */
 313                         raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
 314                         rte_compiler_barrier();
 315                         raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
 316                         rte_compiler_barrier();
 317                         raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
 318                         rte_compiler_barrier();
 319                         raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
 320                 } else
 321 #endif
 322                 {
 323                         const __m128i raw_desc7 =
 324                                 _mm_load_si128((void *)(rxdp + 7));
 325                         rte_compiler_barrier();
 326                         const __m128i raw_desc6 =
 327                                 _mm_load_si128((void *)(rxdp + 6));
 328                         rte_compiler_barrier();
 329                         const __m128i raw_desc5 =
 330                                 _mm_load_si128((void *)(rxdp + 5));
 331                         rte_compiler_barrier();
 332                         const __m128i raw_desc4 =
 333                                 _mm_load_si128((void *)(rxdp + 4));
 334                         rte_compiler_barrier();
 335                         const __m128i raw_desc3 =
 336                                 _mm_load_si128((void *)(rxdp + 3));
 337                         rte_compiler_barrier();
 338                         const __m128i raw_desc2 =
 339                                 _mm_load_si128((void *)(rxdp + 2));
 340                         rte_compiler_barrier();
 341                         const __m128i raw_desc1 =
 342                                 _mm_load_si128((void *)(rxdp + 1));
 343                         rte_compiler_barrier();
 344                         const __m128i raw_desc0 =
 345                                 _mm_load_si128((void *)(rxdp + 0));
 346
 347                         raw_desc6_7 =
 348                                 _mm256_inserti128_si256
 349                                         (_mm256_castsi128_si256(raw_desc6),
 350                                          raw_desc7, 1);
 351                         raw_desc4_5 =
 352                                 _mm256_inserti128_si256
 353                                         (_mm256_castsi128_si256(raw_desc4),
 354                                          raw_desc5, 1);
 355                         raw_desc2_3 =
 356                                 _mm256_inserti128_si256
 357                                         (_mm256_castsi128_si256(raw_desc2),
 358                                          raw_desc3, 1);
 359                         raw_desc0_1 =
 360                                 _mm256_inserti128_si256
 361                                         (_mm256_castsi128_si256(raw_desc0),
 362                                          raw_desc1, 1);
 363                 }
 364
 365                 if (split_packet) {
 366                         int j;
 367
 368                         for (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)
 369                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 370                 }
 371
 372                 /**
 373                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 374                  * Then write into the mbuf.
 375                  */
 376                 __m256i mb6_7 = _mm256_shuffle_epi8(raw_desc6_7, shuf_msk);
 377                 __m256i mb4_5 = _mm256_shuffle_epi8(raw_desc4_5, shuf_msk);
 378
 379                 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
 380                 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
 381                 /**
 382                  * to get packet types, ptype is located in bit16-25
 383                  * of each 128bits
 384                  */
 385                 const __m256i ptype_mask =
 386                         _mm256_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);
 387                 const __m256i ptypes6_7 =
 388                         _mm256_and_si256(raw_desc6_7, ptype_mask);
 389                 const __m256i ptypes4_5 =
 390                         _mm256_and_si256(raw_desc4_5, ptype_mask);
 391                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 392                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 393                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 394                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 395
 396                 mb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype7], 4);
 397                 mb6_7 = _mm256_insert_epi32(mb6_7, ptype_tbl[ptype6], 0);
 398                 mb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype5], 4);
 399                 mb4_5 = _mm256_insert_epi32(mb4_5, ptype_tbl[ptype4], 0);
 400                 /* merge the status bits into one register */
 401                 const __m256i status4_7 = _mm256_unpackhi_epi32(raw_desc6_7,
 402                                 raw_desc4_5);
 403
 404                 /**
 405                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 406                  * Then write into the mbuf.
 407                  */
 408                 __m256i mb2_3 = _mm256_shuffle_epi8(raw_desc2_3, shuf_msk);
 409                 __m256i mb0_1 = _mm256_shuffle_epi8(raw_desc0_1, shuf_msk);
 410
 411                 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
 412                 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
 413                 /**
 414                  * to get packet types, ptype is located in bit16-25
 415                  * of each 128bits
 416                  */
 417                 const __m256i ptypes2_3 =
 418                         _mm256_and_si256(raw_desc2_3, ptype_mask);
 419                 const __m256i ptypes0_1 =
 420                         _mm256_and_si256(raw_desc0_1, ptype_mask);
 421                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 422                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 423                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 424                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 425
 426                 mb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype3], 4);
 427                 mb2_3 = _mm256_insert_epi32(mb2_3, ptype_tbl[ptype2], 0);
 428                 mb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype1], 4);
 429                 mb0_1 = _mm256_insert_epi32(mb0_1, ptype_tbl[ptype0], 0);
 430                 /* merge the status bits into one register */
 431                 const __m256i status0_3 = _mm256_unpackhi_epi32(raw_desc2_3,
 432                                                                 raw_desc0_1);
 433
 434                 /**
 435                  * take the two sets of status bits and merge to one
 436                  * After merge, the packets status flags are in the
 437                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 438                  */
 439                 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
 440                                                           status0_3);
 441
 442                 /* now do flag manipulation */
 443
 444                 /* get only flag/error bits we want */
 445                 const __m256i flag_bits =
 446                         _mm256_and_si256(status0_7, flags_mask);
 447                 /**
 448                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 449                  * of flags in flags_shuf, and finally mask out extra bits
 450                  */
 451                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 452                                 _mm256_srli_epi32(flag_bits, 4));
 453                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 454                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 455                 /* set rss and vlan flags */
 456                 const __m256i rss_vlan_flag_bits =
 457                         _mm256_srli_epi32(flag_bits, 12);
 458                 const __m256i rss_vlan_flags =
 459                         _mm256_shuffle_epi8(rss_vlan_flags_shuf,
 460                                             rss_vlan_flag_bits);
 461
 462                 /* merge flags */
 463                 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 464                                 rss_vlan_flags);
 465                 /**
 466                  * At this point, we have the 8 sets of flags in the low 16-bits
 467                  * of each 32-bit value in vlan0.
 468                  * We want to extract these, and merge them with the mbuf init
 469                  * data so we can do a single write to the mbuf to set the flags
 470                  * and all the other initialization fields. Extracting the
 471                  * appropriate flags means that we have to do a shift and blend
 472                  * for each mbuf before we do the write. However, we can also
 473                  * add in the previously computed rx_descriptor fields to
 474                  * make a single 256-bit write per mbuf
 475                  */
 476                 /* check the structure matches expectations */
 477                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 478                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 479                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 480                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 481                                                     rearm_data),
 482                                            16));
 483                 /* build up data and do writes */
 484                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 485                         rearm6, rearm7;
 486                 rearm6 = _mm256_blend_epi32(mbuf_init,
 487                                             _mm256_slli_si256(mbuf_flags, 8),
 488                                             0x04);
 489                 rearm4 = _mm256_blend_epi32(mbuf_init,
 490                                             _mm256_slli_si256(mbuf_flags, 4),
 491                                             0x04);
 492                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 493                 rearm0 = _mm256_blend_epi32(mbuf_init,
 494                                             _mm256_srli_si256(mbuf_flags, 4),
 495                                             0x04);
 496                 /* permute to add in the rx_descriptor e.g. rss fields */
 497                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 498                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 499                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 500                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 501                 /* write to mbuf */
 502                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 503                                     rearm6);
 504                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 505                                     rearm4);
 506                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 507                                     rearm2);
 508                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 509                                     rearm0);
 510
 511                 /* repeat for the odd mbufs */
 512                 const __m256i odd_flags =
 513                         _mm256_castsi128_si256
 514                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 515                 rearm7 = _mm256_blend_epi32(mbuf_init,
 516                                             _mm256_slli_si256(odd_flags, 8),
 517                                             0x04);
 518                 rearm5 = _mm256_blend_epi32(mbuf_init,
 519                                             _mm256_slli_si256(odd_flags, 4),
 520                                             0x04);
 521                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 522                 rearm1 = _mm256_blend_epi32(mbuf_init,
 523                                             _mm256_srli_si256(odd_flags, 4),
 524                                             0x04);
 525                 /* since odd mbufs are already in hi 128-bits use blend */
 526                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 527                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 528                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 529                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 530                 /* again write to mbufs */
 531                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 532                                     rearm7);
 533                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 534                                     rearm5);
 535                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 536                                     rearm3);
 537                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 538                                     rearm1);
 539
 540                 /* extract and record EOP bit */
 541                 if (split_packet) {
 542                         const __m128i eop_mask =
 543                                 _mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);
 544                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 545                                                                      eop_check);
 546                         /* pack status bits into a single 128-bit register */
 547                         const __m128i eop_bits =
 548                                 _mm_packus_epi32
 549                                         (_mm256_castsi256_si128(eop_bits256),
 550                                          _mm256_extractf128_si256(eop_bits256,
 551                                                                   1));
 552                         /**
 553                          * flip bits, and mask out the EOP bit, which is now
 554                          * a split-packet bit i.e. !EOP, rather than EOP one.
 555                          */
 556                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 557                                         eop_mask);
 558                         /**
 559                          * eop bits are out of order, so we need to shuffle them
 560                          * back into order again. In doing so, only use low 8
 561                          * bits, which acts like another pack instruction
 562                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 563                          * [Since we use epi8, the 16-bit positions are
 564                          * multiplied by 2 in the eop_shuffle value.]
 565                          */
 566                         __m128i eop_shuffle =
 567                                 _mm_set_epi8(/* zero hi 64b */
 568                                              0xFF, 0xFF, 0xFF, 0xFF,
 569                                              0xFF, 0xFF, 0xFF, 0xFF,
 570                                              /* move values to lo 64b */
 571                                              8, 0, 10, 2,
 572                                              12, 4, 14, 6);
 573                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 574                         *(uint64_t *)split_packet =
 575                                 _mm_cvtsi128_si64(split_bits);
 576                         split_packet += ICE_DESCS_PER_LOOP_AVX;
 577                 }
 578
 579                 /* perform dd_check */
 580                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 581                 status0_7 = _mm256_packs_epi32(status0_7,
 582                                                _mm256_setzero_si256());
 583
 584                 uint64_t burst = __builtin_popcountll
 585                                         (_mm_cvtsi128_si64
 586                                                 (_mm256_extracti128_si256
 587                                                         (status0_7, 1)));
 588                 burst += __builtin_popcountll
 589                                 (_mm_cvtsi128_si64
 590                                         (_mm256_castsi256_si128(status0_7)));
 591                 received += burst;
 592                 if (burst != ICE_DESCS_PER_LOOP_AVX)
 593                         break;
 594         }
 595
 596         /* update tail pointers */
 597         rxq->rx_tail += received;
 598         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 599         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 600                 rxq->rx_tail--;
 601                 received--;
 602         }
 603         rxq->rxrearm_nb += received;
 604         return received;
 605 }
 606
 607 /**
 608  * Notice:
 609  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 610  */
 611 uint16_t
 612 ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 613                        uint16_t nb_pkts)
 614 {
 615         return _ice_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
 616 }
 617
 618 /**
 619  * vPMD receive routine that reassembles single burst of 32 scattered packets
 620  * Notice:
 621  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 622  */
 623 static uint16_t
 624 ice_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 625                                   uint16_t nb_pkts)
 626 {
 627         struct ice_rx_queue *rxq = rx_queue;
 628         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 629
 630         /* get some new buffers */
 631         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
 632                                                        split_flags);
 633         if (nb_bufs == 0)
 634                 return 0;
 635
 636         /* happy day case, full burst + no packets to be joined */
 637         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 638
 639         if (!rxq->pkt_first_seg &&
 640             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 641             split_fl64[2] == 0 && split_fl64[3] == 0)
 642                 return nb_bufs;
 643
 644         /* reassemble any packets that need reassembly*/
 645         unsigned int i = 0;
 646
 647         if (!rxq->pkt_first_seg) {
 648                 /* find the first split flag, and only reassemble then*/
 649                 while (i < nb_bufs && !split_flags[i])
 650                         i++;
 651                 if (i == nb_bufs)
 652                         return nb_bufs;
 653                 rxq->pkt_first_seg = rx_pkts[i];
 654         }
 655         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 656                                              &split_flags[i]);
 657 }
 658
 659 /**
 660  * vPMD receive routine that reassembles scattered packets.
 661  * Main receive routine that can handle arbitrary burst sizes
 662  * Notice:
 663  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 664  */
 665 uint16_t
 666 ice_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 667                                  uint16_t nb_pkts)
 668 {
 669         uint16_t retval = 0;
 670
 671         while (nb_pkts > ICE_VPMD_RX_BURST) {
 672                 uint16_t burst = ice_recv_scattered_burst_vec_avx2(rx_queue,
 673                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 674                 retval += burst;
 675                 nb_pkts -= burst;
 676                 if (burst < ICE_VPMD_RX_BURST)
 677                         return retval;
 678         }
 679         return retval + ice_recv_scattered_burst_vec_avx2(rx_queue,
 680                                 rx_pkts + retval, nb_pkts);
 681 }
 682
 683 static inline void
 684 ice_vtx1(volatile struct ice_tx_desc *txdp,
 685          struct rte_mbuf *pkt, uint64_t flags)
 686 {
 687         uint64_t high_qw =
 688                 (ICE_TX_DESC_DTYPE_DATA |
 689                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
 690                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
 691
 692         __m128i descriptor = _mm_set_epi64x(high_qw,
 693                                 pkt->buf_physaddr + pkt->data_off);
 694         _mm_store_si128((__m128i *)txdp, descriptor);
 695 }
 696
 697 static inline void
 698 ice_vtx(volatile struct ice_tx_desc *txdp,
 699         struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 700 {
 701         const uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |
 702                         ((uint64_t)flags  << ICE_TXD_QW1_CMD_S));
 703
 704         /* if unaligned on 32-bit boundary, do one to align */
 705         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
 706                 ice_vtx1(txdp, *pkt, flags);
 707                 nb_pkts--, txdp++, pkt++;
 708         }
 709
 710         /* do two at a time while possible, in bursts */
 711         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
 712                 uint64_t hi_qw3 =
 713                         hi_qw_tmpl |
 714                         ((uint64_t)pkt[3]->data_len <<
 715                          ICE_TXD_QW1_TX_BUF_SZ_S);
 716                 uint64_t hi_qw2 =
 717                         hi_qw_tmpl |
 718                         ((uint64_t)pkt[2]->data_len <<
 719                          ICE_TXD_QW1_TX_BUF_SZ_S);
 720                 uint64_t hi_qw1 =
 721                         hi_qw_tmpl |
 722                         ((uint64_t)pkt[1]->data_len <<
 723                          ICE_TXD_QW1_TX_BUF_SZ_S);
 724                 uint64_t hi_qw0 =
 725                         hi_qw_tmpl |
 726                         ((uint64_t)pkt[0]->data_len <<
 727                          ICE_TXD_QW1_TX_BUF_SZ_S);
 728
 729                 __m256i desc2_3 =
 730                         _mm256_set_epi64x
 731                                 (hi_qw3,
 732                                  pkt[3]->buf_physaddr + pkt[3]->data_off,
 733                                  hi_qw2,
 734                                  pkt[2]->buf_physaddr + pkt[2]->data_off);
 735                 __m256i desc0_1 =
 736                         _mm256_set_epi64x
 737                                 (hi_qw1,
 738                                  pkt[1]->buf_physaddr + pkt[1]->data_off,
 739                                  hi_qw0,
 740                                  pkt[0]->buf_physaddr + pkt[0]->data_off);
 741                 _mm256_store_si256((void *)(txdp + 2), desc2_3);
 742                 _mm256_store_si256((void *)txdp, desc0_1);
 743         }
 744
 745         /* do any last ones */
 746         while (nb_pkts) {
 747                 ice_vtx1(txdp, *pkt, flags);
 748                 txdp++, pkt++, nb_pkts--;
 749         }
 750 }
 751
 752 static inline uint16_t
 753 ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 754                               uint16_t nb_pkts)
 755 {
 756         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 757         volatile struct ice_tx_desc *txdp;
 758         struct ice_tx_entry *txep;
 759         uint16_t n, nb_commit, tx_id;
 760         uint64_t flags = ICE_TD_CMD;
 761         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
 762
 763         /* cross rx_thresh boundary is not allowed */
 764         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 765
 766         if (txq->nb_tx_free < txq->tx_free_thresh)
 767                 ice_tx_free_bufs(txq);
 768
 769         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 770         if (unlikely(nb_pkts == 0))
 771                 return 0;
 772
 773         tx_id = txq->tx_tail;
 774         txdp = &txq->tx_ring[tx_id];
 775         txep = &txq->sw_ring[tx_id];
 776
 777         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 778
 779         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 780         if (nb_commit >= n) {
 781                 ice_tx_backlog_entry(txep, tx_pkts, n);
 782
 783                 ice_vtx(txdp, tx_pkts, n - 1, flags);
 784                 tx_pkts += (n - 1);
 785                 txdp += (n - 1);
 786
 787                 ice_vtx1(txdp, *tx_pkts++, rs);
 788
 789                 nb_commit = (uint16_t)(nb_commit - n);
 790
 791                 tx_id = 0;
 792                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 793
 794                 /* avoid reach the end of ring */
 795                 txdp = &txq->tx_ring[tx_id];
 796                 txep = &txq->sw_ring[tx_id];
 797         }
 798
 799         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
 800
 801         ice_vtx(txdp, tx_pkts, nb_commit, flags);
 802
 803         tx_id = (uint16_t)(tx_id + nb_commit);
 804         if (tx_id > txq->tx_next_rs) {
 805                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 806                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
 807                                          ICE_TXD_QW1_CMD_S);
 808                 txq->tx_next_rs =
 809                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 810         }
 811
 812         txq->tx_tail = tx_id;
 813
 814         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 815
 816         return nb_pkts;
 817 }
 818
 819 uint16_t
 820 ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 821                        uint16_t nb_pkts)
 822 {
 823         uint16_t nb_tx = 0;
 824         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 825
 826         while (nb_pkts) {
 827                 uint16_t ret, num;
 828
 829                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 830                 ret = ice_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
 831                                                     num);
 832                 nb_tx += ret;
 833                 nb_pkts -= ret;
 834                 if (ret < num)
 835                         break;
 836         }
 837
 838         return nb_tx;
 839 }