drivers/net/ice/ice_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <rte_vect.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define ICE_DESCS_PER_LOOP_AVX 8
  14
  15 static inline void
  16 ice_rxq_rearm(struct ice_rx_queue *rxq)
  17 {
  18         int i;
  19         uint16_t rx_id;
  20         volatile union ice_rx_flex_desc *rxdp;
  21         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  22         struct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,
  23                         rte_lcore_id());
  24
  25         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  26
  27         /* We need to pull 'n' more MBUFs into the software ring */
  28         if (cache->len < ICE_RXQ_REARM_THRESH) {
  29                 uint32_t req = ICE_RXQ_REARM_THRESH + (cache->size -
  30                                 cache->len);
  31
  32                 int ret = rte_mempool_ops_dequeue_bulk(rxq->mp,
  33                                 &cache->objs[cache->len], req);
  34                 if (ret == 0) {
  35                         cache->len += req;
  36                 } else {
  37                         if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  38                             rxq->nb_rx_desc) {
  39                                 __m128i dma_addr0;
  40
  41                                 dma_addr0 = _mm_setzero_si128();
  42                                 for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  43                                         rxep[i].mbuf = &rxq->fake_mbuf;
  44                                         _mm_store_si128
  45                                                 ((__m128i *)&rxdp[i].read,
  46                                                         dma_addr0);
  47                                 }
  48                         }
  49                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  50                                 ICE_RXQ_REARM_THRESH;
  51                         return;
  52                 }
  53         }
  54
  55         const __m512i iova_offsets =  _mm512_set1_epi64
  56                 (offsetof(struct rte_mbuf, buf_iova));
  57         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  58
  59 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  60         /* shuffle the iova into correct slots. Values 4-7 will contain
  61          * zeros, so use 7 for a zero-value.
  62          */
  63         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  64 #else
  65         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  66 #endif
  67
  68         /* fill up the rxd in vector, process 8 mbufs in one loop */
  69         for (i = 0; i < ICE_RXQ_REARM_THRESH / 8; i++) {
  70                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  71                         (&cache->objs[cache->len - 8]);
  72                 _mm512_store_si512(rxep, mbuf_ptrs);
  73
  74                 /* gather iova of mbuf0-7 into one zmm reg */
  75                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
  76                         (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
  77                                 0, /* base */
  78                                 1  /* scale */);
  79                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
  80                                 headroom);
  81 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  82                 const __m512i iovas0 = _mm512_castsi256_si512
  83                         (_mm512_extracti64x4_epi64(iova_addrs, 0));
  84                 const __m512i iovas1 = _mm512_castsi256_si512
  85                         (_mm512_extracti64x4_epi64(iova_addrs, 1));
  86
  87                 /* permute leaves iova 2-3 in hdr_addr of desc 0-1
  88                  * but these are ignored by driver since header split not
  89                  * enabled. Similarly for desc 4 & 5.
  90                  */
  91                 const __m512i desc0_1 = _mm512_permutexvar_epi64
  92                         (permute_idx, iovas0);
  93                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
  94
  95                 const __m512i desc4_5 = _mm512_permutexvar_epi64
  96                         (permute_idx, iovas1);
  97                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
  98
  99                 _mm512_store_si512((void *)rxdp, desc0_1);
 100                 _mm512_store_si512((void *)(rxdp + 2), desc2_3);
 101                 _mm512_store_si512((void *)(rxdp + 4), desc4_5);
 102                 _mm512_store_si512((void *)(rxdp + 6), desc6_7);
 103 #else
 104                 /* permute leaves iova 4-7 in hdr_addr of desc 0-3
 105                  * but these are ignored by driver since header split not
 106                  * enabled.
 107                  */
 108                 const __m512i desc0_3 = _mm512_permutexvar_epi64
 109                         (permute_idx, iova_addrs);
 110                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 111
 112                 _mm512_store_si512((void *)rxdp, desc0_3);
 113                 _mm512_store_si512((void *)(rxdp + 4), desc4_7);
 114 #endif
 115                 rxep += 8, rxdp += 8, cache->len -= 8;
 116         }
 117
 118         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
 119         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 120                 rxq->rxrearm_start = 0;
 121
 122         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
 123
 124         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 125                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 126
 127         /* Update the tail pointer on the NIC */
 128         ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 129 }
 130
 131 static inline __m256i
 132 ice_flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
 133 {
 134 #define FDID_MIS_MAGIC 0xFFFFFFFF
 135         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
 136         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
 137         const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
 138                         PKT_RX_FDIR_ID);
 139         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 140         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 141         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 142                         fdir_mis_mask);
 143         /* this XOR op results to bit-reverse the fdir_mask */
 144         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 145         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 146
 147         return fdir_flags;
 148 }
 149
 150 static inline uint16_t
 151 _ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq,
 152                               struct rte_mbuf **rx_pkts,
 153                               uint16_t nb_pkts, uint8_t *split_packet)
 154 {
 155         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 156         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 157                         0, rxq->mbuf_initializer);
 158         struct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
 159         volatile union ice_rx_flex_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 160
 161         rte_prefetch0(rxdp);
 162
 163         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */
 164         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);
 165
 166         /* See if we need to rearm the RX queue - gives the prefetch a bit
 167          * of time to act
 168          */
 169         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 170                 ice_rxq_rearm(rxq);
 171
 172         /* Before we start moving massive data around, check to see if
 173          * there is actually a packet available
 174          */
 175         if (!(rxdp->wb.status_error0 &
 176                         rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 177                 return 0;
 178
 179         /* constants used in processing loop */
 180         const __m512i crc_adjust =
 181                 _mm512_set4_epi32
 182                         (0,             /* ignore non-length fields */
 183                          -rxq->crc_len, /* sub crc on data_len */
 184                          -rxq->crc_len, /* sub crc on pkt_len */
 185                          0              /* ignore non-length fields */
 186                         );
 187
 188         /* 8 packets DD mask, LSB in each 32-bit value */
 189         const __m256i dd_check = _mm256_set1_epi32(1);
 190
 191         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 192         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 193                         ICE_RX_DESC_STATUS_EOF_S);
 194
 195         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 196         const __m512i shuf_msk =
 197                 _mm512_set4_epi32
 198                         (/* rss hash parsed separately */
 199                          0xFFFFFFFF,
 200                          /* octet 10~11, 16 bits vlan_macip */
 201                          /* octet 4~5, 16 bits data_len */
 202                          11 << 24 | 10 << 16 | 5 << 8 | 4,
 203                          /* skip hi 16 bits pkt_len, zero out */
 204                          /* octet 4~5, 16 bits pkt_len */
 205                          0xFFFF << 16 | 5 << 8 | 4,
 206                          /* pkt_type set as unknown */
 207                          0xFFFFFFFF
 208                         );
 209
 210         /**
 211          * compile-time check the above crc and shuffle layout is correct.
 212          * NOTE: the first field (lowest address) is given last in set_epi
 213          * calls above.
 214          */
 215         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 216                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 217         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 218                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 219         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 220                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 221         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 222                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 223
 224         /* Status/Error flag masks */
 225         /**
 226          * mask everything except Checksum Reports, RSS indication
 227          * and VLAN indication.
 228          * bit6:4 for IP/L4 checksum errors.
 229          * bit12 is for RSS indication.
 230          * bit13 is for VLAN indication.
 231          */
 232         const __m256i flags_mask =
 233                  _mm256_set1_epi32((0xF << 4) | (1 << 12) | (1 << 13));
 234         /**
 235          * data to be shuffled by the result of the flags mask shifted by 4
 236          * bits.  This gives use the l3_l4 flags.
 237          */
 238         const __m256i l3_l4_flags_shuf =
 239                 _mm256_set_epi8((PKT_RX_OUTER_L4_CKSUM_BAD >> 20 |
 240                  PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 241                   PKT_RX_IP_CKSUM_BAD) >> 1,
 242                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 243                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 244                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 245                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 246                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 247                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 248                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 249                  PKT_RX_IP_CKSUM_BAD) >> 1,
 250                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 251                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 252                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 253                  PKT_RX_IP_CKSUM_BAD) >> 1,
 254                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 255                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 256                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 257                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 258                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 259                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 260                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 261                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 262                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 263                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 264                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 265                  PKT_RX_IP_CKSUM_BAD) >> 1,
 266                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 267                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 268                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 269                  PKT_RX_IP_CKSUM_BAD) >> 1,
 270                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 271                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 272                 /**
 273                  * second 128-bits
 274                  * shift right 20 bits to use the low two bits to indicate
 275                  * outer checksum status
 276                  * shift right 1 bit to make sure it not exceed 255
 277                  */
 278                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 279                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 280                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 281                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 282                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 283                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 284                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 285                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 286                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 287                  PKT_RX_IP_CKSUM_BAD) >> 1,
 288                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 289                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 290                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 291                  PKT_RX_IP_CKSUM_BAD) >> 1,
 292                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 293                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 294                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 295                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 296                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 297                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 298                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 299                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 300                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 301                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 302                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 303                  PKT_RX_IP_CKSUM_BAD) >> 1,
 304                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 305                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 306                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 307                  PKT_RX_IP_CKSUM_BAD) >> 1,
 308                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 309                  PKT_RX_IP_CKSUM_GOOD) >> 1);
 310         const __m256i cksum_mask =
 311                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_MASK |
 312                                    PKT_RX_L4_CKSUM_MASK |
 313                                    PKT_RX_OUTER_IP_CKSUM_BAD |
 314                                    PKT_RX_OUTER_L4_CKSUM_MASK);
 315         /**
 316          * data to be shuffled by result of flag mask, shifted down 12.
 317          * If RSS(bit12)/VLAN(bit13) are set,
 318          * shuffle moves appropriate flags in place.
 319          */
 320         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 321                         0, 0, 0, 0,
 322                         0, 0, 0, 0,
 323                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 324                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 325                         PKT_RX_RSS_HASH, 0,
 326                         /* 2nd 128-bits */
 327                         0, 0, 0, 0,
 328                         0, 0, 0, 0,
 329                         0, 0, 0, 0,
 330                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 331                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 332                         PKT_RX_RSS_HASH, 0);
 333
 334         uint16_t i, received;
 335
 336         for (i = 0, received = 0; i < nb_pkts;
 337              i += ICE_DESCS_PER_LOOP_AVX,
 338              rxdp += ICE_DESCS_PER_LOOP_AVX) {
 339                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 340                 _mm256_storeu_si256((void *)&rx_pkts[i],
 341                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 342 #ifdef RTE_ARCH_X86_64
 343                 _mm256_storeu_si256
 344                         ((void *)&rx_pkts[i + 4],
 345                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 346 #endif
 347
 348                 __m512i raw_desc0_3, raw_desc4_7;
 349                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 350
 351                 /* load in descriptors, in reverse order */
 352                 const __m128i raw_desc7 =
 353                         _mm_load_si128((void *)(rxdp + 7));
 354                 rte_compiler_barrier();
 355                 const __m128i raw_desc6 =
 356                         _mm_load_si128((void *)(rxdp + 6));
 357                 rte_compiler_barrier();
 358                 const __m128i raw_desc5 =
 359                         _mm_load_si128((void *)(rxdp + 5));
 360                 rte_compiler_barrier();
 361                 const __m128i raw_desc4 =
 362                         _mm_load_si128((void *)(rxdp + 4));
 363                 rte_compiler_barrier();
 364                 const __m128i raw_desc3 =
 365                         _mm_load_si128((void *)(rxdp + 3));
 366                 rte_compiler_barrier();
 367                 const __m128i raw_desc2 =
 368                         _mm_load_si128((void *)(rxdp + 2));
 369                 rte_compiler_barrier();
 370                 const __m128i raw_desc1 =
 371                         _mm_load_si128((void *)(rxdp + 1));
 372                 rte_compiler_barrier();
 373                 const __m128i raw_desc0 =
 374                         _mm_load_si128((void *)(rxdp + 0));
 375
 376                 raw_desc6_7 =
 377                         _mm256_inserti128_si256
 378                                 (_mm256_castsi128_si256(raw_desc6),
 379                                  raw_desc7, 1);
 380                 raw_desc4_5 =
 381                         _mm256_inserti128_si256
 382                                 (_mm256_castsi128_si256(raw_desc4),
 383                                  raw_desc5, 1);
 384                 raw_desc2_3 =
 385                         _mm256_inserti128_si256
 386                                 (_mm256_castsi128_si256(raw_desc2),
 387                                  raw_desc3, 1);
 388                 raw_desc0_1 =
 389                         _mm256_inserti128_si256
 390                                 (_mm256_castsi128_si256(raw_desc0),
 391                                  raw_desc1, 1);
 392
 393                 raw_desc4_7 =
 394                         _mm512_inserti64x4
 395                                 (_mm512_castsi256_si512(raw_desc4_5),
 396                                  raw_desc6_7, 1);
 397                 raw_desc0_3 =
 398                         _mm512_inserti64x4
 399                                 (_mm512_castsi256_si512(raw_desc0_1),
 400                                  raw_desc2_3, 1);
 401
 402                 if (split_packet) {
 403                         int j;
 404
 405                         for (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)
 406                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 407                 }
 408
 409                 /**
 410                  * convert descriptors 0-7 into mbufs, re-arrange fields.
 411                  * Then write into the mbuf.
 412                  */
 413                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 414                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 415
 416                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 417                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 418
 419                 /**
 420                  * to get packet types, ptype is located in bit16-25
 421                  * of each 128bits
 422                  */
 423                 const __m512i ptype_mask =
 424                         _mm512_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);
 425
 426                 /**
 427                  * to get packet types, ptype is located in bit16-25
 428                  * of each 128bits
 429                  */
 430                 const __m512i ptypes4_7 =
 431                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 432                 const __m512i ptypes0_3 =
 433                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 434
 435                 const __m256i ptypes6_7 =
 436                         _mm512_extracti64x4_epi64(ptypes4_7, 1);
 437                 const __m256i ptypes4_5 =
 438                         _mm512_extracti64x4_epi64(ptypes4_7, 0);
 439                 const __m256i ptypes2_3 =
 440                         _mm512_extracti64x4_epi64(ptypes0_3, 1);
 441                 const __m256i ptypes0_1 =
 442                         _mm512_extracti64x4_epi64(ptypes0_3, 0);
 443                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 444                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 445                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 446                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 447                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 448                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 449                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 450                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 451
 452                 const __m512i ptype4_7 = _mm512_set_epi32
 453                         (0, 0, 0, ptype_tbl[ptype7],
 454                          0, 0, 0, ptype_tbl[ptype6],
 455                          0, 0, 0, ptype_tbl[ptype5],
 456                          0, 0, 0, ptype_tbl[ptype4]);
 457                 const __m512i ptype0_3 = _mm512_set_epi32
 458                         (0, 0, 0, ptype_tbl[ptype3],
 459                          0, 0, 0, ptype_tbl[ptype2],
 460                          0, 0, 0, ptype_tbl[ptype1],
 461                          0, 0, 0, ptype_tbl[ptype0]);
 462
 463                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 464                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 465
 466                 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 467                 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 468                 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 469                 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 470
 471                 /**
 472                  * use permute/extract to get status content
 473                  * After the operations, the packets status flags are in the
 474                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 475                  */
 476                 /* merge the status bits into one register */
 477                 const __m512i status_permute_msk = _mm512_set_epi32
 478                         (0, 0, 0, 0,
 479                          0, 0, 0, 0,
 480                          22, 30, 6, 14,
 481                          18, 26, 2, 10);
 482                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 483                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 484                 __m256i status0_7 = _mm512_extracti64x4_epi64
 485                         (raw_status0_7, 0);
 486
 487                 /* now do flag manipulation */
 488
 489                 /* get only flag/error bits we want */
 490                 const __m256i flag_bits =
 491                         _mm256_and_si256(status0_7, flags_mask);
 492                 /**
 493                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 494                  * of flags in flags_shuf, and finally mask out extra bits
 495                  */
 496                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 497                                 _mm256_srli_epi32(flag_bits, 4));
 498                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 499                 __m256i l4_outer_mask = _mm256_set1_epi32(0x6);
 500                 __m256i l4_outer_flags =
 501                                 _mm256_and_si256(l3_l4_flags, l4_outer_mask);
 502                 l4_outer_flags = _mm256_slli_epi32(l4_outer_flags, 20);
 503
 504                 __m256i l3_l4_mask = _mm256_set1_epi32(~0x6);
 505                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, l3_l4_mask);
 506                 l3_l4_flags = _mm256_or_si256(l3_l4_flags, l4_outer_flags);
 507                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 508                 /* set rss and vlan flags */
 509                 const __m256i rss_vlan_flag_bits =
 510                         _mm256_srli_epi32(flag_bits, 12);
 511                 const __m256i rss_vlan_flags =
 512                         _mm256_shuffle_epi8(rss_vlan_flags_shuf,
 513                                             rss_vlan_flag_bits);
 514
 515                 /* merge flags */
 516                 __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 517                                                      rss_vlan_flags);
 518
 519                 if (rxq->fdir_enabled) {
 520                         const __m256i fdir_id4_7 =
 521                                 _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);
 522
 523                         const __m256i fdir_id0_3 =
 524                                 _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);
 525
 526                         const __m256i fdir_id0_7 =
 527                                 _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);
 528
 529                         const __m256i fdir_flags =
 530                                 ice_flex_rxd_to_fdir_flags_vec_avx512
 531                                         (fdir_id0_7);
 532
 533                         /* merge with fdir_flags */
 534                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
 535
 536                         /* write to mbuf: have to use scalar store here */
 537                         rx_pkts[i + 0]->hash.fdir.hi =
 538                                 _mm256_extract_epi32(fdir_id0_7, 3);
 539
 540                         rx_pkts[i + 1]->hash.fdir.hi =
 541                                 _mm256_extract_epi32(fdir_id0_7, 7);
 542
 543                         rx_pkts[i + 2]->hash.fdir.hi =
 544                                 _mm256_extract_epi32(fdir_id0_7, 2);
 545
 546                         rx_pkts[i + 3]->hash.fdir.hi =
 547                                 _mm256_extract_epi32(fdir_id0_7, 6);
 548
 549                         rx_pkts[i + 4]->hash.fdir.hi =
 550                                 _mm256_extract_epi32(fdir_id0_7, 1);
 551
 552                         rx_pkts[i + 5]->hash.fdir.hi =
 553                                 _mm256_extract_epi32(fdir_id0_7, 5);
 554
 555                         rx_pkts[i + 6]->hash.fdir.hi =
 556                                 _mm256_extract_epi32(fdir_id0_7, 0);
 557
 558                         rx_pkts[i + 7]->hash.fdir.hi =
 559                                 _mm256_extract_epi32(fdir_id0_7, 4);
 560                 } /* if() on fdir_enabled */
 561
 562 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 563                 /**
 564                  * needs to load 2nd 16B of each desc for RSS hash parsing,
 565                  * will cause performance drop to get into this context.
 566                  */
 567                 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
 568                                 DEV_RX_OFFLOAD_RSS_HASH) {
 569                         /* load bottom half of every 32B desc */
 570                         const __m128i raw_desc_bh7 =
 571                                 _mm_load_si128
 572                                         ((void *)(&rxdp[7].wb.status_error1));
 573                         rte_compiler_barrier();
 574                         const __m128i raw_desc_bh6 =
 575                                 _mm_load_si128
 576                                         ((void *)(&rxdp[6].wb.status_error1));
 577                         rte_compiler_barrier();
 578                         const __m128i raw_desc_bh5 =
 579                                 _mm_load_si128
 580                                         ((void *)(&rxdp[5].wb.status_error1));
 581                         rte_compiler_barrier();
 582                         const __m128i raw_desc_bh4 =
 583                                 _mm_load_si128
 584                                         ((void *)(&rxdp[4].wb.status_error1));
 585                         rte_compiler_barrier();
 586                         const __m128i raw_desc_bh3 =
 587                                 _mm_load_si128
 588                                         ((void *)(&rxdp[3].wb.status_error1));
 589                         rte_compiler_barrier();
 590                         const __m128i raw_desc_bh2 =
 591                                 _mm_load_si128
 592                                         ((void *)(&rxdp[2].wb.status_error1));
 593                         rte_compiler_barrier();
 594                         const __m128i raw_desc_bh1 =
 595                                 _mm_load_si128
 596                                         ((void *)(&rxdp[1].wb.status_error1));
 597                         rte_compiler_barrier();
 598                         const __m128i raw_desc_bh0 =
 599                                 _mm_load_si128
 600                                         ((void *)(&rxdp[0].wb.status_error1));
 601
 602                         __m256i raw_desc_bh6_7 =
 603                                 _mm256_inserti128_si256
 604                                         (_mm256_castsi128_si256(raw_desc_bh6),
 605                                         raw_desc_bh7, 1);
 606                         __m256i raw_desc_bh4_5 =
 607                                 _mm256_inserti128_si256
 608                                         (_mm256_castsi128_si256(raw_desc_bh4),
 609                                         raw_desc_bh5, 1);
 610                         __m256i raw_desc_bh2_3 =
 611                                 _mm256_inserti128_si256
 612                                         (_mm256_castsi128_si256(raw_desc_bh2),
 613                                         raw_desc_bh3, 1);
 614                         __m256i raw_desc_bh0_1 =
 615                                 _mm256_inserti128_si256
 616                                         (_mm256_castsi128_si256(raw_desc_bh0),
 617                                         raw_desc_bh1, 1);
 618
 619                         /**
 620                          * to shift the 32b RSS hash value to the
 621                          * highest 32b of each 128b before mask
 622                          */
 623                         __m256i rss_hash6_7 =
 624                                 _mm256_slli_epi64(raw_desc_bh6_7, 32);
 625                         __m256i rss_hash4_5 =
 626                                 _mm256_slli_epi64(raw_desc_bh4_5, 32);
 627                         __m256i rss_hash2_3 =
 628                                 _mm256_slli_epi64(raw_desc_bh2_3, 32);
 629                         __m256i rss_hash0_1 =
 630                                 _mm256_slli_epi64(raw_desc_bh0_1, 32);
 631
 632                         __m256i rss_hash_msk =
 633                                 _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
 634                                                  0xFFFFFFFF, 0, 0, 0);
 635
 636                         rss_hash6_7 = _mm256_and_si256
 637                                         (rss_hash6_7, rss_hash_msk);
 638                         rss_hash4_5 = _mm256_and_si256
 639                                         (rss_hash4_5, rss_hash_msk);
 640                         rss_hash2_3 = _mm256_and_si256
 641                                         (rss_hash2_3, rss_hash_msk);
 642                         rss_hash0_1 = _mm256_and_si256
 643                                         (rss_hash0_1, rss_hash_msk);
 644
 645                         mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
 646                         mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
 647                         mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
 648                         mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
 649                 } /* if() on RSS hash parsing */
 650 #endif
 651
 652                 /**
 653                  * At this point, we have the 8 sets of flags in the low 16-bits
 654                  * of each 32-bit value in vlan0.
 655                  * We want to extract these, and merge them with the mbuf init
 656                  * data so we can do a single write to the mbuf to set the flags
 657                  * and all the other initialization fields. Extracting the
 658                  * appropriate flags means that we have to do a shift and blend
 659                  * for each mbuf before we do the write. However, we can also
 660                  * add in the previously computed rx_descriptor fields to
 661                  * make a single 256-bit write per mbuf
 662                  */
 663                 /* check the structure matches expectations */
 664                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 665                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 666                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 667                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 668                                                     rearm_data),
 669                                            16));
 670                 /* build up data and do writes */
 671                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 672                         rearm6, rearm7;
 673
 674                 rearm6 = _mm256_blend_epi32(mbuf_init,
 675                                             _mm256_slli_si256(mbuf_flags, 8),
 676                                             0x04);
 677                 rearm4 = _mm256_blend_epi32(mbuf_init,
 678                                             _mm256_slli_si256(mbuf_flags, 4),
 679                                             0x04);
 680                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 681                 rearm0 = _mm256_blend_epi32(mbuf_init,
 682                                             _mm256_srli_si256(mbuf_flags, 4),
 683                                             0x04);
 684
 685                 /* permute to add in the rx_descriptor e.g. rss fields */
 686                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 687                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 688                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 689                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 690
 691                 /* write to mbuf */
 692                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 693                                     rearm6);
 694                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 695                                     rearm4);
 696                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 697                                     rearm2);
 698                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 699                                     rearm0);
 700
 701                 /* repeat for the odd mbufs */
 702                 const __m256i odd_flags =
 703                         _mm256_castsi128_si256
 704                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 705                 rearm7 = _mm256_blend_epi32(mbuf_init,
 706                                             _mm256_slli_si256(odd_flags, 8),
 707                                             0x04);
 708                 rearm5 = _mm256_blend_epi32(mbuf_init,
 709                                             _mm256_slli_si256(odd_flags, 4),
 710                                             0x04);
 711                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 712                 rearm1 = _mm256_blend_epi32(mbuf_init,
 713                                             _mm256_srli_si256(odd_flags, 4),
 714                                             0x04);
 715
 716                 /* since odd mbufs are already in hi 128-bits use blend */
 717                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 718                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 719                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 720                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 721                 /* again write to mbufs */
 722                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 723                                     rearm7);
 724                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 725                                     rearm5);
 726                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 727                                     rearm3);
 728                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 729                                     rearm1);
 730
 731                 /* extract and record EOP bit */
 732                 if (split_packet) {
 733                         const __m128i eop_mask =
 734                                 _mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);
 735                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 736                                                                      eop_check);
 737                         /* pack status bits into a single 128-bit register */
 738                         const __m128i eop_bits =
 739                                 _mm_packus_epi32
 740                                         (_mm256_castsi256_si128(eop_bits256),
 741                                          _mm256_extractf128_si256(eop_bits256,
 742                                                                   1));
 743                         /**
 744                          * flip bits, and mask out the EOP bit, which is now
 745                          * a split-packet bit i.e. !EOP, rather than EOP one.
 746                          */
 747                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 748                                         eop_mask);
 749                         /**
 750                          * eop bits are out of order, so we need to shuffle them
 751                          * back into order again. In doing so, only use low 8
 752                          * bits, which acts like another pack instruction
 753                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 754                          * [Since we use epi8, the 16-bit positions are
 755                          * multiplied by 2 in the eop_shuffle value.]
 756                          */
 757                         __m128i eop_shuffle =
 758                                 _mm_set_epi8(/* zero hi 64b */
 759                                              0xFF, 0xFF, 0xFF, 0xFF,
 760                                              0xFF, 0xFF, 0xFF, 0xFF,
 761                                              /* move values to lo 64b */
 762                                              8, 0, 10, 2,
 763                                              12, 4, 14, 6);
 764                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 765                         *(uint64_t *)split_packet =
 766                                 _mm_cvtsi128_si64(split_bits);
 767                         split_packet += ICE_DESCS_PER_LOOP_AVX;
 768                 }
 769
 770                 /* perform dd_check */
 771                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 772                 status0_7 = _mm256_packs_epi32(status0_7,
 773                                                _mm256_setzero_si256());
 774
 775                 uint64_t burst = __builtin_popcountll
 776                                         (_mm_cvtsi128_si64
 777                                                 (_mm256_extracti128_si256
 778                                                         (status0_7, 1)));
 779                 burst += __builtin_popcountll
 780                                 (_mm_cvtsi128_si64
 781                                         (_mm256_castsi256_si128(status0_7)));
 782                 received += burst;
 783                 if (burst != ICE_DESCS_PER_LOOP_AVX)
 784                         break;
 785         }
 786
 787         /* update tail pointers */
 788         rxq->rx_tail += received;
 789         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 790         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 791                 rxq->rx_tail--;
 792                 received--;
 793         }
 794         rxq->rxrearm_nb += received;
 795         return received;
 796 }
 797
 798 /**
 799  * Notice:
 800  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 801  */
 802 uint16_t
 803 ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 804                          uint16_t nb_pkts)
 805 {
 806         return _ice_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);
 807 }
 808
 809 /**
 810  * vPMD receive routine that reassembles single burst of 32 scattered packets
 811  * Notice:
 812  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 813  */
 814 static uint16_t
 815 ice_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 816                                     uint16_t nb_pkts)
 817 {
 818         struct ice_rx_queue *rxq = rx_queue;
 819         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 820
 821         /* get some new buffers */
 822         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
 823                                                        split_flags);
 824         if (nb_bufs == 0)
 825                 return 0;
 826
 827         /* happy day case, full burst + no packets to be joined */
 828         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 829
 830         if (!rxq->pkt_first_seg &&
 831             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 832             split_fl64[2] == 0 && split_fl64[3] == 0)
 833                 return nb_bufs;
 834
 835         /* reassemble any packets that need reassembly */
 836         unsigned int i = 0;
 837
 838         if (!rxq->pkt_first_seg) {
 839                 /* find the first split flag, and only reassemble then */
 840                 while (i < nb_bufs && !split_flags[i])
 841                         i++;
 842                 if (i == nb_bufs)
 843                         return nb_bufs;
 844                 rxq->pkt_first_seg = rx_pkts[i];
 845         }
 846         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 847                                              &split_flags[i]);
 848 }
 849
 850 /**
 851  * vPMD receive routine that reassembles scattered packets.
 852  * Main receive routine that can handle arbitrary burst sizes
 853  * Notice:
 854  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 855  */
 856 uint16_t
 857 ice_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 858                                    uint16_t nb_pkts)
 859 {
 860         uint16_t retval = 0;
 861
 862         while (nb_pkts > ICE_VPMD_RX_BURST) {
 863                 uint16_t burst = ice_recv_scattered_burst_vec_avx512(rx_queue,
 864                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 865                 retval += burst;
 866                 nb_pkts -= burst;
 867                 if (burst < ICE_VPMD_RX_BURST)
 868                         return retval;
 869         }
 870         return retval + ice_recv_scattered_burst_vec_avx512(rx_queue,
 871                                 rx_pkts + retval, nb_pkts);
 872 }
 873
 874 static __rte_always_inline int
 875 ice_tx_free_bufs_avx512(struct ice_tx_queue *txq)
 876 {
 877         struct ice_vec_tx_entry *txep;
 878         uint32_t n;
 879         uint32_t i;
 880         int nb_free = 0;
 881         struct rte_mbuf *m, *free[ICE_TX_MAX_FREE_BUF_SZ];
 882
 883         /* check DD bits on threshold descriptor */
 884         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
 885                         rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
 886                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
 887                 return 0;
 888
 889         n = txq->tx_rs_thresh;
 890
 891         /* first buffer to free from S/W ring is at index
 892          * tx_next_dd - (tx_rs_thresh - 1)
 893          */
 894         txep = (void *)txq->sw_ring;
 895         txep += txq->tx_next_dd - (n - 1);
 896
 897         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
 898                 struct rte_mempool *mp = txep[0].mbuf->pool;
 899                 void **cache_objs;
 900                 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
 901                                 rte_lcore_id());
 902
 903                 if (!cache || cache->len == 0)
 904                         goto normal;
 905
 906                 cache_objs = &cache->objs[cache->len];
 907
 908                 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
 909                         rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
 910                         goto done;
 911                 }
 912
 913                 /* The cache follows the following algorithm
 914                  *   1. Add the objects to the cache
 915                  *   2. Anything greater than the cache min value (if it
 916                  *   crosses the cache flush threshold) is flushed to the ring.
 917                  */
 918                 /* Add elements back into the cache */
 919                 uint32_t copied = 0;
 920                 /* n is multiple of 32 */
 921                 while (copied < n) {
 922                         const __m512i a = _mm512_loadu_si512(&txep[copied]);
 923                         const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
 924                         const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
 925                         const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
 926
 927                         _mm512_storeu_si512(&cache_objs[copied], a);
 928                         _mm512_storeu_si512(&cache_objs[copied + 8], b);
 929                         _mm512_storeu_si512(&cache_objs[copied + 16], c);
 930                         _mm512_storeu_si512(&cache_objs[copied + 24], d);
 931                         copied += 32;
 932                 }
 933                 cache->len += n;
 934
 935                 if (cache->len >= cache->flushthresh) {
 936                         rte_mempool_ops_enqueue_bulk
 937                                 (mp, &cache->objs[cache->size],
 938                                  cache->len - cache->size);
 939                         cache->len = cache->size;
 940                 }
 941                 goto done;
 942         }
 943
 944 normal:
 945         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
 946         if (likely(m)) {
 947                 free[0] = m;
 948                 nb_free = 1;
 949                 for (i = 1; i < n; i++) {
 950                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
 951                         if (likely(m)) {
 952                                 if (likely(m->pool == free[0]->pool)) {
 953                                         free[nb_free++] = m;
 954                                 } else {
 955                                         rte_mempool_put_bulk(free[0]->pool,
 956                                                              (void *)free,
 957                                                              nb_free);
 958                                         free[0] = m;
 959                                         nb_free = 1;
 960                                 }
 961                         }
 962                 }
 963                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 964         } else {
 965                 for (i = 1; i < n; i++) {
 966                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
 967                         if (m)
 968                                 rte_mempool_put(m->pool, m);
 969                 }
 970         }
 971
 972 done:
 973         /* buffers were freed, update counters */
 974         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 975         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 976         if (txq->tx_next_dd >= txq->nb_tx_desc)
 977                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 978
 979         return txq->tx_rs_thresh;
 980 }
 981
 982 static inline void
 983 ice_vtx1(volatile struct ice_tx_desc *txdp,
 984          struct rte_mbuf *pkt, uint64_t flags)
 985 {
 986         uint64_t high_qw =
 987                 (ICE_TX_DESC_DTYPE_DATA |
 988                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
 989                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
 990
 991         __m128i descriptor = _mm_set_epi64x(high_qw,
 992                                 pkt->buf_iova + pkt->data_off);
 993         _mm_store_si128((__m128i *)txdp, descriptor);
 994 }
 995
 996 static inline void
 997 ice_vtx(volatile struct ice_tx_desc *txdp,
 998         struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 999 {
1000         const uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |
1001                         ((uint64_t)flags  << ICE_TXD_QW1_CMD_S));
1002
1003         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1004                 uint64_t hi_qw3 =
1005                         hi_qw_tmpl |
1006                         ((uint64_t)pkt[3]->data_len <<
1007                          ICE_TXD_QW1_TX_BUF_SZ_S);
1008                 uint64_t hi_qw2 =
1009                         hi_qw_tmpl |
1010                         ((uint64_t)pkt[2]->data_len <<
1011                          ICE_TXD_QW1_TX_BUF_SZ_S);
1012                 uint64_t hi_qw1 =
1013                         hi_qw_tmpl |
1014                         ((uint64_t)pkt[1]->data_len <<
1015                          ICE_TXD_QW1_TX_BUF_SZ_S);
1016                 uint64_t hi_qw0 =
1017                         hi_qw_tmpl |
1018                         ((uint64_t)pkt[0]->data_len <<
1019                          ICE_TXD_QW1_TX_BUF_SZ_S);
1020
1021                 __m512i desc0_3 =
1022                         _mm512_set_epi64
1023                                 (hi_qw3,
1024                                  pkt[3]->buf_iova + pkt[3]->data_off,
1025                                  hi_qw2,
1026                                  pkt[2]->buf_iova + pkt[2]->data_off,
1027                                  hi_qw1,
1028                                  pkt[1]->buf_iova + pkt[1]->data_off,
1029                                  hi_qw0,
1030                                  pkt[0]->buf_iova + pkt[0]->data_off);
1031                 _mm512_storeu_si512((void *)txdp, desc0_3);
1032         }
1033
1034         /* do any last ones */
1035         while (nb_pkts) {
1036                 ice_vtx1(txdp, *pkt, flags);
1037                 txdp++, pkt++, nb_pkts--;
1038         }
1039 }
1040
1041 static __rte_always_inline void
1042 ice_tx_backlog_entry_avx512(struct ice_vec_tx_entry *txep,
1043                             struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1044 {
1045         int i;
1046
1047         for (i = 0; i < (int)nb_pkts; ++i)
1048                 txep[i].mbuf = tx_pkts[i];
1049 }
1050
1051 static inline uint16_t
1052 ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1053                                 uint16_t nb_pkts)
1054 {
1055         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
1056         volatile struct ice_tx_desc *txdp;
1057         struct ice_vec_tx_entry *txep;
1058         uint16_t n, nb_commit, tx_id;
1059         uint64_t flags = ICE_TD_CMD;
1060         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
1061
1062         /* cross rx_thresh boundary is not allowed */
1063         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1064
1065         if (txq->nb_tx_free < txq->tx_free_thresh)
1066                 ice_tx_free_bufs_avx512(txq);
1067
1068         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1069         if (unlikely(nb_pkts == 0))
1070                 return 0;
1071
1072         tx_id = txq->tx_tail;
1073         txdp = &txq->tx_ring[tx_id];
1074         txep = (void *)txq->sw_ring;
1075         txep += tx_id;
1076
1077         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1078
1079         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1080         if (nb_commit >= n) {
1081                 ice_tx_backlog_entry_avx512(txep, tx_pkts, n);
1082
1083                 ice_vtx(txdp, tx_pkts, n - 1, flags);
1084                 tx_pkts += (n - 1);
1085                 txdp += (n - 1);
1086
1087                 ice_vtx1(txdp, *tx_pkts++, rs);
1088
1089                 nb_commit = (uint16_t)(nb_commit - n);
1090
1091                 tx_id = 0;
1092                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1093
1094                 /* avoid reach the end of ring */
1095                 txdp = txq->tx_ring;
1096                 txep = (void *)txq->sw_ring;
1097         }
1098
1099         ice_tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1100
1101         ice_vtx(txdp, tx_pkts, nb_commit, flags);
1102
1103         tx_id = (uint16_t)(tx_id + nb_commit);
1104         if (tx_id > txq->tx_next_rs) {
1105                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
1106                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
1107                                          ICE_TXD_QW1_CMD_S);
1108                 txq->tx_next_rs =
1109                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1110         }
1111
1112         txq->tx_tail = tx_id;
1113
1114         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1115
1116         return nb_pkts;
1117 }
1118
1119 uint16_t
1120 ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1121                          uint16_t nb_pkts)
1122 {
1123         uint16_t nb_tx = 0;
1124         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
1125
1126         while (nb_pkts) {
1127                 uint16_t ret, num;
1128
1129                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1130                 ret = ice_xmit_fixed_burst_vec_avx512(tx_queue,
1131                                                       &tx_pkts[nb_tx], num);
1132                 nb_tx += ret;
1133                 nb_pkts -= ret;
1134                 if (ret < num)
1135                         break;
1136         }
1137
1138         return nb_tx;
1139 }