drivers/net/ice/ice_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define ICE_DESCS_PER_LOOP_AVX 8
  14
  15 static inline void
  16 ice_rxq_rearm(struct ice_rx_queue *rxq)
  17 {
  18         int i;
  19         uint16_t rx_id;
  20         volatile union ice_rx_flex_desc *rxdp;
  21         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  22         struct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,
  23                         rte_lcore_id());
  24
  25         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  26
  27         /* We need to pull 'n' more MBUFs into the software ring */
  28         if (cache->len < ICE_RXQ_REARM_THRESH) {
  29                 uint32_t req = ICE_RXQ_REARM_THRESH + (cache->size -
  30                                 cache->len);
  31
  32                 int ret = rte_mempool_ops_dequeue_bulk(rxq->mp,
  33                                 &cache->objs[cache->len], req);
  34                 if (ret == 0) {
  35                         cache->len += req;
  36                 } else {
  37                         if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  38                             rxq->nb_rx_desc) {
  39                                 __m128i dma_addr0;
  40
  41                                 dma_addr0 = _mm_setzero_si128();
  42                                 for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  43                                         rxep[i].mbuf = &rxq->fake_mbuf;
  44                                         _mm_store_si128
  45                                                 ((__m128i *)&rxdp[i].read,
  46                                                         dma_addr0);
  47                                 }
  48                         }
  49                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  50                                 ICE_RXQ_REARM_THRESH;
  51                         return;
  52                 }
  53         }
  54
  55         const __m512i iova_offsets =  _mm512_set1_epi64
  56                 (offsetof(struct rte_mbuf, buf_iova));
  57         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  58
  59 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  60         /* shuffle the iova into correct slots. Values 4-7 will contain
  61          * zeros, so use 7 for a zero-value.
  62          */
  63         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  64 #else
  65         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  66 #endif
  67
  68         /* fill up the rxd in vector, process 8 mbufs in one loop */
  69         for (i = 0; i < ICE_RXQ_REARM_THRESH / 8; i++) {
  70                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  71                         (&cache->objs[cache->len - 8]);
  72                 _mm512_store_si512(rxep, mbuf_ptrs);
  73
  74                 /* gather iova of mbuf0-7 into one zmm reg */
  75                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
  76                         (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
  77                                 0, /* base */
  78                                 1  /* scale */);
  79                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
  80                                 headroom);
  81 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  82                 const __m512i iovas0 = _mm512_castsi256_si512
  83                         (_mm512_extracti64x4_epi64(iova_addrs, 0));
  84                 const __m512i iovas1 = _mm512_castsi256_si512
  85                         (_mm512_extracti64x4_epi64(iova_addrs, 1));
  86
  87                 /* permute leaves iova 2-3 in hdr_addr of desc 0-1
  88                  * but these are ignored by driver since header split not
  89                  * enabled. Similarly for desc 4 & 5.
  90                  */
  91                 const __m512i desc0_1 = _mm512_permutexvar_epi64
  92                         (permute_idx, iovas0);
  93                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
  94
  95                 const __m512i desc4_5 = _mm512_permutexvar_epi64
  96                         (permute_idx, iovas1);
  97                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
  98
  99                 _mm512_store_si512((void *)rxdp, desc0_1);
 100                 _mm512_store_si512((void *)(rxdp + 2), desc2_3);
 101                 _mm512_store_si512((void *)(rxdp + 4), desc4_5);
 102                 _mm512_store_si512((void *)(rxdp + 6), desc6_7);
 103 #else
 104                 /* permute leaves iova 4-7 in hdr_addr of desc 0-3
 105                  * but these are ignored by driver since header split not
 106                  * enabled.
 107                  */
 108                 const __m512i desc0_3 = _mm512_permutexvar_epi64
 109                         (permute_idx, iova_addrs);
 110                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 111
 112                 _mm512_store_si512((void *)rxdp, desc0_3);
 113                 _mm512_store_si512((void *)(rxdp + 4), desc4_7);
 114 #endif
 115                 rxep += 8, rxdp += 8, cache->len -= 8;
 116         }
 117
 118         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
 119         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 120                 rxq->rxrearm_start = 0;
 121
 122         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
 123
 124         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 125                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 126
 127         /* Update the tail pointer on the NIC */
 128         ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 129 }
 130
 131 static inline uint16_t
 132 _ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq,
 133                               struct rte_mbuf **rx_pkts,
 134                               uint16_t nb_pkts, uint8_t *split_packet)
 135 {
 136         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 137         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 138                         0, rxq->mbuf_initializer);
 139         struct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
 140         volatile union ice_rx_flex_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 141
 142         rte_prefetch0(rxdp);
 143
 144         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */
 145         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);
 146
 147         /* See if we need to rearm the RX queue - gives the prefetch a bit
 148          * of time to act
 149          */
 150         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 151                 ice_rxq_rearm(rxq);
 152
 153         /* Before we start moving massive data around, check to see if
 154          * there is actually a packet available
 155          */
 156         if (!(rxdp->wb.status_error0 &
 157                         rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 158                 return 0;
 159
 160         /* constants used in processing loop */
 161         const __m512i crc_adjust =
 162                 _mm512_set4_epi32
 163                         (0,             /* ignore non-length fields */
 164                          -rxq->crc_len, /* sub crc on data_len */
 165                          -rxq->crc_len, /* sub crc on pkt_len */
 166                          0              /* ignore non-length fields */
 167                         );
 168
 169         /* 8 packets DD mask, LSB in each 32-bit value */
 170         const __m256i dd_check = _mm256_set1_epi32(1);
 171
 172         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 173         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 174                         ICE_RX_DESC_STATUS_EOF_S);
 175
 176         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 177         const __m512i shuf_msk =
 178                 _mm512_set4_epi32
 179                         (/* octet 12~15, 32 bits rss */
 180                          15 << 24 | 14 << 16 | 13 << 8 | 12,
 181                          /* octet 10~11, 16 bits vlan_macip */
 182                          /* octet 4~5, 16 bits data_len */
 183                          11 << 24 | 10 << 16 | 5 << 8 | 4,
 184                          /* skip hi 16 bits pkt_len, zero out */
 185                          /* octet 4~5, 16 bits pkt_len */
 186                          0xFFFF << 16 | 5 << 8 | 4,
 187                          /* pkt_type set as unknown */
 188                          0xFFFFFFFF
 189                         );
 190
 191         /**
 192          * compile-time check the above crc and shuffle layout is correct.
 193          * NOTE: the first field (lowest address) is given last in set_epi
 194          * calls above.
 195          */
 196         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 197                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 198         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 199                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 200         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 201                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 202         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 203                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 204
 205         /* Status/Error flag masks */
 206         /**
 207          * mask everything except Checksum Reports, RSS indication
 208          * and VLAN indication.
 209          * bit6:4 for IP/L4 checksum errors.
 210          * bit12 is for RSS indication.
 211          * bit13 is for VLAN indication.
 212          */
 213         const __m256i flags_mask =
 214                  _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 215         /**
 216          * data to be shuffled by the result of the flags mask shifted by 4
 217          * bits.  This gives use the l3_l4 flags.
 218          */
 219         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 220                         /* shift right 1 bit to make sure it not exceed 255 */
 221                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 222                          PKT_RX_IP_CKSUM_BAD) >> 1,
 223                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 224                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 225                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 226                          PKT_RX_IP_CKSUM_BAD) >> 1,
 227                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 228                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 229                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 230                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 231                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 232                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 233                         /* 2nd 128-bits */
 234                         0, 0, 0, 0, 0, 0, 0, 0,
 235                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 236                          PKT_RX_IP_CKSUM_BAD) >> 1,
 237                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 238                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 239                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 240                          PKT_RX_IP_CKSUM_BAD) >> 1,
 241                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 242                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 243                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 244                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 245                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 246                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 247         const __m256i cksum_mask =
 248                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 249                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 250                                    PKT_RX_EIP_CKSUM_BAD);
 251         /**
 252          * data to be shuffled by result of flag mask, shifted down 12.
 253          * If RSS(bit12)/VLAN(bit13) are set,
 254          * shuffle moves appropriate flags in place.
 255          */
 256         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 257                         0, 0, 0, 0,
 258                         0, 0, 0, 0,
 259                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 260                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 261                         PKT_RX_RSS_HASH, 0,
 262                         /* 2nd 128-bits */
 263                         0, 0, 0, 0,
 264                         0, 0, 0, 0,
 265                         0, 0, 0, 0,
 266                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 267                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 268                         PKT_RX_RSS_HASH, 0);
 269
 270         uint16_t i, received;
 271
 272         for (i = 0, received = 0; i < nb_pkts;
 273              i += ICE_DESCS_PER_LOOP_AVX,
 274              rxdp += ICE_DESCS_PER_LOOP_AVX) {
 275                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 276                 _mm256_storeu_si256((void *)&rx_pkts[i],
 277                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 278 #ifdef RTE_ARCH_X86_64
 279                 _mm256_storeu_si256
 280                         ((void *)&rx_pkts[i + 4],
 281                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 282 #endif
 283
 284                 __m512i raw_desc0_3, raw_desc4_7;
 285                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 286
 287                 /* load in descriptors, in reverse order */
 288                 const __m128i raw_desc7 =
 289                         _mm_load_si128((void *)(rxdp + 7));
 290                 rte_compiler_barrier();
 291                 const __m128i raw_desc6 =
 292                         _mm_load_si128((void *)(rxdp + 6));
 293                 rte_compiler_barrier();
 294                 const __m128i raw_desc5 =
 295                         _mm_load_si128((void *)(rxdp + 5));
 296                 rte_compiler_barrier();
 297                 const __m128i raw_desc4 =
 298                         _mm_load_si128((void *)(rxdp + 4));
 299                 rte_compiler_barrier();
 300                 const __m128i raw_desc3 =
 301                         _mm_load_si128((void *)(rxdp + 3));
 302                 rte_compiler_barrier();
 303                 const __m128i raw_desc2 =
 304                         _mm_load_si128((void *)(rxdp + 2));
 305                 rte_compiler_barrier();
 306                 const __m128i raw_desc1 =
 307                         _mm_load_si128((void *)(rxdp + 1));
 308                 rte_compiler_barrier();
 309                 const __m128i raw_desc0 =
 310                         _mm_load_si128((void *)(rxdp + 0));
 311
 312                 raw_desc6_7 =
 313                         _mm256_inserti128_si256
 314                                 (_mm256_castsi128_si256(raw_desc6),
 315                                  raw_desc7, 1);
 316                 raw_desc4_5 =
 317                         _mm256_inserti128_si256
 318                                 (_mm256_castsi128_si256(raw_desc4),
 319                                  raw_desc5, 1);
 320                 raw_desc2_3 =
 321                         _mm256_inserti128_si256
 322                                 (_mm256_castsi128_si256(raw_desc2),
 323                                  raw_desc3, 1);
 324                 raw_desc0_1 =
 325                         _mm256_inserti128_si256
 326                                 (_mm256_castsi128_si256(raw_desc0),
 327                                  raw_desc1, 1);
 328
 329                 raw_desc4_7 =
 330                         _mm512_inserti64x4
 331                                 (_mm512_castsi256_si512(raw_desc4_5),
 332                                  raw_desc6_7, 1);
 333                 raw_desc0_3 =
 334                         _mm512_inserti64x4
 335                                 (_mm512_castsi256_si512(raw_desc0_1),
 336                                  raw_desc2_3, 1);
 337
 338                 if (split_packet) {
 339                         int j;
 340
 341                         for (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)
 342                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 343                 }
 344
 345                 /**
 346                  * convert descriptors 0-7 into mbufs, re-arrange fields.
 347                  * Then write into the mbuf.
 348                  */
 349                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 350                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 351
 352                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 353                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 354
 355                 /**
 356                  * to get packet types, ptype is located in bit16-25
 357                  * of each 128bits
 358                  */
 359                 const __m512i ptype_mask =
 360                         _mm512_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);
 361
 362                 /**
 363                  * to get packet types, ptype is located in bit16-25
 364                  * of each 128bits
 365                  */
 366                 const __m512i ptypes4_7 =
 367                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 368                 const __m512i ptypes0_3 =
 369                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 370
 371                 const __m256i ptypes6_7 =
 372                         _mm512_extracti64x4_epi64(ptypes4_7, 1);
 373                 const __m256i ptypes4_5 =
 374                         _mm512_extracti64x4_epi64(ptypes4_7, 0);
 375                 const __m256i ptypes2_3 =
 376                         _mm512_extracti64x4_epi64(ptypes0_3, 1);
 377                 const __m256i ptypes0_1 =
 378                         _mm512_extracti64x4_epi64(ptypes0_3, 0);
 379                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 380                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 381                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 382                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 383                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 384                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 385                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 386                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 387
 388                 const __m512i ptype4_7 = _mm512_set_epi32
 389                         (0, 0, 0, ptype_tbl[ptype7],
 390                          0, 0, 0, ptype_tbl[ptype6],
 391                          0, 0, 0, ptype_tbl[ptype5],
 392                          0, 0, 0, ptype_tbl[ptype4]);
 393                 const __m512i ptype0_3 = _mm512_set_epi32
 394                         (0, 0, 0, ptype_tbl[ptype3],
 395                          0, 0, 0, ptype_tbl[ptype2],
 396                          0, 0, 0, ptype_tbl[ptype1],
 397                          0, 0, 0, ptype_tbl[ptype0]);
 398
 399                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 400                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 401
 402                 /**
 403                  * use permute/extract to get status content
 404                  * After the operations, the packets status flags are in the
 405                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 406                  */
 407                 /* merge the status bits into one register */
 408                 const __m512i status_permute_msk = _mm512_set_epi32
 409                         (0, 0, 0, 0,
 410                          0, 0, 0, 0,
 411                          22, 30, 6, 14,
 412                          18, 26, 2, 10);
 413                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 414                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 415                 __m256i status0_7 = _mm512_extracti64x4_epi64
 416                         (raw_status0_7, 0);
 417
 418                 /* now do flag manipulation */
 419
 420                 /* get only flag/error bits we want */
 421                 const __m256i flag_bits =
 422                         _mm256_and_si256(status0_7, flags_mask);
 423                 /**
 424                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 425                  * of flags in flags_shuf, and finally mask out extra bits
 426                  */
 427                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 428                                 _mm256_srli_epi32(flag_bits, 4));
 429                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 430                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 431                 /* set rss and vlan flags */
 432                 const __m256i rss_vlan_flag_bits =
 433                         _mm256_srli_epi32(flag_bits, 12);
 434                 const __m256i rss_vlan_flags =
 435                         _mm256_shuffle_epi8(rss_vlan_flags_shuf,
 436                                             rss_vlan_flag_bits);
 437
 438                 /* merge flags */
 439                 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 440                                 rss_vlan_flags);
 441                 /**
 442                  * At this point, we have the 8 sets of flags in the low 16-bits
 443                  * of each 32-bit value in vlan0.
 444                  * We want to extract these, and merge them with the mbuf init
 445                  * data so we can do a single write to the mbuf to set the flags
 446                  * and all the other initialization fields. Extracting the
 447                  * appropriate flags means that we have to do a shift and blend
 448                  * for each mbuf before we do the write. However, we can also
 449                  * add in the previously computed rx_descriptor fields to
 450                  * make a single 256-bit write per mbuf
 451                  */
 452                 /* check the structure matches expectations */
 453                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 454                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 455                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 456                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 457                                                     rearm_data),
 458                                            16));
 459                 /* build up data and do writes */
 460                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 461                         rearm6, rearm7;
 462
 463                 rearm6 = _mm256_blend_epi32(mbuf_init,
 464                                             _mm256_slli_si256(mbuf_flags, 8),
 465                                             0x04);
 466                 rearm4 = _mm256_blend_epi32(mbuf_init,
 467                                             _mm256_slli_si256(mbuf_flags, 4),
 468                                             0x04);
 469                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 470                 rearm0 = _mm256_blend_epi32(mbuf_init,
 471                                             _mm256_srli_si256(mbuf_flags, 4),
 472                                             0x04);
 473
 474                 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 475                 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 476                 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 477                 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 478
 479                 /* permute to add in the rx_descriptor e.g. rss fields */
 480                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 481                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 482                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 483                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 484
 485                 /* write to mbuf */
 486                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 487                                     rearm6);
 488                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 489                                     rearm4);
 490                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 491                                     rearm2);
 492                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 493                                     rearm0);
 494
 495                 /* repeat for the odd mbufs */
 496                 const __m256i odd_flags =
 497                         _mm256_castsi128_si256
 498                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 499                 rearm7 = _mm256_blend_epi32(mbuf_init,
 500                                             _mm256_slli_si256(odd_flags, 8),
 501                                             0x04);
 502                 rearm5 = _mm256_blend_epi32(mbuf_init,
 503                                             _mm256_slli_si256(odd_flags, 4),
 504                                             0x04);
 505                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 506                 rearm1 = _mm256_blend_epi32(mbuf_init,
 507                                             _mm256_srli_si256(odd_flags, 4),
 508                                             0x04);
 509
 510                 /* since odd mbufs are already in hi 128-bits use blend */
 511                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 512                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 513                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 514                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 515                 /* again write to mbufs */
 516                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 517                                     rearm7);
 518                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 519                                     rearm5);
 520                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 521                                     rearm3);
 522                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 523                                     rearm1);
 524
 525                 /* extract and record EOP bit */
 526                 if (split_packet) {
 527                         const __m128i eop_mask =
 528                                 _mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);
 529                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 530                                                                      eop_check);
 531                         /* pack status bits into a single 128-bit register */
 532                         const __m128i eop_bits =
 533                                 _mm_packus_epi32
 534                                         (_mm256_castsi256_si128(eop_bits256),
 535                                          _mm256_extractf128_si256(eop_bits256,
 536                                                                   1));
 537                         /**
 538                          * flip bits, and mask out the EOP bit, which is now
 539                          * a split-packet bit i.e. !EOP, rather than EOP one.
 540                          */
 541                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 542                                         eop_mask);
 543                         /**
 544                          * eop bits are out of order, so we need to shuffle them
 545                          * back into order again. In doing so, only use low 8
 546                          * bits, which acts like another pack instruction
 547                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 548                          * [Since we use epi8, the 16-bit positions are
 549                          * multiplied by 2 in the eop_shuffle value.]
 550                          */
 551                         __m128i eop_shuffle =
 552                                 _mm_set_epi8(/* zero hi 64b */
 553                                              0xFF, 0xFF, 0xFF, 0xFF,
 554                                              0xFF, 0xFF, 0xFF, 0xFF,
 555                                              /* move values to lo 64b */
 556                                              8, 0, 10, 2,
 557                                              12, 4, 14, 6);
 558                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 559                         *(uint64_t *)split_packet =
 560                                 _mm_cvtsi128_si64(split_bits);
 561                         split_packet += ICE_DESCS_PER_LOOP_AVX;
 562                 }
 563
 564                 /* perform dd_check */
 565                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 566                 status0_7 = _mm256_packs_epi32(status0_7,
 567                                                _mm256_setzero_si256());
 568
 569                 uint64_t burst = __builtin_popcountll
 570                                         (_mm_cvtsi128_si64
 571                                                 (_mm256_extracti128_si256
 572                                                         (status0_7, 1)));
 573                 burst += __builtin_popcountll
 574                                 (_mm_cvtsi128_si64
 575                                         (_mm256_castsi256_si128(status0_7)));
 576                 received += burst;
 577                 if (burst != ICE_DESCS_PER_LOOP_AVX)
 578                         break;
 579         }
 580
 581         /* update tail pointers */
 582         rxq->rx_tail += received;
 583         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 584         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 585                 rxq->rx_tail--;
 586                 received--;
 587         }
 588         rxq->rxrearm_nb += received;
 589         return received;
 590 }
 591
 592 /**
 593  * Notice:
 594  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 595  */
 596 uint16_t
 597 ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 598                          uint16_t nb_pkts)
 599 {
 600         return _ice_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL);
 601 }
 602
 603 /**
 604  * vPMD receive routine that reassembles single burst of 32 scattered packets
 605  * Notice:
 606  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 607  */
 608 static uint16_t
 609 ice_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 610                                     uint16_t nb_pkts)
 611 {
 612         struct ice_rx_queue *rxq = rx_queue;
 613         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 614
 615         /* get some new buffers */
 616         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
 617                                                        split_flags);
 618         if (nb_bufs == 0)
 619                 return 0;
 620
 621         /* happy day case, full burst + no packets to be joined */
 622         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 623
 624         if (!rxq->pkt_first_seg &&
 625             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 626             split_fl64[2] == 0 && split_fl64[3] == 0)
 627                 return nb_bufs;
 628
 629         /* reassemble any packets that need reassembly */
 630         unsigned int i = 0;
 631
 632         if (!rxq->pkt_first_seg) {
 633                 /* find the first split flag, and only reassemble then */
 634                 while (i < nb_bufs && !split_flags[i])
 635                         i++;
 636                 if (i == nb_bufs)
 637                         return nb_bufs;
 638                 rxq->pkt_first_seg = rx_pkts[i];
 639         }
 640         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 641                                              &split_flags[i]);
 642 }
 643
 644 /**
 645  * vPMD receive routine that reassembles scattered packets.
 646  * Main receive routine that can handle arbitrary burst sizes
 647  * Notice:
 648  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 649  */
 650 uint16_t
 651 ice_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 652                                    uint16_t nb_pkts)
 653 {
 654         uint16_t retval = 0;
 655
 656         while (nb_pkts > ICE_VPMD_RX_BURST) {
 657                 uint16_t burst = ice_recv_scattered_burst_vec_avx512(rx_queue,
 658                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 659                 retval += burst;
 660                 nb_pkts -= burst;
 661                 if (burst < ICE_VPMD_RX_BURST)
 662                         return retval;
 663         }
 664         return retval + ice_recv_scattered_burst_vec_avx512(rx_queue,
 665                                 rx_pkts + retval, nb_pkts);
 666 }
 667
 668 static inline void
 669 ice_vtx1(volatile struct ice_tx_desc *txdp,
 670          struct rte_mbuf *pkt, uint64_t flags)
 671 {
 672         uint64_t high_qw =
 673                 (ICE_TX_DESC_DTYPE_DATA |
 674                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
 675                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
 676
 677         __m128i descriptor = _mm_set_epi64x(high_qw,
 678                                 pkt->buf_iova + pkt->data_off);
 679         _mm_store_si128((__m128i *)txdp, descriptor);
 680 }
 681
 682 static inline void
 683 ice_vtx(volatile struct ice_tx_desc *txdp,
 684         struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 685 {
 686         const uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |
 687                         ((uint64_t)flags  << ICE_TXD_QW1_CMD_S));
 688
 689         /* if unaligned on 32-bit boundary, do one to align */
 690         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
 691                 ice_vtx1(txdp, *pkt, flags);
 692                 nb_pkts--, txdp++, pkt++;
 693         }
 694
 695         /* do two at a time while possible, in bursts */
 696         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
 697                 uint64_t hi_qw3 =
 698                         hi_qw_tmpl |
 699                         ((uint64_t)pkt[3]->data_len <<
 700                          ICE_TXD_QW1_TX_BUF_SZ_S);
 701                 uint64_t hi_qw2 =
 702                         hi_qw_tmpl |
 703                         ((uint64_t)pkt[2]->data_len <<
 704                          ICE_TXD_QW1_TX_BUF_SZ_S);
 705                 uint64_t hi_qw1 =
 706                         hi_qw_tmpl |
 707                         ((uint64_t)pkt[1]->data_len <<
 708                          ICE_TXD_QW1_TX_BUF_SZ_S);
 709                 uint64_t hi_qw0 =
 710                         hi_qw_tmpl |
 711                         ((uint64_t)pkt[0]->data_len <<
 712                          ICE_TXD_QW1_TX_BUF_SZ_S);
 713
 714                 __m256i desc2_3 =
 715                         _mm256_set_epi64x
 716                                 (hi_qw3,
 717                                  pkt[3]->buf_iova + pkt[3]->data_off,
 718                                  hi_qw2,
 719                                  pkt[2]->buf_iova + pkt[2]->data_off);
 720                 __m256i desc0_1 =
 721                         _mm256_set_epi64x
 722                                 (hi_qw1,
 723                                  pkt[1]->buf_iova + pkt[1]->data_off,
 724                                  hi_qw0,
 725                                  pkt[0]->buf_iova + pkt[0]->data_off);
 726                 _mm256_store_si256((void *)(txdp + 2), desc2_3);
 727                 _mm256_store_si256((void *)txdp, desc0_1);
 728         }
 729
 730         /* do any last ones */
 731         while (nb_pkts) {
 732                 ice_vtx1(txdp, *pkt, flags);
 733                 txdp++, pkt++, nb_pkts--;
 734         }
 735 }
 736
 737 static inline uint16_t
 738 ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 739                                 uint16_t nb_pkts)
 740 {
 741         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 742         volatile struct ice_tx_desc *txdp;
 743         struct ice_tx_entry *txep;
 744         uint16_t n, nb_commit, tx_id;
 745         uint64_t flags = ICE_TD_CMD;
 746         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
 747
 748         /* cross rx_thresh boundary is not allowed */
 749         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 750
 751         if (txq->nb_tx_free < txq->tx_free_thresh)
 752                 ice_tx_free_bufs(txq);
 753
 754         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 755         if (unlikely(nb_pkts == 0))
 756                 return 0;
 757
 758         tx_id = txq->tx_tail;
 759         txdp = &txq->tx_ring[tx_id];
 760         txep = &txq->sw_ring[tx_id];
 761
 762         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 763
 764         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 765         if (nb_commit >= n) {
 766                 ice_tx_backlog_entry(txep, tx_pkts, n);
 767
 768                 ice_vtx(txdp, tx_pkts, n - 1, flags);
 769                 tx_pkts += (n - 1);
 770                 txdp += (n - 1);
 771
 772                 ice_vtx1(txdp, *tx_pkts++, rs);
 773
 774                 nb_commit = (uint16_t)(nb_commit - n);
 775
 776                 tx_id = 0;
 777                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 778
 779                 /* avoid reach the end of ring */
 780                 txdp = &txq->tx_ring[tx_id];
 781                 txep = &txq->sw_ring[tx_id];
 782         }
 783
 784         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
 785
 786         ice_vtx(txdp, tx_pkts, nb_commit, flags);
 787
 788         tx_id = (uint16_t)(tx_id + nb_commit);
 789         if (tx_id > txq->tx_next_rs) {
 790                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 791                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
 792                                          ICE_TXD_QW1_CMD_S);
 793                 txq->tx_next_rs =
 794                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 795         }
 796
 797         txq->tx_tail = tx_id;
 798
 799         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 800
 801         return nb_pkts;
 802 }
 803
 804 uint16_t
 805 ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
 806                          uint16_t nb_pkts)
 807 {
 808         uint16_t nb_tx = 0;
 809         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 810
 811         while (nb_pkts) {
 812                 uint16_t ret, num;
 813
 814                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 815                 ret = ice_xmit_fixed_burst_vec_avx512(tx_queue,
 816                                                       &tx_pkts[nb_tx], num);
 817                 nb_tx += ret;
 818                 nb_pkts -= ret;
 819                 if (ret < num)
 820                         break;
 821         }
 822
 823         return nb_tx;
 824 }