net/ice: add memory allocation check in RSS init
[dpdk.git] / drivers / net / ice / ice_rxtx_vec_sse.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2019 Intel Corporation
3  */
4
5 #include "ice_rxtx_vec_common.h"
6
7 #include <tmmintrin.h>
8
9 #ifndef __INTEL_COMPILER
10 #pragma GCC diagnostic ignored "-Wcast-qual"
11 #endif
12
13 static inline void
14 ice_rxq_rearm(struct ice_rx_queue *rxq)
15 {
16         int i;
17         uint16_t rx_id;
18         volatile union ice_rx_flex_desc *rxdp;
19         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
20         struct rte_mbuf *mb0, *mb1;
21         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
22                                           RTE_PKTMBUF_HEADROOM);
23         __m128i dma_addr0, dma_addr1;
24
25         rxdp = rxq->rx_ring + rxq->rxrearm_start;
26
27         /* Pull 'n' more MBUFs into the software ring */
28         if (rte_mempool_get_bulk(rxq->mp,
29                                  (void *)rxep,
30                                  ICE_RXQ_REARM_THRESH) < 0) {
31                 if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
32                     rxq->nb_rx_desc) {
33                         dma_addr0 = _mm_setzero_si128();
34                         for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
35                                 rxep[i].mbuf = &rxq->fake_mbuf;
36                                 _mm_store_si128((__m128i *)&rxdp[i].read,
37                                                 dma_addr0);
38                         }
39                 }
40                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
41                         ICE_RXQ_REARM_THRESH;
42                 return;
43         }
44
45         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
46         for (i = 0; i < ICE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
47                 __m128i vaddr0, vaddr1;
48
49                 mb0 = rxep[0].mbuf;
50                 mb1 = rxep[1].mbuf;
51
52                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
53                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
54                                  offsetof(struct rte_mbuf, buf_addr) + 8);
55                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
56                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
57
58                 /* convert pa to dma_addr hdr/data */
59                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
60                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
61
62                 /* add headroom to pa values */
63                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
64                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
65
66                 /* flush desc with pa dma_addr */
67                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
68                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
69         }
70
71         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
72         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
73                 rxq->rxrearm_start = 0;
74
75         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
76
77         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
78                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
79
80         /* Update the tail pointer on the NIC */
81         ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
82 }
83
84 static inline void
85 ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4],
86                          struct rte_mbuf **rx_pkts)
87 {
88         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
89         __m128i rearm0, rearm1, rearm2, rearm3;
90
91         __m128i tmp_desc, flags, rss_vlan;
92
93         /* mask everything except checksum, RSS and VLAN flags.
94          * bit6:4 for checksum.
95          * bit12 for RSS indication.
96          * bit13 for VLAN indication.
97          */
98         const __m128i desc_mask = _mm_set_epi32(0x3070, 0x3070,
99                                                 0x3070, 0x3070);
100
101         const __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_MASK |
102                                                  PKT_RX_L4_CKSUM_MASK |
103                                                  PKT_RX_EIP_CKSUM_BAD,
104                                                  PKT_RX_IP_CKSUM_MASK |
105                                                  PKT_RX_L4_CKSUM_MASK |
106                                                  PKT_RX_EIP_CKSUM_BAD,
107                                                  PKT_RX_IP_CKSUM_MASK |
108                                                  PKT_RX_L4_CKSUM_MASK |
109                                                  PKT_RX_EIP_CKSUM_BAD,
110                                                  PKT_RX_IP_CKSUM_MASK |
111                                                  PKT_RX_L4_CKSUM_MASK |
112                                                  PKT_RX_EIP_CKSUM_BAD);
113
114         /* map the checksum, rss and vlan fields to the checksum, rss
115          * and vlan flag
116          */
117         const __m128i cksum_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
118                         /* shift right 1 bit to make sure it not exceed 255 */
119                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
120                          PKT_RX_IP_CKSUM_BAD) >> 1,
121                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
122                          PKT_RX_IP_CKSUM_GOOD) >> 1,
123                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
124                          PKT_RX_IP_CKSUM_BAD) >> 1,
125                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
126                          PKT_RX_IP_CKSUM_GOOD) >> 1,
127                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
128                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
129                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
130                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
131
132         const __m128i rss_vlan_flags = _mm_set_epi8(0, 0, 0, 0,
133                         0, 0, 0, 0,
134                         0, 0, 0, 0,
135                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
136                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
137                         PKT_RX_RSS_HASH, 0);
138
139         /* merge 4 descriptors */
140         flags = _mm_unpackhi_epi32(descs[0], descs[1]);
141         tmp_desc = _mm_unpackhi_epi32(descs[2], descs[3]);
142         tmp_desc = _mm_unpacklo_epi64(flags, tmp_desc);
143         tmp_desc = _mm_and_si128(flags, desc_mask);
144
145         /* checksum flags */
146         tmp_desc = _mm_srli_epi32(tmp_desc, 4);
147         flags = _mm_shuffle_epi8(cksum_flags, tmp_desc);
148         /* then we shift left 1 bit */
149         flags = _mm_slli_epi32(flags, 1);
150         /* we need to mask out the reduntant bits introduced by RSS or
151          * VLAN fields.
152          */
153         flags = _mm_and_si128(flags, cksum_mask);
154
155         /* RSS, VLAN flag */
156         tmp_desc = _mm_srli_epi32(tmp_desc, 8);
157         rss_vlan = _mm_shuffle_epi8(rss_vlan_flags, tmp_desc);
158
159         /* merge the flags */
160         flags = _mm_or_si128(flags, rss_vlan);
161
162         /**
163          * At this point, we have the 4 sets of flags in the low 16-bits
164          * of each 32-bit value in flags.
165          * We want to extract these, and merge them with the mbuf init data
166          * so we can do a single 16-byte write to the mbuf to set the flags
167          * and all the other initialization fields. Extracting the
168          * appropriate flags means that we have to do a shift and blend for
169          * each mbuf before we do the write.
170          */
171         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 8), 0x10);
172         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 4), 0x10);
173         rearm2 = _mm_blend_epi16(mbuf_init, flags, 0x10);
174         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x10);
175
176         /* write the rearm data and the olflags in one write */
177         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
178                          offsetof(struct rte_mbuf, rearm_data) + 8);
179         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
180                          RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
181         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
182         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
183         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
184         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
185 }
186
187 static inline void
188 ice_rx_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
189                        uint32_t *ptype_tbl)
190 {
191         const __m128i ptype_mask = _mm_set_epi16(0, ICE_RX_FLEX_DESC_PTYPE_M,
192                                                  0, ICE_RX_FLEX_DESC_PTYPE_M,
193                                                  0, ICE_RX_FLEX_DESC_PTYPE_M,
194                                                  0, ICE_RX_FLEX_DESC_PTYPE_M);
195         __m128i ptype_01 = _mm_unpacklo_epi32(descs[0], descs[1]);
196         __m128i ptype_23 = _mm_unpacklo_epi32(descs[2], descs[3]);
197         __m128i ptype_all = _mm_unpacklo_epi64(ptype_01, ptype_23);
198
199         ptype_all = _mm_and_si128(ptype_all, ptype_mask);
200
201         rx_pkts[0]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 1)];
202         rx_pkts[1]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 3)];
203         rx_pkts[2]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 5)];
204         rx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 7)];
205 }
206
207 /**
208  * Notice:
209  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
210  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
211  *   numbers of DD bits
212  */
213 static inline uint16_t
214 _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,
215                        uint16_t nb_pkts, uint8_t *split_packet)
216 {
217         volatile union ice_rx_flex_desc *rxdp;
218         struct ice_rx_entry *sw_ring;
219         uint16_t nb_pkts_recd;
220         int pos;
221         uint64_t var;
222         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
223         __m128i crc_adjust = _mm_set_epi16
224                                 (0, 0, 0,       /* ignore non-length fields */
225                                  -rxq->crc_len, /* sub crc on data_len */
226                                  0,          /* ignore high-16bits of pkt_len */
227                                  -rxq->crc_len, /* sub crc on pkt_len */
228                                  0, 0           /* ignore pkt_type field */
229                                 );
230         const __m128i zero = _mm_setzero_si128();
231         /* mask to shuffle from desc. to mbuf */
232         const __m128i shuf_msk = _mm_set_epi8
233                         (15, 14, 13, 12,  /* octet 12~15, 32 bits rss */
234                          11, 10,      /* octet 10~11, 16 bits vlan_macip */
235                          5, 4,        /* octet 4~5, 16 bits data_len */
236                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
237                          5, 4,        /* octet 4~5, low 16 bits pkt_len */
238                          0xFF, 0xFF,  /* pkt_type set as unknown */
239                          0xFF, 0xFF   /* pkt_type set as unknown */
240                         );
241         const __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,
242                                                    0xFF, 0xFF,
243                                                    0xFF, 0xFF,
244                                                    0xFF, 0xFF,
245                                                    0xFF, 0xFF,
246                                                    0xFF, 0xFF,
247                                                    0x04, 0x0C,
248                                                    0x00, 0x08);
249
250         /**
251          * compile-time check the above crc_adjust layout is correct.
252          * NOTE: the first field (lowest address) is given last in set_epi16
253          * call above.
254          */
255         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
256                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
257         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
258                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
259
260         /* 4 packets DD mask */
261         const __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,
262                                                 0x0000000100000001LL);
263         /* 4 packets EOP mask */
264         const __m128i eop_check = _mm_set_epi64x(0x0000000200000002LL,
265                                                  0x0000000200000002LL);
266
267         /* nb_pkts shall be less equal than ICE_MAX_RX_BURST */
268         nb_pkts = RTE_MIN(nb_pkts, ICE_MAX_RX_BURST);
269
270         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP */
271         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP);
272
273         /* Just the act of getting into the function from the application is
274          * going to cost about 7 cycles
275          */
276         rxdp = rxq->rx_ring + rxq->rx_tail;
277
278         rte_prefetch0(rxdp);
279
280         /* See if we need to rearm the RX queue - gives the prefetch a bit
281          * of time to act
282          */
283         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
284                 ice_rxq_rearm(rxq);
285
286         /* Before we start moving massive data around, check to see if
287          * there is actually a packet available
288          */
289         if (!(rxdp->wb.status_error0 &
290               rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
291                 return 0;
292
293         /**
294          * Compile-time verify the shuffle mask
295          * NOTE: some field positions already verified above, but duplicated
296          * here for completeness in case of future modifications.
297          */
298         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
299                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
300         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
301                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
302         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
303                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
304         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
305                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
306
307         /* Cache is empty -> need to scan the buffer rings, but first move
308          * the next 'n' mbufs into the cache
309          */
310         sw_ring = &rxq->sw_ring[rxq->rx_tail];
311
312         /* A. load 4 packet in one loop
313          * [A*. mask out 4 unused dirty field in desc]
314          * B. copy 4 mbuf point from swring to rx_pkts
315          * C. calc the number of DD bits among the 4 packets
316          * [C*. extract the end-of-packet bit, if requested]
317          * D. fill info. from desc to mbuf
318          */
319
320         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
321              pos += ICE_DESCS_PER_LOOP,
322              rxdp += ICE_DESCS_PER_LOOP) {
323                 __m128i descs[ICE_DESCS_PER_LOOP];
324                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
325                 __m128i staterr, sterr_tmp1, sterr_tmp2;
326                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
327                 __m128i mbp1;
328 #if defined(RTE_ARCH_X86_64)
329                 __m128i mbp2;
330 #endif
331
332                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
333                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
334                 /* Read desc statuses backwards to avoid race condition */
335                 /* A.1 load 4 pkts desc */
336                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
337                 rte_compiler_barrier();
338
339                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
340                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
341
342 #if defined(RTE_ARCH_X86_64)
343                 /* B.1 load 2 64 bit mbuf points */
344                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
345 #endif
346
347                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
348                 rte_compiler_barrier();
349                 /* B.1 load 2 mbuf point */
350                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
351                 rte_compiler_barrier();
352                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
353
354 #if defined(RTE_ARCH_X86_64)
355                 /* B.2 copy 2 mbuf point into rx_pkts  */
356                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
357 #endif
358
359                 if (split_packet) {
360                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
361                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
362                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
363                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
364                 }
365
366                 /* avoid compiler reorder optimization */
367                 rte_compiler_barrier();
368
369                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
370                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
371                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
372
373                 /* C.1 4=>2 filter staterr info only */
374                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
375                 /* C.1 4=>2 filter staterr info only */
376                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
377
378                 ice_rx_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
379
380                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
381                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
382                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
383
384                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
385                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
386                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
387
388                 /* C.2 get 4 pkts staterr value  */
389                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
390
391                 /* D.3 copy final 3,4 data to rx_pkts */
392                 _mm_storeu_si128
393                         ((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
394                          pkt_mb4);
395                 _mm_storeu_si128
396                         ((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
397                          pkt_mb3);
398
399                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
400                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
401                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
402
403                 /* C* extract and record EOP bit */
404                 if (split_packet) {
405                         /* and with mask to extract bits, flipping 1-0 */
406                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
407                         /* the staterr values are not in order, as the count
408                          * count of dd bits doesn't care. However, for end of
409                          * packet tracking, we do care, so shuffle. This also
410                          * compresses the 32-bit values to 8-bit
411                          */
412                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
413                         /* store the resulting 32-bit value */
414                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
415                         split_packet += ICE_DESCS_PER_LOOP;
416                 }
417
418                 /* C.3 calc available number of desc */
419                 staterr = _mm_and_si128(staterr, dd_check);
420                 staterr = _mm_packs_epi32(staterr, zero);
421
422                 /* D.3 copy final 1,2 data to rx_pkts */
423                 _mm_storeu_si128
424                         ((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
425                          pkt_mb2);
426                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
427                                  pkt_mb1);
428                 ice_rx_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
429                 /* C.4 calc avaialbe number of desc */
430                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
431                 nb_pkts_recd += var;
432                 if (likely(var != ICE_DESCS_PER_LOOP))
433                         break;
434         }
435
436         /* Update our internal tail pointer */
437         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
438         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
439         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
440
441         return nb_pkts_recd;
442 }
443
444 /**
445  * Notice:
446  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
447  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
448  *   numbers of DD bits
449  */
450 uint16_t
451 ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
452                   uint16_t nb_pkts)
453 {
454         return _ice_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
455 }
456
457 /* vPMD receive routine that reassembles scattered packets
458  * Notice:
459  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
460  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
461  *   numbers of DD bits
462  */
463 uint16_t
464 ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
465                             uint16_t nb_pkts)
466 {
467         struct ice_rx_queue *rxq = rx_queue;
468         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
469
470         /* get some new buffers */
471         uint16_t nb_bufs = _ice_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
472                                                   split_flags);
473         if (nb_bufs == 0)
474                 return 0;
475
476         /* happy day case, full burst + no packets to be joined */
477         const uint64_t *split_fl64 = (uint64_t *)split_flags;
478
479         if (!rxq->pkt_first_seg &&
480             split_fl64[0] == 0 && split_fl64[1] == 0 &&
481             split_fl64[2] == 0 && split_fl64[3] == 0)
482                 return nb_bufs;
483
484         /* reassemble any packets that need reassembly*/
485         unsigned int i = 0;
486
487         if (!rxq->pkt_first_seg) {
488                 /* find the first split flag, and only reassemble then*/
489                 while (i < nb_bufs && !split_flags[i])
490                         i++;
491                 if (i == nb_bufs)
492                         return nb_bufs;
493                 rxq->pkt_first_seg = rx_pkts[i];
494         }
495         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
496                                              &split_flags[i]);
497 }
498
499 static inline void
500 ice_vtx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf *pkt,
501          uint64_t flags)
502 {
503         uint64_t high_qw =
504                 (ICE_TX_DESC_DTYPE_DATA |
505                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
506                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
507
508         __m128i descriptor = _mm_set_epi64x(high_qw,
509                                             pkt->buf_iova + pkt->data_off);
510         _mm_store_si128((__m128i *)txdp, descriptor);
511 }
512
513 static inline void
514 ice_vtx(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkt,
515         uint16_t nb_pkts, uint64_t flags)
516 {
517         int i;
518
519         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
520                 ice_vtx1(txdp, *pkt, flags);
521 }
522
523 static uint16_t
524 ice_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
525                          uint16_t nb_pkts)
526 {
527         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
528         volatile struct ice_tx_desc *txdp;
529         struct ice_tx_entry *txep;
530         uint16_t n, nb_commit, tx_id;
531         uint64_t flags = ICE_TD_CMD;
532         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
533         int i;
534
535         /* cross rx_thresh boundary is not allowed */
536         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
537
538         if (txq->nb_tx_free < txq->tx_free_thresh)
539                 ice_tx_free_bufs(txq);
540
541         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
542         nb_commit = nb_pkts;
543         if (unlikely(nb_pkts == 0))
544                 return 0;
545
546         tx_id = txq->tx_tail;
547         txdp = &txq->tx_ring[tx_id];
548         txep = &txq->sw_ring[tx_id];
549
550         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
551
552         n = (uint16_t)(txq->nb_tx_desc - tx_id);
553         if (nb_commit >= n) {
554                 ice_tx_backlog_entry(txep, tx_pkts, n);
555
556                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
557                         ice_vtx1(txdp, *tx_pkts, flags);
558
559                 ice_vtx1(txdp, *tx_pkts++, rs);
560
561                 nb_commit = (uint16_t)(nb_commit - n);
562
563                 tx_id = 0;
564                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
565
566                 /* avoid reach the end of ring */
567                 txdp = &txq->tx_ring[tx_id];
568                 txep = &txq->sw_ring[tx_id];
569         }
570
571         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
572
573         ice_vtx(txdp, tx_pkts, nb_commit, flags);
574
575         tx_id = (uint16_t)(tx_id + nb_commit);
576         if (tx_id > txq->tx_next_rs) {
577                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
578                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
579                                          ICE_TXD_QW1_CMD_S);
580                 txq->tx_next_rs =
581                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
582         }
583
584         txq->tx_tail = tx_id;
585
586         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
587
588         return nb_pkts;
589 }
590
591 uint16_t
592 ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
593                   uint16_t nb_pkts)
594 {
595         uint16_t nb_tx = 0;
596         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
597
598         while (nb_pkts) {
599                 uint16_t ret, num;
600
601                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
602                 ret = ice_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
603                 nb_tx += ret;
604                 nb_pkts -= ret;
605                 if (ret < num)
606                         break;
607         }
608
609         return nb_tx;
610 }
611
612 int __rte_cold
613 ice_rxq_vec_setup(struct ice_rx_queue *rxq)
614 {
615         if (!rxq)
616                 return -1;
617
618         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs_vec;
619         return ice_rxq_vec_setup_default(rxq);
620 }
621
622 int __rte_cold
623 ice_txq_vec_setup(struct ice_tx_queue __rte_unused *txq)
624 {
625         if (!txq)
626                 return -1;
627
628         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs_vec;
629         return 0;
630 }
631
632 int __rte_cold
633 ice_rx_vec_dev_check(struct rte_eth_dev *dev)
634 {
635         return ice_rx_vec_dev_check_default(dev);
636 }
637
638 int __rte_cold
639 ice_tx_vec_dev_check(struct rte_eth_dev *dev)
640 {
641         return ice_tx_vec_dev_check_default(dev);
642 }