1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
8 void igc_init_phy_ops_generic(struct igc_hw *hw);
9 s32 igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
10 void igc_null_phy_generic(struct igc_hw *hw);
11 s32 igc_null_lplu_state(struct igc_hw *hw, bool active);
12 s32 igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
13 s32 igc_null_set_page(struct igc_hw *hw, u16 data);
14 s32 igc_read_i2c_byte_null(struct igc_hw *hw, u8 byte_offset,
15 u8 dev_addr, u8 *data);
16 s32 igc_write_i2c_byte_null(struct igc_hw *hw, u8 byte_offset,
17 u8 dev_addr, u8 data);
18 s32 igc_check_downshift_generic(struct igc_hw *hw);
19 s32 igc_check_polarity_m88(struct igc_hw *hw);
20 s32 igc_check_polarity_igp(struct igc_hw *hw);
21 s32 igc_check_polarity_ife(struct igc_hw *hw);
22 s32 igc_check_reset_block_generic(struct igc_hw *hw);
23 s32 igc_phy_setup_autoneg(struct igc_hw *hw);
24 s32 igc_copper_link_autoneg(struct igc_hw *hw);
25 s32 igc_copper_link_setup_igp(struct igc_hw *hw);
26 s32 igc_copper_link_setup_m88(struct igc_hw *hw);
27 s32 igc_copper_link_setup_m88_gen2(struct igc_hw *hw);
28 s32 igc_phy_force_speed_duplex_igp(struct igc_hw *hw);
29 s32 igc_phy_force_speed_duplex_m88(struct igc_hw *hw);
30 s32 igc_phy_force_speed_duplex_ife(struct igc_hw *hw);
31 s32 igc_get_cable_length_m88(struct igc_hw *hw);
32 s32 igc_get_cable_length_m88_gen2(struct igc_hw *hw);
33 s32 igc_get_cable_length_igp_2(struct igc_hw *hw);
34 s32 igc_get_cfg_done_generic(struct igc_hw *hw);
35 s32 igc_get_phy_id(struct igc_hw *hw);
36 s32 igc_get_phy_info_igp(struct igc_hw *hw);
37 s32 igc_get_phy_info_m88(struct igc_hw *hw);
38 s32 igc_get_phy_info_ife(struct igc_hw *hw);
39 s32 igc_phy_sw_reset_generic(struct igc_hw *hw);
40 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);
41 s32 igc_phy_hw_reset_generic(struct igc_hw *hw);
42 s32 igc_phy_reset_dsp_generic(struct igc_hw *hw);
43 s32 igc_read_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 *data);
44 s32 igc_read_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 *data);
45 s32 igc_set_page_igp(struct igc_hw *hw, u16 page);
46 s32 igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data);
47 s32 igc_read_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 *data);
48 s32 igc_read_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 *data);
49 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);
50 s32 igc_setup_copper_link_generic(struct igc_hw *hw);
51 s32 igc_write_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 data);
52 s32 igc_write_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 data);
53 s32 igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data);
54 s32 igc_write_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 data);
55 s32 igc_write_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 data);
56 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
57 u32 usec_interval, bool *success);
58 s32 igc_phy_init_script_igp3(struct igc_hw *hw);
59 enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
60 s32 igc_determine_phy_address(struct igc_hw *hw);
61 s32 igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data);
62 s32 igc_read_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 *data);
63 s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
64 s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
65 s32 igc_read_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 *data);
66 s32 igc_write_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 data);
67 void igc_power_up_phy_copper(struct igc_hw *hw);
68 void igc_power_down_phy_copper(struct igc_hw *hw);
69 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);
70 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);
71 s32 igc_read_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 *data);
72 s32 igc_write_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 data);
73 s32 igc_read_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 *data);
74 s32 igc_write_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 data);
75 s32 igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data);
76 s32 igc_read_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 *data);
77 s32 igc_read_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 *data);
78 s32 igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data);
79 s32 igc_write_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 data);
80 s32 igc_write_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 data);
81 s32 igc_link_stall_workaround_hv(struct igc_hw *hw);
82 s32 igc_copper_link_setup_82577(struct igc_hw *hw);
83 s32 igc_check_polarity_82577(struct igc_hw *hw);
84 s32 igc_get_phy_info_82577(struct igc_hw *hw);
85 s32 igc_phy_force_speed_duplex_82577(struct igc_hw *hw);
86 s32 igc_get_cable_length_82577(struct igc_hw *hw);
87 s32 igc_write_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 data);
88 s32 igc_read_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 *data);
89 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);
90 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);
91 s32 igc_read_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 *data);
92 s32 igc_write_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 data,
94 bool igc_is_mphy_ready(struct igc_hw *hw);
96 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
98 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
101 #define IGC_MAX_PHY_ADDR 8
103 /* IGP01E1000 Specific Registers */
104 #define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */
105 #define IGP01IGC_PHY_PORT_STATUS 0x11 /* Status */
106 #define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */
107 #define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
108 #define IGP01IGC_GMII_FIFO 0x14 /* GMII FIFO */
109 #define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */
110 #define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */
111 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
112 #define IGP_PAGE_SHIFT 5
113 #define PHY_REG_MASK 0x1F
115 /* GS40G - I210 PHY defines */
116 #define GS40G_PAGE_SELECT 0x16
117 #define GS40G_PAGE_SHIFT 16
118 #define GS40G_OFFSET_MASK 0xFFFF
119 #define GS40G_PAGE_2 0x20000
120 #define GS40G_MAC_REG2 0x15
121 #define GS40G_MAC_LB 0x4140
122 #define GS40G_MAC_SPEED_1G 0X0006
123 #define GS40G_COPPER_SPEC 0x0010
125 #define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */
126 #define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */
127 #define IGC_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */
128 #define IGC_I225_PHPM_GO_LINKD 0x0020 /* Go Link Disconnect */
129 #define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */
130 #define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */
131 #define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */
132 #define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */
133 #define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */
134 #define IGC_I225_PHPM_DIS_2500 0x0800 /* Disable 2.5G globally */
135 #define IGC_I225_PHPM_DIS_2500_D3 0x1000 /* Disable 2.5G in D3 */
136 /* GPY211 - I225 defines */
137 #define GPY_MMD_MASK 0xFFFF0000
138 #define GPY_MMD_SHIFT 16
139 #define GPY_REG_MASK 0x0000FFFF
140 /* BM/HV Specific Registers */
141 #define BM_PORT_CTRL_PAGE 769
142 #define BM_WUC_PAGE 800
143 #define BM_WUC_ADDRESS_OPCODE 0x11
144 #define BM_WUC_DATA_OPCODE 0x12
145 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
146 #define BM_WUC_ENABLE_REG 17
147 #define BM_WUC_ENABLE_BIT (1 << 2)
148 #define BM_WUC_HOST_WU_BIT (1 << 4)
149 #define BM_WUC_ME_WU_BIT (1 << 5)
151 #define PHY_UPPER_SHIFT 21
153 #define BM_PHY_REG(page, reg) ( \
155 typeof(page) _page = (page); \
156 typeof(reg) _reg = (reg); \
157 (_reg & MAX_PHY_REG_ADDRESS) | \
158 ((_page & 0xFFFF) << PHY_PAGE_SHIFT) | \
159 ((_reg & ~MAX_PHY_REG_ADDRESS) << \
160 (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)); \
163 #define BM_PHY_REG_PAGE(offset) \
164 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
166 #define BM_PHY_REG_NUM(offset) ( \
168 typeof(offset) _offset = (offset); \
169 (u16)((_offset & MAX_PHY_REG_ADDRESS) | \
170 ((_offset >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) & \
171 ~MAX_PHY_REG_ADDRESS)); \
174 #define HV_INTC_FC_PAGE_START 768
175 #define I82578_ADDR_REG 29
176 #define I82577_ADDR_REG 16
177 #define I82577_CFG_REG 22
178 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
179 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */
180 #define I82577_CTRL_REG 23
182 /* 82577 specific PHY registers */
183 #define I82577_PHY_CTRL_2 18
184 #define I82577_PHY_LBK_CTRL 19
185 #define I82577_PHY_STATUS_2 26
186 #define I82577_PHY_DIAG_STATUS 31
188 /* I82577 PHY Status 2 */
189 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
190 #define I82577_PHY_STATUS2_MDIX 0x0800
191 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
192 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
194 /* I82577 PHY Control 2 */
195 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
196 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
197 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
199 /* I82577 PHY Diagnostics Status */
200 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
201 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
203 /* 82580 PHY Power Management */
204 #define IGC_82580_PHY_POWER_MGMT 0xE14
205 #define IGC_82580_PM_SPD 0x0001 /* Smart Power Down */
206 #define IGC_82580_PM_D0_LPLU 0x0002 /* For D0a states */
207 #define IGC_82580_PM_D3_LPLU 0x0004 /* For all other states */
208 #define IGC_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
210 #define IGC_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */
211 #define IGC_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */
212 #define IGC_MPHY_BUSY 0x00010000 /* busy bit */
213 #define IGC_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */
214 #define IGC_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */
216 /* BM PHY Copper Specific Control 1 */
217 #define BM_CS_CTRL1 16
219 /* BM PHY Copper Specific Status */
220 #define BM_CS_STATUS 17
221 #define BM_CS_STATUS_LINK_UP 0x0400
222 #define BM_CS_STATUS_RESOLVED 0x0800
223 #define BM_CS_STATUS_SPEED_MASK 0xC000
224 #define BM_CS_STATUS_SPEED_1000 0x8000
226 /* 82577 Mobile Phy Status Register */
227 #define HV_M_STATUS 26
228 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
229 #define HV_M_STATUS_SPEED_MASK 0x0300
230 #define HV_M_STATUS_SPEED_1000 0x0200
231 #define HV_M_STATUS_SPEED_100 0x0100
232 #define HV_M_STATUS_LINK_UP 0x0040
234 #define IGP01IGC_PHY_PCS_INIT_REG 0x00B4
235 #define IGP01IGC_PHY_POLARITY_MASK 0x0078
237 #define IGP01IGC_PSCR_AUTO_MDIX 0x1000
238 #define IGP01IGC_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
240 #define IGP01IGC_PSCFR_SMART_SPEED 0x0080
242 /* Enable flexible speed on link-up */
243 #define IGP01IGC_GMII_FLEX_SPD 0x0010
244 #define IGP01IGC_GMII_SPD 0x0020 /* Enable SPD */
246 #define IGP02IGC_PM_SPD 0x0001 /* Smart Power Down */
247 #define IGP02IGC_PM_D0_LPLU 0x0002 /* For D0a states */
248 #define IGP02IGC_PM_D3_LPLU 0x0004 /* For all other states */
250 #define IGP01IGC_PLHR_SS_DOWNGRADE 0x8000
252 #define IGP01IGC_PSSR_POLARITY_REVERSED 0x0002
253 #define IGP01IGC_PSSR_MDIX 0x0800
254 #define IGP01IGC_PSSR_SPEED_MASK 0xC000
255 #define IGP01IGC_PSSR_SPEED_1000MBPS 0xC000
257 #define IGP02IGC_PHY_CHANNEL_NUM 4
258 #define IGP02IGC_PHY_AGC_A 0x11B1
259 #define IGP02IGC_PHY_AGC_B 0x12B1
260 #define IGP02IGC_PHY_AGC_C 0x14B1
261 #define IGP02IGC_PHY_AGC_D 0x18B1
263 #define IGP02IGC_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
264 #define IGP02IGC_AGC_LENGTH_MASK 0x7F
265 #define IGP02IGC_AGC_RANGE 15
267 #define IGC_CABLE_LENGTH_UNDEFINED 0xFF
269 #define IGC_KMRNCTRLSTA_OFFSET 0x001F0000
270 #define IGC_KMRNCTRLSTA_OFFSET_SHIFT 16
271 #define IGC_KMRNCTRLSTA_REN 0x00200000
272 #define IGC_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
273 #define IGC_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
274 #define IGC_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
275 #define IGC_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
276 #define IGC_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
277 #define IGC_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
278 #define IGC_KMRNCTRLSTA_K1_CONFIG 0x7
279 #define IGC_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
280 #define IGC_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
281 #define IGC_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
282 #define IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
283 #define IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4
284 #define IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \
285 (3 << IGC_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
286 #define IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
287 (7 << IGC_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
288 #define IGC_KMRNCTRLSTA_OP_MODES 0x1F /* Kumeran Modes of Operation */
289 #define IGC_KMRNCTRLSTA_OP_MODES_LSC2CSC 0x0002 /* change LSC to CSC */
291 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
292 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
293 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
294 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
296 /* IFE PHY Extended Status Control */
297 #define IFE_PESC_POLARITY_REVERSED 0x0100
299 /* IFE PHY Special Control */
300 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
301 #define IFE_PSC_FORCE_POLARITY 0x0020
303 /* IFE PHY Special Control and LED Control */
304 #define IFE_PSCL_PROBE_MODE 0x0020
305 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
306 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
308 /* IFE PHY MDIX Control */
309 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
310 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
311 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
313 /* SFP modules ID memory locations */
314 #define IGC_SFF_IDENTIFIER_OFFSET 0x00
315 #define IGC_SFF_IDENTIFIER_SFF 0x02
316 #define IGC_SFF_IDENTIFIER_SFP 0x03
318 #define IGC_SFF_ETH_FLAGS_OFFSET 0x06
319 /* Flags for SFP modules compatible with ETH up to 1Gb */
320 struct sfp_igc_flags {
331 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
332 #define IGC_SFF_VENDOR_OUI_TYCO 0x00407600
333 #define IGC_SFF_VENDOR_OUI_FTL 0x00906500
334 #define IGC_SFF_VENDOR_OUI_AVAGO 0x00176A00
335 #define IGC_SFF_VENDOR_OUI_INTEL 0x001B2100