drivers/net/igc/igc_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2020 Intel Corporation
   3  */
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7
   8 #include <rte_string_fns.h>
   9 #include <rte_pci.h>
  10 #include <rte_bus_pci.h>
  11 #include <rte_ethdev_driver.h>
  12 #include <rte_ethdev_pci.h>
  13 #include <rte_malloc.h>
  14 #include <rte_alarm.h>
  15
  16 #include "igc_logs.h"
  17 #include "igc_txrx.h"
  18 #include "igc_filter.h"
  19 #include "igc_flow.h"
  20
  21 #define IGC_INTEL_VENDOR_ID             0x8086
  22
  23 /*
  24  * The overhead from MTU to max frame size.
  25  * Considering VLAN so tag needs to be counted.
  26  */
  27 #define IGC_ETH_OVERHEAD                (RTE_ETHER_HDR_LEN + \
  28                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE)
  29
  30 #define IGC_FC_PAUSE_TIME               0x0680
  31 #define IGC_LINK_UPDATE_CHECK_TIMEOUT   90  /* 9s */
  32 #define IGC_LINK_UPDATE_CHECK_INTERVAL  100 /* ms */
  33
  34 #define IGC_MISC_VEC_ID                 RTE_INTR_VEC_ZERO_OFFSET
  35 #define IGC_RX_VEC_START                RTE_INTR_VEC_RXTX_OFFSET
  36 #define IGC_MSIX_OTHER_INTR_VEC         0   /* MSI-X other interrupt vector */
  37 #define IGC_FLAG_NEED_LINK_UPDATE       (1u << 0)       /* need update link */
  38
  39 #define IGC_DEFAULT_RX_FREE_THRESH      32
  40
  41 #define IGC_DEFAULT_RX_PTHRESH          8
  42 #define IGC_DEFAULT_RX_HTHRESH          8
  43 #define IGC_DEFAULT_RX_WTHRESH          4
  44
  45 #define IGC_DEFAULT_TX_PTHRESH          8
  46 #define IGC_DEFAULT_TX_HTHRESH          1
  47 #define IGC_DEFAULT_TX_WTHRESH          16
  48
  49 /* MSI-X other interrupt vector */
  50 #define IGC_MSIX_OTHER_INTR_VEC         0
  51
  52 /* External VLAN Enable bit mask */
  53 #define IGC_CTRL_EXT_EXT_VLAN           (1u << 26)
  54
  55 /* Speed select */
  56 #define IGC_CTRL_SPEED_MASK             (7u << 8)
  57 #define IGC_CTRL_SPEED_2500             (6u << 8)
  58
  59 /* External VLAN Ether Type bit mask and shift */
  60 #define IGC_VET_EXT                     0xFFFF0000
  61 #define IGC_VET_EXT_SHIFT               16
  62
  63 /* Force EEE Auto-negotiation */
  64 #define IGC_EEER_EEE_FRC_AN             (1u << 28)
  65
  66 /* Per Queue Good Packets Received Count */
  67 #define IGC_PQGPRC(idx)         (0x10010 + 0x100 * (idx))
  68 /* Per Queue Good Octets Received Count */
  69 #define IGC_PQGORC(idx)         (0x10018 + 0x100 * (idx))
  70 /* Per Queue Good Octets Transmitted Count */
  71 #define IGC_PQGOTC(idx)         (0x10034 + 0x100 * (idx))
  72 /* Per Queue Multicast Packets Received Count */
  73 #define IGC_PQMPRC(idx)         (0x10038 + 0x100 * (idx))
  74 /* Transmit Queue Drop Packet Count */
  75 #define IGC_TQDPC(idx)          (0xe030 + 0x40 * (idx))
  76
  77 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
  78 #define U32_0_IN_U64            0       /* lower bytes of u64 */
  79 #define U32_1_IN_U64            1       /* higher bytes of u64 */
  80 #else
  81 #define U32_0_IN_U64            1
  82 #define U32_1_IN_U64            0
  83 #endif
  84
  85 #define IGC_ALARM_INTERVAL      8000000u
  86 /* us, about 13.6s some per-queue registers will wrap around back to 0. */
  87
  88 static const struct rte_eth_desc_lim rx_desc_lim = {
  89         .nb_max = IGC_MAX_RXD,
  90         .nb_min = IGC_MIN_RXD,
  91         .nb_align = IGC_RXD_ALIGN,
  92 };
  93
  94 static const struct rte_eth_desc_lim tx_desc_lim = {
  95         .nb_max = IGC_MAX_TXD,
  96         .nb_min = IGC_MIN_TXD,
  97         .nb_align = IGC_TXD_ALIGN,
  98         .nb_seg_max = IGC_TX_MAX_SEG,
  99         .nb_mtu_seg_max = IGC_TX_MAX_MTU_SEG,
 100 };
 101
 102 static const struct rte_pci_id pci_id_igc_map[] = {
 103         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_LM) },
 104         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_V)  },
 105         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_I)  },
 106         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_K)  },
 107         { .vendor_id = 0, /* sentinel */ },
 108 };
 109
 110 /* store statistics names and its offset in stats structure */
 111 struct rte_igc_xstats_name_off {
 112         char name[RTE_ETH_XSTATS_NAME_SIZE];
 113         unsigned int offset;
 114 };
 115
 116 static const struct rte_igc_xstats_name_off rte_igc_stats_strings[] = {
 117         {"rx_crc_errors", offsetof(struct igc_hw_stats, crcerrs)},
 118         {"rx_align_errors", offsetof(struct igc_hw_stats, algnerrc)},
 119         {"rx_errors", offsetof(struct igc_hw_stats, rxerrc)},
 120         {"rx_missed_packets", offsetof(struct igc_hw_stats, mpc)},
 121         {"tx_single_collision_packets", offsetof(struct igc_hw_stats, scc)},
 122         {"tx_multiple_collision_packets", offsetof(struct igc_hw_stats, mcc)},
 123         {"tx_excessive_collision_packets", offsetof(struct igc_hw_stats,
 124                 ecol)},
 125         {"tx_late_collisions", offsetof(struct igc_hw_stats, latecol)},
 126         {"tx_total_collisions", offsetof(struct igc_hw_stats, colc)},
 127         {"tx_deferred_packets", offsetof(struct igc_hw_stats, dc)},
 128         {"tx_no_carrier_sense_packets", offsetof(struct igc_hw_stats, tncrs)},
 129         {"tx_discarded_packets", offsetof(struct igc_hw_stats, htdpmc)},
 130         {"rx_length_errors", offsetof(struct igc_hw_stats, rlec)},
 131         {"rx_xon_packets", offsetof(struct igc_hw_stats, xonrxc)},
 132         {"tx_xon_packets", offsetof(struct igc_hw_stats, xontxc)},
 133         {"rx_xoff_packets", offsetof(struct igc_hw_stats, xoffrxc)},
 134         {"tx_xoff_packets", offsetof(struct igc_hw_stats, xofftxc)},
 135         {"rx_flow_control_unsupported_packets", offsetof(struct igc_hw_stats,
 136                 fcruc)},
 137         {"rx_size_64_packets", offsetof(struct igc_hw_stats, prc64)},
 138         {"rx_size_65_to_127_packets", offsetof(struct igc_hw_stats, prc127)},
 139         {"rx_size_128_to_255_packets", offsetof(struct igc_hw_stats, prc255)},
 140         {"rx_size_256_to_511_packets", offsetof(struct igc_hw_stats, prc511)},
 141         {"rx_size_512_to_1023_packets", offsetof(struct igc_hw_stats,
 142                 prc1023)},
 143         {"rx_size_1024_to_max_packets", offsetof(struct igc_hw_stats,
 144                 prc1522)},
 145         {"rx_broadcast_packets", offsetof(struct igc_hw_stats, bprc)},
 146         {"rx_multicast_packets", offsetof(struct igc_hw_stats, mprc)},
 147         {"rx_undersize_errors", offsetof(struct igc_hw_stats, ruc)},
 148         {"rx_fragment_errors", offsetof(struct igc_hw_stats, rfc)},
 149         {"rx_oversize_errors", offsetof(struct igc_hw_stats, roc)},
 150         {"rx_jabber_errors", offsetof(struct igc_hw_stats, rjc)},
 151         {"rx_no_buffers", offsetof(struct igc_hw_stats, rnbc)},
 152         {"rx_management_packets", offsetof(struct igc_hw_stats, mgprc)},
 153         {"rx_management_dropped", offsetof(struct igc_hw_stats, mgpdc)},
 154         {"tx_management_packets", offsetof(struct igc_hw_stats, mgptc)},
 155         {"rx_total_packets", offsetof(struct igc_hw_stats, tpr)},
 156         {"tx_total_packets", offsetof(struct igc_hw_stats, tpt)},
 157         {"rx_total_bytes", offsetof(struct igc_hw_stats, tor)},
 158         {"tx_total_bytes", offsetof(struct igc_hw_stats, tot)},
 159         {"tx_size_64_packets", offsetof(struct igc_hw_stats, ptc64)},
 160         {"tx_size_65_to_127_packets", offsetof(struct igc_hw_stats, ptc127)},
 161         {"tx_size_128_to_255_packets", offsetof(struct igc_hw_stats, ptc255)},
 162         {"tx_size_256_to_511_packets", offsetof(struct igc_hw_stats, ptc511)},
 163         {"tx_size_512_to_1023_packets", offsetof(struct igc_hw_stats,
 164                 ptc1023)},
 165         {"tx_size_1023_to_max_packets", offsetof(struct igc_hw_stats,
 166                 ptc1522)},
 167         {"tx_multicast_packets", offsetof(struct igc_hw_stats, mptc)},
 168         {"tx_broadcast_packets", offsetof(struct igc_hw_stats, bptc)},
 169         {"tx_tso_packets", offsetof(struct igc_hw_stats, tsctc)},
 170         {"rx_sent_to_host_packets", offsetof(struct igc_hw_stats, rpthc)},
 171         {"tx_sent_by_host_packets", offsetof(struct igc_hw_stats, hgptc)},
 172         {"interrupt_assert_count", offsetof(struct igc_hw_stats, iac)},
 173         {"rx_descriptor_lower_threshold",
 174                 offsetof(struct igc_hw_stats, icrxdmtc)},
 175 };
 176
 177 #define IGC_NB_XSTATS (sizeof(rte_igc_stats_strings) / \
 178                 sizeof(rte_igc_stats_strings[0]))
 179
 180 static int eth_igc_configure(struct rte_eth_dev *dev);
 181 static int eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete);
 182 static void eth_igc_stop(struct rte_eth_dev *dev);
 183 static int eth_igc_start(struct rte_eth_dev *dev);
 184 static int eth_igc_set_link_up(struct rte_eth_dev *dev);
 185 static int eth_igc_set_link_down(struct rte_eth_dev *dev);
 186 static int eth_igc_close(struct rte_eth_dev *dev);
 187 static int eth_igc_reset(struct rte_eth_dev *dev);
 188 static int eth_igc_promiscuous_enable(struct rte_eth_dev *dev);
 189 static int eth_igc_promiscuous_disable(struct rte_eth_dev *dev);
 190 static int eth_igc_fw_version_get(struct rte_eth_dev *dev,
 191                                 char *fw_version, size_t fw_size);
 192 static int eth_igc_infos_get(struct rte_eth_dev *dev,
 193                         struct rte_eth_dev_info *dev_info);
 194 static int eth_igc_led_on(struct rte_eth_dev *dev);
 195 static int eth_igc_led_off(struct rte_eth_dev *dev);
 196 static const uint32_t *eth_igc_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static int eth_igc_rar_set(struct rte_eth_dev *dev,
 198                 struct rte_ether_addr *mac_addr, uint32_t index, uint32_t pool);
 199 static void eth_igc_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 200 static int eth_igc_default_mac_addr_set(struct rte_eth_dev *dev,
 201                         struct rte_ether_addr *addr);
 202 static int eth_igc_set_mc_addr_list(struct rte_eth_dev *dev,
 203                          struct rte_ether_addr *mc_addr_set,
 204                          uint32_t nb_mc_addr);
 205 static int eth_igc_allmulticast_enable(struct rte_eth_dev *dev);
 206 static int eth_igc_allmulticast_disable(struct rte_eth_dev *dev);
 207 static int eth_igc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 208 static int eth_igc_stats_get(struct rte_eth_dev *dev,
 209                         struct rte_eth_stats *rte_stats);
 210 static int eth_igc_xstats_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_xstat *xstats, unsigned int n);
 212 static int eth_igc_xstats_get_by_id(struct rte_eth_dev *dev,
 213                                 const uint64_t *ids,
 214                                 uint64_t *values, unsigned int n);
 215 static int eth_igc_xstats_get_names(struct rte_eth_dev *dev,
 216                                 struct rte_eth_xstat_name *xstats_names,
 217                                 unsigned int size);
 218 static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,
 219                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 220                 unsigned int limit);
 221 static int eth_igc_xstats_reset(struct rte_eth_dev *dev);
 222 static int
 223 eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev,
 224         uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx);
 225 static int
 226 eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 227 static int
 228 eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 229 static int
 230 eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
 231 static int
 232 eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
 233 static int eth_igc_rss_reta_update(struct rte_eth_dev *dev,
 234                         struct rte_eth_rss_reta_entry64 *reta_conf,
 235                         uint16_t reta_size);
 236 static int eth_igc_rss_reta_query(struct rte_eth_dev *dev,
 237                        struct rte_eth_rss_reta_entry64 *reta_conf,
 238                        uint16_t reta_size);
 239 static int eth_igc_rss_hash_update(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_conf *rss_conf);
 241 static int eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,
 242                         struct rte_eth_rss_conf *rss_conf);
 243 static int
 244 eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
 245 static int eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 246 static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 247                       enum rte_vlan_type vlan_type, uint16_t tpid);
 248
 249 static const struct eth_dev_ops eth_igc_ops = {
 250         .dev_configure          = eth_igc_configure,
 251         .link_update            = eth_igc_link_update,
 252         .dev_stop               = eth_igc_stop,
 253         .dev_start              = eth_igc_start,
 254         .dev_close              = eth_igc_close,
 255         .dev_reset              = eth_igc_reset,
 256         .dev_set_link_up        = eth_igc_set_link_up,
 257         .dev_set_link_down      = eth_igc_set_link_down,
 258         .promiscuous_enable     = eth_igc_promiscuous_enable,
 259         .promiscuous_disable    = eth_igc_promiscuous_disable,
 260         .allmulticast_enable    = eth_igc_allmulticast_enable,
 261         .allmulticast_disable   = eth_igc_allmulticast_disable,
 262         .fw_version_get         = eth_igc_fw_version_get,
 263         .dev_infos_get          = eth_igc_infos_get,
 264         .dev_led_on             = eth_igc_led_on,
 265         .dev_led_off            = eth_igc_led_off,
 266         .dev_supported_ptypes_get = eth_igc_supported_ptypes_get,
 267         .mtu_set                = eth_igc_mtu_set,
 268         .mac_addr_add           = eth_igc_rar_set,
 269         .mac_addr_remove        = eth_igc_rar_clear,
 270         .mac_addr_set           = eth_igc_default_mac_addr_set,
 271         .set_mc_addr_list       = eth_igc_set_mc_addr_list,
 272
 273         .rx_queue_setup         = eth_igc_rx_queue_setup,
 274         .rx_queue_release       = eth_igc_rx_queue_release,
 275         .tx_queue_setup         = eth_igc_tx_queue_setup,
 276         .tx_queue_release       = eth_igc_tx_queue_release,
 277         .tx_done_cleanup        = eth_igc_tx_done_cleanup,
 278         .rxq_info_get           = eth_igc_rxq_info_get,
 279         .txq_info_get           = eth_igc_txq_info_get,
 280         .stats_get              = eth_igc_stats_get,
 281         .xstats_get             = eth_igc_xstats_get,
 282         .xstats_get_by_id       = eth_igc_xstats_get_by_id,
 283         .xstats_get_names_by_id = eth_igc_xstats_get_names_by_id,
 284         .xstats_get_names       = eth_igc_xstats_get_names,
 285         .stats_reset            = eth_igc_xstats_reset,
 286         .xstats_reset           = eth_igc_xstats_reset,
 287         .queue_stats_mapping_set = eth_igc_queue_stats_mapping_set,
 288         .rx_queue_intr_enable   = eth_igc_rx_queue_intr_enable,
 289         .rx_queue_intr_disable  = eth_igc_rx_queue_intr_disable,
 290         .flow_ctrl_get          = eth_igc_flow_ctrl_get,
 291         .flow_ctrl_set          = eth_igc_flow_ctrl_set,
 292         .reta_update            = eth_igc_rss_reta_update,
 293         .reta_query             = eth_igc_rss_reta_query,
 294         .rss_hash_update        = eth_igc_rss_hash_update,
 295         .rss_hash_conf_get      = eth_igc_rss_hash_conf_get,
 296         .vlan_filter_set        = eth_igc_vlan_filter_set,
 297         .vlan_offload_set       = eth_igc_vlan_offload_set,
 298         .vlan_tpid_set          = eth_igc_vlan_tpid_set,
 299         .vlan_strip_queue_set   = eth_igc_vlan_strip_queue_set,
 300         .filter_ctrl            = eth_igc_filter_ctrl,
 301 };
 302
 303 /*
 304  * multiple queue mode checking
 305  */
 306 static int
 307 igc_check_mq_mode(struct rte_eth_dev *dev)
 308 {
 309         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 310         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 311
 312         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
 313                 PMD_INIT_LOG(ERR, "SRIOV is not supported.");
 314                 return -EINVAL;
 315         }
 316
 317         if (rx_mq_mode != ETH_MQ_RX_NONE &&
 318                 rx_mq_mode != ETH_MQ_RX_RSS) {
 319                 /* RSS together with VMDq not supported*/
 320                 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
 321                                 rx_mq_mode);
 322                 return -EINVAL;
 323         }
 324
 325         /* To no break software that set invalid mode, only display
 326          * warning if invalid mode is used.
 327          */
 328         if (tx_mq_mode != ETH_MQ_TX_NONE)
 329                 PMD_INIT_LOG(WARNING,
 330                         "TX mode %d is not supported. Due to meaningless in this driver, just ignore",
 331                         tx_mq_mode);
 332
 333         return 0;
 334 }
 335
 336 static int
 337 eth_igc_configure(struct rte_eth_dev *dev)
 338 {
 339         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 340         int ret;
 341
 342         PMD_INIT_FUNC_TRACE();
 343
 344         ret  = igc_check_mq_mode(dev);
 345         if (ret != 0)
 346                 return ret;
 347
 348         intr->flags |= IGC_FLAG_NEED_LINK_UPDATE;
 349         return 0;
 350 }
 351
 352 static int
 353 eth_igc_set_link_up(struct rte_eth_dev *dev)
 354 {
 355         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 356
 357         if (hw->phy.media_type == igc_media_type_copper)
 358                 igc_power_up_phy(hw);
 359         else
 360                 igc_power_up_fiber_serdes_link(hw);
 361         return 0;
 362 }
 363
 364 static int
 365 eth_igc_set_link_down(struct rte_eth_dev *dev)
 366 {
 367         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 368
 369         if (hw->phy.media_type == igc_media_type_copper)
 370                 igc_power_down_phy(hw);
 371         else
 372                 igc_shutdown_fiber_serdes_link(hw);
 373         return 0;
 374 }
 375
 376 /*
 377  * disable other interrupt
 378  */
 379 static void
 380 igc_intr_other_disable(struct rte_eth_dev *dev)
 381 {
 382         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 383         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 384         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 385
 386         if (rte_intr_allow_others(intr_handle) &&
 387                 dev->data->dev_conf.intr_conf.lsc) {
 388                 IGC_WRITE_REG(hw, IGC_EIMC, 1u << IGC_MSIX_OTHER_INTR_VEC);
 389         }
 390
 391         IGC_WRITE_REG(hw, IGC_IMC, ~0);
 392         IGC_WRITE_FLUSH(hw);
 393 }
 394
 395 /*
 396  * enable other interrupt
 397  */
 398 static inline void
 399 igc_intr_other_enable(struct rte_eth_dev *dev)
 400 {
 401         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 402         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 403         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 404         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 405
 406         if (rte_intr_allow_others(intr_handle) &&
 407                 dev->data->dev_conf.intr_conf.lsc) {
 408                 IGC_WRITE_REG(hw, IGC_EIMS, 1u << IGC_MSIX_OTHER_INTR_VEC);
 409         }
 410
 411         IGC_WRITE_REG(hw, IGC_IMS, intr->mask);
 412         IGC_WRITE_FLUSH(hw);
 413 }
 414
 415 /*
 416  * It reads ICR and gets interrupt causes, check it and set a bit flag
 417  * to update link status.
 418  */
 419 static void
 420 eth_igc_interrupt_get_status(struct rte_eth_dev *dev)
 421 {
 422         uint32_t icr;
 423         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 424         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 425
 426         /* read-on-clear nic registers here */
 427         icr = IGC_READ_REG(hw, IGC_ICR);
 428
 429         intr->flags = 0;
 430         if (icr & IGC_ICR_LSC)
 431                 intr->flags |= IGC_FLAG_NEED_LINK_UPDATE;
 432 }
 433
 434 /* return 0 means link status changed, -1 means not changed */
 435 static int
 436 eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 437 {
 438         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 439         struct rte_eth_link link;
 440         int link_check, count;
 441
 442         link_check = 0;
 443         hw->mac.get_link_status = 1;
 444
 445         /* possible wait-to-complete in up to 9 seconds */
 446         for (count = 0; count < IGC_LINK_UPDATE_CHECK_TIMEOUT; count++) {
 447                 /* Read the real link status */
 448                 switch (hw->phy.media_type) {
 449                 case igc_media_type_copper:
 450                         /* Do the work to read phy */
 451                         igc_check_for_link(hw);
 452                         link_check = !hw->mac.get_link_status;
 453                         break;
 454
 455                 case igc_media_type_fiber:
 456                         igc_check_for_link(hw);
 457                         link_check = (IGC_READ_REG(hw, IGC_STATUS) &
 458                                       IGC_STATUS_LU);
 459                         break;
 460
 461                 case igc_media_type_internal_serdes:
 462                         igc_check_for_link(hw);
 463                         link_check = hw->mac.serdes_has_link;
 464                         break;
 465
 466                 default:
 467                         break;
 468                 }
 469                 if (link_check || wait_to_complete == 0)
 470                         break;
 471                 rte_delay_ms(IGC_LINK_UPDATE_CHECK_INTERVAL);
 472         }
 473         memset(&link, 0, sizeof(link));
 474
 475         /* Now we check if a transition has happened */
 476         if (link_check) {
 477                 uint16_t duplex, speed;
 478                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 479                 link.link_duplex = (duplex == FULL_DUPLEX) ?
 480                                 ETH_LINK_FULL_DUPLEX :
 481                                 ETH_LINK_HALF_DUPLEX;
 482                 link.link_speed = speed;
 483                 link.link_status = ETH_LINK_UP;
 484                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
 485                                 ETH_LINK_SPEED_FIXED);
 486
 487                 if (speed == SPEED_2500) {
 488                         uint32_t tipg = IGC_READ_REG(hw, IGC_TIPG);
 489                         if ((tipg & IGC_TIPG_IPGT_MASK) != 0x0b) {
 490                                 tipg &= ~IGC_TIPG_IPGT_MASK;
 491                                 tipg |= 0x0b;
 492                                 IGC_WRITE_REG(hw, IGC_TIPG, tipg);
 493                         }
 494                 }
 495         } else {
 496                 link.link_speed = 0;
 497                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
 498                 link.link_status = ETH_LINK_DOWN;
 499                 link.link_autoneg = ETH_LINK_FIXED;
 500         }
 501
 502         return rte_eth_linkstatus_set(dev, &link);
 503 }
 504
 505 /*
 506  * It executes link_update after knowing an interrupt is present.
 507  */
 508 static void
 509 eth_igc_interrupt_action(struct rte_eth_dev *dev)
 510 {
 511         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 513         struct rte_eth_link link;
 514         int ret;
 515
 516         if (intr->flags & IGC_FLAG_NEED_LINK_UPDATE) {
 517                 intr->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
 518
 519                 /* set get_link_status to check register later */
 520                 ret = eth_igc_link_update(dev, 0);
 521
 522                 /* check if link has changed */
 523                 if (ret < 0)
 524                         return;
 525
 526                 rte_eth_linkstatus_get(dev, &link);
 527                 if (link.link_status)
 528                         PMD_DRV_LOG(INFO,
 529                                 " Port %d: Link Up - speed %u Mbps - %s",
 530                                 dev->data->port_id,
 531                                 (unsigned int)link.link_speed,
 532                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
 533                                 "full-duplex" : "half-duplex");
 534                 else
 535                         PMD_DRV_LOG(INFO, " Port %d: Link Down",
 536                                 dev->data->port_id);
 537
 538                 PMD_DRV_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
 539                                 pci_dev->addr.domain,
 540                                 pci_dev->addr.bus,
 541                                 pci_dev->addr.devid,
 542                                 pci_dev->addr.function);
 543                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 544         }
 545 }
 546
 547 /*
 548  * Interrupt handler which shall be registered at first.
 549  *
 550  * @handle
 551  *  Pointer to interrupt handle.
 552  * @param
 553  *  The address of parameter (struct rte_eth_dev *) registered before.
 554  */
 555 static void
 556 eth_igc_interrupt_handler(void *param)
 557 {
 558         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 559
 560         eth_igc_interrupt_get_status(dev);
 561         eth_igc_interrupt_action(dev);
 562 }
 563
 564 static void igc_read_queue_stats_register(struct rte_eth_dev *dev);
 565
 566 /*
 567  * Update the queue status every IGC_ALARM_INTERVAL time.
 568  * @param
 569  *  The address of parameter (struct rte_eth_dev *) registered before.
 570  */
 571 static void
 572 igc_update_queue_stats_handler(void *param)
 573 {
 574         struct rte_eth_dev *dev = param;
 575         igc_read_queue_stats_register(dev);
 576         rte_eal_alarm_set(IGC_ALARM_INTERVAL,
 577                         igc_update_queue_stats_handler, dev);
 578 }
 579
 580 /*
 581  * rx,tx enable/disable
 582  */
 583 static void
 584 eth_igc_rxtx_control(struct rte_eth_dev *dev, bool enable)
 585 {
 586         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 587         uint32_t tctl, rctl;
 588
 589         tctl = IGC_READ_REG(hw, IGC_TCTL);
 590         rctl = IGC_READ_REG(hw, IGC_RCTL);
 591
 592         if (enable) {
 593                 /* enable Tx/Rx */
 594                 tctl |= IGC_TCTL_EN;
 595                 rctl |= IGC_RCTL_EN;
 596         } else {
 597                 /* disable Tx/Rx */
 598                 tctl &= ~IGC_TCTL_EN;
 599                 rctl &= ~IGC_RCTL_EN;
 600         }
 601         IGC_WRITE_REG(hw, IGC_TCTL, tctl);
 602         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
 603         IGC_WRITE_FLUSH(hw);
 604 }
 605
 606 /*
 607  *  This routine disables all traffic on the adapter by issuing a
 608  *  global reset on the MAC.
 609  */
 610 static void
 611 eth_igc_stop(struct rte_eth_dev *dev)
 612 {
 613         struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
 614         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 615         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 616         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 617         struct rte_eth_link link;
 618
 619         adapter->stopped = 1;
 620
 621         /* disable receive and transmit */
 622         eth_igc_rxtx_control(dev, false);
 623
 624         /* disable all MSI-X interrupts */
 625         IGC_WRITE_REG(hw, IGC_EIMC, 0x1f);
 626         IGC_WRITE_FLUSH(hw);
 627
 628         /* clear all MSI-X interrupts */
 629         IGC_WRITE_REG(hw, IGC_EICR, 0x1f);
 630
 631         igc_intr_other_disable(dev);
 632
 633         rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev);
 634
 635         /* disable intr eventfd mapping */
 636         rte_intr_disable(intr_handle);
 637
 638         igc_reset_hw(hw);
 639
 640         /* disable all wake up */
 641         IGC_WRITE_REG(hw, IGC_WUC, 0);
 642
 643         /* disable checking EEE operation in MAC loopback mode */
 644         igc_read_reg_check_clear_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN);
 645
 646         /* Set bit for Go Link disconnect */
 647         igc_read_reg_check_set_bits(hw, IGC_82580_PHY_POWER_MGMT,
 648                         IGC_82580_PM_GO_LINKD);
 649
 650         /* Power down the phy. Needed to make the link go Down */
 651         eth_igc_set_link_down(dev);
 652
 653         igc_dev_clear_queues(dev);
 654
 655         /* clear the recorded link status */
 656         memset(&link, 0, sizeof(link));
 657         rte_eth_linkstatus_set(dev, &link);
 658
 659         if (!rte_intr_allow_others(intr_handle))
 660                 /* resume to the default handler */
 661                 rte_intr_callback_register(intr_handle,
 662                                            eth_igc_interrupt_handler,
 663                                            (void *)dev);
 664
 665         /* Clean datapath event and queue/vec mapping */
 666         rte_intr_efd_disable(intr_handle);
 667         if (intr_handle->intr_vec != NULL) {
 668                 rte_free(intr_handle->intr_vec);
 669                 intr_handle->intr_vec = NULL;
 670         }
 671 }
 672
 673 /*
 674  * write interrupt vector allocation register
 675  * @hw
 676  *  board private structure
 677  * @queue_index
 678  *  queue index, valid 0,1,2,3
 679  * @tx
 680  *  tx:1, rx:0
 681  * @msix_vector
 682  *  msix-vector, valid 0,1,2,3,4
 683  */
 684 static void
 685 igc_write_ivar(struct igc_hw *hw, uint8_t queue_index,
 686                 bool tx, uint8_t msix_vector)
 687 {
 688         uint8_t offset = 0;
 689         uint8_t reg_index = queue_index >> 1;
 690         uint32_t val;
 691
 692         /*
 693          * IVAR(0)
 694          * bit31...24   bit23...16      bit15...8       bit7...0
 695          * TX1          RX1             TX0             RX0
 696          *
 697          * IVAR(1)
 698          * bit31...24   bit23...16      bit15...8       bit7...0
 699          * TX3          RX3             TX2             RX2
 700          */
 701
 702         if (tx)
 703                 offset = 8;
 704
 705         if (queue_index & 1)
 706                 offset += 16;
 707
 708         val = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, reg_index);
 709
 710         /* clear bits */
 711         val &= ~((uint32_t)0xFF << offset);
 712
 713         /* write vector and valid bit */
 714         val |= (uint32_t)(msix_vector | IGC_IVAR_VALID) << offset;
 715
 716         IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, reg_index, val);
 717 }
 718
 719 /* Sets up the hardware to generate MSI-X interrupts properly
 720  * @hw
 721  *  board private structure
 722  */
 723 static void
 724 igc_configure_msix_intr(struct rte_eth_dev *dev)
 725 {
 726         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 727         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 728         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 729
 730         uint32_t intr_mask;
 731         uint32_t vec = IGC_MISC_VEC_ID;
 732         uint32_t base = IGC_MISC_VEC_ID;
 733         uint32_t misc_shift = 0;
 734         int i;
 735
 736         /* won't configure msix register if no mapping is done
 737          * between intr vector and event fd
 738          */
 739         if (!rte_intr_dp_is_en(intr_handle))
 740                 return;
 741
 742         if (rte_intr_allow_others(intr_handle)) {
 743                 base = IGC_RX_VEC_START;
 744                 vec = base;
 745                 misc_shift = 1;
 746         }
 747
 748         /* turn on MSI-X capability first */
 749         IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE |
 750                                 IGC_GPIE_PBA | IGC_GPIE_EIAME |
 751                                 IGC_GPIE_NSICR);
 752         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
 753                 misc_shift;
 754
 755         if (dev->data->dev_conf.intr_conf.lsc)
 756                 intr_mask |= (1u << IGC_MSIX_OTHER_INTR_VEC);
 757
 758         /* enable msix auto-clear */
 759         igc_read_reg_check_set_bits(hw, IGC_EIAC, intr_mask);
 760
 761         /* set other cause interrupt vector */
 762         igc_read_reg_check_set_bits(hw, IGC_IVAR_MISC,
 763                 (uint32_t)(IGC_MSIX_OTHER_INTR_VEC | IGC_IVAR_VALID) << 8);
 764
 765         /* enable auto-mask */
 766         igc_read_reg_check_set_bits(hw, IGC_EIAM, intr_mask);
 767
 768         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 769                 igc_write_ivar(hw, i, 0, vec);
 770                 intr_handle->intr_vec[i] = vec;
 771                 if (vec < base + intr_handle->nb_efd - 1)
 772                         vec++;
 773         }
 774
 775         IGC_WRITE_FLUSH(hw);
 776 }
 777
 778 /**
 779  * It enables the interrupt mask and then enable the interrupt.
 780  *
 781  * @dev
 782  *  Pointer to struct rte_eth_dev.
 783  * @on
 784  *  Enable or Disable
 785  */
 786 static void
 787 igc_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
 788 {
 789         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 790
 791         if (on)
 792                 intr->mask |= IGC_ICR_LSC;
 793         else
 794                 intr->mask &= ~IGC_ICR_LSC;
 795 }
 796
 797 /*
 798  * It enables the interrupt.
 799  * It will be called once only during nic initialized.
 800  */
 801 static void
 802 igc_rxq_interrupt_setup(struct rte_eth_dev *dev)
 803 {
 804         uint32_t mask;
 805         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 806         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 807         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 808         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
 809
 810         /* won't configure msix register if no mapping is done
 811          * between intr vector and event fd
 812          */
 813         if (!rte_intr_dp_is_en(intr_handle))
 814                 return;
 815
 816         mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift;
 817         IGC_WRITE_REG(hw, IGC_EIMS, mask);
 818 }
 819
 820 /*
 821  *  Get hardware rx-buffer size.
 822  */
 823 static inline int
 824 igc_get_rx_buffer_size(struct igc_hw *hw)
 825 {
 826         return (IGC_READ_REG(hw, IGC_RXPBS) & 0x3f) << 10;
 827 }
 828
 829 /*
 830  * igc_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
 831  * For ASF and Pass Through versions of f/w this means
 832  * that the driver is loaded.
 833  */
 834 static void
 835 igc_hw_control_acquire(struct igc_hw *hw)
 836 {
 837         uint32_t ctrl_ext;
 838
 839         /* Let firmware know the driver has taken over */
 840         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
 841         IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
 842 }
 843
 844 /*
 845  * igc_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
 846  * For ASF and Pass Through versions of f/w this means that the
 847  * driver is no longer loaded.
 848  */
 849 static void
 850 igc_hw_control_release(struct igc_hw *hw)
 851 {
 852         uint32_t ctrl_ext;
 853
 854         /* Let firmware taken over control of h/w */
 855         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
 856         IGC_WRITE_REG(hw, IGC_CTRL_EXT,
 857                         ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
 858 }
 859
 860 static int
 861 igc_hardware_init(struct igc_hw *hw)
 862 {
 863         uint32_t rx_buf_size;
 864         int diag;
 865
 866         /* Let the firmware know the OS is in control */
 867         igc_hw_control_acquire(hw);
 868
 869         /* Issue a global reset */
 870         igc_reset_hw(hw);
 871
 872         /* disable all wake up */
 873         IGC_WRITE_REG(hw, IGC_WUC, 0);
 874
 875         /*
 876          * Hardware flow control
 877          * - High water mark should allow for at least two standard size (1518)
 878          *   frames to be received after sending an XOFF.
 879          * - Low water mark works best when it is very near the high water mark.
 880          *   This allows the receiver to restart by sending XON when it has
 881          *   drained a bit. Here we use an arbitrary value of 1500 which will
 882          *   restart after one full frame is pulled from the buffer. There
 883          *   could be several smaller frames in the buffer and if so they will
 884          *   not trigger the XON until their total number reduces the buffer
 885          *   by 1500.
 886          */
 887         rx_buf_size = igc_get_rx_buffer_size(hw);
 888         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
 889         hw->fc.low_water = hw->fc.high_water - 1500;
 890         hw->fc.pause_time = IGC_FC_PAUSE_TIME;
 891         hw->fc.send_xon = 1;
 892         hw->fc.requested_mode = igc_fc_full;
 893
 894         diag = igc_init_hw(hw);
 895         if (diag < 0)
 896                 return diag;
 897
 898         igc_get_phy_info(hw);
 899         igc_check_for_link(hw);
 900
 901         return 0;
 902 }
 903
 904 static int
 905 eth_igc_start(struct rte_eth_dev *dev)
 906 {
 907         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 908         struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
 909         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 910         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 911         uint32_t *speeds;
 912         int ret;
 913
 914         PMD_INIT_FUNC_TRACE();
 915
 916         /* disable all MSI-X interrupts */
 917         IGC_WRITE_REG(hw, IGC_EIMC, 0x1f);
 918         IGC_WRITE_FLUSH(hw);
 919
 920         /* clear all MSI-X interrupts */
 921         IGC_WRITE_REG(hw, IGC_EICR, 0x1f);
 922
 923         /* disable uio/vfio intr/eventfd mapping */
 924         if (!adapter->stopped)
 925                 rte_intr_disable(intr_handle);
 926
 927         /* Power up the phy. Needed to make the link go Up */
 928         eth_igc_set_link_up(dev);
 929
 930         /* Put the address into the Receive Address Array */
 931         igc_rar_set(hw, hw->mac.addr, 0);
 932
 933         /* Initialize the hardware */
 934         if (igc_hardware_init(hw)) {
 935                 PMD_DRV_LOG(ERR, "Unable to initialize the hardware");
 936                 return -EIO;
 937         }
 938         adapter->stopped = 0;
 939
 940         /* check and configure queue intr-vector mapping */
 941         if (rte_intr_cap_multiple(intr_handle) &&
 942                 dev->data->dev_conf.intr_conf.rxq) {
 943                 uint32_t intr_vector = dev->data->nb_rx_queues;
 944                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 945                         return -1;
 946         }
 947
 948         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 949                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
 950                         dev->data->nb_rx_queues * sizeof(int), 0);
 951                 if (intr_handle->intr_vec == NULL) {
 952                         PMD_DRV_LOG(ERR,
 953                                 "Failed to allocate %d rx_queues intr_vec",
 954                                 dev->data->nb_rx_queues);
 955                         return -ENOMEM;
 956                 }
 957         }
 958
 959         /* configure msix for rx interrupt */
 960         igc_configure_msix_intr(dev);
 961
 962         igc_tx_init(dev);
 963
 964         /* This can fail when allocating mbufs for descriptor rings */
 965         ret = igc_rx_init(dev);
 966         if (ret) {
 967                 PMD_DRV_LOG(ERR, "Unable to initialize RX hardware");
 968                 igc_dev_clear_queues(dev);
 969                 return ret;
 970         }
 971
 972         igc_clear_hw_cntrs_base_generic(hw);
 973
 974         /* VLAN Offload Settings */
 975         eth_igc_vlan_offload_set(dev,
 976                 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
 977                 ETH_VLAN_EXTEND_MASK);
 978
 979         /* Setup link speed and duplex */
 980         speeds = &dev->data->dev_conf.link_speeds;
 981         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 982                 hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;
 983                 hw->mac.autoneg = 1;
 984         } else {
 985                 int num_speeds = 0;
 986                 bool autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 987
 988                 /* Reset */
 989                 hw->phy.autoneg_advertised = 0;
 990
 991                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 992                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 993                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
 994                                 ETH_LINK_SPEED_FIXED)) {
 995                         num_speeds = -1;
 996                         goto error_invalid_config;
 997                 }
 998                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 999                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1000                         num_speeds++;
1001                 }
1002                 if (*speeds & ETH_LINK_SPEED_10M) {
1003                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1004                         num_speeds++;
1005                 }
1006                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1007                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1008                         num_speeds++;
1009                 }
1010                 if (*speeds & ETH_LINK_SPEED_100M) {
1011                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1012                         num_speeds++;
1013                 }
1014                 if (*speeds & ETH_LINK_SPEED_1G) {
1015                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1016                         num_speeds++;
1017                 }
1018                 if (*speeds & ETH_LINK_SPEED_2_5G) {
1019                         hw->phy.autoneg_advertised |= ADVERTISE_2500_FULL;
1020                         num_speeds++;
1021                 }
1022                 if (num_speeds == 0 || (!autoneg && num_speeds > 1))
1023                         goto error_invalid_config;
1024
1025                 /* Set/reset the mac.autoneg based on the link speed,
1026                  * fixed or not
1027                  */
1028                 if (!autoneg) {
1029                         hw->mac.autoneg = 0;
1030                         hw->mac.forced_speed_duplex =
1031                                         hw->phy.autoneg_advertised;
1032                 } else {
1033                         hw->mac.autoneg = 1;
1034                 }
1035         }
1036
1037         igc_setup_link(hw);
1038
1039         if (rte_intr_allow_others(intr_handle)) {
1040                 /* check if lsc interrupt is enabled */
1041                 if (dev->data->dev_conf.intr_conf.lsc)
1042                         igc_lsc_interrupt_setup(dev, 1);
1043                 else
1044                         igc_lsc_interrupt_setup(dev, 0);
1045         } else {
1046                 rte_intr_callback_unregister(intr_handle,
1047                                              eth_igc_interrupt_handler,
1048                                              (void *)dev);
1049                 if (dev->data->dev_conf.intr_conf.lsc)
1050                         PMD_DRV_LOG(INFO,
1051                                 "LSC won't enable because of no intr multiplex");
1052         }
1053
1054         /* enable uio/vfio intr/eventfd mapping */
1055         rte_intr_enable(intr_handle);
1056
1057         rte_eal_alarm_set(IGC_ALARM_INTERVAL,
1058                         igc_update_queue_stats_handler, dev);
1059
1060         /* check if rxq interrupt is enabled */
1061         if (dev->data->dev_conf.intr_conf.rxq &&
1062                         rte_intr_dp_is_en(intr_handle))
1063                 igc_rxq_interrupt_setup(dev);
1064
1065         /* resume enabled intr since hw reset */
1066         igc_intr_other_enable(dev);
1067
1068         eth_igc_rxtx_control(dev, true);
1069         eth_igc_link_update(dev, 0);
1070
1071         /* configure MAC-loopback mode */
1072         if (dev->data->dev_conf.lpbk_mode == 1) {
1073                 uint32_t reg_val;
1074
1075                 reg_val = IGC_READ_REG(hw, IGC_CTRL);
1076                 reg_val &= ~IGC_CTRL_SPEED_MASK;
1077                 reg_val |= IGC_CTRL_SLU | IGC_CTRL_FRCSPD |
1078                         IGC_CTRL_FRCDPX | IGC_CTRL_FD | IGC_CTRL_SPEED_2500;
1079                 IGC_WRITE_REG(hw, IGC_CTRL, reg_val);
1080
1081                 igc_read_reg_check_set_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN);
1082         }
1083
1084         return 0;
1085
1086 error_invalid_config:
1087         PMD_DRV_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1088                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1089         igc_dev_clear_queues(dev);
1090         return -EINVAL;
1091 }
1092
1093 static int
1094 igc_reset_swfw_lock(struct igc_hw *hw)
1095 {
1096         int ret_val;
1097
1098         /*
1099          * Do mac ops initialization manually here, since we will need
1100          * some function pointers set by this call.
1101          */
1102         ret_val = igc_init_mac_params(hw);
1103         if (ret_val)
1104                 return ret_val;
1105
1106         /*
1107          * SMBI lock should not fail in this early stage. If this is the case,
1108          * it is due to an improper exit of the application.
1109          * So force the release of the faulty lock.
1110          */
1111         if (igc_get_hw_semaphore_generic(hw) < 0)
1112                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
1113
1114         igc_put_hw_semaphore_generic(hw);
1115
1116         if (hw->mac.ops.acquire_swfw_sync != NULL) {
1117                 uint16_t mask;
1118
1119                 /*
1120                  * Phy lock should not fail in this early stage.
1121                  * If this is the case, it is due to an improper exit of the
1122                  * application. So force the release of the faulty lock.
1123                  */
1124                 mask = IGC_SWFW_PHY0_SM;
1125                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
1126                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
1127                                     hw->bus.func);
1128                 }
1129                 hw->mac.ops.release_swfw_sync(hw, mask);
1130
1131                 /*
1132                  * This one is more tricky since it is common to all ports; but
1133                  * swfw_sync retries last long enough (1s) to be almost sure
1134                  * that if lock can not be taken it is due to an improper lock
1135                  * of the semaphore.
1136                  */
1137                 mask = IGC_SWFW_EEP_SM;
1138                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0)
1139                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1140
1141                 hw->mac.ops.release_swfw_sync(hw, mask);
1142         }
1143
1144         return IGC_SUCCESS;
1145 }
1146
1147 /*
1148  * free all rx/tx queues.
1149  */
1150 static void
1151 igc_dev_free_queues(struct rte_eth_dev *dev)
1152 {
1153         uint16_t i;
1154
1155         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1156                 eth_igc_rx_queue_release(dev->data->rx_queues[i]);
1157                 dev->data->rx_queues[i] = NULL;
1158         }
1159         dev->data->nb_rx_queues = 0;
1160
1161         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1162                 eth_igc_tx_queue_release(dev->data->tx_queues[i]);
1163                 dev->data->tx_queues[i] = NULL;
1164         }
1165         dev->data->nb_tx_queues = 0;
1166 }
1167
1168 static int
1169 eth_igc_close(struct rte_eth_dev *dev)
1170 {
1171         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1172         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1173         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1174         struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
1175         int retry = 0;
1176
1177         PMD_INIT_FUNC_TRACE();
1178
1179         if (!adapter->stopped)
1180                 eth_igc_stop(dev);
1181
1182         igc_flow_flush(dev, NULL);
1183         igc_clear_all_filter(dev);
1184
1185         igc_intr_other_disable(dev);
1186         do {
1187                 int ret = rte_intr_callback_unregister(intr_handle,
1188                                 eth_igc_interrupt_handler, dev);
1189                 if (ret >= 0 || ret == -ENOENT || ret == -EINVAL)
1190                         break;
1191
1192                 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", ret);
1193                 DELAY(200 * 1000); /* delay 200ms */
1194         } while (retry++ < 5);
1195
1196         igc_phy_hw_reset(hw);
1197         igc_hw_control_release(hw);
1198         igc_dev_free_queues(dev);
1199
1200         /* Reset any pending lock */
1201         igc_reset_swfw_lock(hw);
1202
1203         return 0;
1204 }
1205
1206 static void
1207 igc_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
1208 {
1209         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1210
1211         hw->vendor_id = pci_dev->id.vendor_id;
1212         hw->device_id = pci_dev->id.device_id;
1213         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1214         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1215 }
1216
1217 static int
1218 eth_igc_dev_init(struct rte_eth_dev *dev)
1219 {
1220         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1221         struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
1222         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1223         int i, error = 0;
1224
1225         PMD_INIT_FUNC_TRACE();
1226         dev->dev_ops = &eth_igc_ops;
1227         dev->rx_descriptor_done = eth_igc_rx_descriptor_done;
1228         dev->rx_queue_count = eth_igc_rx_queue_count;
1229         dev->rx_descriptor_status = eth_igc_rx_descriptor_status;
1230         dev->tx_descriptor_status = eth_igc_tx_descriptor_status;
1231
1232         /*
1233          * for secondary processes, we don't initialize any further as primary
1234          * has already done this work. Only check we don't need a different
1235          * RX function.
1236          */
1237         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1238                 return 0;
1239
1240         rte_eth_copy_pci_info(dev, pci_dev);
1241
1242         hw->back = pci_dev;
1243         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1244
1245         igc_identify_hardware(dev, pci_dev);
1246         if (igc_setup_init_funcs(hw, false) != IGC_SUCCESS) {
1247                 error = -EIO;
1248                 goto err_late;
1249         }
1250
1251         igc_get_bus_info(hw);
1252
1253         /* Reset any pending lock */
1254         if (igc_reset_swfw_lock(hw) != IGC_SUCCESS) {
1255                 error = -EIO;
1256                 goto err_late;
1257         }
1258
1259         /* Finish initialization */
1260         if (igc_setup_init_funcs(hw, true) != IGC_SUCCESS) {
1261                 error = -EIO;
1262                 goto err_late;
1263         }
1264
1265         hw->mac.autoneg = 1;
1266         hw->phy.autoneg_wait_to_complete = 0;
1267         hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;
1268
1269         /* Copper options */
1270         if (hw->phy.media_type == igc_media_type_copper) {
1271                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
1272                 hw->phy.disable_polarity_correction = 0;
1273                 hw->phy.ms_type = igc_ms_hw_default;
1274         }
1275
1276         /*
1277          * Start from a known state, this is important in reading the nvm
1278          * and mac from that.
1279          */
1280         igc_reset_hw(hw);
1281
1282         /* Make sure we have a good EEPROM before we read from it */
1283         if (igc_validate_nvm_checksum(hw) < 0) {
1284                 /*
1285                  * Some PCI-E parts fail the first check due to
1286                  * the link being in sleep state, call it again,
1287                  * if it fails a second time its a real issue.
1288                  */
1289                 if (igc_validate_nvm_checksum(hw) < 0) {
1290                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
1291                         error = -EIO;
1292                         goto err_late;
1293                 }
1294         }
1295
1296         /* Read the permanent MAC address out of the EEPROM */
1297         if (igc_read_mac_addr(hw) != 0) {
1298                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
1299                 error = -EIO;
1300                 goto err_late;
1301         }
1302
1303         /* Allocate memory for storing MAC addresses */
1304         dev->data->mac_addrs = rte_zmalloc("igc",
1305                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
1306         if (dev->data->mac_addrs == NULL) {
1307                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes for storing MAC",
1308                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1309                 error = -ENOMEM;
1310                 goto err_late;
1311         }
1312
1313         /* Copy the permanent MAC address */
1314         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1315                         &dev->data->mac_addrs[0]);
1316
1317         /* Now initialize the hardware */
1318         if (igc_hardware_init(hw) != 0) {
1319                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
1320                 rte_free(dev->data->mac_addrs);
1321                 dev->data->mac_addrs = NULL;
1322                 error = -ENODEV;
1323                 goto err_late;
1324         }
1325
1326         hw->mac.get_link_status = 1;
1327         igc->stopped = 0;
1328
1329         /* Indicate SOL/IDER usage */
1330         if (igc_check_reset_block(hw) < 0)
1331                 PMD_INIT_LOG(ERR,
1332                         "PHY reset is blocked due to SOL/IDER session.");
1333
1334         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
1335                         dev->data->port_id, pci_dev->id.vendor_id,
1336                         pci_dev->id.device_id);
1337
1338         rte_intr_callback_register(&pci_dev->intr_handle,
1339                         eth_igc_interrupt_handler, (void *)dev);
1340
1341         /* enable uio/vfio intr/eventfd mapping */
1342         rte_intr_enable(&pci_dev->intr_handle);
1343
1344         /* enable support intr */
1345         igc_intr_other_enable(dev);
1346
1347         /* initiate queue status */
1348         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1349                 igc->txq_stats_map[i] = -1;
1350                 igc->rxq_stats_map[i] = -1;
1351         }
1352
1353         igc_flow_init(dev);
1354         igc_clear_all_filter(dev);
1355         return 0;
1356
1357 err_late:
1358         igc_hw_control_release(hw);
1359         return error;
1360 }
1361
1362 static int
1363 eth_igc_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev)
1364 {
1365         PMD_INIT_FUNC_TRACE();
1366
1367         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368                 return 0;
1369
1370         eth_igc_close(eth_dev);
1371         return 0;
1372 }
1373
1374 static int
1375 eth_igc_reset(struct rte_eth_dev *dev)
1376 {
1377         int ret;
1378
1379         PMD_INIT_FUNC_TRACE();
1380
1381         ret = eth_igc_dev_uninit(dev);
1382         if (ret)
1383                 return ret;
1384
1385         return eth_igc_dev_init(dev);
1386 }
1387
1388 static int
1389 eth_igc_promiscuous_enable(struct rte_eth_dev *dev)
1390 {
1391         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1392         uint32_t rctl;
1393
1394         rctl = IGC_READ_REG(hw, IGC_RCTL);
1395         rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE);
1396         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1397         return 0;
1398 }
1399
1400 static int
1401 eth_igc_promiscuous_disable(struct rte_eth_dev *dev)
1402 {
1403         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1404         uint32_t rctl;
1405
1406         rctl = IGC_READ_REG(hw, IGC_RCTL);
1407         rctl &= (~IGC_RCTL_UPE);
1408         if (dev->data->all_multicast == 1)
1409                 rctl |= IGC_RCTL_MPE;
1410         else
1411                 rctl &= (~IGC_RCTL_MPE);
1412         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1413         return 0;
1414 }
1415
1416 static int
1417 eth_igc_allmulticast_enable(struct rte_eth_dev *dev)
1418 {
1419         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1420         uint32_t rctl;
1421
1422         rctl = IGC_READ_REG(hw, IGC_RCTL);
1423         rctl |= IGC_RCTL_MPE;
1424         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1425         return 0;
1426 }
1427
1428 static int
1429 eth_igc_allmulticast_disable(struct rte_eth_dev *dev)
1430 {
1431         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1432         uint32_t rctl;
1433
1434         if (dev->data->promiscuous == 1)
1435                 return 0;       /* must remain in all_multicast mode */
1436
1437         rctl = IGC_READ_REG(hw, IGC_RCTL);
1438         rctl &= (~IGC_RCTL_MPE);
1439         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1440         return 0;
1441 }
1442
1443 static int
1444 eth_igc_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1445                        size_t fw_size)
1446 {
1447         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1448         struct igc_fw_version fw;
1449         int ret;
1450
1451         igc_get_fw_version(hw, &fw);
1452
1453         /* if option rom is valid, display its version too */
1454         if (fw.or_valid) {
1455                 ret = snprintf(fw_version, fw_size,
1456                          "%d.%d, 0x%08x, %d.%d.%d",
1457                          fw.eep_major, fw.eep_minor, fw.etrack_id,
1458                          fw.or_major, fw.or_build, fw.or_patch);
1459         /* no option rom */
1460         } else {
1461                 if (fw.etrack_id != 0X0000) {
1462                         ret = snprintf(fw_version, fw_size,
1463                                  "%d.%d, 0x%08x",
1464                                  fw.eep_major, fw.eep_minor,
1465                                  fw.etrack_id);
1466                 } else {
1467                         ret = snprintf(fw_version, fw_size,
1468                                  "%d.%d.%d",
1469                                  fw.eep_major, fw.eep_minor,
1470                                  fw.eep_build);
1471                 }
1472         }
1473
1474         ret += 1; /* add the size of '\0' */
1475         if (fw_size < (u32)ret)
1476                 return ret;
1477         else
1478                 return 0;
1479 }
1480
1481 static int
1482 eth_igc_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1483 {
1484         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1485
1486         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1487         dev_info->max_rx_pktlen = MAX_RX_JUMBO_FRAME_SIZE;
1488         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1489         dev_info->rx_offload_capa = IGC_RX_OFFLOAD_ALL;
1490         dev_info->tx_offload_capa = IGC_TX_OFFLOAD_ALL;
1491         dev_info->rx_queue_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1492
1493         dev_info->max_rx_queues = IGC_QUEUE_PAIRS_NUM;
1494         dev_info->max_tx_queues = IGC_QUEUE_PAIRS_NUM;
1495         dev_info->max_vmdq_pools = 0;
1496
1497         dev_info->hash_key_size = IGC_HKEY_MAX_INDEX * sizeof(uint32_t);
1498         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1499         dev_info->flow_type_rss_offloads = IGC_RSS_OFFLOAD_ALL;
1500
1501         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1502                 .rx_thresh = {
1503                         .pthresh = IGC_DEFAULT_RX_PTHRESH,
1504                         .hthresh = IGC_DEFAULT_RX_HTHRESH,
1505                         .wthresh = IGC_DEFAULT_RX_WTHRESH,
1506                 },
1507                 .rx_free_thresh = IGC_DEFAULT_RX_FREE_THRESH,
1508                 .rx_drop_en = 0,
1509                 .offloads = 0,
1510         };
1511
1512         dev_info->default_txconf = (struct rte_eth_txconf) {
1513                 .tx_thresh = {
1514                         .pthresh = IGC_DEFAULT_TX_PTHRESH,
1515                         .hthresh = IGC_DEFAULT_TX_HTHRESH,
1516                         .wthresh = IGC_DEFAULT_TX_WTHRESH,
1517                 },
1518                 .offloads = 0,
1519         };
1520
1521         dev_info->rx_desc_lim = rx_desc_lim;
1522         dev_info->tx_desc_lim = tx_desc_lim;
1523
1524         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1525                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1526                         ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G;
1527
1528         dev_info->max_mtu = dev_info->max_rx_pktlen - IGC_ETH_OVERHEAD;
1529         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
1530         return 0;
1531 }
1532
1533 static int
1534 eth_igc_led_on(struct rte_eth_dev *dev)
1535 {
1536         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1537
1538         return igc_led_on(hw) == IGC_SUCCESS ? 0 : -ENOTSUP;
1539 }
1540
1541 static int
1542 eth_igc_led_off(struct rte_eth_dev *dev)
1543 {
1544         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1545
1546         return igc_led_off(hw) == IGC_SUCCESS ? 0 : -ENOTSUP;
1547 }
1548
1549 static const uint32_t *
1550 eth_igc_supported_ptypes_get(__rte_unused struct rte_eth_dev *dev)
1551 {
1552         static const uint32_t ptypes[] = {
1553                 /* refers to rx_desc_pkt_info_to_pkt_type() */
1554                 RTE_PTYPE_L2_ETHER,
1555                 RTE_PTYPE_L3_IPV4,
1556                 RTE_PTYPE_L3_IPV4_EXT,
1557                 RTE_PTYPE_L3_IPV6,
1558                 RTE_PTYPE_L3_IPV6_EXT,
1559                 RTE_PTYPE_L4_TCP,
1560                 RTE_PTYPE_L4_UDP,
1561                 RTE_PTYPE_L4_SCTP,
1562                 RTE_PTYPE_TUNNEL_IP,
1563                 RTE_PTYPE_INNER_L3_IPV6,
1564                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1565                 RTE_PTYPE_INNER_L4_TCP,
1566                 RTE_PTYPE_INNER_L4_UDP,
1567                 RTE_PTYPE_UNKNOWN
1568         };
1569
1570         return ptypes;
1571 }
1572
1573 static int
1574 eth_igc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1575 {
1576         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1577         uint32_t frame_size = mtu + IGC_ETH_OVERHEAD;
1578         uint32_t rctl;
1579
1580         /* if extend vlan has been enabled */
1581         if (IGC_READ_REG(hw, IGC_CTRL_EXT) & IGC_CTRL_EXT_EXT_VLAN)
1582                 frame_size += VLAN_TAG_SIZE;
1583
1584         /* check that mtu is within the allowed range */
1585         if (mtu < RTE_ETHER_MIN_MTU ||
1586                 frame_size > MAX_RX_JUMBO_FRAME_SIZE)
1587                 return -EINVAL;
1588
1589         /*
1590          * refuse mtu that requires the support of scattered packets when
1591          * this feature has not been enabled before.
1592          */
1593         if (!dev->data->scattered_rx &&
1594             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1595                 return -EINVAL;
1596
1597         rctl = IGC_READ_REG(hw, IGC_RCTL);
1598
1599         /* switch to jumbo mode if needed */
1600         if (mtu > RTE_ETHER_MTU) {
1601                 dev->data->dev_conf.rxmode.offloads |=
1602                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1603                 rctl |= IGC_RCTL_LPE;
1604         } else {
1605                 dev->data->dev_conf.rxmode.offloads &=
1606                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1607                 rctl &= ~IGC_RCTL_LPE;
1608         }
1609         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1610
1611         /* update max frame size */
1612         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1613
1614         IGC_WRITE_REG(hw, IGC_RLPML,
1615                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
1616
1617         return 0;
1618 }
1619
1620 static int
1621 eth_igc_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1622                 uint32_t index, uint32_t pool)
1623 {
1624         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1625
1626         igc_rar_set(hw, mac_addr->addr_bytes, index);
1627         RTE_SET_USED(pool);
1628         return 0;
1629 }
1630
1631 static void
1632 eth_igc_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1633 {
1634         uint8_t addr[RTE_ETHER_ADDR_LEN];
1635         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1636
1637         memset(addr, 0, sizeof(addr));
1638         igc_rar_set(hw, addr, index);
1639 }
1640
1641 static int
1642 eth_igc_default_mac_addr_set(struct rte_eth_dev *dev,
1643                         struct rte_ether_addr *addr)
1644 {
1645         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1646         igc_rar_set(hw, addr->addr_bytes, 0);
1647         return 0;
1648 }
1649
1650 static int
1651 eth_igc_set_mc_addr_list(struct rte_eth_dev *dev,
1652                          struct rte_ether_addr *mc_addr_set,
1653                          uint32_t nb_mc_addr)
1654 {
1655         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1656         igc_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1657         return 0;
1658 }
1659
1660 /*
1661  * Read hardware registers
1662  */
1663 static void
1664 igc_read_stats_registers(struct igc_hw *hw, struct igc_hw_stats *stats)
1665 {
1666         int pause_frames;
1667
1668         uint64_t old_gprc  = stats->gprc;
1669         uint64_t old_gptc  = stats->gptc;
1670         uint64_t old_tpr   = stats->tpr;
1671         uint64_t old_tpt   = stats->tpt;
1672         uint64_t old_rpthc = stats->rpthc;
1673         uint64_t old_hgptc = stats->hgptc;
1674
1675         stats->crcerrs += IGC_READ_REG(hw, IGC_CRCERRS);
1676         stats->algnerrc += IGC_READ_REG(hw, IGC_ALGNERRC);
1677         stats->rxerrc += IGC_READ_REG(hw, IGC_RXERRC);
1678         stats->mpc += IGC_READ_REG(hw, IGC_MPC);
1679         stats->scc += IGC_READ_REG(hw, IGC_SCC);
1680         stats->ecol += IGC_READ_REG(hw, IGC_ECOL);
1681
1682         stats->mcc += IGC_READ_REG(hw, IGC_MCC);
1683         stats->latecol += IGC_READ_REG(hw, IGC_LATECOL);
1684         stats->colc += IGC_READ_REG(hw, IGC_COLC);
1685
1686         stats->dc += IGC_READ_REG(hw, IGC_DC);
1687         stats->tncrs += IGC_READ_REG(hw, IGC_TNCRS);
1688         stats->htdpmc += IGC_READ_REG(hw, IGC_HTDPMC);
1689         stats->rlec += IGC_READ_REG(hw, IGC_RLEC);
1690         stats->xonrxc += IGC_READ_REG(hw, IGC_XONRXC);
1691         stats->xontxc += IGC_READ_REG(hw, IGC_XONTXC);
1692
1693         /*
1694          * For watchdog management we need to know if we have been
1695          * paused during the last interval, so capture that here.
1696          */
1697         pause_frames = IGC_READ_REG(hw, IGC_XOFFRXC);
1698         stats->xoffrxc += pause_frames;
1699         stats->xofftxc += IGC_READ_REG(hw, IGC_XOFFTXC);
1700         stats->fcruc += IGC_READ_REG(hw, IGC_FCRUC);
1701         stats->prc64 += IGC_READ_REG(hw, IGC_PRC64);
1702         stats->prc127 += IGC_READ_REG(hw, IGC_PRC127);
1703         stats->prc255 += IGC_READ_REG(hw, IGC_PRC255);
1704         stats->prc511 += IGC_READ_REG(hw, IGC_PRC511);
1705         stats->prc1023 += IGC_READ_REG(hw, IGC_PRC1023);
1706         stats->prc1522 += IGC_READ_REG(hw, IGC_PRC1522);
1707         stats->gprc += IGC_READ_REG(hw, IGC_GPRC);
1708         stats->bprc += IGC_READ_REG(hw, IGC_BPRC);
1709         stats->mprc += IGC_READ_REG(hw, IGC_MPRC);
1710         stats->gptc += IGC_READ_REG(hw, IGC_GPTC);
1711
1712         /* For the 64-bit byte counters the low dword must be read first. */
1713         /* Both registers clear on the read of the high dword */
1714
1715         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1716         stats->gorc += IGC_READ_REG(hw, IGC_GORCL);
1717         stats->gorc += ((uint64_t)IGC_READ_REG(hw, IGC_GORCH) << 32);
1718         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1719         stats->gotc += IGC_READ_REG(hw, IGC_GOTCL);
1720         stats->gotc += ((uint64_t)IGC_READ_REG(hw, IGC_GOTCH) << 32);
1721         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1722
1723         stats->rnbc += IGC_READ_REG(hw, IGC_RNBC);
1724         stats->ruc += IGC_READ_REG(hw, IGC_RUC);
1725         stats->rfc += IGC_READ_REG(hw, IGC_RFC);
1726         stats->roc += IGC_READ_REG(hw, IGC_ROC);
1727         stats->rjc += IGC_READ_REG(hw, IGC_RJC);
1728
1729         stats->mgprc += IGC_READ_REG(hw, IGC_MGTPRC);
1730         stats->mgpdc += IGC_READ_REG(hw, IGC_MGTPDC);
1731         stats->mgptc += IGC_READ_REG(hw, IGC_MGTPTC);
1732         stats->b2ospc += IGC_READ_REG(hw, IGC_B2OSPC);
1733         stats->b2ogprc += IGC_READ_REG(hw, IGC_B2OGPRC);
1734         stats->o2bgptc += IGC_READ_REG(hw, IGC_O2BGPTC);
1735         stats->o2bspc += IGC_READ_REG(hw, IGC_O2BSPC);
1736
1737         stats->tpr += IGC_READ_REG(hw, IGC_TPR);
1738         stats->tpt += IGC_READ_REG(hw, IGC_TPT);
1739
1740         stats->tor += IGC_READ_REG(hw, IGC_TORL);
1741         stats->tor += ((uint64_t)IGC_READ_REG(hw, IGC_TORH) << 32);
1742         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1743         stats->tot += IGC_READ_REG(hw, IGC_TOTL);
1744         stats->tot += ((uint64_t)IGC_READ_REG(hw, IGC_TOTH) << 32);
1745         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1746
1747         stats->ptc64 += IGC_READ_REG(hw, IGC_PTC64);
1748         stats->ptc127 += IGC_READ_REG(hw, IGC_PTC127);
1749         stats->ptc255 += IGC_READ_REG(hw, IGC_PTC255);
1750         stats->ptc511 += IGC_READ_REG(hw, IGC_PTC511);
1751         stats->ptc1023 += IGC_READ_REG(hw, IGC_PTC1023);
1752         stats->ptc1522 += IGC_READ_REG(hw, IGC_PTC1522);
1753         stats->mptc += IGC_READ_REG(hw, IGC_MPTC);
1754         stats->bptc += IGC_READ_REG(hw, IGC_BPTC);
1755         stats->tsctc += IGC_READ_REG(hw, IGC_TSCTC);
1756
1757         stats->iac += IGC_READ_REG(hw, IGC_IAC);
1758         stats->rpthc += IGC_READ_REG(hw, IGC_RPTHC);
1759         stats->hgptc += IGC_READ_REG(hw, IGC_HGPTC);
1760         stats->icrxdmtc += IGC_READ_REG(hw, IGC_ICRXDMTC);
1761
1762         /* Host to Card Statistics */
1763         stats->hgorc += IGC_READ_REG(hw, IGC_HGORCL);
1764         stats->hgorc += ((uint64_t)IGC_READ_REG(hw, IGC_HGORCH) << 32);
1765         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1766         stats->hgotc += IGC_READ_REG(hw, IGC_HGOTCL);
1767         stats->hgotc += ((uint64_t)IGC_READ_REG(hw, IGC_HGOTCH) << 32);
1768         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1769         stats->lenerrs += IGC_READ_REG(hw, IGC_LENERRS);
1770 }
1771
1772 /*
1773  * Write 0 to all queue status registers
1774  */
1775 static void
1776 igc_reset_queue_stats_register(struct igc_hw *hw)
1777 {
1778         int i;
1779
1780         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1781                 IGC_WRITE_REG(hw, IGC_PQGPRC(i), 0);
1782                 IGC_WRITE_REG(hw, IGC_PQGPTC(i), 0);
1783                 IGC_WRITE_REG(hw, IGC_PQGORC(i), 0);
1784                 IGC_WRITE_REG(hw, IGC_PQGOTC(i), 0);
1785                 IGC_WRITE_REG(hw, IGC_PQMPRC(i), 0);
1786                 IGC_WRITE_REG(hw, IGC_RQDPC(i), 0);
1787                 IGC_WRITE_REG(hw, IGC_TQDPC(i), 0);
1788         }
1789 }
1790
1791 /*
1792  * Read all hardware queue status registers
1793  */
1794 static void
1795 igc_read_queue_stats_register(struct rte_eth_dev *dev)
1796 {
1797         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1798         struct igc_hw_queue_stats *queue_stats =
1799                                 IGC_DEV_PRIVATE_QUEUE_STATS(dev);
1800         int i;
1801
1802         /*
1803          * This register is not cleared on read. Furthermore, the register wraps
1804          * around back to 0x00000000 on the next increment when reaching a value
1805          * of 0xFFFFFFFF and then continues normal count operation.
1806          */
1807         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1808                 union {
1809                         u64 ddword;
1810                         u32 dword[2];
1811                 } value;
1812                 u32 tmp;
1813
1814                 /*
1815                  * Read the register first, if the value is smaller than that
1816                  * previous read, that mean the register has been overflowed,
1817                  * then we add the high 4 bytes by 1 and replace the low 4
1818                  * bytes by the new value.
1819                  */
1820                 tmp = IGC_READ_REG(hw, IGC_PQGPRC(i));
1821                 value.ddword = queue_stats->pqgprc[i];
1822                 if (value.dword[U32_0_IN_U64] > tmp)
1823                         value.dword[U32_1_IN_U64]++;
1824                 value.dword[U32_0_IN_U64] = tmp;
1825                 queue_stats->pqgprc[i] = value.ddword;
1826
1827                 tmp = IGC_READ_REG(hw, IGC_PQGPTC(i));
1828                 value.ddword = queue_stats->pqgptc[i];
1829                 if (value.dword[U32_0_IN_U64] > tmp)
1830                         value.dword[U32_1_IN_U64]++;
1831                 value.dword[U32_0_IN_U64] = tmp;
1832                 queue_stats->pqgptc[i] = value.ddword;
1833
1834                 tmp = IGC_READ_REG(hw, IGC_PQGORC(i));
1835                 value.ddword = queue_stats->pqgorc[i];
1836                 if (value.dword[U32_0_IN_U64] > tmp)
1837                         value.dword[U32_1_IN_U64]++;
1838                 value.dword[U32_0_IN_U64] = tmp;
1839                 queue_stats->pqgorc[i] = value.ddword;
1840
1841                 tmp = IGC_READ_REG(hw, IGC_PQGOTC(i));
1842                 value.ddword = queue_stats->pqgotc[i];
1843                 if (value.dword[U32_0_IN_U64] > tmp)
1844                         value.dword[U32_1_IN_U64]++;
1845                 value.dword[U32_0_IN_U64] = tmp;
1846                 queue_stats->pqgotc[i] = value.ddword;
1847
1848                 tmp = IGC_READ_REG(hw, IGC_PQMPRC(i));
1849                 value.ddword = queue_stats->pqmprc[i];
1850                 if (value.dword[U32_0_IN_U64] > tmp)
1851                         value.dword[U32_1_IN_U64]++;
1852                 value.dword[U32_0_IN_U64] = tmp;
1853                 queue_stats->pqmprc[i] = value.ddword;
1854
1855                 tmp = IGC_READ_REG(hw, IGC_RQDPC(i));
1856                 value.ddword = queue_stats->rqdpc[i];
1857                 if (value.dword[U32_0_IN_U64] > tmp)
1858                         value.dword[U32_1_IN_U64]++;
1859                 value.dword[U32_0_IN_U64] = tmp;
1860                 queue_stats->rqdpc[i] = value.ddword;
1861
1862                 tmp = IGC_READ_REG(hw, IGC_TQDPC(i));
1863                 value.ddword = queue_stats->tqdpc[i];
1864                 if (value.dword[U32_0_IN_U64] > tmp)
1865                         value.dword[U32_1_IN_U64]++;
1866                 value.dword[U32_0_IN_U64] = tmp;
1867                 queue_stats->tqdpc[i] = value.ddword;
1868         }
1869 }
1870
1871 static int
1872 eth_igc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1873 {
1874         struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
1875         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1876         struct igc_hw_stats *stats = IGC_DEV_PRIVATE_STATS(dev);
1877         struct igc_hw_queue_stats *queue_stats =
1878                         IGC_DEV_PRIVATE_QUEUE_STATS(dev);
1879         int i;
1880
1881         /*
1882          * Cancel status handler since it will read the queue status registers
1883          */
1884         rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev);
1885
1886         /* Read status register */
1887         igc_read_queue_stats_register(dev);
1888         igc_read_stats_registers(hw, stats);
1889
1890         if (rte_stats == NULL) {
1891                 /* Restart queue status handler */
1892                 rte_eal_alarm_set(IGC_ALARM_INTERVAL,
1893                                 igc_update_queue_stats_handler, dev);
1894                 return -EINVAL;
1895         }
1896
1897         /* Rx Errors */
1898         rte_stats->imissed = stats->mpc;
1899         rte_stats->ierrors = stats->crcerrs +
1900                         stats->rlec + stats->ruc + stats->roc +
1901                         stats->rxerrc + stats->algnerrc;
1902
1903         /* Tx Errors */
1904         rte_stats->oerrors = stats->ecol + stats->latecol;
1905
1906         rte_stats->ipackets = stats->gprc;
1907         rte_stats->opackets = stats->gptc;
1908         rte_stats->ibytes   = stats->gorc;
1909         rte_stats->obytes   = stats->gotc;
1910
1911         /* Get per-queue statuses */
1912         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1913                 /* GET TX queue statuses */
1914                 int map_id = igc->txq_stats_map[i];
1915                 if (map_id >= 0) {
1916                         rte_stats->q_opackets[map_id] += queue_stats->pqgptc[i];
1917                         rte_stats->q_obytes[map_id] += queue_stats->pqgotc[i];
1918                 }
1919                 /* Get RX queue statuses */
1920                 map_id = igc->rxq_stats_map[i];
1921                 if (map_id >= 0) {
1922                         rte_stats->q_ipackets[map_id] += queue_stats->pqgprc[i];
1923                         rte_stats->q_ibytes[map_id] += queue_stats->pqgorc[i];
1924                         rte_stats->q_errors[map_id] += queue_stats->rqdpc[i];
1925                 }
1926         }
1927
1928         /* Restart queue status handler */
1929         rte_eal_alarm_set(IGC_ALARM_INTERVAL,
1930                         igc_update_queue_stats_handler, dev);
1931         return 0;
1932 }
1933
1934 static int
1935 eth_igc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1936                    unsigned int n)
1937 {
1938         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1939         struct igc_hw_stats *hw_stats =
1940                         IGC_DEV_PRIVATE_STATS(dev);
1941         unsigned int i;
1942
1943         igc_read_stats_registers(hw, hw_stats);
1944
1945         if (n < IGC_NB_XSTATS)
1946                 return IGC_NB_XSTATS;
1947
1948         /* If this is a reset xstats is NULL, and we have cleared the
1949          * registers by reading them.
1950          */
1951         if (!xstats)
1952                 return 0;
1953
1954         /* Extended stats */
1955         for (i = 0; i < IGC_NB_XSTATS; i++) {
1956                 xstats[i].id = i;
1957                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1958                         rte_igc_stats_strings[i].offset);
1959         }
1960
1961         return IGC_NB_XSTATS;
1962 }
1963
1964 static int
1965 eth_igc_xstats_reset(struct rte_eth_dev *dev)
1966 {
1967         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1968         struct igc_hw_stats *hw_stats = IGC_DEV_PRIVATE_STATS(dev);
1969         struct igc_hw_queue_stats *queue_stats =
1970                         IGC_DEV_PRIVATE_QUEUE_STATS(dev);
1971
1972         /* Cancel queue status handler for avoid conflict */
1973         rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev);
1974
1975         /* HW registers are cleared on read */
1976         igc_reset_queue_stats_register(hw);
1977         igc_read_stats_registers(hw, hw_stats);
1978
1979         /* Reset software totals */
1980         memset(hw_stats, 0, sizeof(*hw_stats));
1981         memset(queue_stats, 0, sizeof(*queue_stats));
1982
1983         /* Restart the queue status handler */
1984         rte_eal_alarm_set(IGC_ALARM_INTERVAL, igc_update_queue_stats_handler,
1985                         dev);
1986
1987         return 0;
1988 }
1989
1990 static int
1991 eth_igc_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1992         struct rte_eth_xstat_name *xstats_names, unsigned int size)
1993 {
1994         unsigned int i;
1995
1996         if (xstats_names == NULL)
1997                 return IGC_NB_XSTATS;
1998
1999         if (size < IGC_NB_XSTATS) {
2000                 PMD_DRV_LOG(ERR, "not enough buffers!");
2001                 return IGC_NB_XSTATS;
2002         }
2003
2004         for (i = 0; i < IGC_NB_XSTATS; i++)
2005                 strlcpy(xstats_names[i].name, rte_igc_stats_strings[i].name,
2006                         sizeof(xstats_names[i].name));
2007
2008         return IGC_NB_XSTATS;
2009 }
2010
2011 static int
2012 eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,
2013                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
2014                 unsigned int limit)
2015 {
2016         unsigned int i;
2017
2018         if (!ids)
2019                 return eth_igc_xstats_get_names(dev, xstats_names, limit);
2020
2021         for (i = 0; i < limit; i++) {
2022                 if (ids[i] >= IGC_NB_XSTATS) {
2023                         PMD_DRV_LOG(ERR, "id value isn't valid");
2024                         return -EINVAL;
2025                 }
2026                 strlcpy(xstats_names[i].name,
2027                         rte_igc_stats_strings[ids[i]].name,
2028                         sizeof(xstats_names[i].name));
2029         }
2030         return limit;
2031 }
2032
2033 static int
2034 eth_igc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2035                 uint64_t *values, unsigned int n)
2036 {
2037         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2038         struct igc_hw_stats *hw_stats = IGC_DEV_PRIVATE_STATS(dev);
2039         unsigned int i;
2040
2041         igc_read_stats_registers(hw, hw_stats);
2042
2043         if (!ids) {
2044                 if (n < IGC_NB_XSTATS)
2045                         return IGC_NB_XSTATS;
2046
2047                 /* If this is a reset xstats is NULL, and we have cleared the
2048                  * registers by reading them.
2049                  */
2050                 if (!values)
2051                         return 0;
2052
2053                 /* Extended stats */
2054                 for (i = 0; i < IGC_NB_XSTATS; i++)
2055                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2056                                         rte_igc_stats_strings[i].offset);
2057
2058                 return IGC_NB_XSTATS;
2059
2060         } else {
2061                 for (i = 0; i < n; i++) {
2062                         if (ids[i] >= IGC_NB_XSTATS) {
2063                                 PMD_DRV_LOG(ERR, "id value isn't valid");
2064                                 return -EINVAL;
2065                         }
2066                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2067                                         rte_igc_stats_strings[ids[i]].offset);
2068                 }
2069                 return n;
2070         }
2071 }
2072
2073 static int
2074 eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev,
2075                 uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx)
2076 {
2077         struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
2078
2079         /* check queue id is valid */
2080         if (queue_id >= IGC_QUEUE_PAIRS_NUM) {
2081                 PMD_DRV_LOG(ERR, "queue id(%u) error, max is %u",
2082                         queue_id, IGC_QUEUE_PAIRS_NUM - 1);
2083                 return -EINVAL;
2084         }
2085
2086         /* store the mapping status id */
2087         if (is_rx)
2088                 igc->rxq_stats_map[queue_id] = stat_idx;
2089         else
2090                 igc->txq_stats_map[queue_id] = stat_idx;
2091
2092         return 0;
2093 }
2094
2095 static int
2096 eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2097 {
2098         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2099         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2100         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101         uint32_t vec = IGC_MISC_VEC_ID;
2102
2103         if (rte_intr_allow_others(intr_handle))
2104                 vec = IGC_RX_VEC_START;
2105
2106         uint32_t mask = 1u << (queue_id + vec);
2107
2108         IGC_WRITE_REG(hw, IGC_EIMC, mask);
2109         IGC_WRITE_FLUSH(hw);
2110
2111         return 0;
2112 }
2113
2114 static int
2115 eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2116 {
2117         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2118         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2119         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2120         uint32_t vec = IGC_MISC_VEC_ID;
2121
2122         if (rte_intr_allow_others(intr_handle))
2123                 vec = IGC_RX_VEC_START;
2124
2125         uint32_t mask = 1u << (queue_id + vec);
2126
2127         IGC_WRITE_REG(hw, IGC_EIMS, mask);
2128         IGC_WRITE_FLUSH(hw);
2129
2130         rte_intr_enable(intr_handle);
2131
2132         return 0;
2133 }
2134
2135 static int
2136 eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2137 {
2138         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2139         uint32_t ctrl;
2140         int tx_pause;
2141         int rx_pause;
2142
2143         fc_conf->pause_time = hw->fc.pause_time;
2144         fc_conf->high_water = hw->fc.high_water;
2145         fc_conf->low_water = hw->fc.low_water;
2146         fc_conf->send_xon = hw->fc.send_xon;
2147         fc_conf->autoneg = hw->mac.autoneg;
2148
2149         /*
2150          * Return rx_pause and tx_pause status according to actual setting of
2151          * the TFCE and RFCE bits in the CTRL register.
2152          */
2153         ctrl = IGC_READ_REG(hw, IGC_CTRL);
2154         if (ctrl & IGC_CTRL_TFCE)
2155                 tx_pause = 1;
2156         else
2157                 tx_pause = 0;
2158
2159         if (ctrl & IGC_CTRL_RFCE)
2160                 rx_pause = 1;
2161         else
2162                 rx_pause = 0;
2163
2164         if (rx_pause && tx_pause)
2165                 fc_conf->mode = RTE_FC_FULL;
2166         else if (rx_pause)
2167                 fc_conf->mode = RTE_FC_RX_PAUSE;
2168         else if (tx_pause)
2169                 fc_conf->mode = RTE_FC_TX_PAUSE;
2170         else
2171                 fc_conf->mode = RTE_FC_NONE;
2172
2173         return 0;
2174 }
2175
2176 static int
2177 eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2178 {
2179         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2180         uint32_t rx_buf_size;
2181         uint32_t max_high_water;
2182         uint32_t rctl;
2183         int err;
2184
2185         if (fc_conf->autoneg != hw->mac.autoneg)
2186                 return -ENOTSUP;
2187
2188         rx_buf_size = igc_get_rx_buffer_size(hw);
2189         PMD_DRV_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2190
2191         /* At least reserve one Ethernet frame for watermark */
2192         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
2193         if (fc_conf->high_water > max_high_water ||
2194                 fc_conf->high_water < fc_conf->low_water) {
2195                 PMD_DRV_LOG(ERR,
2196                         "Incorrect high(%u)/low(%u) water value, max is %u",
2197                         fc_conf->high_water, fc_conf->low_water,
2198                         max_high_water);
2199                 return -EINVAL;
2200         }
2201
2202         switch (fc_conf->mode) {
2203         case RTE_FC_NONE:
2204                 hw->fc.requested_mode = igc_fc_none;
2205                 break;
2206         case RTE_FC_RX_PAUSE:
2207                 hw->fc.requested_mode = igc_fc_rx_pause;
2208                 break;
2209         case RTE_FC_TX_PAUSE:
2210                 hw->fc.requested_mode = igc_fc_tx_pause;
2211                 break;
2212         case RTE_FC_FULL:
2213                 hw->fc.requested_mode = igc_fc_full;
2214                 break;
2215         default:
2216                 PMD_DRV_LOG(ERR, "unsupported fc mode: %u", fc_conf->mode);
2217                 return -EINVAL;
2218         }
2219
2220         hw->fc.pause_time     = fc_conf->pause_time;
2221         hw->fc.high_water     = fc_conf->high_water;
2222         hw->fc.low_water      = fc_conf->low_water;
2223         hw->fc.send_xon       = fc_conf->send_xon;
2224
2225         err = igc_setup_link_generic(hw);
2226         if (err == IGC_SUCCESS) {
2227                 /**
2228                  * check if we want to forward MAC frames - driver doesn't have
2229                  * native capability to do that, so we'll write the registers
2230                  * ourselves
2231                  **/
2232                 rctl = IGC_READ_REG(hw, IGC_RCTL);
2233
2234                 /* set or clear MFLCN.PMCF bit depending on configuration */
2235                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2236                         rctl |= IGC_RCTL_PMCF;
2237                 else
2238                         rctl &= ~IGC_RCTL_PMCF;
2239
2240                 IGC_WRITE_REG(hw, IGC_RCTL, rctl);
2241                 IGC_WRITE_FLUSH(hw);
2242
2243                 return 0;
2244         }
2245
2246         PMD_DRV_LOG(ERR, "igc_setup_link_generic = 0x%x", err);
2247         return -EIO;
2248 }
2249
2250 static int
2251 eth_igc_rss_reta_update(struct rte_eth_dev *dev,
2252                         struct rte_eth_rss_reta_entry64 *reta_conf,
2253                         uint16_t reta_size)
2254 {
2255         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2256         uint16_t i;
2257
2258         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2259                 PMD_DRV_LOG(ERR,
2260                         "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)",
2261                         reta_size, ETH_RSS_RETA_SIZE_128);
2262                 return -EINVAL;
2263         }
2264
2265         RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
2266
2267         /* set redirection table */
2268         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
2269                 union igc_rss_reta_reg reta, reg;
2270                 uint16_t idx, shift;
2271                 uint8_t j, mask;
2272
2273                 idx = i / RTE_RETA_GROUP_SIZE;
2274                 shift = i % RTE_RETA_GROUP_SIZE;
2275                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2276                                 IGC_RSS_RDT_REG_SIZE_MASK);
2277
2278                 /* if no need to update the register */
2279                 if (!mask ||
2280                     shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
2281                         continue;
2282
2283                 /* check mask whether need to read the register value first */
2284                 if (mask == IGC_RSS_RDT_REG_SIZE_MASK)
2285                         reg.dword = 0;
2286                 else
2287                         reg.dword = IGC_READ_REG_LE_VALUE(hw,
2288                                         IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
2289
2290                 /* update the register */
2291                 RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
2292                 for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
2293                         if (mask & (1u << j))
2294                                 reta.bytes[j] =
2295                                         (uint8_t)reta_conf[idx].reta[shift + j];
2296                         else
2297                                 reta.bytes[j] = reg.bytes[j];
2298                 }
2299                 IGC_WRITE_REG_LE_VALUE(hw,
2300                         IGC_RETA(i / IGC_RSS_RDT_REG_SIZE), reta.dword);
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int
2307 eth_igc_rss_reta_query(struct rte_eth_dev *dev,
2308                        struct rte_eth_rss_reta_entry64 *reta_conf,
2309                        uint16_t reta_size)
2310 {
2311         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2312         uint16_t i;
2313
2314         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2315                 PMD_DRV_LOG(ERR,
2316                         "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)",
2317                         reta_size, ETH_RSS_RETA_SIZE_128);
2318                 return -EINVAL;
2319         }
2320
2321         RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
2322
2323         /* read redirection table */
2324         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
2325                 union igc_rss_reta_reg reta;
2326                 uint16_t idx, shift;
2327                 uint8_t j, mask;
2328
2329                 idx = i / RTE_RETA_GROUP_SIZE;
2330                 shift = i % RTE_RETA_GROUP_SIZE;
2331                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2332                                 IGC_RSS_RDT_REG_SIZE_MASK);
2333
2334                 /* if no need to read register */
2335                 if (!mask ||
2336                     shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
2337                         continue;
2338
2339                 /* read register and get the queue index */
2340                 RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
2341                 reta.dword = IGC_READ_REG_LE_VALUE(hw,
2342                                 IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
2343                 for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
2344                         if (mask & (1u << j))
2345                                 reta_conf[idx].reta[shift + j] = reta.bytes[j];
2346                 }
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int
2353 eth_igc_rss_hash_update(struct rte_eth_dev *dev,
2354                         struct rte_eth_rss_conf *rss_conf)
2355 {
2356         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2357         igc_hw_rss_hash_set(hw, rss_conf);
2358         return 0;
2359 }
2360
2361 static int
2362 eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,
2363                         struct rte_eth_rss_conf *rss_conf)
2364 {
2365         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2366         uint32_t *hash_key = (uint32_t *)rss_conf->rss_key;
2367         uint32_t mrqc;
2368         uint64_t rss_hf;
2369
2370         if (hash_key != NULL) {
2371                 int i;
2372
2373                 /* if not enough space for store hash key */
2374                 if (rss_conf->rss_key_len != IGC_HKEY_SIZE) {
2375                         PMD_DRV_LOG(ERR,
2376                                 "RSS hash key size %u in parameter doesn't match the hardware hash key size %u",
2377                                 rss_conf->rss_key_len, IGC_HKEY_SIZE);
2378                         return -EINVAL;
2379                 }
2380
2381                 /* read RSS key from register */
2382                 for (i = 0; i < IGC_HKEY_MAX_INDEX; i++)
2383                         hash_key[i] = IGC_READ_REG_LE_VALUE(hw, IGC_RSSRK(i));
2384         }
2385
2386         /* get RSS functions configured in MRQC register */
2387         mrqc = IGC_READ_REG(hw, IGC_MRQC);
2388         if ((mrqc & IGC_MRQC_ENABLE_RSS_4Q) == 0)
2389                 return 0;
2390
2391         rss_hf = 0;
2392         if (mrqc & IGC_MRQC_RSS_FIELD_IPV4)
2393                 rss_hf |= ETH_RSS_IPV4;
2394         if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_TCP)
2395                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2396         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6)
2397                 rss_hf |= ETH_RSS_IPV6;
2398         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_EX)
2399                 rss_hf |= ETH_RSS_IPV6_EX;
2400         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP)
2401                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2402         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP_EX)
2403                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2404         if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_UDP)
2405                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2406         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP)
2407                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2408         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP_EX)
2409                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2410
2411         rss_conf->rss_hf |= rss_hf;
2412         return 0;
2413 }
2414
2415 static int
2416 eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2417 {
2418         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2419         struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev);
2420         uint32_t vfta;
2421         uint32_t vid_idx;
2422         uint32_t vid_bit;
2423
2424         vid_idx = (vlan_id >> IGC_VFTA_ENTRY_SHIFT) & IGC_VFTA_ENTRY_MASK;
2425         vid_bit = 1u << (vlan_id & IGC_VFTA_ENTRY_BIT_SHIFT_MASK);
2426         vfta = shadow_vfta->vfta[vid_idx];
2427         if (on)
2428                 vfta |= vid_bit;
2429         else
2430                 vfta &= ~vid_bit;
2431         IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, vid_idx, vfta);
2432
2433         /* update local VFTA copy */
2434         shadow_vfta->vfta[vid_idx] = vfta;
2435
2436         return 0;
2437 }
2438
2439 static void
2440 igc_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2441 {
2442         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2443         igc_read_reg_check_clear_bits(hw, IGC_RCTL,
2444                         IGC_RCTL_CFIEN | IGC_RCTL_VFE);
2445 }
2446
2447 static void
2448 igc_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2449 {
2450         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2451         struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev);
2452         uint32_t reg_val;
2453         int i;
2454
2455         /* Filter Table Enable, CFI not used for packet acceptance */
2456         reg_val = IGC_READ_REG(hw, IGC_RCTL);
2457         reg_val &= ~IGC_RCTL_CFIEN;
2458         reg_val |= IGC_RCTL_VFE;
2459         IGC_WRITE_REG(hw, IGC_RCTL, reg_val);
2460
2461         /* restore VFTA table */
2462         for (i = 0; i < IGC_VFTA_SIZE; i++)
2463                 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, i, shadow_vfta->vfta[i]);
2464 }
2465
2466 static void
2467 igc_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2468 {
2469         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2470
2471         igc_read_reg_check_clear_bits(hw, IGC_CTRL, IGC_CTRL_VME);
2472 }
2473
2474 static void
2475 igc_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2476 {
2477         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2478
2479         igc_read_reg_check_set_bits(hw, IGC_CTRL, IGC_CTRL_VME);
2480 }
2481
2482 static int
2483 igc_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2484 {
2485         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2486         uint32_t ctrl_ext;
2487
2488         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
2489
2490         /* if extend vlan hasn't been enabled */
2491         if ((ctrl_ext & IGC_CTRL_EXT_EXT_VLAN) == 0)
2492                 return 0;
2493
2494         if ((dev->data->dev_conf.rxmode.offloads &
2495                         DEV_RX_OFFLOAD_JUMBO_FRAME) == 0)
2496                 goto write_ext_vlan;
2497
2498         /* Update maximum packet length */
2499         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <
2500                 RTE_ETHER_MIN_MTU + VLAN_TAG_SIZE) {
2501                 PMD_DRV_LOG(ERR, "Maximum packet length %u error, min is %u",
2502                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
2503                         VLAN_TAG_SIZE + RTE_ETHER_MIN_MTU);
2504                 return -EINVAL;
2505         }
2506         dev->data->dev_conf.rxmode.max_rx_pkt_len -= VLAN_TAG_SIZE;
2507         IGC_WRITE_REG(hw, IGC_RLPML,
2508                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2509
2510 write_ext_vlan:
2511         IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_EXT_VLAN);
2512         return 0;
2513 }
2514
2515 static int
2516 igc_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2517 {
2518         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2519         uint32_t ctrl_ext;
2520
2521         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
2522
2523         /* if extend vlan has been enabled */
2524         if (ctrl_ext & IGC_CTRL_EXT_EXT_VLAN)
2525                 return 0;
2526
2527         if ((dev->data->dev_conf.rxmode.offloads &
2528                         DEV_RX_OFFLOAD_JUMBO_FRAME) == 0)
2529                 goto write_ext_vlan;
2530
2531         /* Update maximum packet length */
2532         if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
2533                 MAX_RX_JUMBO_FRAME_SIZE - VLAN_TAG_SIZE) {
2534                 PMD_DRV_LOG(ERR, "Maximum packet length %u error, max is %u",
2535                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2536                         VLAN_TAG_SIZE, MAX_RX_JUMBO_FRAME_SIZE);
2537                 return -EINVAL;
2538         }
2539         dev->data->dev_conf.rxmode.max_rx_pkt_len += VLAN_TAG_SIZE;
2540         IGC_WRITE_REG(hw, IGC_RLPML,
2541                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2542
2543 write_ext_vlan:
2544         IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_EXT_VLAN);
2545         return 0;
2546 }
2547
2548 static int
2549 eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2550 {
2551         struct rte_eth_rxmode *rxmode;
2552
2553         rxmode = &dev->data->dev_conf.rxmode;
2554         if (mask & ETH_VLAN_STRIP_MASK) {
2555                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2556                         igc_vlan_hw_strip_enable(dev);
2557                 else
2558                         igc_vlan_hw_strip_disable(dev);
2559         }
2560
2561         if (mask & ETH_VLAN_FILTER_MASK) {
2562                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2563                         igc_vlan_hw_filter_enable(dev);
2564                 else
2565                         igc_vlan_hw_filter_disable(dev);
2566         }
2567
2568         if (mask & ETH_VLAN_EXTEND_MASK) {
2569                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2570                         return igc_vlan_hw_extend_enable(dev);
2571                 else
2572                         return igc_vlan_hw_extend_disable(dev);
2573         }
2574
2575         return 0;
2576 }
2577
2578 static int
2579 eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
2580                       enum rte_vlan_type vlan_type,
2581                       uint16_t tpid)
2582 {
2583         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2584         uint32_t reg_val;
2585
2586         /* only outer TPID of double VLAN can be configured*/
2587         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2588                 reg_val = IGC_READ_REG(hw, IGC_VET);
2589                 reg_val = (reg_val & (~IGC_VET_EXT)) |
2590                         ((uint32_t)tpid << IGC_VET_EXT_SHIFT);
2591                 IGC_WRITE_REG(hw, IGC_VET, reg_val);
2592
2593                 return 0;
2594         }
2595
2596         /* all other TPID values are read-only*/
2597         PMD_DRV_LOG(ERR, "Not supported");
2598         return -ENOTSUP;
2599 }
2600
2601 static int
2602 eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2603         struct rte_pci_device *pci_dev)
2604 {
2605         PMD_INIT_FUNC_TRACE();
2606         return rte_eth_dev_pci_generic_probe(pci_dev,
2607                 sizeof(struct igc_adapter), eth_igc_dev_init);
2608 }
2609
2610 static int
2611 eth_igc_pci_remove(struct rte_pci_device *pci_dev)
2612 {
2613         PMD_INIT_FUNC_TRACE();
2614         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igc_dev_uninit);
2615 }
2616
2617 static struct rte_pci_driver rte_igc_pmd = {
2618         .id_table = pci_id_igc_map,
2619         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2620         .probe = eth_igc_pci_probe,
2621         .remove = eth_igc_pci_remove,
2622 };
2623
2624 RTE_PMD_REGISTER_PCI(net_igc, rte_igc_pmd);
2625 RTE_PMD_REGISTER_PCI_TABLE(net_igc, pci_id_igc_map);
2626 RTE_PMD_REGISTER_KMOD_DEP(net_igc, "* igb_uio | uio_pci_generic | vfio-pci");