drivers/net/ionic/ionic_lif.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_ethdev_driver.h>
   7
   8 #include "ionic.h"
   9 #include "ionic_logs.h"
  10 #include "ionic_lif.h"
  11 #include "ionic_ethdev.h"
  12 #include "ionic_rx_filter.h"
  13 #include "ionic_rxtx.h"
  14
  15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
  16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
  17
  18 int
  19 ionic_qcq_enable(struct ionic_qcq *qcq)
  20 {
  21         struct ionic_queue *q = &qcq->q;
  22         struct ionic_lif *lif = q->lif;
  23         struct ionic_dev *idev = &lif->adapter->idev;
  24         struct ionic_admin_ctx ctx = {
  25                 .pending_work = true,
  26                 .cmd.q_control = {
  27                         .opcode = IONIC_CMD_Q_CONTROL,
  28                         .lif_index = lif->index,
  29                         .type = q->type,
  30                         .index = q->index,
  31                         .oper = IONIC_Q_ENABLE,
  32                 },
  33         };
  34
  35         if (qcq->flags & IONIC_QCQ_F_INTR) {
  36                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
  37                         IONIC_INTR_MASK_CLEAR);
  38         }
  39
  40         return ionic_adminq_post_wait(lif, &ctx);
  41 }
  42
  43 int
  44 ionic_qcq_disable(struct ionic_qcq *qcq)
  45 {
  46         struct ionic_queue *q = &qcq->q;
  47         struct ionic_lif *lif = q->lif;
  48         struct ionic_dev *idev = &lif->adapter->idev;
  49         struct ionic_admin_ctx ctx = {
  50                 .pending_work = true,
  51                 .cmd.q_control = {
  52                         .opcode = IONIC_CMD_Q_CONTROL,
  53                         .lif_index = lif->index,
  54                         .type = q->type,
  55                         .index = q->index,
  56                         .oper = IONIC_Q_DISABLE,
  57                 },
  58         };
  59
  60         if (qcq->flags & IONIC_QCQ_F_INTR) {
  61                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
  62                         IONIC_INTR_MASK_SET);
  63         }
  64
  65         return ionic_adminq_post_wait(lif, &ctx);
  66 }
  67
  68 int
  69 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
  70 {
  71         /* Carrier OFF here */
  72
  73         return 0;
  74 }
  75
  76 void
  77 ionic_lif_reset(struct ionic_lif *lif)
  78 {
  79         struct ionic_dev *idev = &lif->adapter->idev;
  80
  81         IONIC_PRINT_CALL();
  82
  83         ionic_dev_cmd_lif_reset(idev, lif->index);
  84         ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
  85 }
  86
  87 static int
  88 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
  89 {
  90         struct ionic_admin_ctx ctx = {
  91                 .pending_work = true,
  92                 .cmd.rx_filter_add = {
  93                         .opcode = IONIC_CMD_RX_FILTER_ADD,
  94                         .match = IONIC_RX_FILTER_MATCH_MAC,
  95                 },
  96         };
  97         int err;
  98
  99         memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
 100
 101         err = ionic_adminq_post_wait(lif, &ctx);
 102         if (err)
 103                 return err;
 104
 105         IONIC_PRINT(INFO, "rx_filter add (id %d)",
 106                 ctx.comp.rx_filter_add.filter_id);
 107
 108         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 109 }
 110
 111 static int
 112 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
 113 {
 114         struct ionic_admin_ctx ctx = {
 115                 .pending_work = true,
 116                 .cmd.rx_filter_del = {
 117                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 118                 },
 119         };
 120         struct ionic_rx_filter *f;
 121         int err;
 122
 123         IONIC_PRINT_CALL();
 124
 125         rte_spinlock_lock(&lif->rx_filters.lock);
 126
 127         f = ionic_rx_filter_by_addr(lif, addr);
 128         if (!f) {
 129                 rte_spinlock_unlock(&lif->rx_filters.lock);
 130                 return -ENOENT;
 131         }
 132
 133         ctx.cmd.rx_filter_del.filter_id = f->filter_id;
 134         ionic_rx_filter_free(f);
 135
 136         rte_spinlock_unlock(&lif->rx_filters.lock);
 137
 138         err = ionic_adminq_post_wait(lif, &ctx);
 139         if (err)
 140                 return err;
 141
 142         IONIC_PRINT(INFO, "rx_filter del (id %d)",
 143                 ctx.cmd.rx_filter_del.filter_id);
 144
 145         return 0;
 146 }
 147
 148 int
 149 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
 150                 struct rte_ether_addr *mac_addr,
 151                 uint32_t index __rte_unused, uint32_t pool __rte_unused)
 152 {
 153         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 154
 155         IONIC_PRINT_CALL();
 156
 157         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 158 }
 159
 160 void
 161 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
 162 {
 163         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 164         struct ionic_adapter *adapter = lif->adapter;
 165
 166         IONIC_PRINT_CALL();
 167
 168         if (index >= adapter->max_mac_addrs) {
 169                 IONIC_PRINT(WARNING,
 170                         "Index %u is above MAC filter limit %u",
 171                         index, adapter->max_mac_addrs);
 172                 return;
 173         }
 174
 175         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 176                 return;
 177
 178         ionic_lif_addr_del(lif, (const uint8_t *)
 179                 &eth_dev->data->mac_addrs[index]);
 180 }
 181
 182 int
 183 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 184 {
 185         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 186
 187         IONIC_PRINT_CALL();
 188
 189         if (mac_addr == NULL) {
 190                 IONIC_PRINT(NOTICE, "New mac is null");
 191                 return -1;
 192         }
 193
 194         if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
 195                 IONIC_PRINT(INFO, "Deleting mac addr %pM",
 196                         lif->mac_addr);
 197                 ionic_lif_addr_del(lif, lif->mac_addr);
 198                 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
 199         }
 200
 201         IONIC_PRINT(INFO, "Updating mac addr");
 202
 203         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
 204
 205         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 206 }
 207
 208 static int
 209 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
 210 {
 211         struct ionic_admin_ctx ctx = {
 212                 .pending_work = true,
 213                 .cmd.rx_filter_add = {
 214                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 215                         .match = IONIC_RX_FILTER_MATCH_VLAN,
 216                         .vlan.vlan = vid,
 217                 },
 218         };
 219         int err;
 220
 221         err = ionic_adminq_post_wait(lif, &ctx);
 222         if (err)
 223                 return err;
 224
 225         IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
 226                 ctx.comp.rx_filter_add.filter_id);
 227
 228         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 229 }
 230
 231 static int
 232 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
 233 {
 234         struct ionic_admin_ctx ctx = {
 235                 .pending_work = true,
 236                 .cmd.rx_filter_del = {
 237                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 238                 },
 239         };
 240         struct ionic_rx_filter *f;
 241         int err;
 242
 243         IONIC_PRINT_CALL();
 244
 245         rte_spinlock_lock(&lif->rx_filters.lock);
 246
 247         f = ionic_rx_filter_by_vlan(lif, vid);
 248         if (!f) {
 249                 rte_spinlock_unlock(&lif->rx_filters.lock);
 250                 return -ENOENT;
 251         }
 252
 253         ctx.cmd.rx_filter_del.filter_id = f->filter_id;
 254         ionic_rx_filter_free(f);
 255         rte_spinlock_unlock(&lif->rx_filters.lock);
 256
 257         err = ionic_adminq_post_wait(lif, &ctx);
 258         if (err)
 259                 return err;
 260
 261         IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
 262                 ctx.cmd.rx_filter_del.filter_id);
 263
 264         return 0;
 265 }
 266
 267 int
 268 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
 269                 int on)
 270 {
 271         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 272         int err;
 273
 274         if (on)
 275                 err = ionic_vlan_rx_add_vid(lif, vlan_id);
 276         else
 277                 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
 278
 279         return err;
 280 }
 281
 282 static void
 283 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 284 {
 285         struct ionic_admin_ctx ctx = {
 286                 .pending_work = true,
 287                 .cmd.rx_mode_set = {
 288                         .opcode = IONIC_CMD_RX_MODE_SET,
 289                         .lif_index = lif->index,
 290                         .rx_mode = rx_mode,
 291                 },
 292         };
 293         int err;
 294
 295         if (rx_mode & IONIC_RX_MODE_F_UNICAST)
 296                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
 297         if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
 298                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
 299         if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
 300                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
 301         if (rx_mode & IONIC_RX_MODE_F_PROMISC)
 302                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
 303         if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
 304                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
 305
 306         err = ionic_adminq_post_wait(lif, &ctx);
 307         if (err)
 308                 IONIC_PRINT(ERR, "Failure setting RX mode");
 309 }
 310
 311 static void
 312 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 313 {
 314         if (lif->rx_mode != rx_mode) {
 315                 lif->rx_mode = rx_mode;
 316                 ionic_lif_rx_mode(lif, rx_mode);
 317         }
 318 }
 319
 320 int
 321 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 322 {
 323         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 324         uint32_t rx_mode = lif->rx_mode;
 325
 326         IONIC_PRINT_CALL();
 327
 328         rx_mode |= IONIC_RX_MODE_F_PROMISC;
 329
 330         ionic_set_rx_mode(lif, rx_mode);
 331
 332         return 0;
 333 }
 334
 335 int
 336 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 337 {
 338         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 339         uint32_t rx_mode = lif->rx_mode;
 340
 341         rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
 342
 343         ionic_set_rx_mode(lif, rx_mode);
 344
 345         return 0;
 346 }
 347
 348 int
 349 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 350 {
 351         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 352         uint32_t rx_mode = lif->rx_mode;
 353
 354         rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
 355
 356         ionic_set_rx_mode(lif, rx_mode);
 357
 358         return 0;
 359 }
 360
 361 int
 362 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 363 {
 364         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 365         uint32_t rx_mode = lif->rx_mode;
 366
 367         rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
 368
 369         ionic_set_rx_mode(lif, rx_mode);
 370
 371         return 0;
 372 }
 373
 374 int
 375 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
 376 {
 377         struct ionic_admin_ctx ctx = {
 378                 .pending_work = true,
 379                 .cmd.lif_setattr = {
 380                         .opcode = IONIC_CMD_LIF_SETATTR,
 381                         .index = lif->index,
 382                         .attr = IONIC_LIF_ATTR_MTU,
 383                         .mtu = new_mtu,
 384                 },
 385         };
 386         int err;
 387
 388         err = ionic_adminq_post_wait(lif, &ctx);
 389         if (err)
 390                 return err;
 391
 392         lif->mtu = new_mtu;
 393
 394         return 0;
 395 }
 396
 397 int
 398 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 399 {
 400         struct ionic_adapter *adapter = lif->adapter;
 401         struct ionic_dev *idev = &adapter->idev;
 402         unsigned long index;
 403
 404         /*
 405          * Note: interrupt handler is called for index = 0 only
 406          * (we use interrupts for the notifyq only anyway,
 407          * which hash index = 0)
 408          */
 409
 410         for (index = 0; index < adapter->nintrs; index++)
 411                 if (!adapter->intrs[index])
 412                         break;
 413
 414         if (index == adapter->nintrs)
 415                 return -ENOSPC;
 416
 417         adapter->intrs[index] = true;
 418
 419         ionic_intr_init(idev, intr, index);
 420
 421         return 0;
 422 }
 423
 424 void
 425 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
 426 {
 427         if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
 428                 lif->adapter->intrs[intr->index] = false;
 429 }
 430
 431 static int
 432 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 433                 uint32_t index,
 434                 const char *base, uint32_t flags,
 435                 uint32_t num_descs,
 436                 uint32_t desc_size,
 437                 uint32_t cq_desc_size,
 438                 uint32_t sg_desc_size,
 439                 uint32_t pid, struct ionic_qcq **qcq)
 440 {
 441         struct ionic_dev *idev = &lif->adapter->idev;
 442         struct ionic_qcq *new;
 443         uint32_t q_size, cq_size, sg_size, total_size;
 444         void *q_base, *cq_base, *sg_base;
 445         rte_iova_t q_base_pa = 0;
 446         rte_iova_t cq_base_pa = 0;
 447         rte_iova_t sg_base_pa = 0;
 448         uint32_t socket_id = rte_socket_id();
 449         int err;
 450
 451         *qcq = NULL;
 452
 453         q_size  = num_descs * desc_size;
 454         cq_size = num_descs * cq_desc_size;
 455         sg_size = num_descs * sg_desc_size;
 456
 457         total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
 458                 RTE_ALIGN(cq_size, PAGE_SIZE);
 459         /*
 460          * Note: aligning q_size/cq_size is not enough due to cq_base address
 461          * aligning as q_base could be not aligned to the page.
 462          * Adding PAGE_SIZE.
 463          */
 464         total_size += PAGE_SIZE;
 465
 466         if (flags & IONIC_QCQ_F_SG) {
 467                 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
 468                 total_size += PAGE_SIZE;
 469         }
 470
 471         new = rte_zmalloc("ionic", sizeof(*new), 0);
 472         if (!new) {
 473                 IONIC_PRINT(ERR, "Cannot allocate queue structure");
 474                 return -ENOMEM;
 475         }
 476
 477         new->lif = lif;
 478         new->flags = flags;
 479
 480         new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
 481         if (!new->q.info) {
 482                 IONIC_PRINT(ERR, "Cannot allocate queue info");
 483                 return -ENOMEM;
 484         }
 485
 486         new->q.type = type;
 487
 488         err = ionic_q_init(lif, idev, &new->q, index, num_descs,
 489                 desc_size, sg_desc_size, pid);
 490         if (err) {
 491                 IONIC_PRINT(ERR, "Queue initialization failed");
 492                 return err;
 493         }
 494
 495         if (flags & IONIC_QCQ_F_INTR) {
 496                 err = ionic_intr_alloc(lif, &new->intr);
 497                 if (err)
 498                         return err;
 499
 500                 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
 501                         IONIC_INTR_MASK_SET);
 502         } else {
 503                 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 504         }
 505
 506         err = ionic_cq_init(lif, &new->cq, &new->intr,
 507                 num_descs, cq_desc_size);
 508         if (err) {
 509                 IONIC_PRINT(ERR, "Completion queue initialization failed");
 510                 goto err_out_free_intr;
 511         }
 512
 513         new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 514                 base /* name */, index /* queue_idx */,
 515                 total_size, IONIC_ALIGN, socket_id);
 516
 517         if (!new->base_z) {
 518                 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
 519                 err = -ENOMEM;
 520                 goto err_out_free_intr;
 521         }
 522
 523         new->base = new->base_z->addr;
 524         new->base_pa = new->base_z->iova;
 525         new->total_size = total_size;
 526
 527         q_base = new->base;
 528         q_base_pa = new->base_pa;
 529
 530         cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
 531         cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
 532
 533         if (flags & IONIC_QCQ_F_SG) {
 534                 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
 535                         PAGE_SIZE);
 536                 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
 537                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 538         }
 539
 540         IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
 541                 "SG-base-PA = %ju",
 542                 q_base_pa, cq_base_pa, sg_base_pa);
 543
 544         ionic_q_map(&new->q, q_base, q_base_pa);
 545         ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 546         ionic_cq_bind(&new->cq, &new->q);
 547
 548         *qcq = new;
 549
 550         return 0;
 551
 552 err_out_free_intr:
 553         if (flags & IONIC_QCQ_F_INTR)
 554                 ionic_intr_free(lif, &new->intr);
 555
 556         return err;
 557 }
 558
 559 void
 560 ionic_qcq_free(struct ionic_qcq *qcq)
 561 {
 562         if (qcq->base_z) {
 563                 qcq->base = NULL;
 564                 qcq->base_pa = 0;
 565                 rte_memzone_free(qcq->base_z);
 566                 qcq->base_z = NULL;
 567         }
 568
 569         if (qcq->q.info) {
 570                 rte_free(qcq->q.info);
 571                 qcq->q.info = NULL;
 572         }
 573
 574         rte_free(qcq);
 575 }
 576
 577 int
 578 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
 579                 struct ionic_qcq **qcq)
 580 {
 581         uint32_t flags;
 582         int err = -ENOMEM;
 583
 584         flags = IONIC_QCQ_F_SG;
 585         err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
 586                 nrxq_descs,
 587                 sizeof(struct ionic_rxq_desc),
 588                 sizeof(struct ionic_rxq_comp),
 589                 sizeof(struct ionic_rxq_sg_desc),
 590                 lif->kern_pid, &lif->rxqcqs[index]);
 591         if (err)
 592                 return err;
 593
 594         *qcq = lif->rxqcqs[index];
 595
 596         return 0;
 597 }
 598
 599 int
 600 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
 601                 struct ionic_qcq **qcq)
 602 {
 603         uint32_t flags;
 604         int err = -ENOMEM;
 605
 606         flags = IONIC_QCQ_F_SG;
 607         err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
 608                 ntxq_descs,
 609                 sizeof(struct ionic_txq_desc),
 610                 sizeof(struct ionic_txq_comp),
 611                 sizeof(struct ionic_txq_sg_desc),
 612                 lif->kern_pid, &lif->txqcqs[index]);
 613         if (err)
 614                 return err;
 615
 616         *qcq = lif->txqcqs[index];
 617
 618         return 0;
 619 }
 620
 621 static int
 622 ionic_admin_qcq_alloc(struct ionic_lif *lif)
 623 {
 624         uint32_t flags;
 625         int err = -ENOMEM;
 626
 627         flags = 0;
 628         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 629                 IONIC_ADMINQ_LENGTH,
 630                 sizeof(struct ionic_admin_cmd),
 631                 sizeof(struct ionic_admin_comp),
 632                 0,
 633                 lif->kern_pid, &lif->adminqcq);
 634         if (err)
 635                 return err;
 636
 637         return 0;
 638 }
 639
 640 static int
 641 ionic_notify_qcq_alloc(struct ionic_lif *lif)
 642 {
 643         uint32_t flags;
 644         int err = -ENOMEM;
 645
 646         flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
 647
 648         err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
 649                 flags,
 650                 IONIC_NOTIFYQ_LENGTH,
 651                 sizeof(struct ionic_notifyq_cmd),
 652                 sizeof(union ionic_notifyq_comp),
 653                 0,
 654                 lif->kern_pid, &lif->notifyqcq);
 655         if (err)
 656                 return err;
 657
 658         return 0;
 659 }
 660
 661 static void *
 662 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
 663 {
 664         char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
 665
 666         if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
 667                 return NULL;
 668
 669         return (void *)&vaddr[page_num << PAGE_SHIFT];
 670 }
 671
 672 int
 673 ionic_lif_alloc(struct ionic_lif *lif)
 674 {
 675         struct ionic_adapter *adapter = lif->adapter;
 676         uint32_t socket_id = rte_socket_id();
 677         int dbpage_num;
 678         int err;
 679
 680         snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
 681
 682         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 683
 684         rte_spinlock_init(&lif->adminq_lock);
 685         rte_spinlock_init(&lif->adminq_service_lock);
 686
 687         lif->kern_pid = 0;
 688
 689         dbpage_num = ionic_db_page_num(lif, 0);
 690
 691         lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
 692         if (!lif->kern_dbpage) {
 693                 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
 694                 return -ENOMEM;
 695         }
 696
 697         lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
 698                 adapter->max_ntxqs_per_lif, 0);
 699
 700         if (!lif->txqcqs) {
 701                 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
 702                 return -ENOMEM;
 703         }
 704
 705         lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
 706                 adapter->max_nrxqs_per_lif, 0);
 707
 708         if (!lif->rxqcqs) {
 709                 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
 710                 return -ENOMEM;
 711         }
 712
 713         IONIC_PRINT(DEBUG, "Allocating Notify Queue");
 714
 715         err = ionic_notify_qcq_alloc(lif);
 716         if (err) {
 717                 IONIC_PRINT(ERR, "Cannot allocate notify queue");
 718                 return err;
 719         }
 720
 721         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 722
 723         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 724
 725         err = ionic_admin_qcq_alloc(lif);
 726         if (err) {
 727                 IONIC_PRINT(ERR, "Cannot allocate admin queue");
 728                 return err;
 729         }
 730
 731         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 732
 733         lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
 734
 735         lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 736                 "lif_info", 0 /* queue_idx*/,
 737                 lif->info_sz, IONIC_ALIGN, socket_id);
 738         if (!lif->info_z) {
 739                 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
 740                 return -ENOMEM;
 741         }
 742
 743         lif->info = lif->info_z->addr;
 744         lif->info_pa = lif->info_z->iova;
 745
 746         return 0;
 747 }
 748
 749 void
 750 ionic_lif_free(struct ionic_lif *lif)
 751 {
 752         if (lif->notifyqcq) {
 753                 ionic_qcq_free(lif->notifyqcq);
 754                 lif->notifyqcq = NULL;
 755         }
 756
 757         if (lif->adminqcq) {
 758                 ionic_qcq_free(lif->adminqcq);
 759                 lif->adminqcq = NULL;
 760         }
 761
 762         if (lif->txqcqs) {
 763                 rte_free(lif->txqcqs);
 764                 lif->txqcqs = NULL;
 765         }
 766
 767         if (lif->rxqcqs) {
 768                 rte_free(lif->rxqcqs);
 769                 lif->rxqcqs = NULL;
 770         }
 771
 772         if (lif->info) {
 773                 rte_memzone_free(lif->info_z);
 774                 lif->info = NULL;
 775         }
 776 }
 777
 778 static void
 779 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 780 {
 781         struct ionic_dev *idev = &lif->adapter->idev;
 782
 783         if (!(qcq->flags & IONIC_QCQ_F_INITED))
 784                 return;
 785
 786         if (qcq->flags & IONIC_QCQ_F_INTR)
 787                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 788                         IONIC_INTR_MASK_SET);
 789
 790         qcq->flags &= ~IONIC_QCQ_F_INITED;
 791 }
 792
 793 void
 794 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
 795 {
 796         ionic_lif_qcq_deinit(qcq->lif, qcq);
 797 }
 798
 799 void
 800 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
 801 {
 802         ionic_lif_qcq_deinit(qcq->lif, qcq);
 803 }
 804
 805 bool
 806 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
 807                 void *cb_arg __rte_unused)
 808 {
 809         struct ionic_admin_comp *cq_desc_base = cq->base;
 810         struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
 811
 812         if (!color_match(cq_desc->color, cq->done_color))
 813                 return false;
 814
 815         ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
 816
 817         return true;
 818 }
 819
 820 /* This acts like ionic_napi */
 821 int
 822 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
 823                 void *cb_arg)
 824 {
 825         struct ionic_cq *cq = &qcq->cq;
 826         uint32_t work_done;
 827
 828         work_done = ionic_cq_service(cq, budget, cb, cb_arg);
 829
 830         return work_done;
 831 }
 832
 833 static void
 834 ionic_link_status_check(struct ionic_lif *lif)
 835 {
 836         struct ionic_adapter *adapter = lif->adapter;
 837         bool link_up;
 838
 839         lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
 840
 841         if (!lif->info)
 842                 return;
 843
 844         link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
 845
 846         if ((link_up  && adapter->link_up) ||
 847             (!link_up && !adapter->link_up))
 848                 return;
 849
 850         if (link_up) {
 851                 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
 852                         lif->info->status.link_speed);
 853                 adapter->link_speed = lif->info->status.link_speed;
 854         } else {
 855                 IONIC_PRINT(DEBUG, "Link down");
 856         }
 857
 858         adapter->link_up = link_up;
 859 }
 860
 861 static bool
 862 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
 863 {
 864         union ionic_notifyq_comp *cq_desc_base = cq->base;
 865         union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
 866         struct ionic_lif *lif = cb_arg;
 867
 868         IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
 869                 cq_desc->event.eid, cq_desc->event.ecode);
 870
 871         /* Have we run out of new completions to process? */
 872         if (!(cq_desc->event.eid > lif->last_eid))
 873                 return false;
 874
 875         lif->last_eid = cq_desc->event.eid;
 876
 877         switch (cq_desc->event.ecode) {
 878         case IONIC_EVENT_LINK_CHANGE:
 879                 IONIC_PRINT(DEBUG,
 880                         "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
 881                         cq_desc->event.eid,
 882                         cq_desc->link_change.link_status,
 883                         cq_desc->link_change.link_speed);
 884
 885                 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
 886
 887                 break;
 888         default:
 889                 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
 890                         cq_desc->event.ecode, cq_desc->event.eid);
 891                 break;
 892         }
 893
 894         return true;
 895 }
 896
 897 int
 898 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
 899 {
 900         struct ionic_dev *idev = &lif->adapter->idev;
 901         struct ionic_qcq *qcq = lif->notifyqcq;
 902         uint32_t work_done;
 903
 904         if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
 905                 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
 906                 return -1;
 907         }
 908
 909         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 910                 IONIC_INTR_MASK_SET);
 911
 912         work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
 913
 914         if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
 915                 ionic_link_status_check(lif);
 916
 917         ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
 918                 work_done, IONIC_INTR_CRED_RESET_COALESCE);
 919
 920         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 921                 IONIC_INTR_MASK_CLEAR);
 922
 923         return 0;
 924 }
 925
 926 static int
 927 ionic_lif_adminq_init(struct ionic_lif *lif)
 928 {
 929         struct ionic_dev *idev = &lif->adapter->idev;
 930         struct ionic_qcq *qcq = lif->adminqcq;
 931         struct ionic_queue *q = &qcq->q;
 932         struct ionic_q_init_comp comp;
 933         int err;
 934
 935         ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
 936         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 937         if (err)
 938                 return err;
 939
 940         ionic_dev_cmd_comp(idev, &comp);
 941
 942         q->hw_type = comp.hw_type;
 943         q->hw_index = comp.hw_index;
 944         q->db = ionic_db_map(lif, q);
 945
 946         IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
 947         IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
 948         IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
 949
 950         if (qcq->flags & IONIC_QCQ_F_INTR)
 951                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 952                         IONIC_INTR_MASK_CLEAR);
 953
 954         qcq->flags |= IONIC_QCQ_F_INITED;
 955
 956         return 0;
 957 }
 958
 959 static int
 960 ionic_lif_notifyq_init(struct ionic_lif *lif)
 961 {
 962         struct ionic_dev *idev = &lif->adapter->idev;
 963         struct ionic_qcq *qcq = lif->notifyqcq;
 964         struct ionic_queue *q = &qcq->q;
 965         int err;
 966
 967         struct ionic_admin_ctx ctx = {
 968                 .pending_work = true,
 969                 .cmd.q_init = {
 970                         .opcode = IONIC_CMD_Q_INIT,
 971                         .lif_index = lif->index,
 972                         .type = q->type,
 973                         .index = q->index,
 974                         .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
 975                         .intr_index = qcq->intr.index,
 976                         .pid = q->pid,
 977                         .ring_size = rte_log2_u32(q->num_descs),
 978                         .ring_base = q->base_pa,
 979                 }
 980         };
 981
 982         IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
 983         IONIC_PRINT(DEBUG, "notifyq_init.index %d",
 984                 ctx.cmd.q_init.index);
 985         IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
 986                 ctx.cmd.q_init.ring_base);
 987         IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
 988                 ctx.cmd.q_init.ring_size);
 989
 990         err = ionic_adminq_post_wait(lif, &ctx);
 991         if (err)
 992                 return err;
 993
 994         q->hw_type = ctx.comp.q_init.hw_type;
 995         q->hw_index = ctx.comp.q_init.hw_index;
 996         q->db = NULL;
 997
 998         IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
 999         IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1000         IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1001
1002         if (qcq->flags & IONIC_QCQ_F_INTR)
1003                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1004                         IONIC_INTR_MASK_CLEAR);
1005
1006         qcq->flags |= IONIC_QCQ_F_INITED;
1007
1008         return 0;
1009 }
1010
1011 int
1012 ionic_lif_set_features(struct ionic_lif *lif)
1013 {
1014         struct ionic_admin_ctx ctx = {
1015                 .pending_work = true,
1016                 .cmd.lif_setattr = {
1017                         .opcode = IONIC_CMD_LIF_SETATTR,
1018                         .index = lif->index,
1019                         .attr = IONIC_LIF_ATTR_FEATURES,
1020                         .features = lif->features,
1021                 },
1022         };
1023         int err;
1024
1025         err = ionic_adminq_post_wait(lif, &ctx);
1026         if (err)
1027                 return err;
1028
1029         lif->hw_features = (ctx.cmd.lif_setattr.features &
1030                 ctx.comp.lif_setattr.features);
1031
1032         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1033                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1034         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1035                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1036         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1037                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1038         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1039                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1040         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1041                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1042         if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1043                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1044         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1045                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1046         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1047                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1048         if (lif->hw_features & IONIC_ETH_HW_TSO)
1049                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1050         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1051                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1052         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1053                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1054         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1055                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1056         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1057                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1058         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1059                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1060         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1061                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1062         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1063                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1064         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1065                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1066
1067         return 0;
1068 }
1069
1070 int
1071 ionic_lif_txq_init(struct ionic_qcq *qcq)
1072 {
1073         struct ionic_queue *q = &qcq->q;
1074         struct ionic_lif *lif = qcq->lif;
1075         struct ionic_cq *cq = &qcq->cq;
1076         struct ionic_admin_ctx ctx = {
1077                 .pending_work = true,
1078                 .cmd.q_init = {
1079                         .opcode = IONIC_CMD_Q_INIT,
1080                         .lif_index = lif->index,
1081                         .type = q->type,
1082                         .index = q->index,
1083                         .flags = IONIC_QINIT_F_SG,
1084                         .intr_index = cq->bound_intr->index,
1085                         .pid = q->pid,
1086                         .ring_size = rte_log2_u32(q->num_descs),
1087                         .ring_base = q->base_pa,
1088                         .cq_ring_base = cq->base_pa,
1089                         .sg_ring_base = q->sg_base_pa,
1090                 },
1091         };
1092         int err;
1093
1094         IONIC_PRINT(DEBUG, "txq_init.pid %d", ctx.cmd.q_init.pid);
1095         IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1096         IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1097                 ctx.cmd.q_init.ring_base);
1098         IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1099                 ctx.cmd.q_init.ring_size);
1100
1101         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1102         if (err)
1103                 return err;
1104
1105         q->hw_type = ctx.comp.q_init.hw_type;
1106         q->hw_index = ctx.comp.q_init.hw_index;
1107         q->db = ionic_db_map(lif, q);
1108
1109         IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1110         IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1111         IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1112
1113         qcq->flags |= IONIC_QCQ_F_INITED;
1114
1115         return 0;
1116 }
1117
1118 int
1119 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1120 {
1121         struct ionic_queue *q = &qcq->q;
1122         struct ionic_lif *lif = qcq->lif;
1123         struct ionic_cq *cq = &qcq->cq;
1124         struct ionic_admin_ctx ctx = {
1125                 .pending_work = true,
1126                 .cmd.q_init = {
1127                         .opcode = IONIC_CMD_Q_INIT,
1128                         .lif_index = lif->index,
1129                         .type = q->type,
1130                         .index = q->index,
1131                         .flags = IONIC_QINIT_F_SG,
1132                         .intr_index = cq->bound_intr->index,
1133                         .pid = q->pid,
1134                         .ring_size = rte_log2_u32(q->num_descs),
1135                         .ring_base = q->base_pa,
1136                         .cq_ring_base = cq->base_pa,
1137                         .sg_ring_base = q->sg_base_pa,
1138                 },
1139         };
1140         int err;
1141
1142         IONIC_PRINT(DEBUG, "rxq_init.pid %d", ctx.cmd.q_init.pid);
1143         IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1144         IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1145                 ctx.cmd.q_init.ring_base);
1146         IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1147                 ctx.cmd.q_init.ring_size);
1148
1149         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1150         if (err)
1151                 return err;
1152
1153         q->hw_type = ctx.comp.q_init.hw_type;
1154         q->hw_index = ctx.comp.q_init.hw_index;
1155         q->db = ionic_db_map(lif, q);
1156
1157         qcq->flags |= IONIC_QCQ_F_INITED;
1158
1159         IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1160         IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1161         IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1162
1163         return 0;
1164 }
1165
1166 static int
1167 ionic_station_set(struct ionic_lif *lif)
1168 {
1169         struct ionic_admin_ctx ctx = {
1170                 .pending_work = true,
1171                 .cmd.lif_getattr = {
1172                         .opcode = IONIC_CMD_LIF_GETATTR,
1173                         .index = lif->index,
1174                         .attr = IONIC_LIF_ATTR_MAC,
1175                 },
1176         };
1177         int err;
1178
1179         IONIC_PRINT_CALL();
1180
1181         err = ionic_adminq_post_wait(lif, &ctx);
1182         if (err)
1183                 return err;
1184
1185         if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1186                         lif->mac_addr)) {
1187                 IONIC_PRINT(INFO, "deleting station MAC addr");
1188
1189                 ionic_lif_addr_del(lif, lif->mac_addr);
1190         }
1191
1192         memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1193
1194         if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1195                 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1196                 return 0;
1197         }
1198
1199         IONIC_PRINT(DEBUG, "adding station MAC addr");
1200
1201         ionic_lif_addr_add(lif, lif->mac_addr);
1202
1203         return 0;
1204 }
1205
1206 static void
1207 ionic_lif_set_name(struct ionic_lif *lif)
1208 {
1209         struct ionic_admin_ctx ctx = {
1210                 .pending_work = true,
1211                 .cmd.lif_setattr = {
1212                         .opcode = IONIC_CMD_LIF_SETATTR,
1213                         .index = lif->index,
1214                         .attr = IONIC_LIF_ATTR_NAME,
1215                 },
1216         };
1217
1218         snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
1219                 "%d", lif->port_id);
1220
1221         ionic_adminq_post_wait(lif, &ctx);
1222 }
1223
1224 int
1225 ionic_lif_init(struct ionic_lif *lif)
1226 {
1227         struct ionic_dev *idev = &lif->adapter->idev;
1228         struct ionic_q_init_comp comp;
1229         int err;
1230
1231         ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
1232         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1233         ionic_dev_cmd_comp(idev, &comp);
1234         if (err)
1235                 return err;
1236
1237         lif->hw_index = comp.hw_index;
1238
1239         err = ionic_lif_adminq_init(lif);
1240         if (err)
1241                 return err;
1242
1243         err = ionic_lif_notifyq_init(lif);
1244         if (err)
1245                 goto err_out_adminq_deinit;
1246
1247         lif->features =
1248                   IONIC_ETH_HW_VLAN_TX_TAG
1249                 | IONIC_ETH_HW_VLAN_RX_STRIP
1250                 | IONIC_ETH_HW_VLAN_RX_FILTER
1251                 | IONIC_ETH_HW_RX_HASH
1252                 | IONIC_ETH_HW_TX_SG
1253                 | IONIC_ETH_HW_RX_SG
1254                 | IONIC_ETH_HW_RX_CSUM
1255                 | IONIC_ETH_HW_TSO
1256                 | IONIC_ETH_HW_TSO_IPV6
1257                 | IONIC_ETH_HW_TSO_ECN;
1258
1259         err = ionic_lif_set_features(lif);
1260         if (err)
1261                 goto err_out_notifyq_deinit;
1262
1263         err = ionic_rx_filters_init(lif);
1264         if (err)
1265                 goto err_out_notifyq_deinit;
1266
1267         err = ionic_station_set(lif);
1268         if (err)
1269                 goto err_out_rx_filter_deinit;
1270
1271         ionic_lif_set_name(lif);
1272
1273         lif->state |= IONIC_LIF_F_INITED;
1274
1275         return 0;
1276
1277 err_out_rx_filter_deinit:
1278         ionic_rx_filters_deinit(lif);
1279
1280 err_out_notifyq_deinit:
1281         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1282
1283 err_out_adminq_deinit:
1284         ionic_lif_qcq_deinit(lif, lif->adminqcq);
1285
1286         return err;
1287 }
1288
1289 void
1290 ionic_lif_deinit(struct ionic_lif *lif)
1291 {
1292         if (!(lif->state & IONIC_LIF_F_INITED))
1293                 return;
1294
1295         ionic_rx_filters_deinit(lif);
1296         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1297         ionic_lif_qcq_deinit(lif, lif->adminqcq);
1298
1299         lif->state &= ~IONIC_LIF_F_INITED;
1300 }
1301
1302 int
1303 ionic_lif_configure(struct ionic_lif *lif)
1304 {
1305         lif->port_id = lif->eth_dev->data->port_id;
1306
1307         lif->nrxqcqs = 1;
1308         lif->ntxqcqs = 1;
1309
1310         return 0;
1311 }
1312
1313 int
1314 ionic_lif_start(struct ionic_lif *lif)
1315 {
1316         uint32_t rx_mode = 0;
1317         uint32_t i;
1318         int err;
1319
1320         IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
1321                 lif->port_id);
1322
1323         rx_mode |= IONIC_RX_MODE_F_UNICAST;
1324         rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1325         rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1326
1327         lif->rx_mode = 0; /* set by ionic_set_rx_mode */
1328
1329         ionic_set_rx_mode(lif, rx_mode);
1330
1331         IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1332                 "on port %u",
1333                 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1334
1335         for (i = 0; i < lif->nrxqcqs; i++) {
1336                 struct ionic_qcq *rxq = lif->rxqcqs[i];
1337                 if (!rxq->deferred_start) {
1338                         err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1339
1340                         if (err)
1341                                 return err;
1342                 }
1343         }
1344
1345         for (i = 0; i < lif->ntxqcqs; i++) {
1346                 struct ionic_qcq *txq = lif->txqcqs[i];
1347                 if (!txq->deferred_start) {
1348                         err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1349
1350                         if (err)
1351                                 return err;
1352                 }
1353         }
1354
1355         ionic_link_status_check(lif);
1356
1357         /* Carrier ON here */
1358
1359         return 0;
1360 }
1361
1362 int
1363 ionic_lif_identify(struct ionic_adapter *adapter)
1364 {
1365         struct ionic_dev *idev = &adapter->idev;
1366         struct ionic_identity *ident = &adapter->ident;
1367         int err;
1368         unsigned int i;
1369         unsigned int lif_words = sizeof(ident->lif.words) /
1370                 sizeof(ident->lif.words[0]);
1371         unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1372                 sizeof(idev->dev_cmd->data[0]);
1373         unsigned int nwords;
1374
1375         ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1376                 IONIC_IDENTITY_VERSION_1);
1377         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1378         if (err)
1379                 return (err);
1380
1381         nwords = RTE_MIN(lif_words, cmd_words);
1382         for (i = 0; i < nwords; i++)
1383                 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1384
1385         IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1386                 ident->lif.capabilities);
1387
1388         IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1389                 ident->lif.eth.max_ucast_filters);
1390         IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1391                 ident->lif.eth.max_mcast_filters);
1392
1393         IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1394                 ident->lif.eth.config.features);
1395         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1396                 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1397         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1398                 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1399         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1400                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1401         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1402                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1403
1404         return 0;
1405 }
1406
1407 int
1408 ionic_lifs_size(struct ionic_adapter *adapter)
1409 {
1410         struct ionic_identity *ident = &adapter->ident;
1411         uint32_t nlifs = ident->dev.nlifs;
1412         uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1413
1414         adapter->max_ntxqs_per_lif =
1415                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1416         adapter->max_nrxqs_per_lif =
1417                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1418
1419         nintrs = nlifs * 1 /* notifyq */;
1420
1421         if (nintrs > dev_nintrs) {
1422                 IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
1423                         dev_nintrs, nintrs);
1424                 return -ENOSPC;
1425         }
1426
1427         adapter->nintrs = nintrs;
1428
1429         return 0;
1430 }