drivers/net/ionic/ionic_lif.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_ethdev_driver.h>
   7
   8 #include "ionic.h"
   9 #include "ionic_logs.h"
  10 #include "ionic_lif.h"
  11 #include "ionic_ethdev.h"
  12
  13 int
  14 ionic_qcq_enable(struct ionic_qcq *qcq)
  15 {
  16         struct ionic_queue *q = &qcq->q;
  17         struct ionic_lif *lif = q->lif;
  18         struct ionic_dev *idev = &lif->adapter->idev;
  19         struct ionic_admin_ctx ctx = {
  20                 .pending_work = true,
  21                 .cmd.q_control = {
  22                         .opcode = IONIC_CMD_Q_CONTROL,
  23                         .lif_index = lif->index,
  24                         .type = q->type,
  25                         .index = q->index,
  26                         .oper = IONIC_Q_ENABLE,
  27                 },
  28         };
  29
  30         if (qcq->flags & IONIC_QCQ_F_INTR) {
  31                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
  32                         IONIC_INTR_MASK_CLEAR);
  33         }
  34
  35         return ionic_adminq_post_wait(lif, &ctx);
  36 }
  37
  38 int
  39 ionic_qcq_disable(struct ionic_qcq *qcq)
  40 {
  41         struct ionic_queue *q = &qcq->q;
  42         struct ionic_lif *lif = q->lif;
  43         struct ionic_dev *idev = &lif->adapter->idev;
  44         struct ionic_admin_ctx ctx = {
  45                 .pending_work = true,
  46                 .cmd.q_control = {
  47                         .opcode = IONIC_CMD_Q_CONTROL,
  48                         .lif_index = lif->index,
  49                         .type = q->type,
  50                         .index = q->index,
  51                         .oper = IONIC_Q_DISABLE,
  52                 },
  53         };
  54
  55         if (qcq->flags & IONIC_QCQ_F_INTR) {
  56                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
  57                         IONIC_INTR_MASK_SET);
  58         }
  59
  60         return ionic_adminq_post_wait(lif, &ctx);
  61 }
  62
  63 int
  64 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
  65 {
  66         struct ionic_adapter *adapter = lif->adapter;
  67         struct ionic_dev *idev = &adapter->idev;
  68         unsigned long index;
  69
  70         /*
  71          * Note: interrupt handler is called for index = 0 only
  72          * (we use interrupts for the notifyq only anyway,
  73          * which hash index = 0)
  74          */
  75
  76         for (index = 0; index < adapter->nintrs; index++)
  77                 if (!adapter->intrs[index])
  78                         break;
  79
  80         if (index == adapter->nintrs)
  81                 return -ENOSPC;
  82
  83         adapter->intrs[index] = true;
  84
  85         ionic_intr_init(idev, intr, index);
  86
  87         return 0;
  88 }
  89
  90 void
  91 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
  92 {
  93         if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
  94                 lif->adapter->intrs[intr->index] = false;
  95 }
  96
  97 static int
  98 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
  99                 uint32_t index,
 100                 const char *base, uint32_t flags,
 101                 uint32_t num_descs,
 102                 uint32_t desc_size,
 103                 uint32_t cq_desc_size,
 104                 uint32_t sg_desc_size,
 105                 uint32_t pid, struct ionic_qcq **qcq)
 106 {
 107         struct ionic_dev *idev = &lif->adapter->idev;
 108         struct ionic_qcq *new;
 109         uint32_t q_size, cq_size, sg_size, total_size;
 110         void *q_base, *cq_base, *sg_base;
 111         rte_iova_t q_base_pa = 0;
 112         rte_iova_t cq_base_pa = 0;
 113         rte_iova_t sg_base_pa = 0;
 114         uint32_t socket_id = rte_socket_id();
 115         int err;
 116
 117         *qcq = NULL;
 118
 119         q_size  = num_descs * desc_size;
 120         cq_size = num_descs * cq_desc_size;
 121         sg_size = num_descs * sg_desc_size;
 122
 123         total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
 124                 RTE_ALIGN(cq_size, PAGE_SIZE);
 125         /*
 126          * Note: aligning q_size/cq_size is not enough due to cq_base address
 127          * aligning as q_base could be not aligned to the page.
 128          * Adding PAGE_SIZE.
 129          */
 130         total_size += PAGE_SIZE;
 131
 132         if (flags & IONIC_QCQ_F_SG) {
 133                 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
 134                 total_size += PAGE_SIZE;
 135         }
 136
 137         new = rte_zmalloc("ionic", sizeof(*new), 0);
 138         if (!new) {
 139                 IONIC_PRINT(ERR, "Cannot allocate queue structure");
 140                 return -ENOMEM;
 141         }
 142
 143         new->lif = lif;
 144         new->flags = flags;
 145
 146         new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
 147         if (!new->q.info) {
 148                 IONIC_PRINT(ERR, "Cannot allocate queue info");
 149                 return -ENOMEM;
 150         }
 151
 152         new->q.type = type;
 153
 154         err = ionic_q_init(lif, idev, &new->q, index, num_descs,
 155                 desc_size, sg_desc_size, pid);
 156         if (err) {
 157                 IONIC_PRINT(ERR, "Queue initialization failed");
 158                 return err;
 159         }
 160
 161         if (flags & IONIC_QCQ_F_INTR) {
 162                 err = ionic_intr_alloc(lif, &new->intr);
 163                 if (err)
 164                         return err;
 165
 166                 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
 167                         IONIC_INTR_MASK_SET);
 168         } else {
 169                 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 170         }
 171
 172         err = ionic_cq_init(lif, &new->cq, &new->intr,
 173                 num_descs, cq_desc_size);
 174         if (err) {
 175                 IONIC_PRINT(ERR, "Completion queue initialization failed");
 176                 goto err_out_free_intr;
 177         }
 178
 179         new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 180                 base /* name */, index /* queue_idx */,
 181                 total_size, IONIC_ALIGN, socket_id);
 182
 183         if (!new->base_z) {
 184                 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
 185                 err = -ENOMEM;
 186                 goto err_out_free_intr;
 187         }
 188
 189         new->base = new->base_z->addr;
 190         new->base_pa = new->base_z->iova;
 191         new->total_size = total_size;
 192
 193         q_base = new->base;
 194         q_base_pa = new->base_pa;
 195
 196         cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
 197         cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
 198
 199         if (flags & IONIC_QCQ_F_SG) {
 200                 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
 201                         PAGE_SIZE);
 202                 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
 203                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 204         }
 205
 206         IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
 207                 "SG-base-PA = %ju",
 208                 q_base_pa, cq_base_pa, sg_base_pa);
 209
 210         ionic_q_map(&new->q, q_base, q_base_pa);
 211         ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 212         ionic_cq_bind(&new->cq, &new->q);
 213
 214         *qcq = new;
 215
 216         return 0;
 217
 218 err_out_free_intr:
 219         if (flags & IONIC_QCQ_F_INTR)
 220                 ionic_intr_free(lif, &new->intr);
 221
 222         return err;
 223 }
 224
 225 void
 226 ionic_qcq_free(struct ionic_qcq *qcq)
 227 {
 228         if (qcq->base_z) {
 229                 qcq->base = NULL;
 230                 qcq->base_pa = 0;
 231                 rte_memzone_free(qcq->base_z);
 232                 qcq->base_z = NULL;
 233         }
 234
 235         if (qcq->q.info) {
 236                 rte_free(qcq->q.info);
 237                 qcq->q.info = NULL;
 238         }
 239
 240         rte_free(qcq);
 241 }
 242
 243 static int
 244 ionic_admin_qcq_alloc(struct ionic_lif *lif)
 245 {
 246         uint32_t flags;
 247         int err = -ENOMEM;
 248
 249         flags = 0;
 250         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 251                 IONIC_ADMINQ_LENGTH,
 252                 sizeof(struct ionic_admin_cmd),
 253                 sizeof(struct ionic_admin_comp),
 254                 0,
 255                 lif->kern_pid, &lif->adminqcq);
 256
 257         if (err)
 258                 return err;
 259
 260         return 0;
 261 }
 262
 263 static void *
 264 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
 265 {
 266         char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
 267
 268         if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
 269                 return NULL;
 270
 271         return (void *)&vaddr[page_num << PAGE_SHIFT];
 272 }
 273
 274 int
 275 ionic_lif_alloc(struct ionic_lif *lif)
 276 {
 277         struct ionic_adapter *adapter = lif->adapter;
 278         uint32_t socket_id = rte_socket_id();
 279         int dbpage_num;
 280         int err;
 281
 282         snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
 283
 284         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 285
 286         rte_spinlock_init(&lif->adminq_lock);
 287         rte_spinlock_init(&lif->adminq_service_lock);
 288
 289         lif->kern_pid = 0;
 290
 291         dbpage_num = ionic_db_page_num(lif, 0);
 292
 293         lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
 294         if (!lif->kern_dbpage) {
 295                 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
 296                 return -ENOMEM;
 297         }
 298
 299         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 300
 301         err = ionic_admin_qcq_alloc(lif);
 302         if (err) {
 303                 IONIC_PRINT(ERR, "Cannot allocate admin queue");
 304                 return err;
 305         }
 306
 307         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 308
 309         lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
 310
 311         lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 312                 "lif_info", 0 /* queue_idx*/,
 313                 lif->info_sz, IONIC_ALIGN, socket_id);
 314         if (!lif->info_z) {
 315                 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
 316                 return -ENOMEM;
 317         }
 318
 319         lif->info = lif->info_z->addr;
 320         lif->info_pa = lif->info_z->iova;
 321
 322         return 0;
 323 }
 324
 325 void
 326 ionic_lif_free(struct ionic_lif *lif)
 327 {
 328         if (lif->adminqcq) {
 329                 ionic_qcq_free(lif->adminqcq);
 330                 lif->adminqcq = NULL;
 331         }
 332
 333         if (lif->info) {
 334                 rte_memzone_free(lif->info_z);
 335                 lif->info = NULL;
 336         }
 337 }
 338
 339 static void
 340 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 341 {
 342         struct ionic_dev *idev = &lif->adapter->idev;
 343
 344         if (!(qcq->flags & IONIC_QCQ_F_INITED))
 345                 return;
 346
 347         if (qcq->flags & IONIC_QCQ_F_INTR)
 348                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 349                         IONIC_INTR_MASK_SET);
 350
 351         qcq->flags &= ~IONIC_QCQ_F_INITED;
 352 }
 353
 354 bool
 355 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
 356                 void *cb_arg __rte_unused)
 357 {
 358         struct ionic_admin_comp *cq_desc_base = cq->base;
 359         struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
 360
 361         if (!color_match(cq_desc->color, cq->done_color))
 362                 return false;
 363
 364         ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
 365
 366         return true;
 367 }
 368
 369 /* This acts like ionic_napi */
 370 int
 371 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
 372                 void *cb_arg)
 373 {
 374         struct ionic_cq *cq = &qcq->cq;
 375         uint32_t work_done;
 376
 377         work_done = ionic_cq_service(cq, budget, cb, cb_arg);
 378
 379         return work_done;
 380 }
 381
 382 static int
 383 ionic_lif_adminq_init(struct ionic_lif *lif)
 384 {
 385         struct ionic_dev *idev = &lif->adapter->idev;
 386         struct ionic_qcq *qcq = lif->adminqcq;
 387         struct ionic_queue *q = &qcq->q;
 388         struct ionic_q_init_comp comp;
 389         int err;
 390
 391         ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
 392         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 393         if (err)
 394                 return err;
 395
 396         ionic_dev_cmd_comp(idev, &comp);
 397
 398         q->hw_type = comp.hw_type;
 399         q->hw_index = comp.hw_index;
 400         q->db = ionic_db_map(lif, q);
 401
 402         IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
 403         IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
 404         IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
 405
 406         if (qcq->flags & IONIC_QCQ_F_INTR)
 407                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 408                         IONIC_INTR_MASK_CLEAR);
 409
 410         qcq->flags |= IONIC_QCQ_F_INITED;
 411
 412         return 0;
 413 }
 414
 415 int
 416 ionic_lif_init(struct ionic_lif *lif)
 417 {
 418         struct ionic_dev *idev = &lif->adapter->idev;
 419         struct ionic_q_init_comp comp;
 420         int err;
 421
 422         ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
 423         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 424         ionic_dev_cmd_comp(idev, &comp);
 425         if (err)
 426                 return err;
 427
 428         lif->hw_index = comp.hw_index;
 429
 430         err = ionic_lif_adminq_init(lif);
 431         if (err)
 432                 return err;
 433
 434         lif->state |= IONIC_LIF_F_INITED;
 435
 436         return 0;
 437 }
 438
 439 void
 440 ionic_lif_deinit(struct ionic_lif *lif)
 441 {
 442         if (!(lif->state & IONIC_LIF_F_INITED))
 443                 return;
 444
 445         ionic_lif_qcq_deinit(lif, lif->adminqcq);
 446
 447         lif->state &= ~IONIC_LIF_F_INITED;
 448 }
 449
 450 int
 451 ionic_lif_identify(struct ionic_adapter *adapter)
 452 {
 453         struct ionic_dev *idev = &adapter->idev;
 454         struct ionic_identity *ident = &adapter->ident;
 455         int err;
 456         unsigned int i;
 457         unsigned int lif_words = sizeof(ident->lif.words) /
 458                 sizeof(ident->lif.words[0]);
 459         unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
 460                 sizeof(idev->dev_cmd->data[0]);
 461         unsigned int nwords;
 462
 463         ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
 464                 IONIC_IDENTITY_VERSION_1);
 465         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 466         if (err)
 467                 return (err);
 468
 469         nwords = RTE_MIN(lif_words, cmd_words);
 470         for (i = 0; i < nwords; i++)
 471                 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
 472
 473         IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
 474                 ident->lif.capabilities);
 475
 476         IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
 477                 ident->lif.eth.max_ucast_filters);
 478         IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
 479                 ident->lif.eth.max_mcast_filters);
 480
 481         IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
 482                 ident->lif.eth.config.features);
 483         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
 484                 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
 485         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
 486                 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
 487         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
 488                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
 489         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
 490                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
 491
 492         return 0;
 493 }
 494
 495 int
 496 ionic_lifs_size(struct ionic_adapter *adapter)
 497 {
 498         struct ionic_identity *ident = &adapter->ident;
 499         uint32_t nlifs = ident->dev.nlifs;
 500         uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
 501
 502         adapter->max_ntxqs_per_lif =
 503                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
 504         adapter->max_nrxqs_per_lif =
 505                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
 506
 507         nintrs = nlifs * 1 /* notifyq */;
 508
 509         if (nintrs > dev_nintrs) {
 510                 IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
 511                         dev_nintrs, nintrs);
 512                 return -ENOSPC;
 513         }
 514
 515         adapter->nintrs = nintrs;
 516
 517         return 0;
 518 }