1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
5 #ifndef _IPN3KE_ETHDEV_H_
6 #define _IPN3KE_ETHDEV_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 #include <rte_flow_driver.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_ethdev_vdev.h>
20 #include <rte_malloc.h>
21 #include <rte_memcpy.h>
22 #include <rte_bus_vdev.h>
23 #include <rte_kvargs.h>
24 #include <rte_spinlock.h>
26 #include <rte_cycles.h>
27 #include <rte_bus_ifpga.h>
28 #include <rte_tm_driver.h>
30 #define IPN3KE_TM_SCRATCH_RW 0
33 enum ipn3ke_tm_node_level {
34 IPN3KE_TM_NODE_LEVEL_PORT,
35 IPN3KE_TM_NODE_LEVEL_VT,
36 IPN3KE_TM_NODE_LEVEL_COS,
37 IPN3KE_TM_NODE_LEVEL_MAX,
40 /* TM Shaper Profile */
41 struct ipn3ke_tm_shaper_profile {
46 struct rte_tm_shaper_params params;
49 TAILQ_HEAD(ipn3ke_tm_shaper_profile_list, ipn3ke_tm_shaper_profile);
52 #define IPN3KE_TDROP_TH1_MASK 0x1ffffff
53 #define IPN3KE_TDROP_TH1_SHIFT (25)
54 #define IPN3KE_TDROP_TH2_MASK 0x1ffffff
56 /* TM TDROP Profile */
57 struct ipn3ke_tm_tdrop_profile {
58 uint32_t tdrop_profile_id;
63 struct rte_tm_wred_params params;
66 /* TM node priority */
67 enum ipn3ke_tm_node_state {
68 IPN3KE_TM_NODE_STATE_IDLE = 0,
69 IPN3KE_TM_NODE_STATE_CONFIGURED_ADD,
70 IPN3KE_TM_NODE_STATE_CONFIGURED_DEL,
71 IPN3KE_TM_NODE_STATE_COMMITTED,
72 IPN3KE_TM_NODE_STATE_MAX,
75 TAILQ_HEAD(ipn3ke_tm_node_list, ipn3ke_tm_node);
78 struct ipn3ke_tm_node {
79 TAILQ_ENTRY(ipn3ke_tm_node) node;
83 enum ipn3ke_tm_node_state node_state;
84 uint32_t parent_node_id;
87 struct ipn3ke_tm_node *parent_node;
88 struct ipn3ke_tm_shaper_profile shaper_profile;
89 struct ipn3ke_tm_tdrop_profile *tdrop_profile;
90 struct rte_tm_node_params params;
91 struct rte_tm_node_stats stats;
93 struct ipn3ke_tm_node_list children_node_list;
96 /* IPN3KE TM Hierarchy Specification */
97 struct ipn3ke_tm_hierarchy {
98 struct ipn3ke_tm_node *port_node;
99 /*struct ipn3ke_tm_node_list vt_node_list;*/
100 /*struct ipn3ke_tm_node_list cos_node_list;*/
102 uint32_t n_shaper_profiles;
103 /*uint32_t n_shared_shapers;*/
104 uint32_t n_tdrop_profiles;
106 uint32_t n_cos_nodes;
108 struct ipn3ke_tm_node *port_commit_node;
109 struct ipn3ke_tm_node_list vt_commit_node_list;
110 struct ipn3ke_tm_node_list cos_commit_node_list;
112 /*uint32_t n_tm_nodes[IPN3KE_TM_NODE_LEVEL_MAX];*/
115 struct ipn3ke_tm_internals {
116 /** Hierarchy specification
118 * -Hierarchy is unfrozen at init and when port is stopped.
119 * -Hierarchy is frozen on successful hierarchy commit.
120 * -Run-time hierarchy changes are not allowed, therefore it makes
121 * sense to keep the hierarchy frozen after the port is started.
123 struct ipn3ke_tm_hierarchy h;
124 int hierarchy_frozen;
129 #define IPN3KE_TM_COS_NODE_NUM (64 * 1024)
130 #define IPN3KE_TM_VT_NODE_NUM (IPN3KE_TM_COS_NODE_NUM / 8)
131 #define IPN3KE_TM_10G_PORT_NODE_NUM (8)
132 #define IPN3KE_TM_25G_PORT_NODE_NUM (4)
134 #define IPN3KE_TM_NODE_LEVEL_MOD (100000)
135 #define IPN3KE_TM_NODE_MOUNT_MAX (8)
137 #define IPN3KE_TM_TDROP_PROFILE_NUM (2 * 1024)
139 /* TM node priority */
140 enum ipn3ke_tm_node_priority {
141 IPN3KE_TM_NODE_PRIORITY_NORMAL0 = 0,
142 IPN3KE_TM_NODE_PRIORITY_LOW,
143 IPN3KE_TM_NODE_PRIORITY_NORMAL1,
144 IPN3KE_TM_NODE_PRIORITY_HIGHEST,
147 #define IPN3KE_TM_NODE_WEIGHT_MAX UINT8_MAX
149 /** Set a bit in the uint32 variable */
150 #define IPN3KE_BIT_SET(var, pos) \
151 ((var) |= ((uint32_t)1 << ((pos))))
153 /** Reset the bit in the variable */
154 #define IPN3KE_BIT_RESET(var, pos) \
155 ((var) &= ~((uint32_t)1 << ((pos))))
157 /** Check the bit is set in the variable */
158 #define IPN3KE_BIT_ISSET(var, pos) \
159 (((var) & ((uint32_t)1 << ((pos)))) ? 1 : 0)
163 #define IPN3KE_HW_BASE 0x4000000
165 #define IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET \
166 (IPN3KE_HW_BASE + hw->hw_cap.capability_registers_block_offset)
168 #define IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET \
169 (IPN3KE_HW_BASE + hw->hw_cap.status_registers_block_offset)
171 #define IPN3KE_CTRL_RESET \
172 (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset)
174 #define IPN3KE_CTRL_MTU \
175 (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset + 4)
177 #define IPN3KE_CLASSIFY_OFFSET \
178 (IPN3KE_HW_BASE + hw->hw_cap.classify_offset)
180 #define IPN3KE_POLICER_OFFSET \
181 (IPN3KE_HW_BASE + hw->hw_cap.policer_offset)
183 #define IPN3KE_RSS_KEY_ARRAY_OFFSET \
184 (IPN3KE_HW_BASE + hw->hw_cap.rss_key_array_offset)
186 #define IPN3KE_RSS_INDIRECTION_TABLE_ARRAY_OFFSET \
187 (IPN3KE_HW_BASE + hw->hw_cap.rss_indirection_table_array_offset)
189 #define IPN3KE_DMAC_MAP_OFFSET \
190 (IPN3KE_HW_BASE + hw->hw_cap.dmac_map_offset)
192 #define IPN3KE_QM_OFFSET \
193 (IPN3KE_HW_BASE + hw->hw_cap.qm_offset)
195 #define IPN3KE_CCB_OFFSET \
196 (IPN3KE_HW_BASE + hw->hw_cap.ccb_offset)
198 #define IPN3KE_QOS_OFFSET \
199 (IPN3KE_HW_BASE + hw->hw_cap.qos_offset)
201 struct ipn3ke_hw_cap {
202 uint32_t version_number;
203 uint32_t capability_registers_block_offset;
204 uint32_t status_registers_block_offset;
205 uint32_t control_registers_block_offset;
206 uint32_t classify_offset;
207 uint32_t classy_size;
208 uint32_t policer_offset;
209 uint32_t policer_entry_size;
210 uint32_t rss_key_array_offset;
211 uint32_t rss_key_entry_size;
212 uint32_t rss_indirection_table_array_offset;
213 uint32_t rss_indirection_table_entry_size;
214 uint32_t dmac_map_offset;
215 uint32_t dmac_map_size;
219 uint32_t ccb_entry_size;
223 uint32_t num_rx_flow; /* Default: 64K */
224 uint32_t num_rss_blocks; /* Default: 512 */
225 uint32_t num_dmac_map; /* Default: 1K */
226 uint32_t num_tx_flow; /* Default: 64K */
227 uint32_t num_smac_map; /* Default: 1K */
229 uint32_t link_speed_mbps;
233 * Strucute to store private data for each representor instance
236 TAILQ_ENTRY(ipn3ke_rpst) next; /**< Next in device list. */
237 uint16_t switch_domain_id;
240 struct rte_eth_dev *ethdev;
242 struct ipn3ke_hw *hw;
243 struct rte_eth_dev *i40e_pf_eth;
244 uint16_t i40e_pf_eth_port_id;
245 struct rte_eth_link ori_linfo;
246 struct ipn3ke_tm_internals tm;
247 /**< Private data store of assocaiated physical function */
248 struct ether_addr mac_addr;
252 #define MAP_UUID_10G_LOW 0xffffffffffffffff
253 #define MAP_UUID_10G_HIGH 0xffffffffffffffff
254 #define IPN3KE_UUID_10G_LOW 0xc000c9660d824272
255 #define IPN3KE_UUID_10G_HIGH 0x9aeffe5f84570612
256 #define IPN3KE_UUID_VBNG_LOW 0x8991165349d23ff9
257 #define IPN3KE_UUID_VBNG_HIGH 0xb74cf419d15a481f
258 #define IPN3KE_UUID_25G_LOW 0xb7d9bac566bfbc80
259 #define IPN3KE_UUID_25G_HIGH 0xb07bac1aeef54d67
261 #define IPN3KE_AFU_BUF_SIZE_MIN 1024
262 #define IPN3KE_AFU_FRAME_SIZE_MAX 9728
264 #define IPN3KE_RAWDEV_ATTR_LEN_MAX (64)
266 typedef int (*ipn3ke_indirect_mac_read_t)(struct ipn3ke_hw *hw,
267 uint32_t *rd_data, uint32_t addr, uint32_t mac_num,
268 uint32_t eth_wrapper_sel);
270 typedef int (*ipn3ke_indirect_mac_write_t)(struct ipn3ke_hw *hw,
271 uint32_t wr_data, uint32_t addr, uint32_t mac_num,
272 uint32_t eth_wrapper_sel);
275 struct rte_eth_dev *eth_dev;
278 struct rte_afu_id afu_id;
279 struct rte_rawdev *rawdev;
281 struct ipn3ke_hw_cap hw_cap;
283 struct ifpga_rawdevg_retimer_info retimer;
285 uint16_t switch_domain_id;
288 uint32_t tm_hw_enable;
289 uint32_t flow_hw_enable;
294 uint32_t flow_max_entries;
295 uint32_t flow_num_entries;
297 struct ipn3ke_tm_node *nodes;
298 struct ipn3ke_tm_node *port_nodes;
299 struct ipn3ke_tm_node *vt_nodes;
300 struct ipn3ke_tm_node *cos_nodes;
302 struct ipn3ke_tm_tdrop_profile *tdrop_profile;
303 uint32_t tdrop_profile_num;
306 uint32_t ccb_seg_free;
307 uint32_t ccb_seg_num;
310 uint8_t *eth_group_bar[2];
311 /**< MAC Register read */
312 ipn3ke_indirect_mac_read_t f_mac_read;
313 /**< MAC Register write */
314 ipn3ke_indirect_mac_write_t f_mac_write;
321 * Helper macro for drivers that need to convert to struct rte_afu_device.
323 #define RTE_DEV_TO_AFU(ptr) \
324 container_of(ptr, struct rte_afu_device, device)
326 #define RTE_DEV_TO_AFU_CONST(ptr) \
327 container_of(ptr, const struct rte_afu_device, device)
329 #define RTE_ETH_DEV_TO_AFU(eth_dev) \
330 RTE_DEV_TO_AFU((eth_dev)->device)
336 #define IPN3KE_PCI_REG(reg) rte_read32(reg)
337 #define IPN3KE_PCI_REG_ADDR(a, reg) \
338 ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
339 static inline uint32_t ipn3ke_read_addr(volatile void *addr)
341 return rte_le_to_cpu_32(IPN3KE_PCI_REG(addr));
344 #define WCMD 0x8000000000000000
345 #define RCMD 0x4000000000000000
346 #define UPL_BASE 0x10000
347 static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,
350 uint64_t word_offset;
351 uint64_t read_data = 0;
352 uint64_t indirect_value;
353 volatile void *indirect_addrs;
355 word_offset = (addr & 0x1FFFFFF) >> 2;
356 indirect_value = RCMD | word_offset << 32;
357 indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10);
361 rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
363 indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x18);
364 while ((read_data >> 32) != 1)
365 read_data = rte_read64(indirect_addrs);
367 return rte_le_to_cpu_32(read_data);
370 static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,
371 uint32_t addr, uint32_t value)
373 uint64_t word_offset;
374 uint64_t indirect_value;
375 volatile void *indirect_addrs = 0;
377 word_offset = (addr & 0x1FFFFFF) >> 2;
378 indirect_value = WCMD | word_offset << 32 | value;
379 indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10);
381 rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
385 #define IPN3KE_PCI_REG_WRITE(reg, value) \
386 rte_write32((rte_cpu_to_le_32(value)), reg)
388 #define IPN3KE_PCI_REG_WRITE_RELAXED(reg, value) \
389 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
391 #define IPN3KE_READ_REG(hw, reg) \
392 _ipn3ke_indrct_read((hw), (reg))
394 #define IPN3KE_WRITE_REG(hw, reg, value) \
395 _ipn3ke_indrct_write((hw), (reg), (value))
397 #define IPN3KE_MASK_READ_REG(hw, reg, x, mask) \
398 ((mask) & IPN3KE_READ_REG((hw), ((reg) + (0x4 * (x)))))
400 #define IPN3KE_MASK_WRITE_REG(hw, reg, x, value, mask) \
401 IPN3KE_WRITE_REG((hw), ((reg) + (0x4 * (x))), ((mask) & (value)))
403 #define IPN3KE_DEV_PRIVATE_TO_HW(dev) \
404 (((struct ipn3ke_rpst *)(dev)->data->dev_private)->hw)
406 #define IPN3KE_DEV_PRIVATE_TO_RPST(dev) \
407 ((struct ipn3ke_rpst *)(dev)->data->dev_private)
409 #define IPN3KE_DEV_PRIVATE_TO_TM(dev) \
410 (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm))
412 /* Byte address of IPN3KE internal module */
413 #define IPN3KE_TM_VERSION (IPN3KE_QM_OFFSET + 0x0000)
414 #define IPN3KE_TM_SCRATCH (IPN3KE_QM_OFFSET + 0x0004)
415 #define IPN3KE_TM_STATUS (IPN3KE_QM_OFFSET + 0x0008)
416 #define IPN3KE_TM_MISC_STATUS (IPN3KE_QM_OFFSET + 0x0010)
417 #define IPN3KE_TM_MISC_WARNING_0 (IPN3KE_QM_OFFSET + 0x0040)
418 #define IPN3KE_TM_MISC_MON_0 (IPN3KE_QM_OFFSET + 0x0048)
419 #define IPN3KE_TM_MISC_FATAL_0 (IPN3KE_QM_OFFSET + 0x0050)
420 #define IPN3KE_TM_BW_MON_CTRL_1 (IPN3KE_QM_OFFSET + 0x0080)
421 #define IPN3KE_TM_BW_MON_CTRL_2 (IPN3KE_QM_OFFSET + 0x0084)
422 #define IPN3KE_TM_BW_MON_RATE (IPN3KE_QM_OFFSET + 0x0088)
423 #define IPN3KE_TM_STATS_CTRL (IPN3KE_QM_OFFSET + 0x0100)
424 #define IPN3KE_TM_STATS_DATA_0 (IPN3KE_QM_OFFSET + 0x0110)
425 #define IPN3KE_TM_STATS_DATA_1 (IPN3KE_QM_OFFSET + 0x0114)
426 #define IPN3KE_QM_UID_CONFIG_CTRL (IPN3KE_QM_OFFSET + 0x0200)
427 #define IPN3KE_QM_UID_CONFIG_DATA (IPN3KE_QM_OFFSET + 0x0204)
429 #define IPN3KE_BM_VERSION (IPN3KE_QM_OFFSET + 0x4000)
430 #define IPN3KE_BM_STATUS (IPN3KE_QM_OFFSET + 0x4008)
431 #define IPN3KE_BM_STORE_CTRL (IPN3KE_QM_OFFSET + 0x4010)
432 #define IPN3KE_BM_STORE_STATUS (IPN3KE_QM_OFFSET + 0x4018)
433 #define IPN3KE_BM_STORE_MON (IPN3KE_QM_OFFSET + 0x4028)
434 #define IPN3KE_BM_WARNING_0 (IPN3KE_QM_OFFSET + 0x4040)
435 #define IPN3KE_BM_MON_0 (IPN3KE_QM_OFFSET + 0x4048)
436 #define IPN3KE_BM_FATAL_0 (IPN3KE_QM_OFFSET + 0x4050)
437 #define IPN3KE_BM_DRAM_ACCESS_CTRL (IPN3KE_QM_OFFSET + 0x4100)
438 #define IPN3KE_BM_DRAM_ACCESS_DATA_0 (IPN3KE_QM_OFFSET + 0x4120)
439 #define IPN3KE_BM_DRAM_ACCESS_DATA_1 (IPN3KE_QM_OFFSET + 0x4124)
440 #define IPN3KE_BM_DRAM_ACCESS_DATA_2 (IPN3KE_QM_OFFSET + 0x4128)
441 #define IPN3KE_BM_DRAM_ACCESS_DATA_3 (IPN3KE_QM_OFFSET + 0x412C)
442 #define IPN3KE_BM_DRAM_ACCESS_DATA_4 (IPN3KE_QM_OFFSET + 0x4130)
443 #define IPN3KE_BM_DRAM_ACCESS_DATA_5 (IPN3KE_QM_OFFSET + 0x4134)
444 #define IPN3KE_BM_DRAM_ACCESS_DATA_6 (IPN3KE_QM_OFFSET + 0x4138)
446 #define IPN3KE_QM_VERSION (IPN3KE_QM_OFFSET + 0x8000)
447 #define IPN3KE_QM_STATUS (IPN3KE_QM_OFFSET + 0x8008)
448 #define IPN3KE_QM_LL_TABLE_MON (IPN3KE_QM_OFFSET + 0x8018)
449 #define IPN3KE_QM_WARNING_0 (IPN3KE_QM_OFFSET + 0x8040)
450 #define IPN3KE_QM_MON_0 (IPN3KE_QM_OFFSET + 0x8048)
451 #define IPN3KE_QM_FATAL_0 (IPN3KE_QM_OFFSET + 0x8050)
452 #define IPN3KE_QM_FATAL_1 (IPN3KE_QM_OFFSET + 0x8054)
453 #define IPN3KE_LL_TABLE_ACCESS_CTRL (IPN3KE_QM_OFFSET + 0x8100)
454 #define IPN3KE_LL_TABLE_ACCESS_DATA_0 (IPN3KE_QM_OFFSET + 0x8110)
455 #define IPN3KE_LL_TABLE_ACCESS_DATA_1 (IPN3KE_QM_OFFSET + 0x8114)
457 #define IPN3KE_CCB_ERROR (IPN3KE_CCB_OFFSET + 0x0008)
458 #define IPN3KE_CCB_NSEGFREE (IPN3KE_CCB_OFFSET + 0x200000)
459 #define IPN3KE_CCB_NSEGFREE_MASK 0x3FFFFF
460 #define IPN3KE_CCB_PSEGMAX_COEF (IPN3KE_CCB_OFFSET + 0x200008)
461 #define IPN3KE_CCB_PSEGMAX_COEF_MASK 0xFFFFF
462 #define IPN3KE_CCB_NSEG_P (IPN3KE_CCB_OFFSET + 0x200080)
463 #define IPN3KE_CCB_NSEG_MASK 0x3FFFFF
464 #define IPN3KE_CCB_QPROFILE_Q (IPN3KE_CCB_OFFSET + 0x240000)
465 #define IPN3KE_CCB_QPROFILE_MASK 0x7FF
466 #define IPN3KE_CCB_PROFILE_P (IPN3KE_CCB_OFFSET + 0x280000)
467 #define IPN3KE_CCB_PROFILE_MASK 0x1FFFFFF
468 #define IPN3KE_CCB_PROFILE_MS (IPN3KE_CCB_OFFSET + 0xC)
469 #define IPN3KE_CCB_PROFILE_MS_MASK 0x1FFFFFF
470 #define IPN3KE_CCB_LR_LB_DBG_CTRL (IPN3KE_CCB_OFFSET + 0x2C0000)
471 #define IPN3KE_CCB_LR_LB_DBG_DONE (IPN3KE_CCB_OFFSET + 0x2C0004)
472 #define IPN3KE_CCB_LR_LB_DBG_RDATA (IPN3KE_CCB_OFFSET + 0x2C000C)
474 #define IPN3KE_QOS_MAP_L1_X (IPN3KE_QOS_OFFSET + 0x000000)
475 #define IPN3KE_QOS_MAP_L1_MASK 0x1FFF
476 #define IPN3KE_QOS_MAP_L2_X (IPN3KE_QOS_OFFSET + 0x040000)
477 #define IPN3KE_QOS_MAP_L2_MASK 0x7
478 #define IPN3KE_QOS_TYPE_MASK 0x3
479 #define IPN3KE_QOS_TYPE_L1_X (IPN3KE_QOS_OFFSET + 0x200000)
480 #define IPN3KE_QOS_TYPE_L2_X (IPN3KE_QOS_OFFSET + 0x240000)
481 #define IPN3KE_QOS_TYPE_L3_X (IPN3KE_QOS_OFFSET + 0x280000)
482 #define IPN3KE_QOS_SCH_WT_MASK 0xFF
483 #define IPN3KE_QOS_SCH_WT_L1_X (IPN3KE_QOS_OFFSET + 0x400000)
484 #define IPN3KE_QOS_SCH_WT_L2_X (IPN3KE_QOS_OFFSET + 0x440000)
485 #define IPN3KE_QOS_SCH_WT_L3_X (IPN3KE_QOS_OFFSET + 0x480000)
486 #define IPN3KE_QOS_SHAP_WT_MASK 0x3FFF
487 #define IPN3KE_QOS_SHAP_WT_L1_X (IPN3KE_QOS_OFFSET + 0x600000)
488 #define IPN3KE_QOS_SHAP_WT_L2_X (IPN3KE_QOS_OFFSET + 0x640000)
489 #define IPN3KE_QOS_SHAP_WT_L3_X (IPN3KE_QOS_OFFSET + 0x680000)
491 #define IPN3KE_CLF_BASE_DST_MAC_ADDR_HI (IPN3KE_CLASSIFY_OFFSET + 0x0000)
492 #define IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW (IPN3KE_CLASSIFY_OFFSET + 0x0004)
493 #define IPN3KE_CLF_QINQ_STAG (IPN3KE_CLASSIFY_OFFSET + 0x0008)
494 #define IPN3KE_CLF_LKUP_ENABLE (IPN3KE_CLASSIFY_OFFSET + 0x000C)
495 #define IPN3KE_CLF_DFT_FLOW_ID (IPN3KE_CLASSIFY_OFFSET + 0x0040)
496 #define IPN3KE_CLF_RX_PARSE_CFG (IPN3KE_CLASSIFY_OFFSET + 0x0080)
497 #define IPN3KE_CLF_RX_STATS_CFG (IPN3KE_CLASSIFY_OFFSET + 0x00C0)
498 #define IPN3KE_CLF_RX_STATS_RPT (IPN3KE_CLASSIFY_OFFSET + 0x00C4)
499 #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + 0x0400)
501 #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000)
502 #define IPN3KE_CLF_EM_NUM (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0008)
503 #define IPN3KE_CLF_EM_KEY_WDTH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x000C)
504 #define IPN3KE_CLF_EM_RES_WDTH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0010)
505 #define IPN3KE_CLF_EM_ALARMS (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0014)
506 #define IPN3KE_CLF_EM_DRC_RLAT (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0018)
508 #define IPN3KE_CLF_MHL_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0000)
509 #define IPN3KE_CLF_MHL_GEN_CTRL (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0018)
510 #define IPN3KE_CLF_MHL_MGMT_CTRL (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0020)
511 #define IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY 31
512 #define IPN3KE_CLF_MHL_MGMT_CTRL_FLUSH 0x0
513 #define IPN3KE_CLF_MHL_MGMT_CTRL_INSERT 0x1
514 #define IPN3KE_CLF_MHL_MGMT_CTRL_DELETE 0x2
515 #define IPN3KE_CLF_MHL_MGMT_CTRL_SEARCH 0x3
516 #define IPN3KE_CLF_MHL_FATAL_0 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0050)
517 #define IPN3KE_CLF_MHL_MON_0 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0060)
518 #define IPN3KE_CLF_MHL_TOTAL_ENTRIES (IPN3KE_CLASSIFY_OFFSET + \
520 #define IPN3KE_CLF_MHL_ONEHIT_BUCKETS (IPN3KE_CLASSIFY_OFFSET + \
522 #define IPN3KE_CLF_MHL_KEY_MASK 0xFFFFFFFF
523 #define IPN3KE_CLF_MHL_KEY_0 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1000)
524 #define IPN3KE_CLF_MHL_KEY_1 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1004)
525 #define IPN3KE_CLF_MHL_KEY_2 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1008)
526 #define IPN3KE_CLF_MHL_KEY_3 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x100C)
527 #define IPN3KE_CLF_MHL_RES_MASK 0xFFFFFFFF
528 #define IPN3KE_CLF_MHL_RES (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x2000)
531 ipn3ke_rpst_dev_set_link_up(struct rte_eth_dev *dev);
533 ipn3ke_rpst_dev_set_link_down(struct rte_eth_dev *dev);
535 ipn3ke_rpst_link_update(struct rte_eth_dev *ethdev,
536 __rte_unused int wait_to_complete);
538 ipn3ke_rpst_promiscuous_enable(struct rte_eth_dev *ethdev);
540 ipn3ke_rpst_promiscuous_disable(struct rte_eth_dev *ethdev);
542 ipn3ke_rpst_allmulticast_enable(struct rte_eth_dev *ethdev);
544 ipn3ke_rpst_allmulticast_disable(struct rte_eth_dev *ethdev);
546 ipn3ke_rpst_mac_addr_set(struct rte_eth_dev *ethdev,
547 struct ether_addr *mac_addr);
549 ipn3ke_rpst_mtu_set(struct rte_eth_dev *ethdev, uint16_t mtu);
552 ipn3ke_rpst_init(struct rte_eth_dev *ethdev, void *init_params);
554 ipn3ke_rpst_uninit(struct rte_eth_dev *ethdev);
556 ipn3ke_hw_tm_init(struct ipn3ke_hw *hw);
558 ipn3ke_tm_init(struct ipn3ke_rpst *rpst);
560 ipn3ke_tm_ops_get(struct rte_eth_dev *ethdev,
564 /* IPN3KE_MASK is a macro used on 32 bit registers */
565 #define IPN3KE_MASK(mask, shift) ((mask) << (shift))
567 #define IPN3KE_MAC_CTRL_BASE_0 0x00000000
568 #define IPN3KE_MAC_CTRL_BASE_1 0x00008000
570 #define IPN3KE_MAC_STATS_MASK 0xFFFFFFFFF
572 /* All the address are in 4Bytes*/
573 #define IPN3KE_MAC_PRIMARY_MAC_ADDR0 0x0010
574 #define IPN3KE_MAC_PRIMARY_MAC_ADDR1 0x0011
576 #define IPN3KE_MAC_MAC_RESET_CONTROL 0x001F
577 #define IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT 0
578 #define IPN3KE_MAC_MAC_RESET_CONTROL_TX_MASK \
579 IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT)
581 #define IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT 8
582 #define IPN3KE_MAC_MAC_RESET_CONTROL_RX_MASK \
583 IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT)
585 #define IPN3KE_MAC_TX_PACKET_CONTROL 0x0020
586 #define IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT 0
587 #define IPN3KE_MAC_TX_PACKET_CONTROL_MASK \
588 IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT)
590 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE 0x002A
591 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT 0
592 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK \
593 IPN3KE_MASK(0x1, IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT)
595 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH 0x002C
596 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT 0
597 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH_MASK \
598 IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT)
600 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL 0x0040
601 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT 0
602 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_MASK \
603 IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT)
605 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA 0x0042
606 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT 0
607 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_MASK \
608 IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT)
610 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA 0x0043
611 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT 0
612 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_MASK \
613 IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT)
615 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE 0x0044
616 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT 0
617 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_MASK \
618 IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT)
620 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT 1
621 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_MASK \
622 IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT)
624 #define IPN3KE_MAC_RX_TRANSFER_CONTROL 0x00A0
625 #define IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT 0x0
626 #define IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK \
627 IPN3KE_MASK(0x1, IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT)
629 #define IPN3KE_MAC_RX_FRAME_CONTROL 0x00AC
630 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT 0x0
631 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK \
632 IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT)
634 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT 0x1
635 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK \
636 IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT)
638 #define IPN3KE_VLAN_TAG_SIZE 4
640 * The overhead from MTU to max frame size.
641 * Considering QinQ packet, the VLAN tag needs to be counted twice.
643 #define IPN3KE_ETH_OVERHEAD \
644 (ETHER_HDR_LEN + ETHER_CRC_LEN + IPN3KE_VLAN_TAG_SIZE * 2)
646 #define IPN3KE_MAC_FRAME_SIZE_MAX 9728
647 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH 0x00AE
648 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT 0
649 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \
650 IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)
652 #define IPN3KE_MAC_TX_STATS_CLR 0x0140
653 #define IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT 0
654 #define IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK \
655 IPN3KE_MASK(0x1, IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT)
657 #define IPN3KE_MAC_RX_STATS_CLR 0x01C0
658 #define IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT 0
659 #define IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK \
660 IPN3KE_MASK(0x1, IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT)
662 /*tx_stats_framesOK*/
663 #define IPN3KE_MAC_TX_STATS_FRAMESOK_HI 0x0142
664 #define IPN3KE_MAC_TX_STATS_FRAMESOK_LOW 0x0143
666 /*rx_stats_framesOK*/
667 #define IPN3KE_MAC_RX_STATS_FRAMESOK_HI 0x01C2
668 #define IPN3KE_MAC_RX_STATS_FRAMESOK_LOW 0x01C3
670 /*tx_stats_framesErr*/
671 #define IPN3KE_MAC_TX_STATS_FRAMESERR_HI 0x0144
672 #define IPN3KE_MAC_TX_STATS_FRAMESERR_LOW 0x0145
674 /*rx_stats_framesErr*/
675 #define IPN3KE_MAC_RX_STATS_FRAMESERR_HI 0x01C4
676 #define IPN3KE_MAC_RX_STATS_FRAMESERR_LOW 0x01C5
678 /*rx_stats_framesCRCErr*/
679 #define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_HI 0x01C6
680 #define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_LOW 0x01C7
682 /*tx_stats_octetsOK 64b*/
683 #define IPN3KE_MAC_TX_STATS_OCTETSOK_HI 0x0148
684 #define IPN3KE_MAC_TX_STATS_OCTETSOK_LOW 0x0149
686 /*rx_stats_octetsOK 64b*/
687 #define IPN3KE_MAC_RX_STATS_OCTETSOK_HI 0x01C8
688 #define IPN3KE_MAC_RX_STATS_OCTETSOK_LOW 0x01C9
690 /*tx_stats_pauseMACCtrl_Frames*/
691 #define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_HI 0x014A
692 #define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x014B
694 /*rx_stats_pauseMACCtrl_Frames*/
695 #define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_HI 0x01CA
696 #define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x01CB
698 /*tx_stats_ifErrors*/
699 #define IPN3KE_MAC_TX_STATS_IFERRORS_HI 0x014C
700 #define IPN3KE_MAC_TX_STATS_IFERRORS_LOW 0x014D
702 /*rx_stats_ifErrors*/
703 #define IPN3KE_MAC_RX_STATS_IFERRORS_HI 0x01CC
704 #define IPN3KE_MAC_RX_STATS_IFERRORS_LOW 0x01CD
706 /*tx_stats_unicast_FramesOK*/
707 #define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_HI 0x014E
708 #define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_LOW 0x014F
710 /*rx_stats_unicast_FramesOK*/
711 #define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_HI 0x01CE
712 #define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_LOW 0x01CF
714 /*tx_stats_unicast_FramesErr*/
715 #define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_HI 0x0150
716 #define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_LOW 0x0151
718 /*rx_stats_unicast_FramesErr*/
719 #define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_HI 0x01D0
720 #define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_LOW 0x01D1
722 /*tx_stats_multicast_FramesOK*/
723 #define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_HI 0x0152
724 #define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_LOW 0x0153
726 /*rx_stats_multicast_FramesOK*/
727 #define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_HI 0x01D2
728 #define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_LOW 0x01D3
730 /*tx_stats_multicast_FramesErr*/
731 #define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_HI 0x0154
732 #define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_LOW 0x0155
734 /*rx_stats_multicast_FramesErr*/
735 #define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_HI 0x01D4
736 #define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_LOW 0x01D5
738 /*tx_stats_broadcast_FramesOK*/
739 #define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_HI 0x0156
740 #define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_LOW 0x0157
742 /*rx_stats_broadcast_FramesOK*/
743 #define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_HI 0x01D6
744 #define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_LOW 0x01D7
746 /*tx_stats_broadcast_FramesErr*/
747 #define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_HI 0x0158
748 #define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_LOW 0x0159
750 /*rx_stats_broadcast_FramesErr*/
751 #define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_HI 0x01D8
752 #define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_LOW 0x01D9
754 /*tx_stats_etherStatsOctets 64b*/
755 #define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_HI 0x015A
756 #define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_LOW 0x015B
758 /*rx_stats_etherStatsOctets 64b*/
759 #define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_HI 0x01DA
760 #define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_LOW 0x01DB
762 /*tx_stats_etherStatsPkts*/
763 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_HI 0x015C
764 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_LOW 0x015D
766 /*rx_stats_etherStatsPkts*/
767 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_HI 0x01DC
768 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_LOW 0x01DD
770 /*tx_stats_etherStatsUndersizePkts*/
771 #define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x015E
772 #define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x015F
774 /*rx_stats_etherStatsUndersizePkts*/
775 #define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x01DE
776 #define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x01DF
778 /*tx_stats_etherStatsOversizePkts*/
779 #define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x0160
780 #define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x0161
782 /*rx_stats_etherStatsOversizePkts*/
783 #define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x01E0
784 #define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x01E1
786 /*tx_stats_etherStatsPkts64Octets*/
787 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x0162
788 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x0163
790 /*rx_stats_etherStatsPkts64Octets*/
791 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x01E2
792 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x01E3
794 /*tx_stats_etherStatsPkts65to127Octets*/
795 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x0164
796 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x0165
798 /*rx_stats_etherStatsPkts65to127Octets*/
799 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x01E4
800 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x01E5
802 /*tx_stats_etherStatsPkts128to255Octets*/
803 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x0166
804 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x0167
806 /*rx_stats_etherStatsPkts128to255Octets*/
807 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x01E6
808 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x01E7
810 /*tx_stats_etherStatsPkts256to511Octet*/
811 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_HI 0x0168
812 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_LOW 0x0169
814 /*rx_stats_etherStatsPkts256to511Octets*/
815 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_HI 0x01E8
816 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_LOW 0x01E9
818 /*tx_stats_etherStatsPkts512to1023Octets*/
819 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x016A
820 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x016B
822 /*rx_stats_etherStatsPkts512to1023Octets*/
823 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x01EA
824 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x01EB
826 /*tx_stats_etherStatPkts1024to1518Octets*/
827 #define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x016C
828 #define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x016D
830 /*rx_stats_etherStatPkts1024to1518Octets*/
831 #define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x01EC
832 #define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x01ED
834 /*tx_stats_etherStatsPkts1519toXOctets*/
835 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x016E
836 #define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x016F
838 /*rx_stats_etherStatsPkts1519toXOctets*/
839 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x01EE
840 #define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x01EF
842 /*rx_stats_etherStatsFragments*/
843 #define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_HI 0x01F0
844 #define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_LOW 0x01F1
846 /*rx_stats_etherStatsJabbers*/
847 #define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_HI 0x01F2
848 #define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_LOW 0x01F3
850 /*rx_stats_etherStatsCRCErr*/
851 #define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_HI 0x01F4
852 #define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_LOW 0x01F5
854 /*tx_stats_unicastMACCtrlFrames*/
855 #define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_HI 0x0176
856 #define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_LOW 0x0177
858 /*rx_stats_unicastMACCtrlFrames*/
859 #define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_HI 0x01F6
860 #define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_LOW 0x01F7
862 /*tx_stats_multicastMACCtrlFrames*/
863 #define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_HI 0x0178
864 #define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x0179
866 /*rx_stats_multicastMACCtrlFrames*/
867 #define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_HI 0x01F8
868 #define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x01F9
870 /*tx_stats_broadcastMACCtrlFrames*/
871 #define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_HI 0x017A
872 #define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x017B
874 /*rx_stats_broadcastMACCtrlFrames*/
875 #define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_HI 0x01FA
876 #define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x01FB
878 /*tx_stats_PFCMACCtrlFrames*/
879 #define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_HI 0x017C
880 #define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_LOW 0x017D
882 /*rx_stats_PFCMACCtrlFrames*/
883 #define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_HI 0x01FC
884 #define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_LOW 0x01FD
886 static inline void ipn3ke_xmac_tx_enable(struct ipn3ke_hw *hw,
887 uint32_t mac_num, uint32_t eth_group_sel)
889 #define IPN3KE_XMAC_TX_ENABLE (0 & (IPN3KE_MAC_TX_PACKET_CONTROL_MASK))
891 (*hw->f_mac_write)(hw,
892 IPN3KE_XMAC_TX_ENABLE,
893 IPN3KE_MAC_TX_PACKET_CONTROL,
898 static inline void ipn3ke_xmac_tx_disable(struct ipn3ke_hw *hw,
899 uint32_t mac_num, uint32_t eth_group_sel)
901 #define IPN3KE_XMAC_TX_DISABLE (1 & (IPN3KE_MAC_TX_PACKET_CONTROL_MASK))
903 (*hw->f_mac_write)(hw,
904 IPN3KE_XMAC_TX_DISABLE,
905 IPN3KE_MAC_TX_PACKET_CONTROL,
910 static inline void ipn3ke_xmac_rx_enable(struct ipn3ke_hw *hw,
911 uint32_t mac_num, uint32_t eth_group_sel)
913 #define IPN3KE_XMAC_RX_ENABLE (0 & (IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK))
915 (*hw->f_mac_write)(hw,
916 IPN3KE_XMAC_RX_ENABLE,
917 IPN3KE_MAC_RX_TRANSFER_CONTROL,
922 static inline void ipn3ke_xmac_rx_disable(struct ipn3ke_hw *hw,
923 uint32_t mac_num, uint32_t eth_group_sel)
925 #define IPN3KE_XMAC_RX_DISABLE (1 & (IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK))
927 (*hw->f_mac_write)(hw,
928 IPN3KE_XMAC_RX_DISABLE,
929 IPN3KE_MAC_RX_TRANSFER_CONTROL,
934 static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw,
935 uint32_t mac_num, uint32_t eth_group_sel)
937 #define IPN3KE_XMAC_SMAC_OVERRIDE_DISABLE (0 & \
938 (IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK))
940 (*hw->f_mac_write)(hw,
941 IPN3KE_XMAC_SMAC_OVERRIDE_DISABLE,
942 IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,
947 static inline void ipn3ke_xmac_tx_clr_stcs(struct ipn3ke_hw *hw,
948 uint32_t mac_num, uint32_t eth_group_sel)
950 #define IPN3KE_XMAC_TX_CLR_STCS (1 & \
951 (IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK))
953 (*hw->f_mac_write)(hw,
954 IPN3KE_XMAC_TX_CLR_STCS,
955 IPN3KE_MAC_TX_STATS_CLR,
960 static inline void ipn3ke_xmac_rx_clr_stcs(struct ipn3ke_hw *hw,
961 uint32_t mac_num, uint32_t eth_group_sel)
963 #define IPN3KE_XMAC_RX_CLR_STCS (1 & \
964 (IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK))
966 (*hw->f_mac_write)(hw,
967 IPN3KE_XMAC_RX_CLR_STCS,
968 IPN3KE_MAC_RX_STATS_CLR,
974 #endif /* _IPN3KE_ETHDEV_H_ */