drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 297                 return false;
 298
 299         if (ixgbe_get_phy_id(hw))
 300                 return false;
 301
 302         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 303
 304         if (hw->phy.type == ixgbe_phy_unknown) {
 305                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 307                 if (ext_ability &
 308                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                         hw->phy.type = ixgbe_phy_cu_unknown;
 311                 else
 312                         hw->phy.type = ixgbe_phy_generic;
 313         }
 314
 315         return true;
 316 }
 317
 318 /**
 319  *  ixgbe_identify_phy_generic - Get physical layer module
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Determines the physical layer module found on the current adapter.
 323  **/
 324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 325 {
 326         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 327         u16 phy_addr;
 328
 329         DEBUGFUNC("ixgbe_identify_phy_generic");
 330
 331         if (!hw->phy.phy_semaphore_mask) {
 332                 if (hw->bus.lan_id)
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 334                 else
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 336         }
 337
 338         if (hw->phy.type != ixgbe_phy_unknown)
 339                 return IXGBE_SUCCESS;
 340
 341         if (hw->phy.nw_mng_if_sel) {
 342                 phy_addr = (hw->phy.nw_mng_if_sel &
 343                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 344                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 345                 if (ixgbe_probe_phy(hw, phy_addr))
 346                         return IXGBE_SUCCESS;
 347                 else
 348                         return IXGBE_ERR_PHY_ADDR_INVALID;
 349         }
 350
 351         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 352                 if (ixgbe_probe_phy(hw, phy_addr)) {
 353                         status = IXGBE_SUCCESS;
 354                         break;
 355                 }
 356         }
 357
 358         /* Certain media types do not have a phy so an address will not
 359          * be found and the code will take this path.  Caller has to
 360          * decide if it is an error or not.
 361          */
 362         if (status != IXGBE_SUCCESS)
 363                 hw->phy.addr = 0;
 364
 365         return status;
 366 }
 367
 368 /**
 369  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 370  * @hw: pointer to the hardware structure
 371  *
 372  * This function checks the MMNGC.MNG_VETO bit to see if there are
 373  * any constraints on link from manageability.  For MAC's that don't
 374  * have this bit just return faluse since the link can not be blocked
 375  * via this method.
 376  **/
 377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 378 {
 379         u32 mmngc;
 380
 381         DEBUGFUNC("ixgbe_check_reset_blocked");
 382
 383         /* If we don't have this bit, it can't be blocking */
 384         if (hw->mac.type == ixgbe_mac_82598EB)
 385                 return false;
 386
 387         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 388         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 389                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 390                               "MNG_VETO bit detected.\n");
 391                 return true;
 392         }
 393
 394         return false;
 395 }
 396
 397 /**
 398  *  ixgbe_validate_phy_addr - Determines phy address is valid
 399  *  @hw: pointer to hardware structure
 400  *
 401  **/
 402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 403 {
 404         u16 phy_id = 0;
 405         bool valid = false;
 406
 407         DEBUGFUNC("ixgbe_validate_phy_addr");
 408
 409         hw->phy.addr = phy_addr;
 410         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 411                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 412
 413         if (phy_id != 0xFFFF && phy_id != 0x0)
 414                 valid = true;
 415
 416         return valid;
 417 }
 418
 419 /**
 420  *  ixgbe_get_phy_id - Get the phy type
 421  *  @hw: pointer to hardware structure
 422  *
 423  **/
 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 425 {
 426         u32 status;
 427         u16 phy_id_high = 0;
 428         u16 phy_id_low = 0;
 429
 430         DEBUGFUNC("ixgbe_get_phy_id");
 431
 432         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 433                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 434                                       &phy_id_high);
 435
 436         if (status == IXGBE_SUCCESS) {
 437                 hw->phy.id = (u32)(phy_id_high << 16);
 438                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 439                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 440                                               &phy_id_low);
 441                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 442                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 443         }
 444         return status;
 445 }
 446
 447 /**
 448  *  ixgbe_get_phy_type_from_id - Get the phy type
 449  *  @phy_id: PHY ID information
 450  *
 451  **/
 452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 453 {
 454         enum ixgbe_phy_type phy_type;
 455
 456         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 457
 458         switch (phy_id) {
 459         case TN1010_PHY_ID:
 460                 phy_type = ixgbe_phy_tn;
 461                 break;
 462         case X550_PHY_ID1:
 463         case X550_PHY_ID2:
 464         case X550_PHY_ID3:
 465         case X540_PHY_ID:
 466                 phy_type = ixgbe_phy_aq;
 467                 break;
 468         case QT2022_PHY_ID:
 469                 phy_type = ixgbe_phy_qt;
 470                 break;
 471         case ATH_PHY_ID:
 472                 phy_type = ixgbe_phy_nl;
 473                 break;
 474         case X557_PHY_ID:
 475         case X557_PHY_ID2:
 476                 phy_type = ixgbe_phy_x550em_ext_t;
 477                 break;
 478         case IXGBE_M88E1500_E_PHY_ID:
 479         case IXGBE_M88E1543_E_PHY_ID:
 480                 phy_type = ixgbe_phy_m88;
 481                 break;
 482         default:
 483                 phy_type = ixgbe_phy_unknown;
 484                 break;
 485         }
 486         return phy_type;
 487 }
 488
 489 /**
 490  *  ixgbe_reset_phy_generic - Performs a PHY reset
 491  *  @hw: pointer to hardware structure
 492  **/
 493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 494 {
 495         u32 i;
 496         u16 ctrl = 0;
 497         s32 status = IXGBE_SUCCESS;
 498
 499         DEBUGFUNC("ixgbe_reset_phy_generic");
 500
 501         if (hw->phy.type == ixgbe_phy_unknown)
 502                 status = ixgbe_identify_phy_generic(hw);
 503
 504         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 505                 goto out;
 506
 507         /* Don't reset PHY if it's shut down due to overtemp. */
 508         if (!hw->phy.reset_if_overtemp &&
 509             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 510                 goto out;
 511
 512         /* Blocked by MNG FW so bail */
 513         if (ixgbe_check_reset_blocked(hw))
 514                 goto out;
 515
 516         /*
 517          * Perform soft PHY reset to the PHY_XS.
 518          * This will cause a soft reset to the PHY
 519          */
 520         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 521                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 522                               IXGBE_MDIO_PHY_XS_RESET);
 523
 524         /*
 525          * Poll for reset bit to self-clear indicating reset is complete.
 526          * Some PHYs could take up to 3 seconds to complete and need about
 527          * 1.7 usec delay after the reset is complete.
 528          */
 529         for (i = 0; i < 30; i++) {
 530                 msec_delay(100);
 531                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 532                         status = hw->phy.ops.read_reg(hw,
 533                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 534                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 535                                                   &ctrl);
 536                         if (status != IXGBE_SUCCESS)
 537                                 return status;
 538
 539                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 540                                 usec_delay(2);
 541                                 break;
 542                         }
 543                 } else {
 544                         status = hw->phy.ops.read_reg(hw,
 545                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 546                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 547                                                      &ctrl);
 548                         if (status != IXGBE_SUCCESS)
 549                                 return status;
 550
 551                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 552                                 usec_delay(2);
 553                                 break;
 554                         }
 555                 }
 556         }
 557
 558         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 559                 status = IXGBE_ERR_RESET_FAILED;
 560                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 561                              "PHY reset polling failed to complete.\n");
 562         }
 563
 564 out:
 565         return status;
 566 }
 567
 568 /**
 569  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 570  *  the SWFW lock
 571  *  @hw: pointer to hardware structure
 572  *  @reg_addr: 32 bit address of PHY register to read
 573  *  @phy_data: Pointer to read data from PHY register
 574  **/
 575 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 576                        u16 *phy_data)
 577 {
 578         u32 i, data, command;
 579
 580         /* Setup and write the address cycle command */
 581         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 582                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 583                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 584                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 585
 586         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 587
 588         /*
 589          * Check every 10 usec to see if the address cycle completed.
 590          * The MDI Command bit will clear when the operation is
 591          * complete
 592          */
 593         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 594                 usec_delay(10);
 595
 596                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 597                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 598                                 break;
 599         }
 600
 601
 602         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 603                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 604                 return IXGBE_ERR_PHY;
 605         }
 606
 607         /*
 608          * Address cycle complete, setup and write the read
 609          * command
 610          */
 611         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 612                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 613                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 614                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 615
 616         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 617
 618         /*
 619          * Check every 10 usec to see if the address cycle
 620          * completed. The MDI Command bit will clear when the
 621          * operation is complete
 622          */
 623         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 624                 usec_delay(10);
 625
 626                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 627                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 628                         break;
 629         }
 630
 631         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 632                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 633                 return IXGBE_ERR_PHY;
 634         }
 635
 636         /*
 637          * Read operation is complete.  Get the data
 638          * from MSRWD
 639          */
 640         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 641         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 642         *phy_data = (u16)(data);
 643
 644         return IXGBE_SUCCESS;
 645 }
 646
 647 /**
 648  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 649  *  using the SWFW lock - this function is needed in most cases
 650  *  @hw: pointer to hardware structure
 651  *  @reg_addr: 32 bit address of PHY register to read
 652  *  @phy_data: Pointer to read data from PHY register
 653  **/
 654 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 655                                u32 device_type, u16 *phy_data)
 656 {
 657         s32 status;
 658         u32 gssr = hw->phy.phy_semaphore_mask;
 659
 660         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 661
 662         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 663                 return IXGBE_ERR_SWFW_SYNC;
 664
 665         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 666
 667         hw->mac.ops.release_swfw_sync(hw, gssr);
 668
 669         return status;
 670 }
 671
 672 /**
 673  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 674  *  without SWFW lock
 675  *  @hw: pointer to hardware structure
 676  *  @reg_addr: 32 bit PHY register to write
 677  *  @device_type: 5 bit device type
 678  *  @phy_data: Data to write to the PHY register
 679  **/
 680 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 681                                 u32 device_type, u16 phy_data)
 682 {
 683         u32 i, command;
 684
 685         /* Put the data in the MDI single read and write data register*/
 686         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 687
 688         /* Setup and write the address cycle command */
 689         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 690                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 691                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 692                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 693
 694         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 695
 696         /*
 697          * Check every 10 usec to see if the address cycle completed.
 698          * The MDI Command bit will clear when the operation is
 699          * complete
 700          */
 701         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 702                 usec_delay(10);
 703
 704                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 705                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 706                         break;
 707         }
 708
 709         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 710                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 711                 return IXGBE_ERR_PHY;
 712         }
 713
 714         /*
 715          * Address cycle complete, setup and write the write
 716          * command
 717          */
 718         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 719                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 720                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 721                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 722
 723         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 724
 725         /*
 726          * Check every 10 usec to see if the address cycle
 727          * completed. The MDI Command bit will clear when the
 728          * operation is complete
 729          */
 730         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 731                 usec_delay(10);
 732
 733                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 734                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 735                         break;
 736         }
 737
 738         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 739                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 740                 return IXGBE_ERR_PHY;
 741         }
 742
 743         return IXGBE_SUCCESS;
 744 }
 745
 746 /**
 747  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 748  *  using SWFW lock- this function is needed in most cases
 749  *  @hw: pointer to hardware structure
 750  *  @reg_addr: 32 bit PHY register to write
 751  *  @device_type: 5 bit device type
 752  *  @phy_data: Data to write to the PHY register
 753  **/
 754 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 755                                 u32 device_type, u16 phy_data)
 756 {
 757         s32 status;
 758         u32 gssr = hw->phy.phy_semaphore_mask;
 759
 760         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 761
 762         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 763                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 764                                                  phy_data);
 765                 hw->mac.ops.release_swfw_sync(hw, gssr);
 766         } else {
 767                 status = IXGBE_ERR_SWFW_SYNC;
 768         }
 769
 770         return status;
 771 }
 772
 773 /**
 774  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 775  *  @hw: pointer to hardware structure
 776  *
 777  *  Restart auto-negotiation and PHY and waits for completion.
 778  **/
 779 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 780 {
 781         s32 status = IXGBE_SUCCESS;
 782         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 783         bool autoneg = false;
 784         ixgbe_link_speed speed;
 785
 786         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 787
 788         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 789
 790         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 791                 /* Set or unset auto-negotiation 10G advertisement */
 792                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 793                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 794                                      &autoneg_reg);
 795
 796                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 797                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 798                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 799
 800                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 801                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                                       autoneg_reg);
 803         }
 804
 805         if (hw->mac.type == ixgbe_mac_X550) {
 806                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 807                         /* Set or unset auto-negotiation 5G advertisement */
 808                         hw->phy.ops.read_reg(hw,
 809                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 810                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 811                                 &autoneg_reg);
 812
 813                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 814                         if (hw->phy.autoneg_advertised &
 815                              IXGBE_LINK_SPEED_5GB_FULL)
 816                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 817
 818                         hw->phy.ops.write_reg(hw,
 819                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 820                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 821                                 autoneg_reg);
 822                 }
 823
 824                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 825                         /* Set or unset auto-negotiation 2.5G advertisement */
 826                         hw->phy.ops.read_reg(hw,
 827                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 828                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 829                                 &autoneg_reg);
 830
 831                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 832                         if (hw->phy.autoneg_advertised &
 833                             IXGBE_LINK_SPEED_2_5GB_FULL)
 834                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 835
 836                         hw->phy.ops.write_reg(hw,
 837                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 838                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 839                                 autoneg_reg);
 840                 }
 841         }
 842
 843         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 844                 /* Set or unset auto-negotiation 1G advertisement */
 845                 hw->phy.ops.read_reg(hw,
 846                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 847                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 848                                      &autoneg_reg);
 849
 850                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 851                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 852                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 853
 854                 hw->phy.ops.write_reg(hw,
 855                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 856                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 857                                       autoneg_reg);
 858         }
 859
 860         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 861                 /* Set or unset auto-negotiation 100M advertisement */
 862                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 863                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 864                                      &autoneg_reg);
 865
 866                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 867                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 868                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 869                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 870
 871                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 872                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 873                                       autoneg_reg);
 874         }
 875
 876         /* Blocked by MNG FW so don't reset PHY */
 877         if (ixgbe_check_reset_blocked(hw))
 878                 return status;
 879
 880         /* Restart PHY auto-negotiation. */
 881         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 882                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 883
 884         autoneg_reg |= IXGBE_MII_RESTART;
 885
 886         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 887                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 888
 889         return status;
 890 }
 891
 892 /**
 893  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 894  *  @hw: pointer to hardware structure
 895  *  @speed: new link speed
 896  **/
 897 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 898                                        ixgbe_link_speed speed,
 899                                        bool autoneg_wait_to_complete)
 900 {
 901         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 902
 903         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 904
 905         /*
 906          * Clear autoneg_advertised and set new values based on input link
 907          * speed.
 908          */
 909         hw->phy.autoneg_advertised = 0;
 910
 911         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 912                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 913
 914         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 915                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 916
 917         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 918                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 919
 920         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 921                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 922
 923         if (speed & IXGBE_LINK_SPEED_100_FULL)
 924                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 925
 926         if (speed & IXGBE_LINK_SPEED_10_FULL)
 927                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 928
 929         /* Setup link based on the new speed settings */
 930         ixgbe_setup_phy_link(hw);
 931
 932         return IXGBE_SUCCESS;
 933 }
 934
 935 /**
 936  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 937  * @hw: pointer to hardware structure
 938  *
 939  * Determines the supported link capabilities by reading the PHY auto
 940  * negotiation register.
 941  **/
 942 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 943 {
 944         s32 status;
 945         u16 speed_ability;
 946
 947         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 948                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 949                                       &speed_ability);
 950         if (status)
 951                 return status;
 952
 953         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 954                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 955         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 956                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 957         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 958                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 959
 960         switch (hw->mac.type) {
 961         case ixgbe_mac_X550:
 962                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 963                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 964                 break;
 965         case ixgbe_mac_X550EM_x:
 966         case ixgbe_mac_X550EM_a:
 967                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 968                 break;
 969         default:
 970                 break;
 971         }
 972
 973         return status;
 974 }
 975
 976 /**
 977  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 978  *  @hw: pointer to hardware structure
 979  *  @speed: pointer to link speed
 980  *  @autoneg: boolean auto-negotiation value
 981  **/
 982 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 983                                                ixgbe_link_speed *speed,
 984                                                bool *autoneg)
 985 {
 986         s32 status = IXGBE_SUCCESS;
 987
 988         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 989
 990         *autoneg = true;
 991         if (!hw->phy.speeds_supported)
 992                 status = ixgbe_get_copper_speeds_supported(hw);
 993
 994         *speed = hw->phy.speeds_supported;
 995         return status;
 996 }
 997
 998 /**
 999  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1000  *  @hw: pointer to hardware structure
1001  *
1002  *  Reads the VS1 register to determine if link is up and the current speed for
1003  *  the PHY.
1004  **/
1005 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1006                              bool *link_up)
1007 {
1008         s32 status = IXGBE_SUCCESS;
1009         u32 time_out;
1010         u32 max_time_out = 10;
1011         u16 phy_link = 0;
1012         u16 phy_speed = 0;
1013         u16 phy_data = 0;
1014
1015         DEBUGFUNC("ixgbe_check_phy_link_tnx");
1016
1017         /* Initialize speed and link to default case */
1018         *link_up = false;
1019         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1020
1021         /*
1022          * Check current speed and link status of the PHY register.
1023          * This is a vendor specific register and may have to
1024          * be changed for other copper PHYs.
1025          */
1026         for (time_out = 0; time_out < max_time_out; time_out++) {
1027                 usec_delay(10);
1028                 status = hw->phy.ops.read_reg(hw,
1029                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1030                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1031                                         &phy_data);
1032                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1033                 phy_speed = phy_data &
1034                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1035                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1036                         *link_up = true;
1037                         if (phy_speed ==
1038                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1039                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1040                         break;
1041                 }
1042         }
1043
1044         return status;
1045 }
1046
1047 /**
1048  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1049  *      @hw: pointer to hardware structure
1050  *
1051  *      Restart auto-negotiation and PHY and waits for completion.
1052  **/
1053 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1054 {
1055         s32 status = IXGBE_SUCCESS;
1056         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1057         bool autoneg = false;
1058         ixgbe_link_speed speed;
1059
1060         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1061
1062         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1063
1064         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1065                 /* Set or unset auto-negotiation 10G advertisement */
1066                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1067                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1068                                      &autoneg_reg);
1069
1070                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1071                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1072                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1073
1074                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1075                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1076                                       autoneg_reg);
1077         }
1078
1079         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1080                 /* Set or unset auto-negotiation 1G advertisement */
1081                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1082                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1083                                      &autoneg_reg);
1084
1085                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1086                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1087                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1088
1089                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1090                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1091                                       autoneg_reg);
1092         }
1093
1094         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1095                 /* Set or unset auto-negotiation 100M advertisement */
1096                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1097                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1098                                      &autoneg_reg);
1099
1100                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1101                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1102                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1103
1104                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1105                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1106                                       autoneg_reg);
1107         }
1108
1109         /* Blocked by MNG FW so don't reset PHY */
1110         if (ixgbe_check_reset_blocked(hw))
1111                 return status;
1112
1113         /* Restart PHY auto-negotiation. */
1114         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1115                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1116
1117         autoneg_reg |= IXGBE_MII_RESTART;
1118
1119         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1120                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1121
1122         return status;
1123 }
1124
1125 /**
1126  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1127  *  @hw: pointer to hardware structure
1128  *  @firmware_version: pointer to the PHY Firmware Version
1129  **/
1130 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1131                                        u16 *firmware_version)
1132 {
1133         s32 status;
1134
1135         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1136
1137         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1138                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1139                                       firmware_version);
1140
1141         return status;
1142 }
1143
1144 /**
1145  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1146  *  @hw: pointer to hardware structure
1147  *  @firmware_version: pointer to the PHY Firmware Version
1148  **/
1149 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1150                                            u16 *firmware_version)
1151 {
1152         s32 status;
1153
1154         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1155
1156         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1157                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1158                                       firmware_version);
1159
1160         return status;
1161 }
1162
1163 /**
1164  *  ixgbe_reset_phy_nl - Performs a PHY reset
1165  *  @hw: pointer to hardware structure
1166  **/
1167 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1168 {
1169         u16 phy_offset, control, eword, edata, block_crc;
1170         bool end_data = false;
1171         u16 list_offset, data_offset;
1172         u16 phy_data = 0;
1173         s32 ret_val = IXGBE_SUCCESS;
1174         u32 i;
1175
1176         DEBUGFUNC("ixgbe_reset_phy_nl");
1177
1178         /* Blocked by MNG FW so bail */
1179         if (ixgbe_check_reset_blocked(hw))
1180                 goto out;
1181
1182         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1183                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1184
1185         /* reset the PHY and poll for completion */
1186         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1187                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1188                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1189
1190         for (i = 0; i < 100; i++) {
1191                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1192                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1193                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1194                         break;
1195                 msec_delay(10);
1196         }
1197
1198         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1199                 DEBUGOUT("PHY reset did not complete.\n");
1200                 ret_val = IXGBE_ERR_PHY;
1201                 goto out;
1202         }
1203
1204         /* Get init offsets */
1205         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1206                                                       &data_offset);
1207         if (ret_val != IXGBE_SUCCESS)
1208                 goto out;
1209
1210         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1211         data_offset++;
1212         while (!end_data) {
1213                 /*
1214                  * Read control word from PHY init contents offset
1215                  */
1216                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1217                 if (ret_val)
1218                         goto err_eeprom;
1219                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1220                            IXGBE_CONTROL_SHIFT_NL;
1221                 edata = eword & IXGBE_DATA_MASK_NL;
1222                 switch (control) {
1223                 case IXGBE_DELAY_NL:
1224                         data_offset++;
1225                         DEBUGOUT1("DELAY: %d MS\n", edata);
1226                         msec_delay(edata);
1227                         break;
1228                 case IXGBE_DATA_NL:
1229                         DEBUGOUT("DATA:\n");
1230                         data_offset++;
1231                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1232                                                       &phy_offset);
1233                         if (ret_val)
1234                                 goto err_eeprom;
1235                         data_offset++;
1236                         for (i = 0; i < edata; i++) {
1237                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1238                                                               &eword);
1239                                 if (ret_val)
1240                                         goto err_eeprom;
1241                                 hw->phy.ops.write_reg(hw, phy_offset,
1242                                                       IXGBE_TWINAX_DEV, eword);
1243                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1244                                           phy_offset);
1245                                 data_offset++;
1246                                 phy_offset++;
1247                         }
1248                         break;
1249                 case IXGBE_CONTROL_NL:
1250                         data_offset++;
1251                         DEBUGOUT("CONTROL:\n");
1252                         if (edata == IXGBE_CONTROL_EOL_NL) {
1253                                 DEBUGOUT("EOL\n");
1254                                 end_data = true;
1255                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1256                                 DEBUGOUT("SOL\n");
1257                         } else {
1258                                 DEBUGOUT("Bad control value\n");
1259                                 ret_val = IXGBE_ERR_PHY;
1260                                 goto out;
1261                         }
1262                         break;
1263                 default:
1264                         DEBUGOUT("Bad control type\n");
1265                         ret_val = IXGBE_ERR_PHY;
1266                         goto out;
1267                 }
1268         }
1269
1270 out:
1271         return ret_val;
1272
1273 err_eeprom:
1274         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1275                       "eeprom read at offset %d failed", data_offset);
1276         return IXGBE_ERR_PHY;
1277 }
1278
1279 /**
1280  *  ixgbe_identify_module_generic - Identifies module type
1281  *  @hw: pointer to hardware structure
1282  *
1283  *  Determines HW type and calls appropriate function.
1284  **/
1285 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1286 {
1287         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1288
1289         DEBUGFUNC("ixgbe_identify_module_generic");
1290
1291         switch (hw->mac.ops.get_media_type(hw)) {
1292         case ixgbe_media_type_fiber:
1293                 status = ixgbe_identify_sfp_module_generic(hw);
1294                 break;
1295
1296         case ixgbe_media_type_fiber_qsfp:
1297                 status = ixgbe_identify_qsfp_module_generic(hw);
1298                 break;
1299
1300         default:
1301                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1302                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1303                 break;
1304         }
1305
1306         return status;
1307 }
1308
1309 /**
1310  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1311  *  @hw: pointer to hardware structure
1312  *
1313  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1314  **/
1315 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1316 {
1317         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1318         u32 vendor_oui = 0;
1319         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1320         u8 identifier = 0;
1321         u8 comp_codes_1g = 0;
1322         u8 comp_codes_10g = 0;
1323         u8 oui_bytes[3] = {0, 0, 0};
1324         u8 cable_tech = 0;
1325         u8 cable_spec = 0;
1326         u16 enforce_sfp = 0;
1327
1328         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1329
1330         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1331                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1332                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1333                 goto out;
1334         }
1335
1336         /* LAN ID is needed for I2C access */
1337         hw->mac.ops.set_lan_id(hw);
1338
1339         status = hw->phy.ops.read_i2c_eeprom(hw,
1340                                              IXGBE_SFF_IDENTIFIER,
1341                                              &identifier);
1342
1343         if (status != IXGBE_SUCCESS)
1344                 goto err_read_i2c_eeprom;
1345
1346         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1347                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1348                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1349         } else {
1350                 status = hw->phy.ops.read_i2c_eeprom(hw,
1351                                                      IXGBE_SFF_1GBE_COMP_CODES,
1352                                                      &comp_codes_1g);
1353
1354                 if (status != IXGBE_SUCCESS)
1355                         goto err_read_i2c_eeprom;
1356
1357                 status = hw->phy.ops.read_i2c_eeprom(hw,
1358                                                      IXGBE_SFF_10GBE_COMP_CODES,
1359                                                      &comp_codes_10g);
1360
1361                 if (status != IXGBE_SUCCESS)
1362                         goto err_read_i2c_eeprom;
1363                 status = hw->phy.ops.read_i2c_eeprom(hw,
1364                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1365                                                      &cable_tech);
1366
1367                 if (status != IXGBE_SUCCESS)
1368                         goto err_read_i2c_eeprom;
1369
1370                  /* ID Module
1371                   * =========
1372                   * 0   SFP_DA_CU
1373                   * 1   SFP_SR
1374                   * 2   SFP_LR
1375                   * 3   SFP_DA_CORE0 - 82599-specific
1376                   * 4   SFP_DA_CORE1 - 82599-specific
1377                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1378                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1379                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1380                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1381                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1382                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1383                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1384                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1385                   */
1386                 if (hw->mac.type == ixgbe_mac_82598EB) {
1387                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1388                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1389                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1390                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1391                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1392                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1393                         else
1394                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1395                 } else {
1396                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1397                                 if (hw->bus.lan_id == 0)
1398                                         hw->phy.sfp_type =
1399                                                      ixgbe_sfp_type_da_cu_core0;
1400                                 else
1401                                         hw->phy.sfp_type =
1402                                                      ixgbe_sfp_type_da_cu_core1;
1403                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1404                                 hw->phy.ops.read_i2c_eeprom(
1405                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1406                                                 &cable_spec);
1407                                 if (cable_spec &
1408                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1409                                         if (hw->bus.lan_id == 0)
1410                                                 hw->phy.sfp_type =
1411                                                 ixgbe_sfp_type_da_act_lmt_core0;
1412                                         else
1413                                                 hw->phy.sfp_type =
1414                                                 ixgbe_sfp_type_da_act_lmt_core1;
1415                                 } else {
1416                                         hw->phy.sfp_type =
1417                                                         ixgbe_sfp_type_unknown;
1418                                 }
1419                         } else if (comp_codes_10g &
1420                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1421                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1422                                 if (hw->bus.lan_id == 0)
1423                                         hw->phy.sfp_type =
1424                                                       ixgbe_sfp_type_srlr_core0;
1425                                 else
1426                                         hw->phy.sfp_type =
1427                                                       ixgbe_sfp_type_srlr_core1;
1428                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1429                                 if (hw->bus.lan_id == 0)
1430                                         hw->phy.sfp_type =
1431                                                 ixgbe_sfp_type_1g_cu_core0;
1432                                 else
1433                                         hw->phy.sfp_type =
1434                                                 ixgbe_sfp_type_1g_cu_core1;
1435                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1436                                 if (hw->bus.lan_id == 0)
1437                                         hw->phy.sfp_type =
1438                                                 ixgbe_sfp_type_1g_sx_core0;
1439                                 else
1440                                         hw->phy.sfp_type =
1441                                                 ixgbe_sfp_type_1g_sx_core1;
1442                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1443                                 if (hw->bus.lan_id == 0)
1444                                         hw->phy.sfp_type =
1445                                                 ixgbe_sfp_type_1g_lx_core0;
1446                                 else
1447                                         hw->phy.sfp_type =
1448                                                 ixgbe_sfp_type_1g_lx_core1;
1449                         } else {
1450                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1451                         }
1452                 }
1453
1454                 if (hw->phy.sfp_type != stored_sfp_type)
1455                         hw->phy.sfp_setup_needed = true;
1456
1457                 /* Determine if the SFP+ PHY is dual speed or not. */
1458                 hw->phy.multispeed_fiber = false;
1459                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1460                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1461                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1462                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1463                         hw->phy.multispeed_fiber = true;
1464
1465                 /* Determine PHY vendor */
1466                 if (hw->phy.type != ixgbe_phy_nl) {
1467                         hw->phy.id = identifier;
1468                         status = hw->phy.ops.read_i2c_eeprom(hw,
1469                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1470                                                     &oui_bytes[0]);
1471
1472                         if (status != IXGBE_SUCCESS)
1473                                 goto err_read_i2c_eeprom;
1474
1475                         status = hw->phy.ops.read_i2c_eeprom(hw,
1476                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1477                                                     &oui_bytes[1]);
1478
1479                         if (status != IXGBE_SUCCESS)
1480                                 goto err_read_i2c_eeprom;
1481
1482                         status = hw->phy.ops.read_i2c_eeprom(hw,
1483                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1484                                                     &oui_bytes[2]);
1485
1486                         if (status != IXGBE_SUCCESS)
1487                                 goto err_read_i2c_eeprom;
1488
1489                         vendor_oui =
1490                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1491                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1492                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1493
1494                         switch (vendor_oui) {
1495                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1496                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1497                                         hw->phy.type =
1498                                                     ixgbe_phy_sfp_passive_tyco;
1499                                 break;
1500                         case IXGBE_SFF_VENDOR_OUI_FTL:
1501                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1503                                 else
1504                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1505                                 break;
1506                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1507                                 hw->phy.type = ixgbe_phy_sfp_avago;
1508                                 break;
1509                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1510                                 hw->phy.type = ixgbe_phy_sfp_intel;
1511                                 break;
1512                         default:
1513                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1514                                         hw->phy.type =
1515                                                  ixgbe_phy_sfp_passive_unknown;
1516                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1517                                         hw->phy.type =
1518                                                 ixgbe_phy_sfp_active_unknown;
1519                                 else
1520                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1521                                 break;
1522                         }
1523                 }
1524
1525                 /* Allow any DA cable vendor */
1526                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1527                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1528                         status = IXGBE_SUCCESS;
1529                         goto out;
1530                 }
1531
1532                 /* Verify supported 1G SFP modules */
1533                 if (comp_codes_10g == 0 &&
1534                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1535                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1536                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1537                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1538                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1539                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1540                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1541                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1542                         goto out;
1543                 }
1544
1545                 /* Anything else 82598-based is supported */
1546                 if (hw->mac.type == ixgbe_mac_82598EB) {
1547                         status = IXGBE_SUCCESS;
1548                         goto out;
1549                 }
1550
1551                 ixgbe_get_device_caps(hw, &enforce_sfp);
1552                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1553                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1554                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1555                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1556                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1557                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1558                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1559                         /* Make sure we're a supported PHY type */
1560                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1561                                 status = IXGBE_SUCCESS;
1562                         } else {
1563                                 if (hw->allow_unsupported_sfp == true) {
1564                                         EWARN(hw, "WARNING: Intel (R) Network "
1565                                               "Connections are quality tested "
1566                                               "using Intel (R) Ethernet Optics."
1567                                               " Using untested modules is not "
1568                                               "supported and may cause unstable"
1569                                               " operation or damage to the "
1570                                               "module or the adapter. Intel "
1571                                               "Corporation is not responsible "
1572                                               "for any harm caused by using "
1573                                               "untested modules.\n", status);
1574                                         status = IXGBE_SUCCESS;
1575                                 } else {
1576                                         DEBUGOUT("SFP+ module not supported\n");
1577                                         hw->phy.type =
1578                                                 ixgbe_phy_sfp_unsupported;
1579                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1580                                 }
1581                         }
1582                 } else {
1583                         status = IXGBE_SUCCESS;
1584                 }
1585         }
1586
1587 out:
1588         return status;
1589
1590 err_read_i2c_eeprom:
1591         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1592         if (hw->phy.type != ixgbe_phy_nl) {
1593                 hw->phy.id = 0;
1594                 hw->phy.type = ixgbe_phy_unknown;
1595         }
1596         return IXGBE_ERR_SFP_NOT_PRESENT;
1597 }
1598
1599 /**
1600  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1601  *  @hw: pointer to hardware structure
1602  *
1603  *  Determines physical layer capabilities of the current SFP.
1604  */
1605 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1606 {
1607         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1608         u8 comp_codes_10g = 0;
1609         u8 comp_codes_1g = 0;
1610
1611         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1612
1613         hw->phy.ops.identify_sfp(hw);
1614         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1615                 return physical_layer;
1616
1617         switch (hw->phy.type) {
1618         case ixgbe_phy_sfp_passive_tyco:
1619         case ixgbe_phy_sfp_passive_unknown:
1620         case ixgbe_phy_qsfp_passive_unknown:
1621                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1622                 break;
1623         case ixgbe_phy_sfp_ftl_active:
1624         case ixgbe_phy_sfp_active_unknown:
1625         case ixgbe_phy_qsfp_active_unknown:
1626                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1627                 break;
1628         case ixgbe_phy_sfp_avago:
1629         case ixgbe_phy_sfp_ftl:
1630         case ixgbe_phy_sfp_intel:
1631         case ixgbe_phy_sfp_unknown:
1632                 hw->phy.ops.read_i2c_eeprom(hw,
1633                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1634                 hw->phy.ops.read_i2c_eeprom(hw,
1635                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1636                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1637                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1638                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1639                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1640                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1641                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1642                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1643                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1644                 break;
1645         case ixgbe_phy_qsfp_intel:
1646         case ixgbe_phy_qsfp_unknown:
1647                 hw->phy.ops.read_i2c_eeprom(hw,
1648                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1649                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1650                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1651                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1652                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1653                 break;
1654         default:
1655                 break;
1656         }
1657
1658         return physical_layer;
1659 }
1660
1661 /**
1662  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1663  *  @hw: pointer to hardware structure
1664  *
1665  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1666  **/
1667 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1668 {
1669         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1670         u32 vendor_oui = 0;
1671         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1672         u8 identifier = 0;
1673         u8 comp_codes_1g = 0;
1674         u8 comp_codes_10g = 0;
1675         u8 oui_bytes[3] = {0, 0, 0};
1676         u16 enforce_sfp = 0;
1677         u8 connector = 0;
1678         u8 cable_length = 0;
1679         u8 device_tech = 0;
1680         bool active_cable = false;
1681
1682         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1683
1684         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1685                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1686                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1687                 goto out;
1688         }
1689
1690         /* LAN ID is needed for I2C access */
1691         hw->mac.ops.set_lan_id(hw);
1692
1693         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1694                                              &identifier);
1695
1696         if (status != IXGBE_SUCCESS)
1697                 goto err_read_i2c_eeprom;
1698
1699         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1700                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1701                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1702                 goto out;
1703         }
1704
1705         hw->phy.id = identifier;
1706
1707         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1708                                              &comp_codes_10g);
1709
1710         if (status != IXGBE_SUCCESS)
1711                 goto err_read_i2c_eeprom;
1712
1713         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1714                                              &comp_codes_1g);
1715
1716         if (status != IXGBE_SUCCESS)
1717                 goto err_read_i2c_eeprom;
1718
1719         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1720                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1721                 if (hw->bus.lan_id == 0)
1722                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1723                 else
1724                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1725         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1726                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1727                 if (hw->bus.lan_id == 0)
1728                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1729                 else
1730                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1731         } else {
1732                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1733                         active_cable = true;
1734
1735                 if (!active_cable) {
1736                         /* check for active DA cables that pre-date
1737                          * SFF-8436 v3.6 */
1738                         hw->phy.ops.read_i2c_eeprom(hw,
1739                                         IXGBE_SFF_QSFP_CONNECTOR,
1740                                         &connector);
1741
1742                         hw->phy.ops.read_i2c_eeprom(hw,
1743                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1744                                         &cable_length);
1745
1746                         hw->phy.ops.read_i2c_eeprom(hw,
1747                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1748                                         &device_tech);
1749
1750                         if ((connector ==
1751                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1752                             (cable_length > 0) &&
1753                             ((device_tech >> 4) ==
1754                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1755                                 active_cable = true;
1756                 }
1757
1758                 if (active_cable) {
1759                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1760                         if (hw->bus.lan_id == 0)
1761                                 hw->phy.sfp_type =
1762                                                 ixgbe_sfp_type_da_act_lmt_core0;
1763                         else
1764                                 hw->phy.sfp_type =
1765                                                 ixgbe_sfp_type_da_act_lmt_core1;
1766                 } else {
1767                         /* unsupported module type */
1768                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1769                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1770                         goto out;
1771                 }
1772         }
1773
1774         if (hw->phy.sfp_type != stored_sfp_type)
1775                 hw->phy.sfp_setup_needed = true;
1776
1777         /* Determine if the QSFP+ PHY is dual speed or not. */
1778         hw->phy.multispeed_fiber = false;
1779         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1780            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1781            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1782            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1783                 hw->phy.multispeed_fiber = true;
1784
1785         /* Determine PHY vendor for optical modules */
1786         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1787                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1788                 status = hw->phy.ops.read_i2c_eeprom(hw,
1789                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1790                                             &oui_bytes[0]);
1791
1792                 if (status != IXGBE_SUCCESS)
1793                         goto err_read_i2c_eeprom;
1794
1795                 status = hw->phy.ops.read_i2c_eeprom(hw,
1796                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1797                                             &oui_bytes[1]);
1798
1799                 if (status != IXGBE_SUCCESS)
1800                         goto err_read_i2c_eeprom;
1801
1802                 status = hw->phy.ops.read_i2c_eeprom(hw,
1803                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1804                                             &oui_bytes[2]);
1805
1806                 if (status != IXGBE_SUCCESS)
1807                         goto err_read_i2c_eeprom;
1808
1809                 vendor_oui =
1810                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1811                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1812                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1813
1814                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1815                         hw->phy.type = ixgbe_phy_qsfp_intel;
1816                 else
1817                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1818
1819                 ixgbe_get_device_caps(hw, &enforce_sfp);
1820                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1821                         /* Make sure we're a supported PHY type */
1822                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1823                                 status = IXGBE_SUCCESS;
1824                         } else {
1825                                 if (hw->allow_unsupported_sfp == true) {
1826                                         EWARN(hw, "WARNING: Intel (R) Network "
1827                                               "Connections are quality tested "
1828                                               "using Intel (R) Ethernet Optics."
1829                                               " Using untested modules is not "
1830                                               "supported and may cause unstable"
1831                                               " operation or damage to the "
1832                                               "module or the adapter. Intel "
1833                                               "Corporation is not responsible "
1834                                               "for any harm caused by using "
1835                                               "untested modules.\n", status);
1836                                         status = IXGBE_SUCCESS;
1837                                 } else {
1838                                         DEBUGOUT("QSFP module not supported\n");
1839                                         hw->phy.type =
1840                                                 ixgbe_phy_sfp_unsupported;
1841                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1842                                 }
1843                         }
1844                 } else {
1845                         status = IXGBE_SUCCESS;
1846                 }
1847         }
1848
1849 out:
1850         return status;
1851
1852 err_read_i2c_eeprom:
1853         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1854         hw->phy.id = 0;
1855         hw->phy.type = ixgbe_phy_unknown;
1856
1857         return IXGBE_ERR_SFP_NOT_PRESENT;
1858 }
1859
1860
1861 /**
1862  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1863  *  @hw: pointer to hardware structure
1864  *  @list_offset: offset to the SFP ID list
1865  *  @data_offset: offset to the SFP data block
1866  *
1867  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1868  *  so it returns the offsets to the phy init sequence block.
1869  **/
1870 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1871                                         u16 *list_offset,
1872                                         u16 *data_offset)
1873 {
1874         u16 sfp_id;
1875         u16 sfp_type = hw->phy.sfp_type;
1876
1877         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1878
1879         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1880                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1881
1882         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1883                 return IXGBE_ERR_SFP_NOT_PRESENT;
1884
1885         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1886             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1887                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1888
1889         /*
1890          * Limiting active cables and 1G Phys must be initialized as
1891          * SR modules
1892          */
1893         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1894             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1895             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1896             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1897                 sfp_type = ixgbe_sfp_type_srlr_core0;
1898         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1899                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1900                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1901                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1902                 sfp_type = ixgbe_sfp_type_srlr_core1;
1903
1904         /* Read offset to PHY init contents */
1905         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1906                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1907                               "eeprom read at offset %d failed",
1908                               IXGBE_PHY_INIT_OFFSET_NL);
1909                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1910         }
1911
1912         if ((!*list_offset) || (*list_offset == 0xFFFF))
1913                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1914
1915         /* Shift offset to first ID word */
1916         (*list_offset)++;
1917
1918         /*
1919          * Find the matching SFP ID in the EEPROM
1920          * and program the init sequence
1921          */
1922         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1923                 goto err_phy;
1924
1925         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1926                 if (sfp_id == sfp_type) {
1927                         (*list_offset)++;
1928                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1929                                 goto err_phy;
1930                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1931                                 DEBUGOUT("SFP+ module not supported\n");
1932                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1933                         } else {
1934                                 break;
1935                         }
1936                 } else {
1937                         (*list_offset) += 2;
1938                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1939                                 goto err_phy;
1940                 }
1941         }
1942
1943         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1944                 DEBUGOUT("No matching SFP+ module found\n");
1945                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1946         }
1947
1948         return IXGBE_SUCCESS;
1949
1950 err_phy:
1951         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1952                       "eeprom read at offset %d failed", *list_offset);
1953         return IXGBE_ERR_PHY;
1954 }
1955
1956 /**
1957  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1958  *  @hw: pointer to hardware structure
1959  *  @byte_offset: EEPROM byte offset to read
1960  *  @eeprom_data: value read
1961  *
1962  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1963  **/
1964 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1965                                   u8 *eeprom_data)
1966 {
1967         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1968
1969         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1970                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1971                                          eeprom_data);
1972 }
1973
1974 /**
1975  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1976  *  @hw: pointer to hardware structure
1977  *  @byte_offset: byte offset at address 0xA2
1978  *  @eeprom_data: value read
1979  *
1980  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1981  **/
1982 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1983                                           u8 *sff8472_data)
1984 {
1985         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1986                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1987                                          sff8472_data);
1988 }
1989
1990 /**
1991  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1992  *  @hw: pointer to hardware structure
1993  *  @byte_offset: EEPROM byte offset to write
1994  *  @eeprom_data: value to write
1995  *
1996  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1997  **/
1998 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1999                                    u8 eeprom_data)
2000 {
2001         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2002
2003         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2004                                           IXGBE_I2C_EEPROM_DEV_ADDR,
2005                                           eeprom_data);
2006 }
2007
2008 /**
2009  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2010  * @hw: pointer to hardware structure
2011  * @offset: eeprom offset to be read
2012  * @addr: I2C address to be read
2013  */
2014 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2015 {
2016         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2017             offset == IXGBE_SFF_IDENTIFIER &&
2018             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2019                 return true;
2020         return false;
2021 }
2022
2023 /**
2024  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2025  *  @hw: pointer to hardware structure
2026  *  @byte_offset: byte offset to read
2027  *  @data: value read
2028  *  @lock: true if to take and release semaphore
2029  *
2030  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2031  *  a specified device address.
2032  **/
2033 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2034                                            u8 dev_addr, u8 *data, bool lock)
2035 {
2036         s32 status;
2037         u32 max_retry = 10;
2038         u32 retry = 0;
2039         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2040         bool nack = 1;
2041         *data = 0;
2042
2043         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2044
2045         if (hw->mac.type >= ixgbe_mac_X550)
2046                 max_retry = 3;
2047         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2048                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2049
2050         do {
2051                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2052                         return IXGBE_ERR_SWFW_SYNC;
2053
2054                 ixgbe_i2c_start(hw);
2055
2056                 /* Device Address and write indication */
2057                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2058                 if (status != IXGBE_SUCCESS)
2059                         goto fail;
2060
2061                 status = ixgbe_get_i2c_ack(hw);
2062                 if (status != IXGBE_SUCCESS)
2063                         goto fail;
2064
2065                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2066                 if (status != IXGBE_SUCCESS)
2067                         goto fail;
2068
2069                 status = ixgbe_get_i2c_ack(hw);
2070                 if (status != IXGBE_SUCCESS)
2071                         goto fail;
2072
2073                 ixgbe_i2c_start(hw);
2074
2075                 /* Device Address and read indication */
2076                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2077                 if (status != IXGBE_SUCCESS)
2078                         goto fail;
2079
2080                 status = ixgbe_get_i2c_ack(hw);
2081                 if (status != IXGBE_SUCCESS)
2082                         goto fail;
2083
2084                 status = ixgbe_clock_in_i2c_byte(hw, data);
2085                 if (status != IXGBE_SUCCESS)
2086                         goto fail;
2087
2088                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2089                 if (status != IXGBE_SUCCESS)
2090                         goto fail;
2091
2092                 ixgbe_i2c_stop(hw);
2093                 if (lock)
2094                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2095                 return IXGBE_SUCCESS;
2096
2097 fail:
2098                 ixgbe_i2c_bus_clear(hw);
2099                 if (lock) {
2100                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2101                         msec_delay(100);
2102                 }
2103                 retry++;
2104                 if (retry < max_retry)
2105                         DEBUGOUT("I2C byte read error - Retrying.\n");
2106                 else
2107                         DEBUGOUT("I2C byte read error.\n");
2108
2109         } while (retry < max_retry);
2110
2111         return status;
2112 }
2113
2114 /**
2115  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2116  *  @hw: pointer to hardware structure
2117  *  @byte_offset: byte offset to read
2118  *  @data: value read
2119  *
2120  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2121  *  a specified device address.
2122  **/
2123 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2124                                 u8 dev_addr, u8 *data)
2125 {
2126         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2127                                                data, true);
2128 }
2129
2130 /**
2131  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2132  *  @hw: pointer to hardware structure
2133  *  @byte_offset: byte offset to read
2134  *  @data: value read
2135  *
2136  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2137  *  a specified device address.
2138  **/
2139 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2140                                          u8 dev_addr, u8 *data)
2141 {
2142         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2143                                                data, false);
2144 }
2145
2146 /**
2147  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2148  *  @hw: pointer to hardware structure
2149  *  @byte_offset: byte offset to write
2150  *  @data: value to write
2151  *  @lock: true if to take and release semaphore
2152  *
2153  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2154  *  a specified device address.
2155  **/
2156 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2157                                             u8 dev_addr, u8 data, bool lock)
2158 {
2159         s32 status;
2160         u32 max_retry = 1;
2161         u32 retry = 0;
2162         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2163
2164         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2165
2166         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2167             IXGBE_SUCCESS)
2168                 return IXGBE_ERR_SWFW_SYNC;
2169
2170         do {
2171                 ixgbe_i2c_start(hw);
2172
2173                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2174                 if (status != IXGBE_SUCCESS)
2175                         goto fail;
2176
2177                 status = ixgbe_get_i2c_ack(hw);
2178                 if (status != IXGBE_SUCCESS)
2179                         goto fail;
2180
2181                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2182                 if (status != IXGBE_SUCCESS)
2183                         goto fail;
2184
2185                 status = ixgbe_get_i2c_ack(hw);
2186                 if (status != IXGBE_SUCCESS)
2187                         goto fail;
2188
2189                 status = ixgbe_clock_out_i2c_byte(hw, data);
2190                 if (status != IXGBE_SUCCESS)
2191                         goto fail;
2192
2193                 status = ixgbe_get_i2c_ack(hw);
2194                 if (status != IXGBE_SUCCESS)
2195                         goto fail;
2196
2197                 ixgbe_i2c_stop(hw);
2198                 if (lock)
2199                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2200                 return IXGBE_SUCCESS;
2201
2202 fail:
2203                 ixgbe_i2c_bus_clear(hw);
2204                 retry++;
2205                 if (retry < max_retry)
2206                         DEBUGOUT("I2C byte write error - Retrying.\n");
2207                 else
2208                         DEBUGOUT("I2C byte write error.\n");
2209         } while (retry < max_retry);
2210
2211         if (lock)
2212                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2213
2214         return status;
2215 }
2216
2217 /**
2218  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2219  *  @hw: pointer to hardware structure
2220  *  @byte_offset: byte offset to write
2221  *  @data: value to write
2222  *
2223  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2224  *  a specified device address.
2225  **/
2226 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2227                                  u8 dev_addr, u8 data)
2228 {
2229         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2230                                                 data, true);
2231 }
2232
2233 /**
2234  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2235  *  @hw: pointer to hardware structure
2236  *  @byte_offset: byte offset to write
2237  *  @data: value to write
2238  *
2239  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2240  *  a specified device address.
2241  **/
2242 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2243                                           u8 dev_addr, u8 data)
2244 {
2245         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2246                                                 data, false);
2247 }
2248
2249 /**
2250  *  ixgbe_i2c_start - Sets I2C start condition
2251  *  @hw: pointer to hardware structure
2252  *
2253  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2254  *  Set bit-bang mode on X550 hardware.
2255  **/
2256 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2257 {
2258         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2259
2260         DEBUGFUNC("ixgbe_i2c_start");
2261
2262         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2263
2264         /* Start condition must begin with data and clock high */
2265         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2266         ixgbe_raise_i2c_clk(hw, &i2cctl);
2267
2268         /* Setup time for start condition (4.7us) */
2269         usec_delay(IXGBE_I2C_T_SU_STA);
2270
2271         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2272
2273         /* Hold time for start condition (4us) */
2274         usec_delay(IXGBE_I2C_T_HD_STA);
2275
2276         ixgbe_lower_i2c_clk(hw, &i2cctl);
2277
2278         /* Minimum low period of clock is 4.7 us */
2279         usec_delay(IXGBE_I2C_T_LOW);
2280
2281 }
2282
2283 /**
2284  *  ixgbe_i2c_stop - Sets I2C stop condition
2285  *  @hw: pointer to hardware structure
2286  *
2287  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2288  *  Disables bit-bang mode and negates data output enable on X550
2289  *  hardware.
2290  **/
2291 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2292 {
2293         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2294         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2295         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2296         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2297
2298         DEBUGFUNC("ixgbe_i2c_stop");
2299
2300         /* Stop condition must begin with data low and clock high */
2301         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2302         ixgbe_raise_i2c_clk(hw, &i2cctl);
2303
2304         /* Setup time for stop condition (4us) */
2305         usec_delay(IXGBE_I2C_T_SU_STO);
2306
2307         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2308
2309         /* bus free time between stop and start (4.7us)*/
2310         usec_delay(IXGBE_I2C_T_BUF);
2311
2312         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2313                 i2cctl &= ~bb_en_bit;
2314                 i2cctl |= data_oe_bit | clk_oe_bit;
2315                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2316                 IXGBE_WRITE_FLUSH(hw);
2317         }
2318 }
2319
2320 /**
2321  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2322  *  @hw: pointer to hardware structure
2323  *  @data: data byte to clock in
2324  *
2325  *  Clocks in one byte data via I2C data/clock
2326  **/
2327 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2328 {
2329         s32 i;
2330         bool bit = 0;
2331
2332         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2333
2334         *data = 0;
2335         for (i = 7; i >= 0; i--) {
2336                 ixgbe_clock_in_i2c_bit(hw, &bit);
2337                 *data |= bit << i;
2338         }
2339
2340         return IXGBE_SUCCESS;
2341 }
2342
2343 /**
2344  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2345  *  @hw: pointer to hardware structure
2346  *  @data: data byte clocked out
2347  *
2348  *  Clocks out one byte data via I2C data/clock
2349  **/
2350 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2351 {
2352         s32 status = IXGBE_SUCCESS;
2353         s32 i;
2354         u32 i2cctl;
2355         bool bit;
2356
2357         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2358
2359         for (i = 7; i >= 0; i--) {
2360                 bit = (data >> i) & 0x1;
2361                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2362
2363                 if (status != IXGBE_SUCCESS)
2364                         break;
2365         }
2366
2367         /* Release SDA line (set high) */
2368         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2369         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2370         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2371         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2372         IXGBE_WRITE_FLUSH(hw);
2373
2374         return status;
2375 }
2376
2377 /**
2378  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2379  *  @hw: pointer to hardware structure
2380  *
2381  *  Clocks in/out one bit via I2C data/clock
2382  **/
2383 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2384 {
2385         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2386         s32 status = IXGBE_SUCCESS;
2387         u32 i = 0;
2388         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2389         u32 timeout = 10;
2390         bool ack = 1;
2391
2392         DEBUGFUNC("ixgbe_get_i2c_ack");
2393
2394         if (data_oe_bit) {
2395                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2396                 i2cctl |= data_oe_bit;
2397                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2398                 IXGBE_WRITE_FLUSH(hw);
2399         }
2400         ixgbe_raise_i2c_clk(hw, &i2cctl);
2401
2402         /* Minimum high period of clock is 4us */
2403         usec_delay(IXGBE_I2C_T_HIGH);
2404
2405         /* Poll for ACK.  Note that ACK in I2C spec is
2406          * transition from 1 to 0 */
2407         for (i = 0; i < timeout; i++) {
2408                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2409                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2410
2411                 usec_delay(1);
2412                 if (!ack)
2413                         break;
2414         }
2415
2416         if (ack) {
2417                 DEBUGOUT("I2C ack was not received.\n");
2418                 status = IXGBE_ERR_I2C;
2419         }
2420
2421         ixgbe_lower_i2c_clk(hw, &i2cctl);
2422
2423         /* Minimum low period of clock is 4.7 us */
2424         usec_delay(IXGBE_I2C_T_LOW);
2425
2426         return status;
2427 }
2428
2429 /**
2430  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2431  *  @hw: pointer to hardware structure
2432  *  @data: read data value
2433  *
2434  *  Clocks in one bit via I2C data/clock
2435  **/
2436 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2437 {
2438         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2439         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2440
2441         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2442
2443         if (data_oe_bit) {
2444                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2445                 i2cctl |= data_oe_bit;
2446                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2447                 IXGBE_WRITE_FLUSH(hw);
2448         }
2449         ixgbe_raise_i2c_clk(hw, &i2cctl);
2450
2451         /* Minimum high period of clock is 4us */
2452         usec_delay(IXGBE_I2C_T_HIGH);
2453
2454         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2455         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2456
2457         ixgbe_lower_i2c_clk(hw, &i2cctl);
2458
2459         /* Minimum low period of clock is 4.7 us */
2460         usec_delay(IXGBE_I2C_T_LOW);
2461
2462         return IXGBE_SUCCESS;
2463 }
2464
2465 /**
2466  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2467  *  @hw: pointer to hardware structure
2468  *  @data: data value to write
2469  *
2470  *  Clocks out one bit via I2C data/clock
2471  **/
2472 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2473 {
2474         s32 status;
2475         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2476
2477         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2478
2479         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2480         if (status == IXGBE_SUCCESS) {
2481                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2482
2483                 /* Minimum high period of clock is 4us */
2484                 usec_delay(IXGBE_I2C_T_HIGH);
2485
2486                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2487
2488                 /* Minimum low period of clock is 4.7 us.
2489                  * This also takes care of the data hold time.
2490                  */
2491                 usec_delay(IXGBE_I2C_T_LOW);
2492         } else {
2493                 status = IXGBE_ERR_I2C;
2494                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2495                              "I2C data was not set to %X\n", data);
2496         }
2497
2498         return status;
2499 }
2500
2501 /**
2502  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2503  *  @hw: pointer to hardware structure
2504  *  @i2cctl: Current value of I2CCTL register
2505  *
2506  *  Raises the I2C clock line '0'->'1'
2507  *  Negates the I2C clock output enable on X550 hardware.
2508  **/
2509 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2510 {
2511         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2512         u32 i = 0;
2513         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2514         u32 i2cctl_r = 0;
2515
2516         DEBUGFUNC("ixgbe_raise_i2c_clk");
2517
2518         if (clk_oe_bit) {
2519                 *i2cctl |= clk_oe_bit;
2520                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2521         }
2522
2523         for (i = 0; i < timeout; i++) {
2524                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2525
2526                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2527                 IXGBE_WRITE_FLUSH(hw);
2528                 /* SCL rise time (1000ns) */
2529                 usec_delay(IXGBE_I2C_T_RISE);
2530
2531                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2532                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2533                         break;
2534         }
2535 }
2536
2537 /**
2538  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2539  *  @hw: pointer to hardware structure
2540  *  @i2cctl: Current value of I2CCTL register
2541  *
2542  *  Lowers the I2C clock line '1'->'0'
2543  *  Asserts the I2C clock output enable on X550 hardware.
2544  **/
2545 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2546 {
2547         DEBUGFUNC("ixgbe_lower_i2c_clk");
2548
2549         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2550         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2551
2552         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553         IXGBE_WRITE_FLUSH(hw);
2554
2555         /* SCL fall time (300ns) */
2556         usec_delay(IXGBE_I2C_T_FALL);
2557 }
2558
2559 /**
2560  *  ixgbe_set_i2c_data - Sets the I2C data bit
2561  *  @hw: pointer to hardware structure
2562  *  @i2cctl: Current value of I2CCTL register
2563  *  @data: I2C data value (0 or 1) to set
2564  *
2565  *  Sets the I2C data bit
2566  *  Asserts the I2C data output enable on X550 hardware.
2567  **/
2568 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2569 {
2570         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2571         s32 status = IXGBE_SUCCESS;
2572
2573         DEBUGFUNC("ixgbe_set_i2c_data");
2574
2575         if (data)
2576                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2577         else
2578                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2579         *i2cctl &= ~data_oe_bit;
2580
2581         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2582         IXGBE_WRITE_FLUSH(hw);
2583
2584         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2585         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2586
2587         if (!data)      /* Can't verify data in this case */
2588                 return IXGBE_SUCCESS;
2589         if (data_oe_bit) {
2590                 *i2cctl |= data_oe_bit;
2591                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2592                 IXGBE_WRITE_FLUSH(hw);
2593         }
2594
2595         /* Verify data was set correctly */
2596         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2597         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2598                 status = IXGBE_ERR_I2C;
2599                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2600                              "Error - I2C data was not set to %X.\n",
2601                              data);
2602         }
2603
2604         return status;
2605 }
2606
2607 /**
2608  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2609  *  @hw: pointer to hardware structure
2610  *  @i2cctl: Current value of I2CCTL register
2611  *
2612  *  Returns the I2C data bit value
2613  *  Negates the I2C data output enable on X550 hardware.
2614  **/
2615 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2616 {
2617         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2618         bool data;
2619
2620         DEBUGFUNC("ixgbe_get_i2c_data");
2621
2622         if (data_oe_bit) {
2623                 *i2cctl |= data_oe_bit;
2624                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2625                 IXGBE_WRITE_FLUSH(hw);
2626                 usec_delay(IXGBE_I2C_T_FALL);
2627         }
2628
2629         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2630                 data = 1;
2631         else
2632                 data = 0;
2633
2634         return data;
2635 }
2636
2637 /**
2638  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2639  *  @hw: pointer to hardware structure
2640  *
2641  *  Clears the I2C bus by sending nine clock pulses.
2642  *  Used when data line is stuck low.
2643  **/
2644 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2645 {
2646         u32 i2cctl;
2647         u32 i;
2648
2649         DEBUGFUNC("ixgbe_i2c_bus_clear");
2650
2651         ixgbe_i2c_start(hw);
2652         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2653
2654         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2655
2656         for (i = 0; i < 9; i++) {
2657                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2658
2659                 /* Min high period of clock is 4us */
2660                 usec_delay(IXGBE_I2C_T_HIGH);
2661
2662                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2663
2664                 /* Min low period of clock is 4.7us*/
2665                 usec_delay(IXGBE_I2C_T_LOW);
2666         }
2667
2668         ixgbe_i2c_start(hw);
2669
2670         /* Put the i2c bus back to default state */
2671         ixgbe_i2c_stop(hw);
2672 }
2673
2674 /**
2675  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2676  *  @hw: pointer to hardware structure
2677  *
2678  *  Checks if the LASI temp alarm status was triggered due to overtemp
2679  **/
2680 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2681 {
2682         s32 status = IXGBE_SUCCESS;
2683         u16 phy_data = 0;
2684
2685         DEBUGFUNC("ixgbe_tn_check_overtemp");
2686
2687         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2688                 goto out;
2689
2690         /* Check that the LASI temp alarm status was triggered */
2691         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2692                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2693
2694         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2695                 goto out;
2696
2697         status = IXGBE_ERR_OVERTEMP;
2698         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2699 out:
2700         return status;
2701 }
2702
2703 /**
2704  * ixgbe_set_copper_phy_power - Control power for copper phy
2705  * @hw: pointer to hardware structure
2706  * @on: true for on, false for off
2707  */
2708 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2709 {
2710         u32 status;
2711         u16 reg;
2712
2713         if (!on && ixgbe_mng_present(hw))
2714                 return 0;
2715
2716         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2717                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2718                                       &reg);
2719         if (status)
2720                 return status;
2721
2722         if (on) {
2723                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2724         } else {
2725                 if (ixgbe_check_reset_blocked(hw))
2726                         return 0;
2727                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2728         }
2729
2730         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2731                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2732                                        reg);
2733         return status;
2734 }