drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  98                 if (hw->bus.lan_id) {
  99
 100                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 101                         esdp |= IXGBE_ESDP_SDP1_DIR;
 102                 }
 103                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 104                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 105
 106                 return ixgbe_identify_module_generic(hw);
 107                 break;
 108         case IXGBE_DEV_ID_X550EM_X_KX4:
 109                 hw->phy.type = ixgbe_phy_x550em_kx4;
 110                 break;
 111         case IXGBE_DEV_ID_X550EM_X_KR:
 112                 hw->phy.type = ixgbe_phy_x550em_kr;
 113                 break;
 114         case IXGBE_DEV_ID_X550EM_X_1G_T:
 115         case IXGBE_DEV_ID_X550EM_X_10G_T:
 116                 return ixgbe_identify_phy_generic(hw);
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* X550EM bus type is internal*/
 177         hw->bus.type = ixgbe_bus_type_internal;
 178         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 179
 180         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 181         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 182         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 183         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 184         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 185         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 186         mac->ops.get_supported_physical_layer =
 187                                     ixgbe_get_supported_physical_layer_X550em;
 188
 189         /* PHY */
 190         phy->ops.init = ixgbe_init_phy_ops_X550em;
 191         phy->ops.identify = ixgbe_identify_phy_x550em;
 192         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 193                 phy->ops.set_phy_power = NULL;
 194
 195
 196         /* EEPROM */
 197         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 198         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 199         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 200         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 201         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 202         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 203         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 204         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_dmac_config_X550
 211  *  @hw: pointer to hardware structure
 212  *
 213  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 214  *  When disabling dmac, dmac enable dmac bit is cleared.
 215  **/
 216 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 217 {
 218         u32 reg, high_pri_tc;
 219
 220         DEBUGFUNC("ixgbe_dmac_config_X550");
 221
 222         /* Disable DMA coalescing before configuring */
 223         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 224         reg &= ~IXGBE_DMACR_DMAC_EN;
 225         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 226
 227         /* Disable DMA Coalescing if the watchdog timer is 0 */
 228         if (!hw->mac.dmac_config.watchdog_timer)
 229                 goto out;
 230
 231         ixgbe_dmac_config_tcs_X550(hw);
 232
 233         /* Configure DMA Coalescing Control Register */
 234         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 235
 236         /* Set the watchdog timer in units of 40.96 usec */
 237         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 238         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 239
 240         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 241         /* If fcoe is enabled, set high priority traffic class */
 242         if (hw->mac.dmac_config.fcoe_en) {
 243                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 244                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 245                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 246         }
 247         reg |= IXGBE_DMACR_EN_MNG_IND;
 248
 249         /* Enable DMA coalescing after configuration */
 250         reg |= IXGBE_DMACR_DMAC_EN;
 251         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 252
 253 out:
 254         return IXGBE_SUCCESS;
 255 }
 256
 257 /**
 258  *  ixgbe_dmac_config_tcs_X550
 259  *  @hw: pointer to hardware structure
 260  *
 261  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 262  *  be cleared before configuring.
 263  **/
 264 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 265 {
 266         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 267
 268         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 269
 270         /* Configure DMA coalescing enabled */
 271         switch (hw->mac.dmac_config.link_speed) {
 272         case IXGBE_LINK_SPEED_100_FULL:
 273                 pb_headroom = IXGBE_DMACRXT_100M;
 274                 break;
 275         case IXGBE_LINK_SPEED_1GB_FULL:
 276                 pb_headroom = IXGBE_DMACRXT_1G;
 277                 break;
 278         default:
 279                 pb_headroom = IXGBE_DMACRXT_10G;
 280                 break;
 281         }
 282
 283         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 284                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 285
 286         /* Set the per Rx packet buffer receive threshold */
 287         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 288                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 289                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 290
 291                 if (tc < hw->mac.dmac_config.num_tcs) {
 292                         /* Get Rx PB size */
 293                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 294                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 295                                 IXGBE_RXPBSIZE_SHIFT;
 296
 297                         /* Calculate receive buffer threshold in kilobytes */
 298                         if (rx_pb_size > pb_headroom)
 299                                 rx_pb_size = rx_pb_size - pb_headroom;
 300                         else
 301                                 rx_pb_size = 0;
 302
 303                         /* Minimum of MFS shall be set for DMCTH */
 304                         reg |= (rx_pb_size > maxframe_size_kb) ?
 305                                 rx_pb_size : maxframe_size_kb;
 306                 }
 307                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 308         }
 309         return IXGBE_SUCCESS;
 310 }
 311
 312 /**
 313  *  ixgbe_dmac_update_tcs_X550
 314  *  @hw: pointer to hardware structure
 315  *
 316  *  Disables dmac, updates per TC settings, and then enables dmac.
 317  **/
 318 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 319 {
 320         u32 reg;
 321
 322         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 323
 324         /* Disable DMA coalescing before configuring */
 325         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 326         reg &= ~IXGBE_DMACR_DMAC_EN;
 327         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 328
 329         ixgbe_dmac_config_tcs_X550(hw);
 330
 331         /* Enable DMA coalescing after configuration */
 332         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 333         reg |= IXGBE_DMACR_DMAC_EN;
 334         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 335
 336         return IXGBE_SUCCESS;
 337 }
 338
 339 /**
 340  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 341  *  @hw: pointer to hardware structure
 342  *
 343  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 344  *  ixgbe_hw struct in order to set up EEPROM access.
 345  **/
 346 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 347 {
 348         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 349         u32 eec;
 350         u16 eeprom_size;
 351
 352         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 353
 354         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 355                 eeprom->semaphore_delay = 10;
 356                 eeprom->type = ixgbe_flash;
 357
 358                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 359                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 360                                     IXGBE_EEC_SIZE_SHIFT);
 361                 eeprom->word_size = 1 << (eeprom_size +
 362                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 363
 364                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 365                           eeprom->type, eeprom->word_size);
 366         }
 367
 368         return IXGBE_SUCCESS;
 369 }
 370
 371 /**
 372  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 373  *  @hw: pointer to the HW structure
 374  *  @enable_eee: boolean flag to enable EEE
 375  *
 376  *  Enable/disable EEE based on enable_eee flag.
 377  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 378  *  are modified.
 379  *
 380  **/
 381 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 382 {
 383         u32 eeer;
 384         u16 autoneg_eee_reg;
 385         u32 link_reg;
 386         s32 status;
 387
 388         DEBUGFUNC("ixgbe_setup_eee_X550");
 389
 390         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 391         /* Enable or disable EEE per flag */
 392         if (enable_eee) {
 393                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 394
 395                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 396                         /* Advertise EEE capability */
 397                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 398                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 399
 400                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 401                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 402                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 403
 404                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 405                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 406                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 407                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 408                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 409                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 410                         if (status != IXGBE_SUCCESS)
 411                                 return status;
 412
 413                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 414                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 415
 416                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 417                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 418                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 419                         if (status != IXGBE_SUCCESS)
 420                                 return status;
 421                 }
 422         } else {
 423                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 424
 425                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 426                         /* Disable advertised EEE capability */
 427                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 428                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 429
 430                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 431                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 432                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 433
 434                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 435                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 436                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 437                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 438                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 439                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 440                         if (status != IXGBE_SUCCESS)
 441                                 return status;
 442
 443                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 444                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 445
 446                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 447                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 448                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 449                         if (status != IXGBE_SUCCESS)
 450                                 return status;
 451                 }
 452         }
 453         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 454
 455         return IXGBE_SUCCESS;
 456 }
 457
 458 /**
 459  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 460  * @hw: pointer to hardware structure
 461  * @enable: enable or disable source address pruning
 462  * @pool: Rx pool to set source address pruning for
 463  **/
 464 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 465                                            unsigned int pool)
 466 {
 467         u64 pfflp;
 468
 469         /* max rx pool is 63 */
 470         if (pool > 63)
 471                 return;
 472
 473         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 474         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 475
 476         if (enable)
 477                 pfflp |= (1ULL << pool);
 478         else
 479                 pfflp &= ~(1ULL << pool);
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 482         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 483 }
 484
 485 /**
 486  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 487  *  @hw: pointer to hardware structure
 488  *  @enable: enable or disable switch for Ethertype anti-spoofing
 489  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 490  *
 491  **/
 492 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 493                 bool enable, int vf)
 494 {
 495         int vf_target_reg = vf >> 3;
 496         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 497         u32 pfvfspoof;
 498
 499         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 500
 501         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 502         if (enable)
 503                 pfvfspoof |= (1 << vf_target_shift);
 504         else
 505                 pfvfspoof &= ~(1 << vf_target_shift);
 506
 507         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 508 }
 509
 510 /**
 511  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 512  *  device
 513  *  @hw: pointer to hardware structure
 514  *  @reg_addr: 32 bit PHY register to write
 515  *  @device_type: 3 bit device type
 516  *  @data: Data to write to the register
 517  **/
 518 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 519                             u32 device_type, u32 data)
 520 {
 521         u32 i, command, error;
 522
 523         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 524                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 525
 526         /* Write IOSF control register */
 527         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 528
 529         /* Write IOSF data register */
 530         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 531         /*
 532          * Check every 10 usec to see if the address cycle completed.
 533          * The SB IOSF BUSY bit will clear when the operation is
 534          * complete
 535          */
 536         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 537                 usec_delay(10);
 538
 539                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 540                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 541                         break;
 542         }
 543
 544         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 545                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 546                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 547                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 548                               "Failed to write, error %x\n", error);
 549                 return IXGBE_ERR_PHY;
 550         }
 551
 552         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 553                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 554                 return IXGBE_ERR_PHY;
 555         }
 556
 557         return IXGBE_SUCCESS;
 558 }
 559
 560 /**
 561  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 562  *  device
 563  *  @hw: pointer to hardware structure
 564  *  @reg_addr: 32 bit PHY register to write
 565  *  @device_type: 3 bit device type
 566  *  @phy_data: Pointer to read data from the register
 567  **/
 568 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 569                            u32 device_type, u32 *data)
 570 {
 571         u32 i, command, error;
 572
 573         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 574                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 575
 576         /* Write IOSF control register */
 577         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 578
 579         /*
 580          * Check every 10 usec to see if the address cycle completed.
 581          * The SB IOSF BUSY bit will clear when the operation is
 582          * complete
 583          */
 584         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 585                 usec_delay(10);
 586
 587                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 588                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 589                         break;
 590         }
 591
 592         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 593                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 594                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 595                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 596                                 "Failed to read, error %x\n", error);
 597                 return IXGBE_ERR_PHY;
 598         }
 599
 600         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 601                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 602                 return IXGBE_ERR_PHY;
 603         }
 604
 605         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 606
 607         return IXGBE_SUCCESS;
 608 }
 609
 610 /**
 611  *  ixgbe_disable_mdd_X550
 612  *  @hw: pointer to hardware structure
 613  *
 614  *  Disable malicious driver detection
 615  **/
 616 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 617 {
 618         u32 reg;
 619
 620         DEBUGFUNC("ixgbe_disable_mdd_X550");
 621
 622         /* Disable MDD for TX DMA and interrupt */
 623         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 624         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 625         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 626
 627         /* Disable MDD for RX and interrupt */
 628         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 629         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 630         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 631 }
 632
 633 /**
 634  *  ixgbe_enable_mdd_X550
 635  *  @hw: pointer to hardware structure
 636  *
 637  *  Enable malicious driver detection
 638  **/
 639 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 640 {
 641         u32 reg;
 642
 643         DEBUGFUNC("ixgbe_enable_mdd_X550");
 644
 645         /* Enable MDD for TX DMA and interrupt */
 646         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 647         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 648         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 649
 650         /* Enable MDD for RX and interrupt */
 651         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 652         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 653         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 654 }
 655
 656 /**
 657  *  ixgbe_restore_mdd_vf_X550
 658  *  @hw: pointer to hardware structure
 659  *  @vf: vf index
 660  *
 661  *  Restore VF that was disabled during malicious driver detection event
 662  **/
 663 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 664 {
 665         u32 idx, reg, num_qs, start_q, bitmask;
 666
 667         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 668
 669         /* Map VF to queues */
 670         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 671         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 672         case IXGBE_MRQC_VMDQRT8TCEN:
 673                 num_qs = 8;  /* 16 VFs / pools */
 674                 bitmask = 0x000000FF;
 675                 break;
 676         case IXGBE_MRQC_VMDQRSS32EN:
 677         case IXGBE_MRQC_VMDQRT4TCEN:
 678                 num_qs = 4;  /* 32 VFs / pools */
 679                 bitmask = 0x0000000F;
 680                 break;
 681         default:            /* 64 VFs / pools */
 682                 num_qs = 2;
 683                 bitmask = 0x00000003;
 684                 break;
 685         }
 686         start_q = vf * num_qs;
 687
 688         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 689         idx = start_q / 32;
 690         reg = 0;
 691         reg |= (bitmask << (start_q % 32));
 692         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 693         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 694 }
 695
 696 /**
 697  *  ixgbe_mdd_event_X550
 698  *  @hw: pointer to hardware structure
 699  *  @vf_bitmap: vf bitmap of malicious vfs
 700  *
 701  *  Handle malicious driver detection event.
 702  **/
 703 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 704 {
 705         u32 wqbr;
 706         u32 i, j, reg, q, shift, vf, idx;
 707
 708         DEBUGFUNC("ixgbe_mdd_event_X550");
 709
 710         /* figure out pool size for mapping to vf's */
 711         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 712         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 713         case IXGBE_MRQC_VMDQRT8TCEN:
 714                 shift = 3;  /* 16 VFs / pools */
 715                 break;
 716         case IXGBE_MRQC_VMDQRSS32EN:
 717         case IXGBE_MRQC_VMDQRT4TCEN:
 718                 shift = 2;  /* 32 VFs / pools */
 719                 break;
 720         default:
 721                 shift = 1;  /* 64 VFs / pools */
 722                 break;
 723         }
 724
 725         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 726         for (i = 0; i < 4; i++) {
 727                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 728                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 729
 730                 if (!wqbr)
 731                         continue;
 732
 733                 /* Get malicious queue */
 734                 for (j = 0; j < 32 && wqbr; j++) {
 735
 736                         if (!(wqbr & (1 << j)))
 737                                 continue;
 738
 739                         /* Get queue from bitmask */
 740                         q = j + (i * 32);
 741
 742                         /* Map queue to vf */
 743                         vf = (q >> shift);
 744
 745                         /* Set vf bit in vf_bitmap */
 746                         idx = vf / 32;
 747                         vf_bitmap[idx] |= (1 << (vf % 32));
 748                         wqbr &= ~(1 << j);
 749                 }
 750         }
 751 }
 752
 753 /**
 754  *  ixgbe_get_media_type_X550em - Get media type
 755  *  @hw: pointer to hardware structure
 756  *
 757  *  Returns the media type (fiber, copper, backplane)
 758  */
 759 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 760 {
 761         enum ixgbe_media_type media_type;
 762
 763         DEBUGFUNC("ixgbe_get_media_type_X550em");
 764
 765         /* Detect if there is a copper PHY attached. */
 766         switch (hw->device_id) {
 767         case IXGBE_DEV_ID_X550EM_X_KR:
 768         case IXGBE_DEV_ID_X550EM_X_KX4:
 769                 media_type = ixgbe_media_type_backplane;
 770                 break;
 771         case IXGBE_DEV_ID_X550EM_X_SFP:
 772                 media_type = ixgbe_media_type_fiber;
 773                 break;
 774         case IXGBE_DEV_ID_X550EM_X_1G_T:
 775         case IXGBE_DEV_ID_X550EM_X_10G_T:
 776                 media_type = ixgbe_media_type_copper;
 777                 break;
 778         default:
 779                 media_type = ixgbe_media_type_unknown;
 780                 break;
 781         }
 782         return media_type;
 783 }
 784
 785 /**
 786  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 787  *  @hw: pointer to hardware structure
 788  */
 789 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 790 {
 791         bool setup_linear;
 792         u16 reg_slice, edc_mode;
 793         s32 ret_val;
 794
 795         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 796
 797         switch (hw->phy.sfp_type) {
 798         case ixgbe_sfp_type_unknown:
 799                 return IXGBE_SUCCESS;
 800         case ixgbe_sfp_type_not_present:
 801                 return IXGBE_ERR_SFP_NOT_PRESENT;
 802         case ixgbe_sfp_type_da_cu_core0:
 803         case ixgbe_sfp_type_da_cu_core1:
 804                 setup_linear = true;
 805                 break;
 806         case ixgbe_sfp_type_srlr_core0:
 807         case ixgbe_sfp_type_srlr_core1:
 808         case ixgbe_sfp_type_da_act_lmt_core0:
 809         case ixgbe_sfp_type_da_act_lmt_core1:
 810         case ixgbe_sfp_type_1g_sx_core0:
 811         case ixgbe_sfp_type_1g_sx_core1:
 812         case ixgbe_sfp_type_1g_lx_core0:
 813         case ixgbe_sfp_type_1g_lx_core1:
 814                 setup_linear = false;
 815                 break;
 816         default:
 817                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 818         }
 819
 820         ixgbe_init_mac_link_ops_X550em(hw);
 821         hw->phy.ops.reset = NULL;
 822
 823         /* The CS4227 slice address is the base address + the port-pair reg
 824          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 825          */
 826         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
 827
 828         if (setup_linear)
 829                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 830         else
 831                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 832
 833         /* Configure CS4227 for connection type. */
 834         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 835                                            edc_mode);
 836
 837         if (ret_val != IXGBE_SUCCESS)
 838                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 839                                                    edc_mode);
 840
 841         return ret_val;
 842 }
 843
 844 /**
 845  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 846  *  @hw: pointer to hardware structure
 847  */
 848 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 849 {
 850         struct ixgbe_mac_info *mac = &hw->mac;
 851
 852         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 853
 854         /* CS4227 does not support autoneg, so disable the laser control
 855          * functions for SFP+ fiber
 856          */
 857          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 858                 mac->ops.disable_tx_laser = NULL;
 859                 mac->ops.enable_tx_laser = NULL;
 860                 mac->ops.flap_tx_laser = NULL;
 861          }
 862 }
 863
 864 /**
 865  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 866  *  @hw: pointer to hardware structure
 867  *  @speed: pointer to link speed
 868  *  @autoneg: true when autoneg or autotry is enabled
 869  */
 870 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 871                                        ixgbe_link_speed *speed,
 872                                        bool *autoneg)
 873 {
 874         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 875
 876         /* SFP */
 877         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 878
 879                 /* CS4227 SFP must not enable auto-negotiation */
 880                 *autoneg = false;
 881
 882                 /* Check if 1G SFP module. */
 883                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 884                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 885                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 886                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 887                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 888                         return IXGBE_SUCCESS;
 889                 }
 890
 891                 /* Link capabilities are based on SFP */
 892                 if (hw->phy.multispeed_fiber)
 893                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 894                                  IXGBE_LINK_SPEED_1GB_FULL;
 895                 else
 896                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 897         } else {
 898                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 899                          IXGBE_LINK_SPEED_1GB_FULL;
 900                 *autoneg = true;
 901         }
 902
 903         return IXGBE_SUCCESS;
 904 }
 905
 906 /**
 907  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 908  *  @hw: pointer to hardware structure
 909  *
 910  *  Initialize any function pointers that were not able to be
 911  *  set during init_shared_code because the PHY/SFP type was
 912  *  not known.  Perform the SFP init if necessary.
 913  */
 914 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 915 {
 916         struct ixgbe_phy_info *phy = &hw->phy;
 917         s32 ret_val;
 918         u32 esdp;
 919
 920         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 921
 922         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 923                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 924                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 925
 926                 if (hw->bus.lan_id) {
 927                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 928                         esdp |= IXGBE_ESDP_SDP1_DIR;
 929                 }
 930                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 931                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 932         }
 933
 934         /* Identify the PHY or SFP module */
 935         ret_val = phy->ops.identify(hw);
 936         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 937                 return ret_val;
 938
 939         /* Setup function pointers based on detected SFP module and speeds */
 940         ixgbe_init_mac_link_ops_X550em(hw);
 941         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 942                 phy->ops.reset = NULL;
 943
 944         /* Set functions pointers based on phy type */
 945         switch (hw->phy.type) {
 946         case ixgbe_phy_x550em_kx4:
 947                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
 948                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 949                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 950                 break;
 951         case ixgbe_phy_x550em_kr:
 952                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 953                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 954                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 955                 break;
 956         case ixgbe_phy_x550em_ext_t:
 957                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
 958                 break;
 959         default:
 960                 break;
 961         }
 962         return ret_val;
 963 }
 964
 965 /**
 966  *  ixgbe_reset_hw_X550em - Perform hardware reset
 967  *  @hw: pointer to hardware structure
 968  *
 969  *  Resets the hardware by resetting the transmit and receive units, masks
 970  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 971  *  reset.
 972  */
 973 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 974 {
 975         struct ixgbe_hic_hdr fw_cmd;
 976         ixgbe_link_speed link_speed;
 977         s32 status;
 978         u32 ctrl = 0;
 979         u32 i;
 980         bool link_up = false;
 981
 982         DEBUGFUNC("ixgbe_reset_hw_X550em");
 983
 984         fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD;
 985         fw_cmd.buf_len = 0;
 986         fw_cmd.cmd_or_resp.cmd_resv = 0;
 987         fw_cmd.checksum = FW_DEFAULT_CHECKSUM;
 988         status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 989                                               sizeof(fw_cmd),
 990                                               IXGBE_HI_PHY_MGMT_REQ_TIMEOUT,
 991                                               true);
 992         if (status)
 993                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 994                               "PHY mgmt command failed with %d\n", status);
 995         else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS)
 996                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 997                               "PHY mgmt command returned %d\n",
 998                               fw_cmd.cmd_or_resp.ret_status);
 999
1000         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1001         status = hw->mac.ops.stop_adapter(hw);
1002         if (status != IXGBE_SUCCESS)
1003                 return status;
1004
1005         /* flush pending Tx transactions */
1006         ixgbe_clear_tx_pending(hw);
1007
1008         /* PHY ops must be identified and initialized prior to reset */
1009
1010         /* Identify PHY and related function pointers */
1011         status = hw->phy.ops.init(hw);
1012
1013         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1014                 return status;
1015
1016         /* start the external PHY */
1017         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1018                 status = ixgbe_init_ext_t_x550em(hw);
1019                 if (status)
1020                         return status;
1021         }
1022
1023         /* Setup SFP module if there is one present. */
1024         if (hw->phy.sfp_setup_needed) {
1025                 status = hw->mac.ops.setup_sfp(hw);
1026                 hw->phy.sfp_setup_needed = false;
1027         }
1028
1029         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1030                 return status;
1031
1032         /* Reset PHY */
1033         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1034                 hw->phy.ops.reset(hw);
1035
1036 mac_reset_top:
1037         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1038          * If link reset is used when link is up, it might reset the PHY when
1039          * mng is using it.  If link is down or the flag to force full link
1040          * reset is set, then perform link reset.
1041          */
1042         ctrl = IXGBE_CTRL_LNK_RST;
1043         if (!hw->force_full_reset) {
1044                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1045                 if (link_up)
1046                         ctrl = IXGBE_CTRL_RST;
1047         }
1048
1049         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1050         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1051         IXGBE_WRITE_FLUSH(hw);
1052
1053         /* Poll for reset bit to self-clear meaning reset is complete */
1054         for (i = 0; i < 10; i++) {
1055                 usec_delay(1);
1056                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1057                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1058                         break;
1059         }
1060
1061         if (ctrl & IXGBE_CTRL_RST_MASK) {
1062                 status = IXGBE_ERR_RESET_FAILED;
1063                 DEBUGOUT("Reset polling failed to complete.\n");
1064         }
1065
1066         msec_delay(50);
1067
1068         /* Double resets are required for recovery from certain error
1069          * conditions.  Between resets, it is necessary to stall to
1070          * allow time for any pending HW events to complete.
1071          */
1072         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1073                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1074                 goto mac_reset_top;
1075         }
1076
1077         /* Store the permanent mac address */
1078         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1079
1080         /* Store MAC address from RAR0, clear receive address registers, and
1081          * clear the multicast table.  Also reset num_rar_entries to 128,
1082          * since we modify this value when programming the SAN MAC address.
1083          */
1084         hw->mac.num_rar_entries = 128;
1085         hw->mac.ops.init_rx_addrs(hw);
1086
1087
1088         return status;
1089 }
1090
1091 /**
1092  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1093  * @hw: pointer to hardware structure
1094  */
1095 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1096 {
1097         u32 status;
1098         u16 reg;
1099         u32 retries = 1;
1100
1101         /* TODO: The number of attempts and delay between attempts is undefined */
1102         do {
1103                 /* decrement retries counter and exit if we hit 0 */
1104                 if (retries < 1) {
1105                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1106                                       "External PHY not yet finished resetting.");
1107                         return IXGBE_ERR_PHY;
1108                 }
1109                 retries--;
1110
1111                 usec_delay(0);
1112
1113                 status = hw->phy.ops.read_reg(hw,
1114                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1115                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1116                                               &reg);
1117
1118                 if (status != IXGBE_SUCCESS)
1119                         return status;
1120
1121                 /* Verify PHY FW reset has completed */
1122         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1123
1124         /* Set port to low power mode */
1125         status = hw->phy.ops.read_reg(hw,
1126                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1127                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1128                                       &reg);
1129
1130         if (status != IXGBE_SUCCESS)
1131                 return status;
1132
1133         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1134
1135         status = hw->phy.ops.write_reg(hw,
1136                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1137                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1138                                        reg);
1139
1140         if (status != IXGBE_SUCCESS)
1141                 return status;
1142
1143         /* Enable the transmitter */
1144         status = hw->phy.ops.read_reg(hw,
1145                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1146                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1147                                       &reg);
1148
1149         if (status != IXGBE_SUCCESS)
1150                 return status;
1151
1152         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1153
1154         status = hw->phy.ops.write_reg(hw,
1155                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1156                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1157                                        reg);
1158
1159         if (status != IXGBE_SUCCESS)
1160                 return status;
1161
1162         /* Un-stall the PHY FW */
1163         status = hw->phy.ops.read_reg(hw,
1164                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1165                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1166                                       &reg);
1167
1168         if (status != IXGBE_SUCCESS)
1169                 return status;
1170
1171         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1172
1173         status = hw->phy.ops.write_reg(hw,
1174                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1175                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1176                                        reg);
1177
1178         return status;
1179 }
1180
1181 /**
1182  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1183  *  @hw: pointer to hardware structure
1184  *
1185  *  Configures the integrated KR PHY.
1186  **/
1187 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1188 {
1189         s32 status;
1190         u32 reg_val;
1191
1192         status = ixgbe_read_iosf_sb_reg_x550(hw,
1193                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1194                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1195         if (status)
1196                 return status;
1197
1198         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1199         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1200         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1201         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1202                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1203
1204         /* Advertise 10G support. */
1205         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1206                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1207
1208         /* Advertise 1G support. */
1209         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1210                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1211
1212         /* Restart auto-negotiation. */
1213         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1214         status = ixgbe_write_iosf_sb_reg_x550(hw,
1215                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1216                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1217
1218         return status;
1219 }
1220
1221 /**
1222  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1223  *  @hw: pointer to hardware structure
1224  *
1225  *  Configures the integrated KX4 PHY.
1226  **/
1227 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1228 {
1229         s32 status;
1230         u32 reg_val;
1231
1232         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1233                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1234         if (status)
1235                 return status;
1236
1237         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1238                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1239
1240         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1241
1242         /* Advertise 10G support. */
1243         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1244                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1245
1246         /* Advertise 1G support. */
1247         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1248                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1249
1250         /* Restart auto-negotiation. */
1251         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1252         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1253                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1254
1255         return status;
1256 }
1257
1258 /**
1259  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1260  *  @hw: pointer to hardware structure
1261  *  @speed: the link speed to force
1262  *
1263  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1264  *  internal and external PHY at a specific speed, without autonegotiation.
1265  **/
1266 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1267 {
1268         s32 status;
1269         u32 reg_val;
1270
1271         /* Disable AN and force speed to 10G Serial. */
1272         status = ixgbe_read_iosf_sb_reg_x550(hw,
1273                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1274                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1275         if (status != IXGBE_SUCCESS)
1276                 return status;
1277
1278         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1279         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1280
1281         /* Select forced link speed for internal PHY. */
1282         switch (*speed) {
1283         case IXGBE_LINK_SPEED_10GB_FULL:
1284                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1285                 break;
1286         case IXGBE_LINK_SPEED_1GB_FULL:
1287                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1288                 break;
1289         default:
1290                 /* Other link speeds are not supported by internal KR PHY. */
1291                 return IXGBE_ERR_LINK_SETUP;
1292         }
1293
1294         status = ixgbe_write_iosf_sb_reg_x550(hw,
1295                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1296                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1297         if (status != IXGBE_SUCCESS)
1298                 return status;
1299
1300         /* Disable training protocol FSM. */
1301         status = ixgbe_read_iosf_sb_reg_x550(hw,
1302                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1303                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1304         if (status != IXGBE_SUCCESS)
1305                 return status;
1306         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1307         status = ixgbe_write_iosf_sb_reg_x550(hw,
1308                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1309                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1310         if (status != IXGBE_SUCCESS)
1311                 return status;
1312
1313         /* Disable Flex from training TXFFE. */
1314         status = ixgbe_read_iosf_sb_reg_x550(hw,
1315                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1316                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1317         if (status != IXGBE_SUCCESS)
1318                 return status;
1319         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1320         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1321         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1322         status = ixgbe_write_iosf_sb_reg_x550(hw,
1323                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1324                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1325         if (status != IXGBE_SUCCESS)
1326                 return status;
1327         status = ixgbe_read_iosf_sb_reg_x550(hw,
1328                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1329                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1330         if (status != IXGBE_SUCCESS)
1331                 return status;
1332         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1333         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1334         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1335         status = ixgbe_write_iosf_sb_reg_x550(hw,
1336                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1337                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1338         if (status != IXGBE_SUCCESS)
1339                 return status;
1340
1341         /* Enable override for coefficients. */
1342         status = ixgbe_read_iosf_sb_reg_x550(hw,
1343                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1344                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1345         if (status != IXGBE_SUCCESS)
1346                 return status;
1347         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1348         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1349         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1350         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1351         status = ixgbe_write_iosf_sb_reg_x550(hw,
1352                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1353                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1354         if (status != IXGBE_SUCCESS)
1355                 return status;
1356
1357         /* Toggle port SW reset by AN reset. */
1358         status = ixgbe_read_iosf_sb_reg_x550(hw,
1359                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1360                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1361         if (status != IXGBE_SUCCESS)
1362                 return status;
1363         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1364         status = ixgbe_write_iosf_sb_reg_x550(hw,
1365                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1366                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1367
1368         return status;
1369 }
1370
1371 /**
1372  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1373  * @hw: point to hardware structure
1374  *
1375  * Configures the integrated KR PHY to talk to the external PHY. The base
1376  * driver will call this function when it gets notification via interrupt from
1377  * the external PHY. This function forces the internal PHY into iXFI mode at
1378  * the correct speed.
1379  *
1380  * A return of a non-zero value indicates an error, and the base driver should
1381  * not report link up.
1382  */
1383 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1384 {
1385         u32 status;
1386         u16 lasi, autoneg_status, speed;
1387         ixgbe_link_speed force_speed;
1388
1389         /* Verify that the external link status has changed */
1390         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1391                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1392                                       &lasi);
1393         if (status != IXGBE_SUCCESS)
1394                 return status;
1395
1396         /* If there was no change in link status, we can just exit */
1397         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1398                 return IXGBE_SUCCESS;
1399
1400         /* we read this twice back to back to indicate current status */
1401         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1402                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1403                                       &autoneg_status);
1404         if (status != IXGBE_SUCCESS)
1405                 return status;
1406
1407         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1408                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1409                                       &autoneg_status);
1410         if (status != IXGBE_SUCCESS)
1411                 return status;
1412
1413         /* If link is not up return an error indicating treat link as down */
1414         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1415                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1416
1417         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1418                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1419                                       &speed);
1420
1421         /* clear everything but the speed and duplex bits */
1422         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1423
1424         switch (speed) {
1425         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1426                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1427                 break;
1428         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1429                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1430                 break;
1431         default:
1432                 /* Internal PHY does not support anything else */
1433                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1434         }
1435
1436         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1437 }
1438
1439 /**
1440  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1441  *  @hw: pointer to hardware structure
1442  *
1443  *  Configures the integrated KR PHY to use internal loopback mode.
1444  **/
1445 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1446 {
1447         s32 status;
1448         u32 reg_val;
1449
1450         /* Disable AN and force speed to 10G Serial. */
1451         status = ixgbe_read_iosf_sb_reg_x550(hw,
1452                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1453                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1454         if (status != IXGBE_SUCCESS)
1455                 return status;
1456         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1457         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1458         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1459         status = ixgbe_write_iosf_sb_reg_x550(hw,
1460                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1461                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1462         if (status != IXGBE_SUCCESS)
1463                 return status;
1464
1465         /* Set near-end loopback clocks. */
1466         status = ixgbe_read_iosf_sb_reg_x550(hw,
1467                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1468                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1469         if (status != IXGBE_SUCCESS)
1470                 return status;
1471         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1472         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1473         status = ixgbe_write_iosf_sb_reg_x550(hw,
1474                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1475                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1476         if (status != IXGBE_SUCCESS)
1477                 return status;
1478
1479         /* Set loopback enable. */
1480         status = ixgbe_read_iosf_sb_reg_x550(hw,
1481                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1482                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1483         if (status != IXGBE_SUCCESS)
1484                 return status;
1485         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1486         status = ixgbe_write_iosf_sb_reg_x550(hw,
1487                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1488                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1489         if (status != IXGBE_SUCCESS)
1490                 return status;
1491
1492         /* Training bypass. */
1493         status = ixgbe_read_iosf_sb_reg_x550(hw,
1494                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1495                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1496         if (status != IXGBE_SUCCESS)
1497                 return status;
1498         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1499         status = ixgbe_write_iosf_sb_reg_x550(hw,
1500                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1501                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1502
1503         return status;
1504 }
1505
1506 /**
1507  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1508  *  assuming that the semaphore is already obtained.
1509  *  @hw: pointer to hardware structure
1510  *  @offset: offset of  word in the EEPROM to read
1511  *  @data: word read from the EEPROM
1512  *
1513  *  Reads a 16 bit word from the EEPROM using the hostif.
1514  **/
1515 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1516                                    u16 *data)
1517 {
1518         s32 status;
1519         struct ixgbe_hic_read_shadow_ram buffer;
1520
1521         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1522         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1523         buffer.hdr.req.buf_lenh = 0;
1524         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1525         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1526
1527         /* convert offset from words to bytes */
1528         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1529         /* one word */
1530         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1531
1532         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1533                                               sizeof(buffer),
1534                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1535
1536         if (status)
1537                 return status;
1538
1539         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1540                                           FW_NVM_DATA_OFFSET);
1541
1542         return 0;
1543 }
1544
1545 /**
1546  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1547  *  @hw: pointer to hardware structure
1548  *  @offset: offset of  word in the EEPROM to read
1549  *  @data: word read from the EEPROM
1550  *
1551  *  Reads a 16 bit word from the EEPROM using the hostif.
1552  **/
1553 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1554                               u16 *data)
1555 {
1556         s32 status = IXGBE_SUCCESS;
1557
1558         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1559
1560         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1561             IXGBE_SUCCESS) {
1562                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1563                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1564         } else {
1565                 status = IXGBE_ERR_SWFW_SYNC;
1566         }
1567
1568         return status;
1569 }
1570
1571 /**
1572  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1573  *  @hw: pointer to hardware structure
1574  *  @offset: offset of  word in the EEPROM to read
1575  *  @words: number of words
1576  *  @data: word(s) read from the EEPROM
1577  *
1578  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1579  **/
1580 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1581                                      u16 offset, u16 words, u16 *data)
1582 {
1583         struct ixgbe_hic_read_shadow_ram buffer;
1584         u32 current_word = 0;
1585         u16 words_to_read;
1586         s32 status;
1587         u32 i;
1588
1589         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1590
1591         /* Take semaphore for the entire operation. */
1592         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1593         if (status) {
1594                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1595                 return status;
1596         }
1597         while (words) {
1598                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1599                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1600                 else
1601                         words_to_read = words;
1602
1603                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1604                 buffer.hdr.req.buf_lenh = 0;
1605                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1606                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1607
1608                 /* convert offset from words to bytes */
1609                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1610                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1611
1612                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1613                                                       sizeof(buffer),
1614                                                       IXGBE_HI_COMMAND_TIMEOUT,
1615                                                       false);
1616
1617                 if (status) {
1618                         DEBUGOUT("Host interface command failed\n");
1619                         goto out;
1620                 }
1621
1622                 for (i = 0; i < words_to_read; i++) {
1623                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1624                                   2 * i;
1625                         u32 value = IXGBE_READ_REG(hw, reg);
1626
1627                         data[current_word] = (u16)(value & 0xffff);
1628                         current_word++;
1629                         i++;
1630                         if (i < words_to_read) {
1631                                 value >>= 16;
1632                                 data[current_word] = (u16)(value & 0xffff);
1633                                 current_word++;
1634                         }
1635                 }
1636                 words -= words_to_read;
1637         }
1638
1639 out:
1640         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1641         return status;
1642 }
1643
1644 /**
1645  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1646  *  @hw: pointer to hardware structure
1647  *  @offset: offset of  word in the EEPROM to write
1648  *  @data: word write to the EEPROM
1649  *
1650  *  Write a 16 bit word to the EEPROM using the hostif.
1651  **/
1652 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1653                                     u16 data)
1654 {
1655         s32 status;
1656         struct ixgbe_hic_write_shadow_ram buffer;
1657
1658         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1659
1660         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1661         buffer.hdr.req.buf_lenh = 0;
1662         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1663         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1664
1665          /* one word */
1666         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1667         buffer.data = data;
1668         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1669
1670         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1671                                               sizeof(buffer),
1672                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1673
1674         return status;
1675 }
1676
1677 /**
1678  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1679  *  @hw: pointer to hardware structure
1680  *  @offset: offset of  word in the EEPROM to write
1681  *  @data: word write to the EEPROM
1682  *
1683  *  Write a 16 bit word to the EEPROM using the hostif.
1684  **/
1685 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1686                                u16 data)
1687 {
1688         s32 status = IXGBE_SUCCESS;
1689
1690         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1691
1692         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1693             IXGBE_SUCCESS) {
1694                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1695                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1696         } else {
1697                 DEBUGOUT("write ee hostif failed to get semaphore");
1698                 status = IXGBE_ERR_SWFW_SYNC;
1699         }
1700
1701         return status;
1702 }
1703
1704 /**
1705  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1706  *  @hw: pointer to hardware structure
1707  *  @offset: offset of  word in the EEPROM to write
1708  *  @words: number of words
1709  *  @data: word(s) write to the EEPROM
1710  *
1711  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1712  **/
1713 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1714                                       u16 offset, u16 words, u16 *data)
1715 {
1716         s32 status = IXGBE_SUCCESS;
1717         u32 i = 0;
1718
1719         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1720
1721         /* Take semaphore for the entire operation. */
1722         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1723         if (status != IXGBE_SUCCESS) {
1724                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1725                 goto out;
1726         }
1727
1728         for (i = 0; i < words; i++) {
1729                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1730                                                          data[i]);
1731
1732                 if (status != IXGBE_SUCCESS) {
1733                         DEBUGOUT("Eeprom buffered write failed\n");
1734                         break;
1735                 }
1736         }
1737
1738         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1739 out:
1740
1741         return status;
1742 }
1743
1744 /**
1745  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1746  * @hw: pointer to hardware structure
1747  * @ptr: pointer offset in eeprom
1748  * @size: size of section pointed by ptr, if 0 first word will be used as size
1749  * @csum: address of checksum to update
1750  *
1751  * Returns error status for any failure
1752  */
1753 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1754                                    u16 size, u16 *csum, u16 *buffer,
1755                                    u32 buffer_size)
1756 {
1757         u16 buf[256];
1758         s32 status;
1759         u16 length, bufsz, i, start;
1760         u16 *local_buffer;
1761
1762         bufsz = sizeof(buf) / sizeof(buf[0]);
1763
1764         /* Read a chunk at the pointer location */
1765         if (!buffer) {
1766                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1767                 if (status) {
1768                         DEBUGOUT("Failed to read EEPROM image\n");
1769                         return status;
1770                 }
1771                 local_buffer = buf;
1772         } else {
1773                 if (buffer_size < ptr)
1774                         return  IXGBE_ERR_PARAM;
1775                 local_buffer = &buffer[ptr];
1776         }
1777
1778         if (size) {
1779                 start = 0;
1780                 length = size;
1781         } else {
1782                 start = 1;
1783                 length = local_buffer[0];
1784
1785                 /* Skip pointer section if length is invalid. */
1786                 if (length == 0xFFFF || length == 0 ||
1787                     (ptr + length) >= hw->eeprom.word_size)
1788                         return IXGBE_SUCCESS;
1789         }
1790
1791         if (buffer && ((u32)start + (u32)length > buffer_size))
1792                 return IXGBE_ERR_PARAM;
1793
1794         for (i = start; length; i++, length--) {
1795                 if (i == bufsz && !buffer) {
1796                         ptr += bufsz;
1797                         i = 0;
1798                         if (length < bufsz)
1799                                 bufsz = length;
1800
1801                         /* Read a chunk at the pointer location */
1802                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1803                                                                   bufsz, buf);
1804                         if (status) {
1805                                 DEBUGOUT("Failed to read EEPROM image\n");
1806                                 return status;
1807                         }
1808                 }
1809                 *csum += local_buffer[i];
1810         }
1811         return IXGBE_SUCCESS;
1812 }
1813
1814 /**
1815  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1816  *  @hw: pointer to hardware structure
1817  *  @buffer: pointer to buffer containing calculated checksum
1818  *  @buffer_size: size of buffer
1819  *
1820  *  Returns a negative error code on error, or the 16-bit checksum
1821  **/
1822 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1823 {
1824         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1825         u16 *local_buffer;
1826         s32 status;
1827         u16 checksum = 0;
1828         u16 pointer, i, size;
1829
1830         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1831
1832         hw->eeprom.ops.init_params(hw);
1833
1834         if (!buffer) {
1835                 /* Read pointer area */
1836                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1837                                                      IXGBE_EEPROM_LAST_WORD + 1,
1838                                                      eeprom_ptrs);
1839                 if (status) {
1840                         DEBUGOUT("Failed to read EEPROM image\n");
1841                         return status;
1842                 }
1843                 local_buffer = eeprom_ptrs;
1844         } else {
1845                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1846                         return IXGBE_ERR_PARAM;
1847                 local_buffer = buffer;
1848         }
1849
1850         /*
1851          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1852          * checksum word itself
1853          */
1854         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1855                 if (i != IXGBE_EEPROM_CHECKSUM)
1856                         checksum += local_buffer[i];
1857
1858         /*
1859          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1860          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1861          */
1862         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1863                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1864                         continue;
1865
1866                 pointer = local_buffer[i];
1867
1868                 /* Skip pointer section if the pointer is invalid. */
1869                 if (pointer == 0xFFFF || pointer == 0 ||
1870                     pointer >= hw->eeprom.word_size)
1871                         continue;
1872
1873                 switch (i) {
1874                 case IXGBE_PCIE_GENERAL_PTR:
1875                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1876                         break;
1877                 case IXGBE_PCIE_CONFIG0_PTR:
1878                 case IXGBE_PCIE_CONFIG1_PTR:
1879                         size = IXGBE_PCIE_CONFIG_SIZE;
1880                         break;
1881                 default:
1882                         size = 0;
1883                         break;
1884                 }
1885
1886                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1887                                                 buffer, buffer_size);
1888                 if (status)
1889                         return status;
1890         }
1891
1892         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1893
1894         return (s32)checksum;
1895 }
1896
1897 /**
1898  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1899  *  @hw: pointer to hardware structure
1900  *
1901  *  Returns a negative error code on error, or the 16-bit checksum
1902  **/
1903 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1904 {
1905         return ixgbe_calc_checksum_X550(hw, NULL, 0);
1906 }
1907
1908 /**
1909  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1910  *  @hw: pointer to hardware structure
1911  *  @checksum_val: calculated checksum
1912  *
1913  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1914  *  caller does not need checksum_val, the value can be NULL.
1915  **/
1916 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1917 {
1918         s32 status;
1919         u16 checksum;
1920         u16 read_checksum = 0;
1921
1922         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1923
1924         /* Read the first word from the EEPROM. If this times out or fails, do
1925          * not continue or we could be in for a very long wait while every
1926          * EEPROM read fails
1927          */
1928         status = hw->eeprom.ops.read(hw, 0, &checksum);
1929         if (status) {
1930                 DEBUGOUT("EEPROM read failed\n");
1931                 return status;
1932         }
1933
1934         status = hw->eeprom.ops.calc_checksum(hw);
1935         if (status < 0)
1936                 return status;
1937
1938         checksum = (u16)(status & 0xffff);
1939
1940         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1941                                            &read_checksum);
1942         if (status)
1943                 return status;
1944
1945         /* Verify read checksum from EEPROM is the same as
1946          * calculated checksum
1947          */
1948         if (read_checksum != checksum) {
1949                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1950                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1951                              "Invalid EEPROM checksum");
1952         }
1953
1954         /* If the user cares, return the calculated checksum */
1955         if (checksum_val)
1956                 *checksum_val = checksum;
1957
1958         return status;
1959 }
1960
1961 /**
1962  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1963  * @hw: pointer to hardware structure
1964  *
1965  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1966  * checksum and updates the EEPROM and instructs the hardware to update
1967  * the flash.
1968  **/
1969 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1970 {
1971         s32 status;
1972         u16 checksum = 0;
1973
1974         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1975
1976         /* Read the first word from the EEPROM. If this times out or fails, do
1977          * not continue or we could be in for a very long wait while every
1978          * EEPROM read fails
1979          */
1980         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1981         if (status) {
1982                 DEBUGOUT("EEPROM read failed\n");
1983                 return status;
1984         }
1985
1986         status = ixgbe_calc_eeprom_checksum_X550(hw);
1987         if (status < 0)
1988                 return status;
1989
1990         checksum = (u16)(status & 0xffff);
1991
1992         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1993                                             checksum);
1994         if (status)
1995                 return status;
1996
1997         status = ixgbe_update_flash_X550(hw);
1998
1999         return status;
2000 }
2001
2002 /**
2003  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2004  *  @hw: pointer to hardware structure
2005  *
2006  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2007  **/
2008 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2009 {
2010         s32 status = IXGBE_SUCCESS;
2011         union ixgbe_hic_hdr2 buffer;
2012
2013         DEBUGFUNC("ixgbe_update_flash_X550");
2014
2015         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2016         buffer.req.buf_lenh = 0;
2017         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2018         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2019
2020         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2021                                               sizeof(buffer),
2022                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2023
2024         return status;
2025 }
2026
2027 /**
2028  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2029  *  @hw: pointer to hardware structure
2030  *
2031  *  Determines physical layer capabilities of the current configuration.
2032  **/
2033 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2034 {
2035         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2036         u16 ext_ability = 0;
2037
2038         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2039
2040         hw->phy.ops.identify(hw);
2041
2042         switch (hw->phy.type) {
2043         case ixgbe_phy_x550em_kr:
2044                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2045                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2046                 break;
2047         case ixgbe_phy_x550em_kx4:
2048                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2049                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2050                 break;
2051         case ixgbe_phy_x550em_ext_t:
2052                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2053                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2054                                      &ext_ability);
2055                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2056                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2057                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2058                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2059                 break;
2060         default:
2061                 break;
2062         }
2063
2064         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2065                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2066
2067         return physical_layer;
2068 }
2069
2070 /**
2071  * ixgbe_get_bus_info_x550em - Set PCI bus info
2072  * @hw: pointer to hardware structure
2073  *
2074  * Sets bus link width and speed to unknown because X550em is
2075  * not a PCI device.
2076  **/
2077 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2078 {
2079
2080         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2081
2082         hw->bus.width = ixgbe_bus_width_unknown;
2083         hw->bus.speed = ixgbe_bus_speed_unknown;
2084
2085         return IXGBE_SUCCESS;
2086 }
2087
2088 /**
2089  * ixgbe_disable_rx_x550 - Disable RX unit
2090  *
2091  * Enables the Rx DMA unit for x550
2092  **/
2093 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2094 {
2095         u32 rxctrl, pfdtxgswc;
2096         s32 status;
2097         struct ixgbe_hic_disable_rxen fw_cmd;
2098
2099         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2100
2101         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2102         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2103                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2104                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2105                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2106                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2107                         hw->mac.set_lben = true;
2108                 } else {
2109                         hw->mac.set_lben = false;
2110                 }
2111
2112                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2113                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2114                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2115                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2116
2117                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2118                                         sizeof(struct ixgbe_hic_disable_rxen),
2119                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2120
2121                 /* If we fail - disable RX using register write */
2122                 if (status) {
2123                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2124                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2125                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2126                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2127                         }
2128                 }
2129         }
2130 }