drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
  45
  46 /**
  47  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  48  *  @hw: pointer to hardware structure
  49  *
  50  *  Initialize the function pointers and assign the MAC type for X550.
  51  *  Does not touch the hardware.
  52  **/
  53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  54 {
  55         struct ixgbe_mac_info *mac = &hw->mac;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X550");
  60
  61         ret_val = ixgbe_init_ops_X540(hw);
  62         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  63         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  64         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  65         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  66         mac->ops.set_source_address_pruning =
  67                         ixgbe_set_source_address_pruning_X550;
  68         mac->ops.set_ethertype_anti_spoofing =
  69                         ixgbe_set_ethertype_anti_spoofing_X550;
  70
  71         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  72         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  73         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  74         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  75         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  76         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  77         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  78         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  79         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  80
  81         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  82         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  83         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  84         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  85         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  86         switch (hw->device_id) {
  87         case IXGBE_DEV_ID_X550EM_X_10G_T:
  88         case IXGBE_DEV_ID_X550EM_A_10G_T:
  89                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  90                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  91                 break;
  92         default:
  93                 break;
  94         }
  95         return ret_val;
  96 }
  97
  98 /**
  99  * ixgbe_read_cs4227 - Read CS4227 register
 100  * @hw: pointer to hardware structure
 101  * @reg: register number to write
 102  * @value: pointer to receive value read
 103  *
 104  * Returns status code
 105  **/
 106 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 107 {
 108         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 109 }
 110
 111 /**
 112  * ixgbe_write_cs4227 - Write CS4227 register
 113  * @hw: pointer to hardware structure
 114  * @reg: register number to write
 115  * @value: value to write to register
 116  *
 117  * Returns status code
 118  **/
 119 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 120 {
 121         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 122 }
 123
 124 /**
 125  * ixgbe_read_pe - Read register from port expander
 126  * @hw: pointer to hardware structure
 127  * @reg: register number to read
 128  * @value: pointer to receive read value
 129  *
 130  * Returns status code
 131  **/
 132 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 133 {
 134         s32 status;
 135
 136         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 137         if (status != IXGBE_SUCCESS)
 138                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 139                               "port expander access failed with %d\n", status);
 140         return status;
 141 }
 142
 143 /**
 144  * ixgbe_write_pe - Write register to port expander
 145  * @hw: pointer to hardware structure
 146  * @reg: register number to write
 147  * @value: value to write
 148  *
 149  * Returns status code
 150  **/
 151 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 152 {
 153         s32 status;
 154
 155         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 156         if (status != IXGBE_SUCCESS)
 157                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 158                               "port expander access failed with %d\n", status);
 159         return status;
 160 }
 161
 162 /**
 163  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 164  * @hw: pointer to hardware structure
 165  *
 166  * This function assumes that the caller has acquired the proper semaphore.
 167  * Returns error code
 168  **/
 169 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 170 {
 171         s32 status;
 172         u32 retry;
 173         u16 value;
 174         u8 reg;
 175
 176         /* Trigger hard reset. */
 177         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 178         if (status != IXGBE_SUCCESS)
 179                 return status;
 180         reg |= IXGBE_PE_BIT1;
 181         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 182         if (status != IXGBE_SUCCESS)
 183                 return status;
 184
 185         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 186         if (status != IXGBE_SUCCESS)
 187                 return status;
 188         reg &= ~IXGBE_PE_BIT1;
 189         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 190         if (status != IXGBE_SUCCESS)
 191                 return status;
 192
 193         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 194         if (status != IXGBE_SUCCESS)
 195                 return status;
 196         reg &= ~IXGBE_PE_BIT1;
 197         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 198         if (status != IXGBE_SUCCESS)
 199                 return status;
 200
 201         usec_delay(IXGBE_CS4227_RESET_HOLD);
 202
 203         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 204         if (status != IXGBE_SUCCESS)
 205                 return status;
 206         reg |= IXGBE_PE_BIT1;
 207         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 208         if (status != IXGBE_SUCCESS)
 209                 return status;
 210
 211         /* Wait for the reset to complete. */
 212         msec_delay(IXGBE_CS4227_RESET_DELAY);
 213         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 214                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 215                                            &value);
 216                 if (status == IXGBE_SUCCESS &&
 217                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 218                         break;
 219                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 220         }
 221         if (retry == IXGBE_CS4227_RETRIES) {
 222                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 223                         "CS4227 reset did not complete.");
 224                 return IXGBE_ERR_PHY;
 225         }
 226
 227         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 228         if (status != IXGBE_SUCCESS ||
 229             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 230                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 231                         "CS4227 EEPROM did not load successfully.");
 232                 return IXGBE_ERR_PHY;
 233         }
 234
 235         return IXGBE_SUCCESS;
 236 }
 237
 238 /**
 239  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 240  * @hw: pointer to hardware structure
 241  **/
 242 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 243 {
 244         s32 status = IXGBE_SUCCESS;
 245         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 246         u16 value = 0;
 247         u8 retry;
 248
 249         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 250                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 251                 if (status != IXGBE_SUCCESS) {
 252                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 253                                 "semaphore failed with %d", status);
 254                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 255                         continue;
 256                 }
 257
 258                 /* Get status of reset flow. */
 259                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 260
 261                 if (status == IXGBE_SUCCESS &&
 262                     value == IXGBE_CS4227_RESET_COMPLETE)
 263                         goto out;
 264
 265                 if (status != IXGBE_SUCCESS ||
 266                     value != IXGBE_CS4227_RESET_PENDING)
 267                         break;
 268
 269                 /* Reset is pending. Wait and check again. */
 270                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 271                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 272         }
 273
 274         /* If still pending, assume other instance failed. */
 275         if (retry == IXGBE_CS4227_RETRIES) {
 276                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 277                 if (status != IXGBE_SUCCESS) {
 278                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 279                                       "semaphore failed with %d", status);
 280                         return;
 281                 }
 282         }
 283
 284         /* Reset the CS4227. */
 285         status = ixgbe_reset_cs4227(hw);
 286         if (status != IXGBE_SUCCESS) {
 287                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 288                         "CS4227 reset failed: %d", status);
 289                 goto out;
 290         }
 291
 292         /* Reset takes so long, temporarily release semaphore in case the
 293          * other driver instance is waiting for the reset indication.
 294          */
 295         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 296                            IXGBE_CS4227_RESET_PENDING);
 297         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 298         msec_delay(10);
 299         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 300         if (status != IXGBE_SUCCESS) {
 301                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 302                         "semaphore failed with %d", status);
 303                 return;
 304         }
 305
 306         /* Record completion for next time. */
 307         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 308                 IXGBE_CS4227_RESET_COMPLETE);
 309
 310 out:
 311         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 312         msec_delay(hw->eeprom.semaphore_delay);
 313 }
 314
 315 /**
 316  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 317  * @hw: pointer to hardware structure
 318  **/
 319 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 320 {
 321         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 322
 323         if (hw->bus.lan_id) {
 324                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 325                 esdp |= IXGBE_ESDP_SDP1_DIR;
 326         }
 327         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 328         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 329         IXGBE_WRITE_FLUSH(hw);
 330 }
 331
 332 /**
 333  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 334  * @hw: pointer to hardware structure
 335  * @reg_addr: 32 bit address of PHY register to read
 336  * @dev_type: always unused
 337  * @phy_data: Pointer to read data from PHY register
 338  */
 339 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 340                                      u32 dev_type, u16 *phy_data)
 341 {
 342         u32 i, data, command;
 343         UNREFERENCED_1PARAMETER(dev_type);
 344
 345         /* Setup and write the read command */
 346         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 347                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 348                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
 349                   IXGBE_MSCA_MDI_COMMAND;
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 352
 353         /* Check every 10 usec to see if the access completed.
 354          * The MDI Command bit will clear when the operation is
 355          * complete
 356          */
 357         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 358                 usec_delay(10);
 359
 360                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 361                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 362                         break;
 363         }
 364
 365         if (command & IXGBE_MSCA_MDI_COMMAND) {
 366                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 367                               "PHY read command did not complete.\n");
 368                 return IXGBE_ERR_PHY;
 369         }
 370
 371         /* Read operation is complete.  Get the data from MSRWD */
 372         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 373         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 374         *phy_data = (u16)data;
 375
 376         return IXGBE_SUCCESS;
 377 }
 378
 379 /**
 380  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 381  * @hw: pointer to hardware structure
 382  * @reg_addr: 32 bit PHY register to write
 383  * @dev_type: always unused
 384  * @phy_data: Data to write to the PHY register
 385  */
 386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 387                                       u32 dev_type, u16 phy_data)
 388 {
 389         u32 i, command;
 390         UNREFERENCED_1PARAMETER(dev_type);
 391
 392         /* Put the data in the MDI single read and write data register*/
 393         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 394
 395         /* Setup and write the write command */
 396         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 397                   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 398                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 399                   IXGBE_MSCA_MDI_COMMAND;
 400
 401         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 402
 403         /* Check every 10 usec to see if the access completed.
 404          * The MDI Command bit will clear when the operation is
 405          * complete
 406          */
 407         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 408                 usec_delay(10);
 409
 410                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 411                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 412                         break;
 413         }
 414
 415         if (command & IXGBE_MSCA_MDI_COMMAND) {
 416                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 417                               "PHY write cmd didn't complete\n");
 418                 return IXGBE_ERR_PHY;
 419         }
 420
 421         return IXGBE_SUCCESS;
 422 }
 423
 424 /**
 425  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 426  * @hw: pointer to hardware structure
 427  *
 428  * Returns error code
 429  */
 430 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 431 {
 432         hw->mac.ops.set_lan_id(hw);
 433
 434         ixgbe_read_mng_if_sel_x550em(hw);
 435
 436         switch (hw->device_id) {
 437         case IXGBE_DEV_ID_X550EM_A_SFP:
 438                 return ixgbe_identify_module_generic(hw);
 439         case IXGBE_DEV_ID_X550EM_X_SFP:
 440                 /* set up for CS4227 usage */
 441                 ixgbe_setup_mux_ctl(hw);
 442                 ixgbe_check_cs4227(hw);
 443                 /* Fallthrough */
 444
 445         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 446                 return ixgbe_identify_module_generic(hw);
 447                 break;
 448         case IXGBE_DEV_ID_X550EM_X_KX4:
 449                 hw->phy.type = ixgbe_phy_x550em_kx4;
 450                 break;
 451         case IXGBE_DEV_ID_X550EM_X_KR:
 452         case IXGBE_DEV_ID_X550EM_A_KR:
 453         case IXGBE_DEV_ID_X550EM_A_KR_L:
 454                 hw->phy.type = ixgbe_phy_x550em_kr;
 455                 break;
 456         case IXGBE_DEV_ID_X550EM_A_10G_T:
 457         case IXGBE_DEV_ID_X550EM_A_1G_T:
 458         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 459         case IXGBE_DEV_ID_X550EM_X_1G_T:
 460         case IXGBE_DEV_ID_X550EM_X_10G_T:
 461                 return ixgbe_identify_phy_generic(hw);
 462         default:
 463                 break;
 464         }
 465         return IXGBE_SUCCESS;
 466 }
 467
 468 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 469                                      u32 device_type, u16 *phy_data)
 470 {
 471         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 472         return IXGBE_NOT_IMPLEMENTED;
 473 }
 474
 475 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 476                                       u32 device_type, u16 phy_data)
 477 {
 478         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 479         return IXGBE_NOT_IMPLEMENTED;
 480 }
 481
 482 /**
 483  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 484  * @hw: pointer to the hardware structure
 485  * @addr: I2C bus address to read from
 486  * @reg: I2C device register to read from
 487  * @val: pointer to location to receive read value
 488  *
 489  * Returns an error code on error.
 490  **/
 491 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 492                                            u16 reg, u16 *val)
 493 {
 494         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 495 }
 496
 497 /**
 498  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 499  * @hw: pointer to the hardware structure
 500  * @addr: I2C bus address to read from
 501  * @reg: I2C device register to read from
 502  * @val: pointer to location to receive read value
 503  *
 504  * Returns an error code on error.
 505  **/
 506 STATIC s32
 507 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 508                                          u16 reg, u16 *val)
 509 {
 510         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 511 }
 512
 513 /**
 514  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 515  * @hw: pointer to the hardware structure
 516  * @addr: I2C bus address to write to
 517  * @reg: I2C device register to write to
 518  * @val: value to write
 519  *
 520  * Returns an error code on error.
 521  **/
 522 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 523                                             u8 addr, u16 reg, u16 val)
 524 {
 525         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 526 }
 527
 528 /**
 529  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 530  * @hw: pointer to the hardware structure
 531  * @addr: I2C bus address to write to
 532  * @reg: I2C device register to write to
 533  * @val: value to write
 534  *
 535  * Returns an error code on error.
 536  **/
 537 STATIC s32
 538 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 539                                           u8 addr, u16 reg, u16 val)
 540 {
 541         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 542 }
 543
 544 /**
 545 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 546 *  @hw: pointer to hardware structure
 547 *
 548 *  Initialize the function pointers and for MAC type X550EM.
 549 *  Does not touch the hardware.
 550 **/
 551 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 552 {
 553         struct ixgbe_mac_info *mac = &hw->mac;
 554         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 555         struct ixgbe_phy_info *phy = &hw->phy;
 556         s32 ret_val;
 557
 558         DEBUGFUNC("ixgbe_init_ops_X550EM");
 559
 560         /* Similar to X550 so start there. */
 561         ret_val = ixgbe_init_ops_X550(hw);
 562
 563         /* Since this function eventually calls
 564          * ixgbe_init_ops_540 by design, we are setting
 565          * the pointers to NULL explicitly here to overwrite
 566          * the values being set in the x540 function.
 567          */
 568         /* Thermal sensor not supported in x550EM */
 569         mac->ops.get_thermal_sensor_data = NULL;
 570         mac->ops.init_thermal_sensor_thresh = NULL;
 571         mac->thermal_sensor_enabled = false;
 572
 573         /* FCOE not supported in x550EM */
 574         mac->ops.get_san_mac_addr = NULL;
 575         mac->ops.set_san_mac_addr = NULL;
 576         mac->ops.get_wwn_prefix = NULL;
 577         mac->ops.get_fcoe_boot_status = NULL;
 578
 579         /* IPsec not supported in x550EM */
 580         mac->ops.disable_sec_rx_path = NULL;
 581         mac->ops.enable_sec_rx_path = NULL;
 582
 583         /* AUTOC register is not present in x550EM. */
 584         mac->ops.prot_autoc_read = NULL;
 585         mac->ops.prot_autoc_write = NULL;
 586
 587         /* X550EM bus type is internal*/
 588         hw->bus.type = ixgbe_bus_type_internal;
 589         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 590
 591
 592         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 593         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 594         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 595         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 596         mac->ops.get_supported_physical_layer =
 597                                     ixgbe_get_supported_physical_layer_X550em;
 598
 599         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 600                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 601         else
 602                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 603
 604         switch (hw->device_id) {
 605         case IXGBE_DEV_ID_X550EM_X_KR:
 606         case IXGBE_DEV_ID_X550EM_A_KR:
 607         case IXGBE_DEV_ID_X550EM_A_KR_L:
 608                 break;
 609         default:
 610                 mac->ops.setup_eee = NULL;
 611         }
 612
 613         /* PHY */
 614         phy->ops.init = ixgbe_init_phy_ops_X550em;
 615         phy->ops.identify = ixgbe_identify_phy_x550em;
 616         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 617                 phy->ops.set_phy_power = NULL;
 618
 619
 620         /* EEPROM */
 621         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 622         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 623         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 624         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 625         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 626         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 627         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 628         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 629
 630         return ret_val;
 631 }
 632
 633 /**
 634 *  ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
 635 *  @hw: pointer to hardware structure
 636 *
 637 *  Initialize the function pointers and for MAC type X550EM_a.
 638 *  Does not touch the hardware.
 639 **/
 640 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
 641 {
 642         struct ixgbe_mac_info *mac = &hw->mac;
 643         s32 ret_val;
 644
 645         DEBUGFUNC("ixgbe_init_ops_X550EM_a");
 646
 647         /* Start with generic X550EM init */
 648         ret_val = ixgbe_init_ops_X550EM(hw);
 649
 650         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
 651             hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
 652                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 653                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 654         } else {
 655                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 656                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 657         }
 658         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 659         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 660
 661         switch (mac->ops.get_media_type(hw)) {
 662         case ixgbe_media_type_fiber:
 663                 mac->ops.setup_fc = ixgbe_setup_fc_fiber_x550em_a;
 664                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
 665                 break;
 666         case ixgbe_media_type_backplane:
 667                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
 668                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
 669                 break;
 670         default:
 671                 break;
 672         }
 673
 674         if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
 675                 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
 676                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
 677                 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
 678         }
 679
 680         return ret_val;
 681 }
 682
 683 /**
 684 *  ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
 685 *  @hw: pointer to hardware structure
 686 *
 687 *  Initialize the function pointers and for MAC type X550EM_x.
 688 *  Does not touch the hardware.
 689 **/
 690 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
 691 {
 692         struct ixgbe_mac_info *mac = &hw->mac;
 693         struct ixgbe_link_info *link = &hw->link;
 694         s32 ret_val;
 695
 696         DEBUGFUNC("ixgbe_init_ops_X550EM_x");
 697
 698         /* Start with generic X550EM init */
 699         ret_val = ixgbe_init_ops_X550EM(hw);
 700
 701         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 702         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 703         mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 704         mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 705         link->ops.read_link = ixgbe_read_i2c_combined_generic;
 706         link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
 707         link->ops.write_link = ixgbe_write_i2c_combined_generic;
 708         link->ops.write_link_unlocked =
 709                                       ixgbe_write_i2c_combined_generic_unlocked;
 710         link->addr = IXGBE_CS4227;
 711
 712         return ret_val;
 713 }
 714
 715 /**
 716  *  ixgbe_dmac_config_X550
 717  *  @hw: pointer to hardware structure
 718  *
 719  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 720  *  When disabling dmac, dmac enable dmac bit is cleared.
 721  **/
 722 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 723 {
 724         u32 reg, high_pri_tc;
 725
 726         DEBUGFUNC("ixgbe_dmac_config_X550");
 727
 728         /* Disable DMA coalescing before configuring */
 729         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 730         reg &= ~IXGBE_DMACR_DMAC_EN;
 731         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 732
 733         /* Disable DMA Coalescing if the watchdog timer is 0 */
 734         if (!hw->mac.dmac_config.watchdog_timer)
 735                 goto out;
 736
 737         ixgbe_dmac_config_tcs_X550(hw);
 738
 739         /* Configure DMA Coalescing Control Register */
 740         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 741
 742         /* Set the watchdog timer in units of 40.96 usec */
 743         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 744         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 745
 746         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 747         /* If fcoe is enabled, set high priority traffic class */
 748         if (hw->mac.dmac_config.fcoe_en) {
 749                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 750                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 751                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 752         }
 753         reg |= IXGBE_DMACR_EN_MNG_IND;
 754
 755         /* Enable DMA coalescing after configuration */
 756         reg |= IXGBE_DMACR_DMAC_EN;
 757         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 758
 759 out:
 760         return IXGBE_SUCCESS;
 761 }
 762
 763 /**
 764  *  ixgbe_dmac_config_tcs_X550
 765  *  @hw: pointer to hardware structure
 766  *
 767  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 768  *  be cleared before configuring.
 769  **/
 770 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 771 {
 772         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 773
 774         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 775
 776         /* Configure DMA coalescing enabled */
 777         switch (hw->mac.dmac_config.link_speed) {
 778         case IXGBE_LINK_SPEED_10_FULL:
 779         case IXGBE_LINK_SPEED_100_FULL:
 780                 pb_headroom = IXGBE_DMACRXT_100M;
 781                 break;
 782         case IXGBE_LINK_SPEED_1GB_FULL:
 783                 pb_headroom = IXGBE_DMACRXT_1G;
 784                 break;
 785         default:
 786                 pb_headroom = IXGBE_DMACRXT_10G;
 787                 break;
 788         }
 789
 790         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 791                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 792
 793         /* Set the per Rx packet buffer receive threshold */
 794         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 795                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 796                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 797
 798                 if (tc < hw->mac.dmac_config.num_tcs) {
 799                         /* Get Rx PB size */
 800                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 801                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 802                                 IXGBE_RXPBSIZE_SHIFT;
 803
 804                         /* Calculate receive buffer threshold in kilobytes */
 805                         if (rx_pb_size > pb_headroom)
 806                                 rx_pb_size = rx_pb_size - pb_headroom;
 807                         else
 808                                 rx_pb_size = 0;
 809
 810                         /* Minimum of MFS shall be set for DMCTH */
 811                         reg |= (rx_pb_size > maxframe_size_kb) ?
 812                                 rx_pb_size : maxframe_size_kb;
 813                 }
 814                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 815         }
 816         return IXGBE_SUCCESS;
 817 }
 818
 819 /**
 820  *  ixgbe_dmac_update_tcs_X550
 821  *  @hw: pointer to hardware structure
 822  *
 823  *  Disables dmac, updates per TC settings, and then enables dmac.
 824  **/
 825 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 826 {
 827         u32 reg;
 828
 829         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 830
 831         /* Disable DMA coalescing before configuring */
 832         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 833         reg &= ~IXGBE_DMACR_DMAC_EN;
 834         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 835
 836         ixgbe_dmac_config_tcs_X550(hw);
 837
 838         /* Enable DMA coalescing after configuration */
 839         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 840         reg |= IXGBE_DMACR_DMAC_EN;
 841         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 842
 843         return IXGBE_SUCCESS;
 844 }
 845
 846 /**
 847  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 848  *  @hw: pointer to hardware structure
 849  *
 850  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 851  *  ixgbe_hw struct in order to set up EEPROM access.
 852  **/
 853 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 854 {
 855         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 856         u32 eec;
 857         u16 eeprom_size;
 858
 859         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 860
 861         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 862                 eeprom->semaphore_delay = 10;
 863                 eeprom->type = ixgbe_flash;
 864
 865                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 866                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 867                                     IXGBE_EEC_SIZE_SHIFT);
 868                 eeprom->word_size = 1 << (eeprom_size +
 869                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 870
 871                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 872                           eeprom->type, eeprom->word_size);
 873         }
 874
 875         return IXGBE_SUCCESS;
 876 }
 877
 878 /**
 879  * ixgbe_enable_eee_x550 - Enable EEE support
 880  * @hw: pointer to hardware structure
 881  */
 882 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 883 {
 884         u16 autoneg_eee_reg;
 885         u32 link_reg;
 886         s32 status;
 887
 888         if (hw->mac.type == ixgbe_mac_X550) {
 889                 /* Advertise EEE capability */
 890                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 891                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 892                                      &autoneg_eee_reg);
 893
 894                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 895                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 896                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 897
 898                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 899                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 900                                       autoneg_eee_reg);
 901                 return IXGBE_SUCCESS;
 902         }
 903
 904         switch (hw->device_id) {
 905         case IXGBE_DEV_ID_X550EM_X_KR:
 906         case IXGBE_DEV_ID_X550EM_A_KR:
 907         case IXGBE_DEV_ID_X550EM_A_KR_L:
 908                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 909                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 910                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 911                 if (status != IXGBE_SUCCESS)
 912                         return status;
 913
 914                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 915                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 916
 917                 /* Don't advertise FEC capability when EEE enabled. */
 918                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 919
 920                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 921                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 922                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 923                 if (status != IXGBE_SUCCESS)
 924                         return status;
 925                 break;
 926         default:
 927                 break;
 928         }
 929
 930         return IXGBE_SUCCESS;
 931 }
 932
 933 /**
 934  * ixgbe_disable_eee_x550 - Disable EEE support
 935  * @hw: pointer to hardware structure
 936  */
 937 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 938 {
 939         u16 autoneg_eee_reg;
 940         u32 link_reg;
 941         s32 status;
 942
 943         if (hw->mac.type == ixgbe_mac_X550) {
 944                 /* Disable advertised EEE capability */
 945                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 946                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 947                                      &autoneg_eee_reg);
 948
 949                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 950                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 951                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 952
 953                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 954                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 955                                       autoneg_eee_reg);
 956                 return IXGBE_SUCCESS;
 957         }
 958
 959         switch (hw->device_id) {
 960         case IXGBE_DEV_ID_X550EM_X_KR:
 961         case IXGBE_DEV_ID_X550EM_A_KR:
 962         case IXGBE_DEV_ID_X550EM_A_KR_L:
 963                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 964                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 965                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 966                 if (status != IXGBE_SUCCESS)
 967                         return status;
 968
 969                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 970                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 971
 972                 /* Advertise FEC capability when EEE is disabled. */
 973                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 974
 975                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 976                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 977                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 978                 if (status != IXGBE_SUCCESS)
 979                         return status;
 980                 break;
 981         default:
 982                 break;
 983         }
 984
 985         return IXGBE_SUCCESS;
 986 }
 987
 988 /**
 989  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 990  *  @hw: pointer to the HW structure
 991  *  @enable_eee: boolean flag to enable EEE
 992  *
 993  *  Enable/disable EEE based on enable_eee flag.
 994  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 995  *  are modified.
 996  *
 997  **/
 998 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 999 {
1000         s32 status;
1001         u32 eeer;
1002
1003         DEBUGFUNC("ixgbe_setup_eee_X550");
1004
1005         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1006         /* Enable or disable EEE per flag */
1007         if (enable_eee) {
1008                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1009
1010                 /* Not supported on first revision of X550EM_x. */
1011                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1012                     !(IXGBE_FUSES0_REV_MASK &
1013                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1014                         return IXGBE_SUCCESS;
1015                 status = ixgbe_enable_eee_x550(hw);
1016                 if (status)
1017                         return status;
1018         } else {
1019                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1020
1021                 status = ixgbe_disable_eee_x550(hw);
1022                 if (status)
1023                         return status;
1024         }
1025         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1026
1027         return IXGBE_SUCCESS;
1028 }
1029
1030 /**
1031  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1032  * @hw: pointer to hardware structure
1033  * @enable: enable or disable source address pruning
1034  * @pool: Rx pool to set source address pruning for
1035  **/
1036 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1037                                            unsigned int pool)
1038 {
1039         u64 pfflp;
1040
1041         /* max rx pool is 63 */
1042         if (pool > 63)
1043                 return;
1044
1045         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1046         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1047
1048         if (enable)
1049                 pfflp |= (1ULL << pool);
1050         else
1051                 pfflp &= ~(1ULL << pool);
1052
1053         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1054         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1055 }
1056
1057 /**
1058  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1059  *  @hw: pointer to hardware structure
1060  *  @enable: enable or disable switch for Ethertype anti-spoofing
1061  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1062  *
1063  **/
1064 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1065                 bool enable, int vf)
1066 {
1067         int vf_target_reg = vf >> 3;
1068         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1069         u32 pfvfspoof;
1070
1071         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1072
1073         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1074         if (enable)
1075                 pfvfspoof |= (1 << vf_target_shift);
1076         else
1077                 pfvfspoof &= ~(1 << vf_target_shift);
1078
1079         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1080 }
1081
1082 /**
1083  * ixgbe_iosf_wait - Wait for IOSF command completion
1084  * @hw: pointer to hardware structure
1085  * @ctrl: pointer to location to receive final IOSF control value
1086  *
1087  * Returns failing status on timeout
1088  *
1089  * Note: ctrl can be NULL if the IOSF control register value is not needed
1090  **/
1091 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1092 {
1093         u32 i, command = 0;
1094
1095         /* Check every 10 usec to see if the address cycle completed.
1096          * The SB IOSF BUSY bit will clear when the operation is
1097          * complete
1098          */
1099         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1100                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1101                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1102                         break;
1103                 usec_delay(10);
1104         }
1105         if (ctrl)
1106                 *ctrl = command;
1107         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1108                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1109                 return IXGBE_ERR_PHY;
1110         }
1111
1112         return IXGBE_SUCCESS;
1113 }
1114
1115 /**
1116  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1117  *  of the IOSF device
1118  *  @hw: pointer to hardware structure
1119  *  @reg_addr: 32 bit PHY register to write
1120  *  @device_type: 3 bit device type
1121  *  @data: Data to write to the register
1122  **/
1123 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1124                             u32 device_type, u32 data)
1125 {
1126         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1127         u32 command, error;
1128         s32 ret;
1129
1130         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1131         if (ret != IXGBE_SUCCESS)
1132                 return ret;
1133
1134         ret = ixgbe_iosf_wait(hw, NULL);
1135         if (ret != IXGBE_SUCCESS)
1136                 goto out;
1137
1138         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1139                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1140
1141         /* Write IOSF control register */
1142         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1143
1144         /* Write IOSF data register */
1145         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1146
1147         ret = ixgbe_iosf_wait(hw, &command);
1148
1149         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1150                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1151                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1152                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1153                               "Failed to write, error %x\n", error);
1154                 ret = IXGBE_ERR_PHY;
1155         }
1156
1157 out:
1158         ixgbe_release_swfw_semaphore(hw, gssr);
1159         return ret;
1160 }
1161
1162 /**
1163  *  ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1164  *  @hw: pointer to hardware structure
1165  *  @reg_addr: 32 bit PHY register to write
1166  *  @device_type: 3 bit device type
1167  *  @data: Pointer to read data from the register
1168  **/
1169 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1170                            u32 device_type, u32 *data)
1171 {
1172         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1173         u32 command, error;
1174         s32 ret;
1175
1176         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1177         if (ret != IXGBE_SUCCESS)
1178                 return ret;
1179
1180         ret = ixgbe_iosf_wait(hw, NULL);
1181         if (ret != IXGBE_SUCCESS)
1182                 goto out;
1183
1184         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1185                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1186
1187         /* Write IOSF control register */
1188         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1189
1190         ret = ixgbe_iosf_wait(hw, &command);
1191
1192         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1193                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1194                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1195                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1196                                 "Failed to read, error %x\n", error);
1197                 ret = IXGBE_ERR_PHY;
1198         }
1199
1200         if (ret == IXGBE_SUCCESS)
1201                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1202
1203 out:
1204         ixgbe_release_swfw_semaphore(hw, gssr);
1205         return ret;
1206 }
1207
1208 /**
1209  * ixgbe_get_phy_token - Get the token for shared phy access
1210  * @hw: Pointer to hardware structure
1211  */
1212
1213 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1214 {
1215         struct ixgbe_hic_phy_token_req token_cmd;
1216         s32 status;
1217
1218         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1219         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1220         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1221         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1222         token_cmd.port_number = hw->bus.lan_id;
1223         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1224         token_cmd.pad = 0;
1225         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1226                                               sizeof(token_cmd),
1227                                               IXGBE_HI_COMMAND_TIMEOUT,
1228                                               true);
1229         if (status)
1230                 return status;
1231         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1232                 return IXGBE_SUCCESS;
1233         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1234                 return IXGBE_ERR_FW_RESP_INVALID;
1235
1236         return IXGBE_ERR_TOKEN_RETRY;
1237 }
1238
1239 /**
1240  * ixgbe_put_phy_token - Put the token for shared phy access
1241  * @hw: Pointer to hardware structure
1242  */
1243
1244 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1245 {
1246         struct ixgbe_hic_phy_token_req token_cmd;
1247         s32 status;
1248
1249         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1250         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1251         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1252         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1253         token_cmd.port_number = hw->bus.lan_id;
1254         token_cmd.command_type = FW_PHY_TOKEN_REL;
1255         token_cmd.pad = 0;
1256         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1257                                               sizeof(token_cmd),
1258                                               IXGBE_HI_COMMAND_TIMEOUT,
1259                                               true);
1260         if (status)
1261                 return status;
1262         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1263                 return IXGBE_SUCCESS;
1264
1265         DEBUGOUT("Put PHY Token host interface command failed");
1266         return IXGBE_ERR_FW_RESP_INVALID;
1267 }
1268
1269 /**
1270  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1271  *  of the IOSF device
1272  *  @hw: pointer to hardware structure
1273  *  @reg_addr: 32 bit PHY register to write
1274  *  @device_type: 3 bit device type
1275  *  @data: Data to write to the register
1276  **/
1277 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1278                                   u32 device_type, u32 data)
1279 {
1280         struct ixgbe_hic_internal_phy_req write_cmd;
1281         s32 status;
1282         UNREFERENCED_1PARAMETER(device_type);
1283
1284         memset(&write_cmd, 0, sizeof(write_cmd));
1285         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1286         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1287         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1288         write_cmd.port_number = hw->bus.lan_id;
1289         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1290         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1291         write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1292
1293         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1294                                               sizeof(write_cmd),
1295                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1296
1297         return status;
1298 }
1299
1300 /**
1301  *  ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1302  *  @hw: pointer to hardware structure
1303  *  @reg_addr: 32 bit PHY register to write
1304  *  @device_type: 3 bit device type
1305  *  @data: Pointer to read data from the register
1306  **/
1307 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1308                                  u32 device_type, u32 *data)
1309 {
1310         union {
1311                 struct ixgbe_hic_internal_phy_req cmd;
1312                 struct ixgbe_hic_internal_phy_resp rsp;
1313         } hic;
1314         s32 status;
1315         UNREFERENCED_1PARAMETER(device_type);
1316
1317         memset(&hic, 0, sizeof(hic));
1318         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1319         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1320         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1321         hic.cmd.port_number = hw->bus.lan_id;
1322         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1323         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1324
1325         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1326                                               sizeof(hic.cmd),
1327                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1328
1329         /* Extract the register value from the response. */
1330         *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1331
1332         return status;
1333 }
1334
1335 /**
1336  *  ixgbe_disable_mdd_X550
1337  *  @hw: pointer to hardware structure
1338  *
1339  *  Disable malicious driver detection
1340  **/
1341 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1342 {
1343         u32 reg;
1344
1345         DEBUGFUNC("ixgbe_disable_mdd_X550");
1346
1347         /* Disable MDD for TX DMA and interrupt */
1348         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1349         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1350         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1351
1352         /* Disable MDD for RX and interrupt */
1353         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1354         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1355         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1356 }
1357
1358 /**
1359  *  ixgbe_enable_mdd_X550
1360  *  @hw: pointer to hardware structure
1361  *
1362  *  Enable malicious driver detection
1363  **/
1364 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1365 {
1366         u32 reg;
1367
1368         DEBUGFUNC("ixgbe_enable_mdd_X550");
1369
1370         /* Enable MDD for TX DMA and interrupt */
1371         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1372         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1373         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1374
1375         /* Enable MDD for RX and interrupt */
1376         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1377         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1378         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1379 }
1380
1381 /**
1382  *  ixgbe_restore_mdd_vf_X550
1383  *  @hw: pointer to hardware structure
1384  *  @vf: vf index
1385  *
1386  *  Restore VF that was disabled during malicious driver detection event
1387  **/
1388 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1389 {
1390         u32 idx, reg, num_qs, start_q, bitmask;
1391
1392         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1393
1394         /* Map VF to queues */
1395         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1396         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1397         case IXGBE_MRQC_VMDQRT8TCEN:
1398                 num_qs = 8;  /* 16 VFs / pools */
1399                 bitmask = 0x000000FF;
1400                 break;
1401         case IXGBE_MRQC_VMDQRSS32EN:
1402         case IXGBE_MRQC_VMDQRT4TCEN:
1403                 num_qs = 4;  /* 32 VFs / pools */
1404                 bitmask = 0x0000000F;
1405                 break;
1406         default:            /* 64 VFs / pools */
1407                 num_qs = 2;
1408                 bitmask = 0x00000003;
1409                 break;
1410         }
1411         start_q = vf * num_qs;
1412
1413         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1414         idx = start_q / 32;
1415         reg = 0;
1416         reg |= (bitmask << (start_q % 32));
1417         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1418         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1419 }
1420
1421 /**
1422  *  ixgbe_mdd_event_X550
1423  *  @hw: pointer to hardware structure
1424  *  @vf_bitmap: vf bitmap of malicious vfs
1425  *
1426  *  Handle malicious driver detection event.
1427  **/
1428 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1429 {
1430         u32 wqbr;
1431         u32 i, j, reg, q, shift, vf, idx;
1432
1433         DEBUGFUNC("ixgbe_mdd_event_X550");
1434
1435         /* figure out pool size for mapping to vf's */
1436         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1437         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1438         case IXGBE_MRQC_VMDQRT8TCEN:
1439                 shift = 3;  /* 16 VFs / pools */
1440                 break;
1441         case IXGBE_MRQC_VMDQRSS32EN:
1442         case IXGBE_MRQC_VMDQRT4TCEN:
1443                 shift = 2;  /* 32 VFs / pools */
1444                 break;
1445         default:
1446                 shift = 1;  /* 64 VFs / pools */
1447                 break;
1448         }
1449
1450         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1451         for (i = 0; i < 4; i++) {
1452                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1453                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1454
1455                 if (!wqbr)
1456                         continue;
1457
1458                 /* Get malicious queue */
1459                 for (j = 0; j < 32 && wqbr; j++) {
1460
1461                         if (!(wqbr & (1 << j)))
1462                                 continue;
1463
1464                         /* Get queue from bitmask */
1465                         q = j + (i * 32);
1466
1467                         /* Map queue to vf */
1468                         vf = (q >> shift);
1469
1470                         /* Set vf bit in vf_bitmap */
1471                         idx = vf / 32;
1472                         vf_bitmap[idx] |= (1 << (vf % 32));
1473                         wqbr &= ~(1 << j);
1474                 }
1475         }
1476 }
1477
1478 /**
1479  *  ixgbe_get_media_type_X550em - Get media type
1480  *  @hw: pointer to hardware structure
1481  *
1482  *  Returns the media type (fiber, copper, backplane)
1483  */
1484 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1485 {
1486         enum ixgbe_media_type media_type;
1487
1488         DEBUGFUNC("ixgbe_get_media_type_X550em");
1489
1490         /* Detect if there is a copper PHY attached. */
1491         switch (hw->device_id) {
1492         case IXGBE_DEV_ID_X550EM_X_KR:
1493         case IXGBE_DEV_ID_X550EM_X_KX4:
1494         case IXGBE_DEV_ID_X550EM_A_KR:
1495         case IXGBE_DEV_ID_X550EM_A_KR_L:
1496                 media_type = ixgbe_media_type_backplane;
1497                 break;
1498         case IXGBE_DEV_ID_X550EM_X_SFP:
1499         case IXGBE_DEV_ID_X550EM_A_SFP:
1500         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1501         case IXGBE_DEV_ID_X550EM_A_QSFP:
1502         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1503                 media_type = ixgbe_media_type_fiber;
1504                 break;
1505         case IXGBE_DEV_ID_X550EM_X_1G_T:
1506         case IXGBE_DEV_ID_X550EM_X_10G_T:
1507         case IXGBE_DEV_ID_X550EM_A_10G_T:
1508                 media_type = ixgbe_media_type_copper;
1509                 break;
1510         case IXGBE_DEV_ID_X550EM_A_SGMII:
1511         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1512                 media_type = ixgbe_media_type_backplane;
1513                 hw->phy.type = ixgbe_phy_sgmii;
1514                 break;
1515         case IXGBE_DEV_ID_X550EM_A_1G_T:
1516         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1517                 media_type = ixgbe_media_type_copper;
1518                 break;
1519         default:
1520                 media_type = ixgbe_media_type_unknown;
1521                 break;
1522         }
1523         return media_type;
1524 }
1525
1526 /**
1527  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1528  *  @hw: pointer to hardware structure
1529  *  @linear: true if SFP module is linear
1530  */
1531 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1532 {
1533         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1534
1535         switch (hw->phy.sfp_type) {
1536         case ixgbe_sfp_type_not_present:
1537                 return IXGBE_ERR_SFP_NOT_PRESENT;
1538         case ixgbe_sfp_type_da_cu_core0:
1539         case ixgbe_sfp_type_da_cu_core1:
1540                 *linear = true;
1541                 break;
1542         case ixgbe_sfp_type_srlr_core0:
1543         case ixgbe_sfp_type_srlr_core1:
1544         case ixgbe_sfp_type_da_act_lmt_core0:
1545         case ixgbe_sfp_type_da_act_lmt_core1:
1546         case ixgbe_sfp_type_1g_sx_core0:
1547         case ixgbe_sfp_type_1g_sx_core1:
1548         case ixgbe_sfp_type_1g_lx_core0:
1549         case ixgbe_sfp_type_1g_lx_core1:
1550                 *linear = false;
1551                 break;
1552         case ixgbe_sfp_type_unknown:
1553         case ixgbe_sfp_type_1g_cu_core0:
1554         case ixgbe_sfp_type_1g_cu_core1:
1555         default:
1556                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1557         }
1558
1559         return IXGBE_SUCCESS;
1560 }
1561
1562 /**
1563  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1564  *  @hw: pointer to hardware structure
1565  *
1566  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1567  **/
1568 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1569 {
1570         s32 status;
1571         bool linear;
1572
1573         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1574
1575         status = ixgbe_identify_module_generic(hw);
1576
1577         if (status != IXGBE_SUCCESS)
1578                 return status;
1579
1580         /* Check if SFP module is supported */
1581         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1582
1583         return status;
1584 }
1585
1586 /**
1587  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1588  *  @hw: pointer to hardware structure
1589  */
1590 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1591 {
1592         s32 status;
1593         bool linear;
1594
1595         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1596
1597         /* Check if SFP module is supported */
1598         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1599
1600         if (status != IXGBE_SUCCESS)
1601                 return status;
1602
1603         ixgbe_init_mac_link_ops_X550em(hw);
1604         hw->phy.ops.reset = NULL;
1605
1606         return IXGBE_SUCCESS;
1607 }
1608
1609 /**
1610  * ixgbe_setup_sgmii - Set up link for sgmii
1611  * @hw: pointer to hardware structure
1612  */
1613 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1614                              bool autoneg_wait)
1615 {
1616         struct ixgbe_mac_info *mac = &hw->mac;
1617         u32 lval, sval;
1618         s32 rc;
1619
1620         rc = mac->ops.read_iosf_sb_reg(hw,
1621                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1622                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1623         if (rc)
1624                 return rc;
1625
1626         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1627         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1628         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1629         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1630         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1631         rc = mac->ops.write_iosf_sb_reg(hw,
1632                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1633                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1634         if (rc)
1635                 return rc;
1636
1637         rc = mac->ops.read_iosf_sb_reg(hw,
1638                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1639                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1640         if (rc)
1641                 return rc;
1642
1643         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1644         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1645         rc = mac->ops.write_iosf_sb_reg(hw,
1646                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1647                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1648         if (rc)
1649                 return rc;
1650
1651         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1652         rc = mac->ops.write_iosf_sb_reg(hw,
1653                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1654                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1655         if (rc)
1656                 return rc;
1657
1658         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1659 }
1660
1661  /**
1662  * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1663  * @hw: pointer to hardware structure
1664  */
1665 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1666                                  bool autoneg_wait)
1667 {
1668         struct ixgbe_mac_info *mac = &hw->mac;
1669         u32 lval, sval;
1670         s32 rc;
1671
1672         rc = mac->ops.read_iosf_sb_reg(hw,
1673                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1674                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1675         if (rc)
1676                 return rc;
1677
1678         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1679         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1680         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1681         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1682         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1683         rc = mac->ops.write_iosf_sb_reg(hw,
1684                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1685                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1686         if (rc)
1687                 return rc;
1688
1689         rc = mac->ops.read_iosf_sb_reg(hw,
1690                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1691                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1692         if (rc)
1693                 return rc;
1694
1695         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1696         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1697         rc = mac->ops.write_iosf_sb_reg(hw,
1698                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1699                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1700         if (rc)
1701                 return rc;
1702
1703         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1704         rc = mac->ops.write_iosf_sb_reg(hw,
1705                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1706                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1707         if (rc)
1708                 return rc;
1709
1710         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1711 }
1712
1713 /**
1714  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1715  *  @hw: pointer to hardware structure
1716  */
1717 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1718 {
1719         struct ixgbe_mac_info *mac = &hw->mac;
1720
1721         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1722
1723         switch (hw->mac.ops.get_media_type(hw)) {
1724         case ixgbe_media_type_fiber:
1725                 /* CS4227 does not support autoneg, so disable the laser control
1726                  * functions for SFP+ fiber
1727                  */
1728                 mac->ops.disable_tx_laser = NULL;
1729                 mac->ops.enable_tx_laser = NULL;
1730                 mac->ops.flap_tx_laser = NULL;
1731                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1732                 mac->ops.set_rate_select_speed =
1733                                         ixgbe_set_soft_rate_select_speed;
1734                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1735                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1736                         mac->ops.setup_mac_link =
1737                                 ixgbe_setup_mac_link_sfp_x550a;
1738                 else
1739                         mac->ops.setup_mac_link =
1740                                 ixgbe_setup_mac_link_sfp_x550em;
1741                 break;
1742         case ixgbe_media_type_copper:
1743                 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1744                         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1745                             hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1746                                 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1747                         } else {
1748                                 mac->ops.setup_link =
1749                                                   ixgbe_setup_mac_link_t_X550em;
1750                         }
1751                 } else {
1752                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1753                         mac->ops.check_link = ixgbe_check_link_t_X550em;
1754                 }
1755                 break;
1756         case ixgbe_media_type_backplane:
1757                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1758                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1759                         mac->ops.setup_link = ixgbe_setup_sgmii;
1760                 break;
1761         default:
1762                 break;
1763         }
1764 }
1765
1766 /**
1767  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1768  *  @hw: pointer to hardware structure
1769  *  @speed: pointer to link speed
1770  *  @autoneg: true when autoneg or autotry is enabled
1771  */
1772 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1773                                        ixgbe_link_speed *speed,
1774                                        bool *autoneg)
1775 {
1776         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1777
1778         /* SFP */
1779         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1780
1781                 /* CS4227 SFP must not enable auto-negotiation */
1782                 *autoneg = false;
1783
1784                 /* Check if 1G SFP module. */
1785                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1786                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1787                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1788                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1789                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1790                         return IXGBE_SUCCESS;
1791                 }
1792
1793                 /* Link capabilities are based on SFP */
1794                 if (hw->phy.multispeed_fiber)
1795                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1796                                  IXGBE_LINK_SPEED_1GB_FULL;
1797                 else
1798                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1799         } else {
1800                 switch (hw->phy.type) {
1801                 case ixgbe_phy_m88:
1802                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
1803                                  IXGBE_LINK_SPEED_100_FULL |
1804                                  IXGBE_LINK_SPEED_10_FULL;
1805                         break;
1806                 case ixgbe_phy_sgmii:
1807                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1808                         break;
1809                 default:
1810                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1811                                  IXGBE_LINK_SPEED_1GB_FULL;
1812                         break;
1813                 }
1814                 *autoneg = true;
1815         }
1816
1817         return IXGBE_SUCCESS;
1818 }
1819
1820 /**
1821  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1822  * @hw: pointer to hardware structure
1823  * @lsc: pointer to boolean flag which indicates whether external Base T
1824  *       PHY interrupt is lsc
1825  *
1826  * Determime if external Base T PHY interrupt cause is high temperature
1827  * failure alarm or link status change.
1828  *
1829  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1830  * failure alarm, else return PHY access status.
1831  */
1832 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1833 {
1834         u32 status;
1835         u16 reg;
1836
1837         *lsc = false;
1838
1839         /* Vendor alarm triggered */
1840         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1841                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1842                                       &reg);
1843
1844         if (status != IXGBE_SUCCESS ||
1845             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1846                 return status;
1847
1848         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1849         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1850                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1851                                       &reg);
1852
1853         if (status != IXGBE_SUCCESS ||
1854             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1855             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1856                 return status;
1857
1858         /* Global alarm triggered */
1859         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1860                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1861                                       &reg);
1862
1863         if (status != IXGBE_SUCCESS)
1864                 return status;
1865
1866         /* If high temperature failure, then return over temp error and exit */
1867         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1868                 /* power down the PHY in case the PHY FW didn't already */
1869                 ixgbe_set_copper_phy_power(hw, false);
1870                 return IXGBE_ERR_OVERTEMP;
1871         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1872                 /*  device fault alarm triggered */
1873                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1874                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1875                                           &reg);
1876
1877                 if (status != IXGBE_SUCCESS)
1878                         return status;
1879
1880                 /* if device fault was due to high temp alarm handle and exit */
1881                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1882                         /* power down the PHY in case the PHY FW didn't */
1883                         ixgbe_set_copper_phy_power(hw, false);
1884                         return IXGBE_ERR_OVERTEMP;
1885                 }
1886         }
1887
1888         /* Vendor alarm 2 triggered */
1889         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1890                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1891
1892         if (status != IXGBE_SUCCESS ||
1893             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1894                 return status;
1895
1896         /* link connect/disconnect event occurred */
1897         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1898                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1899
1900         if (status != IXGBE_SUCCESS)
1901                 return status;
1902
1903         /* Indicate LSC */
1904         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1905                 *lsc = true;
1906
1907         return IXGBE_SUCCESS;
1908 }
1909
1910 /**
1911  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1912  * @hw: pointer to hardware structure
1913  *
1914  * Enable link status change and temperature failure alarm for the external
1915  * Base T PHY
1916  *
1917  * Returns PHY access status
1918  */
1919 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1920 {
1921         u32 status;
1922         u16 reg;
1923         bool lsc;
1924
1925         /* Clear interrupt flags */
1926         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1927
1928         /* Enable link status change alarm */
1929         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1930                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1931
1932         if (status != IXGBE_SUCCESS)
1933                 return status;
1934
1935         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1936
1937         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1938                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1939
1940         if (status != IXGBE_SUCCESS)
1941                 return status;
1942
1943         /* Enable high temperature failure and global fault alarms */
1944         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1945                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1946                                       &reg);
1947
1948         if (status != IXGBE_SUCCESS)
1949                 return status;
1950
1951         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1952                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1953
1954         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1955                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1956                                        reg);
1957
1958         if (status != IXGBE_SUCCESS)
1959                 return status;
1960
1961         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1962         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1963                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1964                                       &reg);
1965
1966         if (status != IXGBE_SUCCESS)
1967                 return status;
1968
1969         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1970                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1971
1972         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1973                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1974                                        reg);
1975
1976         if (status != IXGBE_SUCCESS)
1977                 return status;
1978
1979         /* Enable chip-wide vendor alarm */
1980         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1981                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1982                                       &reg);
1983
1984         if (status != IXGBE_SUCCESS)
1985                 return status;
1986
1987         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1988
1989         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1990                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1991                                        reg);
1992
1993         return status;
1994 }
1995
1996 /**
1997  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1998  *  @hw: pointer to hardware structure
1999  *  @speed: link speed
2000  *
2001  *  Configures the integrated KR PHY.
2002  **/
2003 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2004                                        ixgbe_link_speed speed)
2005 {
2006         s32 status;
2007         u32 reg_val;
2008
2009         status = hw->mac.ops.read_iosf_sb_reg(hw,
2010                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2011                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2012         if (status)
2013                 return status;
2014
2015         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2016         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2017                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2018
2019         /* Advertise 10G support. */
2020         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2021                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2022
2023         /* Advertise 1G support. */
2024         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2025                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2026
2027         /* Restart auto-negotiation. */
2028         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2029         status = hw->mac.ops.write_iosf_sb_reg(hw,
2030                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2031                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2032
2033         return status;
2034 }
2035
2036 /**
2037  * ixgbe_setup_m88 - setup m88 PHY
2038  * @hw: pointer to hardware structure
2039  */
2040 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2041 {
2042         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2043         u16 reg;
2044         s32 rc;
2045
2046         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2047                 return IXGBE_SUCCESS;
2048
2049         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2050         if (rc)
2051                 return rc;
2052
2053         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2054         if (rc)
2055                 goto out;
2056         if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2057                 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2058                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2059                                           reg);
2060         }
2061
2062         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, &reg);
2063         if (rc)
2064                 goto out;
2065         if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2066                 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2067                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2068                                           reg);
2069         }
2070
2071         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2072         if (rc)
2073                 goto out;
2074
2075         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2076                                       &reg);
2077         if (rc)
2078                 goto out;
2079         if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2080                 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2081                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2082                                           reg);
2083                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2084                                                0);
2085                 if (rc)
2086                         goto out;
2087                 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2088                                               &reg);
2089                 if (rc)
2090                         goto out;
2091                 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2092                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2093                                           reg);
2094                 usec_delay(50);
2095         } else {
2096                 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2097                                                0);
2098                 if (rc)
2099                         goto out;
2100         }
2101
2102         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2103         if (rc)
2104                 goto out;
2105
2106         if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2107                 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2108                 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2109                                           reg);
2110         }
2111
2112         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, &reg);
2113         if (rc)
2114                 goto out;
2115         reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2116         reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2117         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2118                 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2119         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2120
2121         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, &reg);
2122         if (rc)
2123                 goto out;
2124         reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2125         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2126         reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2127         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2128         reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2129
2130         /* Flow control auto negotiation configuration was moved from here to
2131          * the function ixgbe_setup_fc_sgmii_x550em_a()
2132          */
2133
2134         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2135                 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2136         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2137                 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2138         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2139
2140         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2141         if (rc)
2142                 goto out;
2143         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2144         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2145
2146
2147         hw->mac.ops.release_swfw_sync(hw, mask);
2148         return rc;
2149
2150 out:
2151         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2152         hw->mac.ops.release_swfw_sync(hw, mask);
2153         return rc;
2154 }
2155
2156 /**
2157  * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2158  * @hw: pointer to hardware structure
2159  *
2160  * The PHY token must be held when calling this function.
2161  */
2162 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2163 {
2164         u16 reg;
2165         s32 rc;
2166
2167         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2168         if (rc)
2169                 return rc;
2170
2171         rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, &reg);
2172         if (rc)
2173                 return rc;
2174
2175         reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2176         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2177
2178         usec_delay(10);
2179
2180         return rc;
2181 }
2182
2183 /**
2184  * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2185  * @hw: pointer to hardware structure
2186  *
2187  * The PHY token must be held when calling this function.
2188  */
2189 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2190 {
2191         return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2192 }
2193
2194 /**
2195  * ixgbe_reset_phy_m88 - Reset m88 PHY
2196  * @hw: pointer to hardware structure
2197  */
2198 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2199 {
2200         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2201         u16 reg;
2202         s32 rc;
2203
2204         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2205                 return IXGBE_SUCCESS;
2206
2207         rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2208         if (rc)
2209                 return rc;
2210
2211         switch (hw->phy.id) {
2212         case IXGBE_M88E1500_E_PHY_ID:
2213                 rc = ixgbe_reset_phy_m88e1500(hw);
2214                 break;
2215         case IXGBE_M88E1543_E_PHY_ID:
2216                 rc = ixgbe_reset_phy_m88e1543(hw);
2217                 break;
2218         default:
2219                 rc = IXGBE_ERR_PHY;
2220                 break;
2221         }
2222
2223         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2224         if (rc)
2225                 goto out;
2226
2227         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2228               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2229               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2230         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2231         if (rc)
2232                 goto out;
2233
2234         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2235         if (rc)
2236                 goto out;
2237
2238         reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2239               IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2240         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2241         if (rc)
2242                 goto out;
2243
2244         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2245         if (rc)
2246                 goto out;
2247
2248         reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2249               IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2250               IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2251               IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2252         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2253         if (rc)
2254                 goto out;
2255
2256         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2257         if (rc)
2258                 goto out;
2259
2260         reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2261                IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2262               (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2263                IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2264               (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2265                IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2266         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2267         if (rc)
2268                 goto out;
2269
2270         reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2271               IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2272               IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2273               IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2274               IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2275         rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2276         if (rc)
2277                 goto out;
2278
2279         hw->mac.ops.release_swfw_sync(hw, mask);
2280
2281         /* In case of first reset set advertised speeds to default value */
2282         if (!hw->phy.autoneg_advertised)
2283                 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2284                                              IXGBE_LINK_SPEED_100_FULL |
2285                                              IXGBE_LINK_SPEED_10_FULL;
2286
2287         return ixgbe_setup_m88(hw);
2288
2289 out:
2290         hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2291         hw->mac.ops.release_swfw_sync(hw, mask);
2292         return rc;
2293 }
2294
2295 /**
2296  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2297  *  @hw: pointer to hardware structure
2298  *
2299  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2300  *  values.
2301  **/
2302 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2303 {
2304         /* Save NW management interface connected on board. This is used
2305          * to determine internal PHY mode.
2306          */
2307         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2308
2309         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2310          * PHY address. This register field was has only been used for X552.
2311          */
2312         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2313             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2314                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2315                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2316                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2317         }
2318
2319         return IXGBE_SUCCESS;
2320 }
2321
2322 /**
2323  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2324  *  @hw: pointer to hardware structure
2325  *
2326  *  Initialize any function pointers that were not able to be
2327  *  set during init_shared_code because the PHY/SFP type was
2328  *  not known.  Perform the SFP init if necessary.
2329  */
2330 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2331 {
2332         struct ixgbe_phy_info *phy = &hw->phy;
2333         s32 ret_val;
2334
2335         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2336
2337         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2338                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2339                 ixgbe_setup_mux_ctl(hw);
2340                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2341         }
2342
2343         switch (hw->device_id) {
2344         case IXGBE_DEV_ID_X550EM_A_1G_T:
2345         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2346                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2347                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2348                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2349                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2350                 if (hw->bus.lan_id)
2351                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2352                 else
2353                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2354
2355                 break;
2356         case IXGBE_DEV_ID_X550EM_A_10G_T:
2357         case IXGBE_DEV_ID_X550EM_A_SFP:
2358                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2359                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2360                 if (hw->bus.lan_id)
2361                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2362                 else
2363                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2364                 break;
2365         case IXGBE_DEV_ID_X550EM_X_SFP:
2366                 /* set up for CS4227 usage */
2367                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2368                 break;
2369         default:
2370                 break;
2371         }
2372
2373         /* Identify the PHY or SFP module */
2374         ret_val = phy->ops.identify(hw);
2375         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2376                 return ret_val;
2377
2378         /* Setup function pointers based on detected hardware */
2379         ixgbe_init_mac_link_ops_X550em(hw);
2380         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2381                 phy->ops.reset = NULL;
2382
2383         /* Set functions pointers based on phy type */
2384         switch (hw->phy.type) {
2385         case ixgbe_phy_x550em_kx4:
2386                 phy->ops.setup_link = NULL;
2387                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2388                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2389                 break;
2390         case ixgbe_phy_x550em_kr:
2391                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2392                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2393                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2394                 break;
2395         case ixgbe_phy_x550em_ext_t:
2396                 /* If internal link mode is XFI, then setup iXFI internal link,
2397                  * else setup KR now.
2398                  */
2399                 phy->ops.setup_internal_link =
2400                                               ixgbe_setup_internal_phy_t_x550em;
2401
2402                 /* setup SW LPLU only for first revision of X550EM_x */
2403                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2404                     !(IXGBE_FUSES0_REV_MASK &
2405                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2406                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2407
2408                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2409                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2410                 break;
2411         case ixgbe_phy_sgmii:
2412                 phy->ops.setup_link = NULL;
2413                 break;
2414         case ixgbe_phy_m88:
2415                 phy->ops.setup_link = ixgbe_setup_m88;
2416                 phy->ops.reset = ixgbe_reset_phy_m88;
2417                 break;
2418         default:
2419                 break;
2420         }
2421         return ret_val;
2422 }
2423
2424 /**
2425  * ixgbe_set_mdio_speed - Set MDIO clock speed
2426  *  @hw: pointer to hardware structure
2427  */
2428 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2429 {
2430         u32 hlreg0;
2431
2432         switch (hw->device_id) {
2433         case IXGBE_DEV_ID_X550EM_X_10G_T:
2434         case IXGBE_DEV_ID_X550EM_A_SGMII:
2435         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2436         case IXGBE_DEV_ID_X550EM_A_1G_T:
2437         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2438         case IXGBE_DEV_ID_X550EM_A_10G_T:
2439         case IXGBE_DEV_ID_X550EM_A_SFP:
2440         case IXGBE_DEV_ID_X550EM_A_QSFP:
2441                 /* Config MDIO clock speed before the first MDIO PHY access */
2442                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2443                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2444                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2445                 break;
2446         default:
2447                 break;
2448         }
2449 }
2450
2451 /**
2452  *  ixgbe_reset_hw_X550em - Perform hardware reset
2453  *  @hw: pointer to hardware structure
2454  *
2455  *  Resets the hardware by resetting the transmit and receive units, masks
2456  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2457  *  reset.
2458  */
2459 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2460 {
2461         ixgbe_link_speed link_speed;
2462         s32 status;
2463         u32 ctrl = 0;
2464         u32 i;
2465         bool link_up = false;
2466
2467         DEBUGFUNC("ixgbe_reset_hw_X550em");
2468
2469         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2470         status = hw->mac.ops.stop_adapter(hw);
2471         if (status != IXGBE_SUCCESS)
2472                 return status;
2473
2474         /* flush pending Tx transactions */
2475         ixgbe_clear_tx_pending(hw);
2476
2477         ixgbe_set_mdio_speed(hw);
2478
2479         /* PHY ops must be identified and initialized prior to reset */
2480         status = hw->phy.ops.init(hw);
2481
2482         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2483                 return status;
2484
2485         /* start the external PHY */
2486         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2487                 status = ixgbe_init_ext_t_x550em(hw);
2488                 if (status)
2489                         return status;
2490         }
2491
2492         /* Setup SFP module if there is one present. */
2493         if (hw->phy.sfp_setup_needed) {
2494                 status = hw->mac.ops.setup_sfp(hw);
2495                 hw->phy.sfp_setup_needed = false;
2496         }
2497
2498         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2499                 return status;
2500
2501         /* Reset PHY */
2502         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2503                 hw->phy.ops.reset(hw);
2504
2505 mac_reset_top:
2506         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2507          * If link reset is used when link is up, it might reset the PHY when
2508          * mng is using it.  If link is down or the flag to force full link
2509          * reset is set, then perform link reset.
2510          */
2511         ctrl = IXGBE_CTRL_LNK_RST;
2512         if (!hw->force_full_reset) {
2513                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2514                 if (link_up)
2515                         ctrl = IXGBE_CTRL_RST;
2516         }
2517
2518         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2519         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2520         IXGBE_WRITE_FLUSH(hw);
2521
2522         /* Poll for reset bit to self-clear meaning reset is complete */
2523         for (i = 0; i < 10; i++) {
2524                 usec_delay(1);
2525                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2526                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2527                         break;
2528         }
2529
2530         if (ctrl & IXGBE_CTRL_RST_MASK) {
2531                 status = IXGBE_ERR_RESET_FAILED;
2532                 DEBUGOUT("Reset polling failed to complete.\n");
2533         }
2534
2535         msec_delay(50);
2536
2537         /* Double resets are required for recovery from certain error
2538          * conditions.  Between resets, it is necessary to stall to
2539          * allow time for any pending HW events to complete.
2540          */
2541         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2542                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2543                 goto mac_reset_top;
2544         }
2545
2546         /* Store the permanent mac address */
2547         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2548
2549         /* Store MAC address from RAR0, clear receive address registers, and
2550          * clear the multicast table.  Also reset num_rar_entries to 128,
2551          * since we modify this value when programming the SAN MAC address.
2552          */
2553         hw->mac.num_rar_entries = 128;
2554         hw->mac.ops.init_rx_addrs(hw);
2555
2556         ixgbe_set_mdio_speed(hw);
2557
2558         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2559                 ixgbe_setup_mux_ctl(hw);
2560
2561         return status;
2562 }
2563
2564 /**
2565  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2566  * @hw: pointer to hardware structure
2567  */
2568 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2569 {
2570         u32 status;
2571         u16 reg;
2572
2573         status = hw->phy.ops.read_reg(hw,
2574                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2575                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2576                                       &reg);
2577
2578         if (status != IXGBE_SUCCESS)
2579                 return status;
2580
2581         /* If PHY FW reset completed bit is set then this is the first
2582          * SW instance after a power on so the PHY FW must be un-stalled.
2583          */
2584         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2585                 status = hw->phy.ops.read_reg(hw,
2586                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2587                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2588                                         &reg);
2589
2590                 if (status != IXGBE_SUCCESS)
2591                         return status;
2592
2593                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2594
2595                 status = hw->phy.ops.write_reg(hw,
2596                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2597                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2598                                         reg);
2599
2600                 if (status != IXGBE_SUCCESS)
2601                         return status;
2602         }
2603
2604         return status;
2605 }
2606
2607 /**
2608  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2609  *  @hw: pointer to hardware structure
2610  *
2611  *  Configures the integrated KR PHY for X550EM_x.
2612  **/
2613 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2614 {
2615         if (hw->mac.type != ixgbe_mac_X550EM_x)
2616                 return IXGBE_SUCCESS;
2617
2618         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2619 }
2620
2621 /**
2622  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2623  *  @hw: pointer to hardware structure
2624  *
2625  *  Configure the external PHY and the integrated KR PHY for SFP support.
2626  **/
2627 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2628                                     ixgbe_link_speed speed,
2629                                     bool autoneg_wait_to_complete)
2630 {
2631         s32 ret_val;
2632         u16 reg_slice, reg_val;
2633         bool setup_linear = false;
2634         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2635
2636         /* Check if SFP module is supported and linear */
2637         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2638
2639         /* If no SFP module present, then return success. Return success since
2640          * there is no reason to configure CS4227 and SFP not present error is
2641          * not excepted in the setup MAC link flow.
2642          */
2643         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2644                 return IXGBE_SUCCESS;
2645
2646         if (ret_val != IXGBE_SUCCESS)
2647                 return ret_val;
2648
2649         /* Configure internal PHY for KR/KX. */
2650         ixgbe_setup_kr_speed_x550em(hw, speed);
2651
2652         /* Configure CS4227 LINE side to proper mode. */
2653         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2654                     (hw->bus.lan_id << 12);
2655         if (setup_linear)
2656                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2657         else
2658                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2659         ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2660                                           reg_val);
2661         return ret_val;
2662 }
2663
2664 /**
2665  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2666  *  @hw: pointer to hardware structure
2667  *
2668  *  Configure the the integrated PHY for SFP support.
2669  **/
2670 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2671                                    ixgbe_link_speed speed,
2672                                    bool autoneg_wait_to_complete)
2673 {
2674         s32 ret_val;
2675         u16 reg_phy_ext;
2676         bool setup_linear = false;
2677         u32 reg_slice, reg_phy_int, slice_offset;
2678
2679         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2680
2681         /* Check if SFP module is supported and linear */
2682         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2683
2684         /* If no SFP module present, then return success. Return success since
2685          * SFP not present error is not excepted in the setup MAC link flow.
2686          */
2687         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2688                 return IXGBE_SUCCESS;
2689
2690         if (ret_val != IXGBE_SUCCESS)
2691                 return ret_val;
2692
2693         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2694                 /* Configure internal PHY for native SFI */
2695                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2696                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2697                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2698
2699                 if (ret_val != IXGBE_SUCCESS)
2700                         return ret_val;
2701
2702                 if (setup_linear) {
2703                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2704                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2705                 } else {
2706                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2707                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2708                 }
2709
2710                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2711                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2712                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2713
2714                 if (ret_val != IXGBE_SUCCESS)
2715                         return ret_val;
2716
2717                 /* Setup XFI/SFI internal link. */
2718                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2719         } else {
2720                 /* Configure internal PHY for KR/KX. */
2721                 ixgbe_setup_kr_speed_x550em(hw, speed);
2722
2723                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2724                         /* Find Address */
2725                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2726                         return IXGBE_ERR_PHY_ADDR_INVALID;
2727                 }
2728
2729                 /* Get external PHY device id */
2730                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2731                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2732
2733                 if (ret_val != IXGBE_SUCCESS)
2734                         return ret_val;
2735
2736                 /* When configuring quad port CS4223, the MAC instance is part
2737                  * of the slice offset.
2738                  */
2739                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2740                         slice_offset = (hw->bus.lan_id +
2741                                         (hw->bus.instance_id << 1)) << 12;
2742                 else
2743                         slice_offset = hw->bus.lan_id << 12;
2744
2745                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2746                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2747                 if (setup_linear)
2748                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2749                 else
2750                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2751                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2752                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2753         }
2754         return ret_val;
2755 }
2756
2757 /**
2758  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2759  *  @hw: pointer to hardware structure
2760  *
2761  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2762  **/
2763 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2764 {
2765         struct ixgbe_mac_info *mac = &hw->mac;
2766         s32 status;
2767         u32 reg_val;
2768
2769         /* Disable training protocol FSM. */
2770         status = mac->ops.read_iosf_sb_reg(hw,
2771                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2772                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2773         if (status != IXGBE_SUCCESS)
2774                 return status;
2775         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2776         status = mac->ops.write_iosf_sb_reg(hw,
2777                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2778                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2779         if (status != IXGBE_SUCCESS)
2780                 return status;
2781
2782         /* Disable Flex from training TXFFE. */
2783         status = mac->ops.read_iosf_sb_reg(hw,
2784                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2785                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2786         if (status != IXGBE_SUCCESS)
2787                 return status;
2788         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2789         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2790         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2791         status = mac->ops.write_iosf_sb_reg(hw,
2792                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2793                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2794         if (status != IXGBE_SUCCESS)
2795                 return status;
2796         status = mac->ops.read_iosf_sb_reg(hw,
2797                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2798                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2799         if (status != IXGBE_SUCCESS)
2800                 return status;
2801         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2802         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2803         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2804         status = mac->ops.write_iosf_sb_reg(hw,
2805                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2806                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2807         if (status != IXGBE_SUCCESS)
2808                 return status;
2809
2810         /* Enable override for coefficients. */
2811         status = mac->ops.read_iosf_sb_reg(hw,
2812                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2813                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2814         if (status != IXGBE_SUCCESS)
2815                 return status;
2816         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2817         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2818         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2819         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2820         status = mac->ops.write_iosf_sb_reg(hw,
2821                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2822                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2823         return status;
2824 }
2825
2826 /**
2827  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2828  *  @hw: pointer to hardware structure
2829  *  @speed: the link speed to force
2830  *
2831  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2832  *  internal and external PHY at a specific speed, without autonegotiation.
2833  **/
2834 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2835 {
2836         struct ixgbe_mac_info *mac = &hw->mac;
2837         s32 status;
2838         u32 reg_val;
2839
2840         /* Disable AN and force speed to 10G Serial. */
2841         status = mac->ops.read_iosf_sb_reg(hw,
2842                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2843                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2844         if (status != IXGBE_SUCCESS)
2845                 return status;
2846
2847         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2848         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2849
2850         /* Select forced link speed for internal PHY. */
2851         switch (*speed) {
2852         case IXGBE_LINK_SPEED_10GB_FULL:
2853                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2854                 break;
2855         case IXGBE_LINK_SPEED_1GB_FULL:
2856                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2857                 break;
2858         default:
2859                 /* Other link speeds are not supported by internal KR PHY. */
2860                 return IXGBE_ERR_LINK_SETUP;
2861         }
2862
2863         status = mac->ops.write_iosf_sb_reg(hw,
2864                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2865                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2866         if (status != IXGBE_SUCCESS)
2867                 return status;
2868
2869         /* Additional configuration needed for x550em_x */
2870         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2871                 status = ixgbe_setup_ixfi_x550em_x(hw);
2872                 if (status != IXGBE_SUCCESS)
2873                         return status;
2874         }
2875
2876         /* Toggle port SW reset by AN reset. */
2877         status = mac->ops.read_iosf_sb_reg(hw,
2878                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2879                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2880         if (status != IXGBE_SUCCESS)
2881                 return status;
2882         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2883         status = mac->ops.write_iosf_sb_reg(hw,
2884                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2885                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2886
2887         return status;
2888 }
2889
2890 /**
2891  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2892  * @hw: address of hardware structure
2893  * @link_up: address of boolean to indicate link status
2894  *
2895  * Returns error code if unable to get link status.
2896  */
2897 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2898 {
2899         u32 ret;
2900         u16 autoneg_status;
2901
2902         *link_up = false;
2903
2904         /* read this twice back to back to indicate current status */
2905         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2906                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2907                                    &autoneg_status);
2908         if (ret != IXGBE_SUCCESS)
2909                 return ret;
2910
2911         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2912                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2913                                    &autoneg_status);
2914         if (ret != IXGBE_SUCCESS)
2915                 return ret;
2916
2917         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2918
2919         return IXGBE_SUCCESS;
2920 }
2921
2922 /**
2923  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2924  * @hw: point to hardware structure
2925  *
2926  * Configures the link between the integrated KR PHY and the external X557 PHY
2927  * The driver will call this function when it gets a link status change
2928  * interrupt from the X557 PHY. This function configures the link speed
2929  * between the PHYs to match the link speed of the BASE-T link.
2930  *
2931  * A return of a non-zero value indicates an error, and the base driver should
2932  * not report link up.
2933  */
2934 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2935 {
2936         ixgbe_link_speed force_speed;
2937         bool link_up;
2938         u32 status;
2939         u16 speed;
2940
2941         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2942                 return IXGBE_ERR_CONFIG;
2943
2944         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2945                 /* If link is down, there is no setup necessary so return  */
2946                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2947                 if (status != IXGBE_SUCCESS)
2948                         return status;
2949
2950                 if (!link_up)
2951                         return IXGBE_SUCCESS;
2952
2953                 status = hw->phy.ops.read_reg(hw,
2954                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2955                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2956                                               &speed);
2957                 if (status != IXGBE_SUCCESS)
2958                         return status;
2959
2960                 /* If link is still down - no setup is required so return */
2961                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2962                 if (status != IXGBE_SUCCESS)
2963                         return status;
2964                 if (!link_up)
2965                         return IXGBE_SUCCESS;
2966
2967                 /* clear everything but the speed and duplex bits */
2968                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2969
2970                 switch (speed) {
2971                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2972                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2973                         break;
2974                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2975                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2976                         break;
2977                 default:
2978                         /* Internal PHY does not support anything else */
2979                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2980                 }
2981
2982                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2983         } else {
2984                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2985                         IXGBE_LINK_SPEED_1GB_FULL;
2986                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2987         }
2988 }
2989
2990 /**
2991  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2992  *  @hw: pointer to hardware structure
2993  *
2994  *  Configures the integrated KR PHY to use internal loopback mode.
2995  **/
2996 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2997 {
2998         s32 status;
2999         u32 reg_val;
3000
3001         /* Disable AN and force speed to 10G Serial. */
3002         status = hw->mac.ops.read_iosf_sb_reg(hw,
3003                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3004                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3005         if (status != IXGBE_SUCCESS)
3006                 return status;
3007         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3008         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3009         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3010         status = hw->mac.ops.write_iosf_sb_reg(hw,
3011                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3012                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3013         if (status != IXGBE_SUCCESS)
3014                 return status;
3015
3016         /* Set near-end loopback clocks. */
3017         status = hw->mac.ops.read_iosf_sb_reg(hw,
3018                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3019                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3020         if (status != IXGBE_SUCCESS)
3021                 return status;
3022         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3023         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3024         status = hw->mac.ops.write_iosf_sb_reg(hw,
3025                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3026                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3027         if (status != IXGBE_SUCCESS)
3028                 return status;
3029
3030         /* Set loopback enable. */
3031         status = hw->mac.ops.read_iosf_sb_reg(hw,
3032                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3033                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3034         if (status != IXGBE_SUCCESS)
3035                 return status;
3036         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3037         status = hw->mac.ops.write_iosf_sb_reg(hw,
3038                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3039                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3040         if (status != IXGBE_SUCCESS)
3041                 return status;
3042
3043         /* Training bypass. */
3044         status = hw->mac.ops.read_iosf_sb_reg(hw,
3045                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3046                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3047         if (status != IXGBE_SUCCESS)
3048                 return status;
3049         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3050         status = hw->mac.ops.write_iosf_sb_reg(hw,
3051                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3052                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3053
3054         return status;
3055 }
3056
3057 /**
3058  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3059  *  assuming that the semaphore is already obtained.
3060  *  @hw: pointer to hardware structure
3061  *  @offset: offset of  word in the EEPROM to read
3062  *  @data: word read from the EEPROM
3063  *
3064  *  Reads a 16 bit word from the EEPROM using the hostif.
3065  **/
3066 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3067                                    u16 *data)
3068 {
3069         s32 status;
3070         struct ixgbe_hic_read_shadow_ram buffer;
3071
3072         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
3073         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3074         buffer.hdr.req.buf_lenh = 0;
3075         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3076         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3077
3078         /* convert offset from words to bytes */
3079         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3080         /* one word */
3081         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3082
3083         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3084                                               sizeof(buffer),
3085                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3086
3087         if (status)
3088                 return status;
3089
3090         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3091                                           FW_NVM_DATA_OFFSET);
3092
3093         return 0;
3094 }
3095
3096 /**
3097  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3098  *  @hw: pointer to hardware structure
3099  *  @offset: offset of  word in the EEPROM to read
3100  *  @data: word read from the EEPROM
3101  *
3102  *  Reads a 16 bit word from the EEPROM using the hostif.
3103  **/
3104 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3105                               u16 *data)
3106 {
3107         s32 status = IXGBE_SUCCESS;
3108
3109         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3110
3111         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3112             IXGBE_SUCCESS) {
3113                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
3114                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3115         } else {
3116                 status = IXGBE_ERR_SWFW_SYNC;
3117         }
3118
3119         return status;
3120 }
3121
3122 /**
3123  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3124  *  @hw: pointer to hardware structure
3125  *  @offset: offset of  word in the EEPROM to read
3126  *  @words: number of words
3127  *  @data: word(s) read from the EEPROM
3128  *
3129  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
3130  **/
3131 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3132                                      u16 offset, u16 words, u16 *data)
3133 {
3134         struct ixgbe_hic_read_shadow_ram buffer;
3135         u32 current_word = 0;
3136         u16 words_to_read;
3137         s32 status;
3138         u32 i;
3139
3140         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3141
3142         /* Take semaphore for the entire operation. */
3143         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3144         if (status) {
3145                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3146                 return status;
3147         }
3148         while (words) {
3149                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3150                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3151                 else
3152                         words_to_read = words;
3153
3154                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3155                 buffer.hdr.req.buf_lenh = 0;
3156                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3157                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3158
3159                 /* convert offset from words to bytes */
3160                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3161                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3162
3163                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3164                                                       sizeof(buffer),
3165                                                       IXGBE_HI_COMMAND_TIMEOUT,
3166                                                       false);
3167
3168                 if (status) {
3169                         DEBUGOUT("Host interface command failed\n");
3170                         goto out;
3171                 }
3172
3173                 for (i = 0; i < words_to_read; i++) {
3174                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3175                                   2 * i;
3176                         u32 value = IXGBE_READ_REG(hw, reg);
3177
3178                         data[current_word] = (u16)(value & 0xffff);
3179                         current_word++;
3180                         i++;
3181                         if (i < words_to_read) {
3182                                 value >>= 16;
3183                                 data[current_word] = (u16)(value & 0xffff);
3184                                 current_word++;
3185                         }
3186                 }
3187                 words -= words_to_read;
3188         }
3189
3190 out:
3191         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3192         return status;
3193 }
3194
3195 /**
3196  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3197  *  @hw: pointer to hardware structure
3198  *  @offset: offset of  word in the EEPROM to write
3199  *  @data: word write to the EEPROM
3200  *
3201  *  Write a 16 bit word to the EEPROM using the hostif.
3202  **/
3203 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3204                                     u16 data)
3205 {
3206         s32 status;
3207         struct ixgbe_hic_write_shadow_ram buffer;
3208
3209         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3210
3211         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3212         buffer.hdr.req.buf_lenh = 0;
3213         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3214         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3215
3216          /* one word */
3217         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3218         buffer.data = data;
3219         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3220
3221         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3222                                               sizeof(buffer),
3223                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3224
3225         return status;
3226 }
3227
3228 /**
3229  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3230  *  @hw: pointer to hardware structure
3231  *  @offset: offset of  word in the EEPROM to write
3232  *  @data: word write to the EEPROM
3233  *
3234  *  Write a 16 bit word to the EEPROM using the hostif.
3235  **/
3236 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3237                                u16 data)
3238 {
3239         s32 status = IXGBE_SUCCESS;
3240
3241         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3242
3243         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3244             IXGBE_SUCCESS) {
3245                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3246                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3247         } else {
3248                 DEBUGOUT("write ee hostif failed to get semaphore");
3249                 status = IXGBE_ERR_SWFW_SYNC;
3250         }
3251
3252         return status;
3253 }
3254
3255 /**
3256  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3257  *  @hw: pointer to hardware structure
3258  *  @offset: offset of  word in the EEPROM to write
3259  *  @words: number of words
3260  *  @data: word(s) write to the EEPROM
3261  *
3262  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3263  **/
3264 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3265                                       u16 offset, u16 words, u16 *data)
3266 {
3267         s32 status = IXGBE_SUCCESS;
3268         u32 i = 0;
3269
3270         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3271
3272         /* Take semaphore for the entire operation. */
3273         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3274         if (status != IXGBE_SUCCESS) {
3275                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3276                 goto out;
3277         }
3278
3279         for (i = 0; i < words; i++) {
3280                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3281                                                          data[i]);
3282
3283                 if (status != IXGBE_SUCCESS) {
3284                         DEBUGOUT("Eeprom buffered write failed\n");
3285                         break;
3286                 }
3287         }
3288
3289         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3290 out:
3291
3292         return status;
3293 }
3294
3295 /**
3296  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3297  * @hw: pointer to hardware structure
3298  * @ptr: pointer offset in eeprom
3299  * @size: size of section pointed by ptr, if 0 first word will be used as size
3300  * @csum: address of checksum to update
3301  *
3302  * Returns error status for any failure
3303  */
3304 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3305                                    u16 size, u16 *csum, u16 *buffer,
3306                                    u32 buffer_size)
3307 {
3308         u16 buf[256];
3309         s32 status;
3310         u16 length, bufsz, i, start;
3311         u16 *local_buffer;
3312
3313         bufsz = sizeof(buf) / sizeof(buf[0]);
3314
3315         /* Read a chunk at the pointer location */
3316         if (!buffer) {
3317                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3318                 if (status) {
3319                         DEBUGOUT("Failed to read EEPROM image\n");
3320                         return status;
3321                 }
3322                 local_buffer = buf;
3323         } else {
3324                 if (buffer_size < ptr)
3325                         return  IXGBE_ERR_PARAM;
3326                 local_buffer = &buffer[ptr];
3327         }
3328
3329         if (size) {
3330                 start = 0;
3331                 length = size;
3332         } else {
3333                 start = 1;
3334                 length = local_buffer[0];
3335
3336                 /* Skip pointer section if length is invalid. */
3337                 if (length == 0xFFFF || length == 0 ||
3338                     (ptr + length) >= hw->eeprom.word_size)
3339                         return IXGBE_SUCCESS;
3340         }
3341
3342         if (buffer && ((u32)start + (u32)length > buffer_size))
3343                 return IXGBE_ERR_PARAM;
3344
3345         for (i = start; length; i++, length--) {
3346                 if (i == bufsz && !buffer) {
3347                         ptr += bufsz;
3348                         i = 0;
3349                         if (length < bufsz)
3350                                 bufsz = length;
3351
3352                         /* Read a chunk at the pointer location */
3353                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3354                                                                   bufsz, buf);
3355                         if (status) {
3356                                 DEBUGOUT("Failed to read EEPROM image\n");
3357                                 return status;
3358                         }
3359                 }
3360                 *csum += local_buffer[i];
3361         }
3362         return IXGBE_SUCCESS;
3363 }
3364
3365 /**
3366  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3367  *  @hw: pointer to hardware structure
3368  *  @buffer: pointer to buffer containing calculated checksum
3369  *  @buffer_size: size of buffer
3370  *
3371  *  Returns a negative error code on error, or the 16-bit checksum
3372  **/
3373 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3374 {
3375         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3376         u16 *local_buffer;
3377         s32 status;
3378         u16 checksum = 0;
3379         u16 pointer, i, size;
3380
3381         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3382
3383         hw->eeprom.ops.init_params(hw);
3384
3385         if (!buffer) {
3386                 /* Read pointer area */
3387                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3388                                                      IXGBE_EEPROM_LAST_WORD + 1,
3389                                                      eeprom_ptrs);
3390                 if (status) {
3391                         DEBUGOUT("Failed to read EEPROM image\n");
3392                         return status;
3393                 }
3394                 local_buffer = eeprom_ptrs;
3395         } else {
3396                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3397                         return IXGBE_ERR_PARAM;
3398                 local_buffer = buffer;
3399         }
3400
3401         /*
3402          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3403          * checksum word itself
3404          */
3405         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3406                 if (i != IXGBE_EEPROM_CHECKSUM)
3407                         checksum += local_buffer[i];
3408
3409         /*
3410          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3411          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3412          */
3413         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3414                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3415                         continue;
3416
3417                 pointer = local_buffer[i];
3418
3419                 /* Skip pointer section if the pointer is invalid. */
3420                 if (pointer == 0xFFFF || pointer == 0 ||
3421                     pointer >= hw->eeprom.word_size)
3422                         continue;
3423
3424                 switch (i) {
3425                 case IXGBE_PCIE_GENERAL_PTR:
3426                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3427                         break;
3428                 case IXGBE_PCIE_CONFIG0_PTR:
3429                 case IXGBE_PCIE_CONFIG1_PTR:
3430                         size = IXGBE_PCIE_CONFIG_SIZE;
3431                         break;
3432                 default:
3433                         size = 0;
3434                         break;
3435                 }
3436
3437                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3438                                                 buffer, buffer_size);
3439                 if (status)
3440                         return status;
3441         }
3442
3443         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3444
3445         return (s32)checksum;
3446 }
3447
3448 /**
3449  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3450  *  @hw: pointer to hardware structure
3451  *
3452  *  Returns a negative error code on error, or the 16-bit checksum
3453  **/
3454 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3455 {
3456         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3457 }
3458
3459 /**
3460  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3461  *  @hw: pointer to hardware structure
3462  *  @checksum_val: calculated checksum
3463  *
3464  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3465  *  caller does not need checksum_val, the value can be NULL.
3466  **/
3467 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3468 {
3469         s32 status;
3470         u16 checksum;
3471         u16 read_checksum = 0;
3472
3473         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3474
3475         /* Read the first word from the EEPROM. If this times out or fails, do
3476          * not continue or we could be in for a very long wait while every
3477          * EEPROM read fails
3478          */
3479         status = hw->eeprom.ops.read(hw, 0, &checksum);
3480         if (status) {
3481                 DEBUGOUT("EEPROM read failed\n");
3482                 return status;
3483         }
3484
3485         status = hw->eeprom.ops.calc_checksum(hw);
3486         if (status < 0)
3487                 return status;
3488
3489         checksum = (u16)(status & 0xffff);
3490
3491         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3492                                            &read_checksum);
3493         if (status)
3494                 return status;
3495
3496         /* Verify read checksum from EEPROM is the same as
3497          * calculated checksum
3498          */
3499         if (read_checksum != checksum) {
3500                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3501                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3502                              "Invalid EEPROM checksum");
3503         }
3504
3505         /* If the user cares, return the calculated checksum */
3506         if (checksum_val)
3507                 *checksum_val = checksum;
3508
3509         return status;
3510 }
3511
3512 /**
3513  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3514  * @hw: pointer to hardware structure
3515  *
3516  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3517  * checksum and updates the EEPROM and instructs the hardware to update
3518  * the flash.
3519  **/
3520 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3521 {
3522         s32 status;
3523         u16 checksum = 0;
3524
3525         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3526
3527         /* Read the first word from the EEPROM. If this times out or fails, do
3528          * not continue or we could be in for a very long wait while every
3529          * EEPROM read fails
3530          */
3531         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3532         if (status) {
3533                 DEBUGOUT("EEPROM read failed\n");
3534                 return status;
3535         }
3536
3537         status = ixgbe_calc_eeprom_checksum_X550(hw);
3538         if (status < 0)
3539                 return status;
3540
3541         checksum = (u16)(status & 0xffff);
3542
3543         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3544                                             checksum);
3545         if (status)
3546                 return status;
3547
3548         status = ixgbe_update_flash_X550(hw);
3549
3550         return status;
3551 }
3552
3553 /**
3554  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3555  *  @hw: pointer to hardware structure
3556  *
3557  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3558  **/
3559 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3560 {
3561         s32 status = IXGBE_SUCCESS;
3562         union ixgbe_hic_hdr2 buffer;
3563
3564         DEBUGFUNC("ixgbe_update_flash_X550");
3565
3566         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3567         buffer.req.buf_lenh = 0;
3568         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3569         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3570
3571         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3572                                               sizeof(buffer),
3573                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3574
3575         return status;
3576 }
3577
3578 /**
3579  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3580  *  @hw: pointer to hardware structure
3581  *
3582  *  Determines physical layer capabilities of the current configuration.
3583  **/
3584 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3585 {
3586         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3587         u16 ext_ability = 0;
3588
3589         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3590
3591         hw->phy.ops.identify(hw);
3592
3593         switch (hw->phy.type) {
3594         case ixgbe_phy_x550em_kr:
3595                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3596                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3597                 break;
3598         case ixgbe_phy_x550em_kx4:
3599                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3600                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3601                 break;
3602         case ixgbe_phy_x550em_ext_t:
3603                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3604                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3605                                      &ext_ability);
3606                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3607                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3608                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3609                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3610                 break;
3611         default:
3612                 break;
3613         }
3614
3615         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3616                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3617
3618         return physical_layer;
3619 }
3620
3621 /**
3622  * ixgbe_get_bus_info_x550em - Set PCI bus info
3623  * @hw: pointer to hardware structure
3624  *
3625  * Sets bus link width and speed to unknown because X550em is
3626  * not a PCI device.
3627  **/
3628 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3629 {
3630
3631         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3632
3633         hw->bus.width = ixgbe_bus_width_unknown;
3634         hw->bus.speed = ixgbe_bus_speed_unknown;
3635
3636         hw->mac.ops.set_lan_id(hw);
3637
3638         return IXGBE_SUCCESS;
3639 }
3640
3641 /**
3642  * ixgbe_disable_rx_x550 - Disable RX unit
3643  *
3644  * Enables the Rx DMA unit for x550
3645  **/
3646 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3647 {
3648         u32 rxctrl, pfdtxgswc;
3649         s32 status;
3650         struct ixgbe_hic_disable_rxen fw_cmd;
3651
3652         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3653
3654         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3655         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3656                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3657                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3658                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3659                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3660                         hw->mac.set_lben = true;
3661                 } else {
3662                         hw->mac.set_lben = false;
3663                 }
3664
3665                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3666                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3667                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3668                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3669
3670                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3671                                         sizeof(struct ixgbe_hic_disable_rxen),
3672                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3673
3674                 /* If we fail - disable RX using register write */
3675                 if (status) {
3676                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3677                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3678                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3679                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3680                         }
3681                 }
3682         }
3683 }
3684
3685 /**
3686  * ixgbe_enter_lplu_x550em - Transition to low power states
3687  *  @hw: pointer to hardware structure
3688  *
3689  * Configures Low Power Link Up on transition to low power states
3690  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3691  * X557 PHY immediately prior to entering LPLU.
3692  **/
3693 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3694 {
3695         u16 an_10g_cntl_reg, autoneg_reg, speed;
3696         s32 status;
3697         ixgbe_link_speed lcd_speed;
3698         u32 save_autoneg;
3699         bool link_up;
3700
3701         /* SW LPLU not required on later HW revisions. */
3702         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3703             (IXGBE_FUSES0_REV_MASK &
3704              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3705                 return IXGBE_SUCCESS;
3706
3707         /* If blocked by MNG FW, then don't restart AN */
3708         if (ixgbe_check_reset_blocked(hw))
3709                 return IXGBE_SUCCESS;
3710
3711         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3712         if (status != IXGBE_SUCCESS)
3713                 return status;
3714
3715         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3716
3717         if (status != IXGBE_SUCCESS)
3718                 return status;
3719
3720         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3721          * disabled, then force link down by entering low power mode.
3722          */
3723         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3724             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3725                 return ixgbe_set_copper_phy_power(hw, FALSE);
3726
3727         /* Determine LCD */
3728         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3729
3730         if (status != IXGBE_SUCCESS)
3731                 return status;
3732
3733         /* If no valid LCD link speed, then force link down and exit. */
3734         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3735                 return ixgbe_set_copper_phy_power(hw, FALSE);
3736
3737         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3738                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3739                                       &speed);
3740
3741         if (status != IXGBE_SUCCESS)
3742                 return status;
3743
3744         /* If no link now, speed is invalid so take link down */
3745         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3746         if (status != IXGBE_SUCCESS)
3747                 return ixgbe_set_copper_phy_power(hw, false);
3748
3749         /* clear everything but the speed bits */
3750         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3751
3752         /* If current speed is already LCD, then exit. */
3753         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3754              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3755             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3756              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3757                 return status;
3758
3759         /* Clear AN completed indication */
3760         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3761                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3762                                       &autoneg_reg);
3763
3764         if (status != IXGBE_SUCCESS)
3765                 return status;
3766
3767         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3768                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3769                              &an_10g_cntl_reg);
3770
3771         if (status != IXGBE_SUCCESS)
3772                 return status;
3773
3774         status = hw->phy.ops.read_reg(hw,
3775                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3776                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3777                              &autoneg_reg);
3778
3779         if (status != IXGBE_SUCCESS)
3780                 return status;
3781
3782         save_autoneg = hw->phy.autoneg_advertised;
3783
3784         /* Setup link at least common link speed */
3785         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3786
3787         /* restore autoneg from before setting lplu speed */
3788         hw->phy.autoneg_advertised = save_autoneg;
3789
3790         return status;
3791 }
3792
3793 /**
3794  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3795  *  @hw: pointer to hardware structure
3796  *  @lcd_speed: pointer to lowest common link speed
3797  *
3798  * Determine lowest common link speed with link partner.
3799  **/
3800 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3801 {
3802         u16 an_lp_status;
3803         s32 status;
3804         u16 word = hw->eeprom.ctrl_word_3;
3805
3806         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3807
3808         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3809                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3810                                       &an_lp_status);
3811
3812         if (status != IXGBE_SUCCESS)
3813                 return status;
3814
3815         /* If link partner advertised 1G, return 1G */
3816         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3817                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3818                 return status;
3819         }
3820
3821         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3822         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3823             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3824                 return status;
3825
3826         /* Link partner not capable of lower speeds, return 10G */
3827         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3828         return status;
3829 }
3830
3831 /**
3832  *  ixgbe_setup_fc_X550em - Set up flow control
3833  *  @hw: pointer to hardware structure
3834  *
3835  *  Called at init time to set up flow control.
3836  **/
3837 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3838 {
3839         s32 ret_val = IXGBE_SUCCESS;
3840         u32 pause, asm_dir, reg_val;
3841
3842         DEBUGFUNC("ixgbe_setup_fc_X550em");
3843
3844         /* Validate the requested mode */
3845         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3846                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3847                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3848                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3849                 goto out;
3850         }
3851
3852         /* 10gig parts do not have a word in the EEPROM to determine the
3853          * default flow control setting, so we explicitly set it to full.
3854          */
3855         if (hw->fc.requested_mode == ixgbe_fc_default)
3856                 hw->fc.requested_mode = ixgbe_fc_full;
3857
3858         /* Determine PAUSE and ASM_DIR bits. */
3859         switch (hw->fc.requested_mode) {
3860         case ixgbe_fc_none:
3861                 pause = 0;
3862                 asm_dir = 0;
3863                 break;
3864         case ixgbe_fc_tx_pause:
3865                 pause = 0;
3866                 asm_dir = 1;
3867                 break;
3868         case ixgbe_fc_rx_pause:
3869                 /* Rx Flow control is enabled and Tx Flow control is
3870                  * disabled by software override. Since there really
3871                  * isn't a way to advertise that we are capable of RX
3872                  * Pause ONLY, we will advertise that we support both
3873                  * symmetric and asymmetric Rx PAUSE, as such we fall
3874                  * through to the fc_full statement.  Later, we will
3875                  * disable the adapter's ability to send PAUSE frames.
3876                  */
3877         case ixgbe_fc_full:
3878                 pause = 1;
3879                 asm_dir = 1;
3880                 break;
3881         default:
3882                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3883                         "Flow control param set incorrectly\n");
3884                 ret_val = IXGBE_ERR_CONFIG;
3885                 goto out;
3886         }
3887
3888         switch (hw->device_id) {
3889         case IXGBE_DEV_ID_X550EM_X_KR:
3890         case IXGBE_DEV_ID_X550EM_A_KR:
3891         case IXGBE_DEV_ID_X550EM_A_KR_L:
3892                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3893                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3894                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3895                 if (ret_val != IXGBE_SUCCESS)
3896                         goto out;
3897                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3898                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3899                 if (pause)
3900                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3901                 if (asm_dir)
3902                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3903                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3904                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3905                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3906
3907                 /* This device does not fully support AN. */
3908                 hw->fc.disable_fc_autoneg = true;
3909                 break;
3910         default:
3911                 break;
3912         }
3913
3914 out:
3915         return ret_val;
3916 }
3917
3918 /**
3919  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
3920  *  @hw: pointer to hardware structure
3921  *
3922  *  Enable flow control according to IEEE clause 37.
3923  **/
3924 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
3925 {
3926         u32 link_s1, lp_an_page_low, an_cntl_1;
3927         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3928         ixgbe_link_speed speed;
3929         bool link_up;
3930
3931         /* AN should have completed when the cable was plugged in.
3932          * Look for reasons to bail out.  Bail out if:
3933          * - FC autoneg is disabled, or if
3934          * - link is not up.
3935          */
3936         if (hw->fc.disable_fc_autoneg) {
3937                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3938                               "Flow control autoneg is disabled");
3939                 goto out;
3940         }
3941
3942         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3943         if (!link_up) {
3944                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3945                 goto out;
3946         }
3947
3948         /* Check at auto-negotiation has completed */
3949         status = hw->mac.ops.read_iosf_sb_reg(hw,
3950                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3951                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3952
3953         if (status != IXGBE_SUCCESS ||
3954             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3955                 DEBUGOUT("Auto-Negotiation did not complete\n");
3956                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3957                 goto out;
3958         }
3959
3960         /* Read the 10g AN autoc and LP ability registers and resolve
3961          * local flow control settings accordingly
3962          */
3963         status = hw->mac.ops.read_iosf_sb_reg(hw,
3964                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3965                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3966
3967         if (status != IXGBE_SUCCESS) {
3968                 DEBUGOUT("Auto-Negotiation did not complete\n");
3969                 goto out;
3970         }
3971
3972         status = hw->mac.ops.read_iosf_sb_reg(hw,
3973                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3974                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3975
3976         if (status != IXGBE_SUCCESS) {
3977                 DEBUGOUT("Auto-Negotiation did not complete\n");
3978                 goto out;
3979         }
3980
3981         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3982                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3983                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3984                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3985                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3986
3987 out:
3988         if (status == IXGBE_SUCCESS) {
3989                 hw->fc.fc_was_autonegged = true;
3990         } else {
3991                 hw->fc.fc_was_autonegged = false;
3992                 hw->fc.current_mode = hw->fc.requested_mode;
3993         }
3994 }
3995
3996 /**
3997  *  ixgbe_fc_autoneg_fiber_x550em_a - Enable flow control IEEE clause 37
3998  *  @hw: pointer to hardware structure
3999  *
4000  *  Enable flow control according to IEEE clause 37.
4001  **/
4002 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4003 {
4004         u32 link_s1, pcs_an_lp, pcs_an;
4005         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4006         ixgbe_link_speed speed;
4007         bool link_up;
4008
4009         /* AN should have completed when the cable was plugged in.
4010          * Look for reasons to bail out.  Bail out if:
4011          * - FC autoneg is disabled, or if
4012          * - link is not up.
4013          */
4014         if (hw->fc.disable_fc_autoneg) {
4015                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4016                              "Flow control autoneg is disabled");
4017                 goto out;
4018         }
4019
4020         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4021         if (!link_up) {
4022                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4023                 goto out;
4024         }
4025
4026         /* Check if auto-negotiation has completed */
4027         status = hw->mac.ops.read_iosf_sb_reg(hw,
4028                                          IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4029                                          IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4030
4031         if (status != IXGBE_SUCCESS ||
4032             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4033                 DEBUGOUT("Auto-Negotiation did not complete\n");
4034                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4035                 goto out;
4036         }
4037
4038         /* Determine advertised flow control */
4039         status = hw->mac.ops.read_iosf_sb_reg(hw,
4040                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4041                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4042
4043         if (status != IXGBE_SUCCESS) {
4044                 DEBUGOUT("Auto-Negotiation did not complete\n");
4045                 goto out;
4046         }
4047
4048         /* Determine link parter flow control */
4049         status = hw->mac.ops.read_iosf_sb_reg(hw,
4050                                   IXGBE_KRM_PCS_KX_AN_LP(hw->bus.lan_id),
4051                                   IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an_lp);
4052
4053         if (status != IXGBE_SUCCESS) {
4054                 DEBUGOUT("Auto-Negotiation did not complete\n");
4055                 goto out;
4056         }
4057
4058         status = ixgbe_negotiate_fc(hw, pcs_an, pcs_an_lp,
4059                                     IXGBE_KRM_PCS_KX_AN_SYM_PAUSE,
4060                                     IXGBE_KRM_PCS_KX_AN_ASM_PAUSE,
4061                                     IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE,
4062                                     IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE);
4063
4064 out:
4065         if (status == IXGBE_SUCCESS) {
4066                 hw->fc.fc_was_autonegged = true;
4067         } else {
4068                 hw->fc.fc_was_autonegged = false;
4069                 hw->fc.current_mode = hw->fc.requested_mode;
4070         }
4071 }
4072
4073 /**
4074  *  ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4075  *  @hw: pointer to hardware structure
4076  *
4077  *  Enable flow control according to IEEE clause 37.
4078  **/
4079 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4080 {
4081         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4082         u16 reg, pcs_an_lp, pcs_an;
4083         ixgbe_link_speed speed;
4084         bool link_up;
4085
4086         /* AN should have completed when the cable was plugged in.
4087          * Look for reasons to bail out.  Bail out if:
4088          * - FC autoneg is disabled, or if
4089          * - link is not up.
4090          */
4091         if (hw->fc.disable_fc_autoneg) {
4092                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4093                              "Flow control autoneg is disabled");
4094                 goto out;
4095         }
4096
4097         hw->mac.ops.check_link(hw, &speed, &link_up, false);
4098         if (!link_up) {
4099                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4100                 goto out;
4101         }
4102
4103         /* Check if auto-negotiation has completed */
4104         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4105                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4106         if (status != IXGBE_SUCCESS ||
4107             (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4108                 DEBUGOUT("Auto-Negotiation did not complete\n");
4109                 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4110                 goto out;
4111         }
4112
4113         /* Get the advertized flow control */
4114         status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4115                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4116         if (status != IXGBE_SUCCESS)
4117                 goto out;
4118
4119         /* Get link partner's flow control */
4120         status = hw->phy.ops.read_reg(hw,
4121                         IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4122                                         IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4123         if (status != IXGBE_SUCCESS)
4124                 goto out;
4125
4126         /* Negotiate the flow control */
4127         status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4128                                     IXGBE_M88E1500_COPPER_AN_PAUSE,
4129                                     IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4130                                     IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4131                                     IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4132
4133 out:
4134         if (status == IXGBE_SUCCESS) {
4135                 hw->fc.fc_was_autonegged = true;
4136         } else {
4137                 hw->fc.fc_was_autonegged = false;
4138                 hw->fc.current_mode = hw->fc.requested_mode;
4139         }
4140 }
4141
4142 /**
4143  *  ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4144  *  @hw: pointer to hardware structure
4145  *
4146  *  Called at init time to set up flow control.
4147  **/
4148 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4149 {
4150         u16 reg;
4151         s32 rc;
4152
4153         /* Validate the requested mode */
4154         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4155                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4156                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4157                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4158         }
4159
4160         if (hw->fc.requested_mode == ixgbe_fc_default)
4161                 hw->fc.requested_mode = ixgbe_fc_full;
4162
4163         /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4164         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4165                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4166         if (rc)
4167                 goto out;
4168
4169         /* Disable all the settings related to Flow control Auto-negotiation */
4170         reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4171         reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4172
4173         /* Configure the Asymmetric and symmetric pause according to the user
4174          * requested mode.
4175          */
4176         switch (hw->fc.requested_mode) {
4177         case ixgbe_fc_full:
4178                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4179                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4180                 break;
4181         case ixgbe_fc_rx_pause:
4182                 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4183                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4184                 break;
4185         case ixgbe_fc_tx_pause:
4186                 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4187                 break;
4188         default:
4189                 break;
4190         }
4191
4192         /* Write back to the Auto-Negotiation register with newly configured
4193          * fields
4194          */
4195         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4196                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4197
4198         /* In this section of the code we restart Auto-negotiation */
4199
4200         /* Read the CONTROL register, Page 0 reg 0 */
4201         rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4202                                         IXGBE_MDIO_ZERO_DEV_TYPE, &reg);
4203         if (rc)
4204                 goto out;
4205
4206         /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4207          * by default
4208          */
4209         reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4210
4211         /* write the new values to the register to restart Auto-Negotiation */
4212         hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4213                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4214
4215 out:
4216         return rc;
4217 }
4218
4219 /**
4220  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4221  *  @hw: pointer to hardware structure
4222  *
4223  *  Called at init time to set up flow control.
4224  **/
4225 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4226 {
4227         s32 status = IXGBE_SUCCESS;
4228         u32 an_cntl, link_ctrl = 0;
4229
4230         DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4231
4232         /* Validate the requested mode */
4233         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4234                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4235                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4236                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4237         }
4238
4239         if (hw->fc.requested_mode == ixgbe_fc_default)
4240                 hw->fc.requested_mode = ixgbe_fc_full;
4241
4242         /* Set up the 1G and 10G flow control advertisement registers so the
4243          * HW will be able to do FC autoneg once the cable is plugged in.  If
4244          * we link at 10G, the 1G advertisement is harmless and vice versa.
4245          */
4246         status = hw->mac.ops.read_iosf_sb_reg(hw,
4247                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4248                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4249
4250         if (status != IXGBE_SUCCESS) {
4251                 DEBUGOUT("Auto-Negotiation did not complete\n");
4252                 return status;
4253         }
4254
4255         /* The possible values of fc.requested_mode are:
4256          * 0: Flow control is completely disabled
4257          * 1: Rx flow control is enabled (we can receive pause frames,
4258          *    but not send pause frames).
4259          * 2: Tx flow control is enabled (we can send pause frames but
4260          *    we do not support receiving pause frames).
4261          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4262          * other: Invalid.
4263          */
4264         switch (hw->fc.requested_mode) {
4265         case ixgbe_fc_none:
4266                 /* Flow control completely disabled by software override. */
4267                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4268                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4269                 break;
4270         case ixgbe_fc_tx_pause:
4271                 /* Tx Flow control is enabled, and Rx Flow control is
4272                  * disabled by software override.
4273                  */
4274                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4275                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4276                 break;
4277         case ixgbe_fc_rx_pause:
4278                 /* Rx Flow control is enabled and Tx Flow control is
4279                  * disabled by software override. Since there really
4280                  * isn't a way to advertise that we are capable of RX
4281                  * Pause ONLY, we will advertise that we support both
4282                  * symmetric and asymmetric Rx PAUSE, as such we fall
4283                  * through to the fc_full statement.  Later, we will
4284                  * disable the adapter's ability to send PAUSE frames.
4285                  */
4286         case ixgbe_fc_full:
4287                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4288                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4289                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4290                 break;
4291         default:
4292                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4293                               "Flow control param set incorrectly\n");
4294                 return IXGBE_ERR_CONFIG;
4295         }
4296
4297         status = hw->mac.ops.write_iosf_sb_reg(hw,
4298                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4299                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4300
4301         /* Restart auto-negotiation. */
4302         status = hw->mac.ops.read_iosf_sb_reg(hw,
4303                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4304                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
4305
4306         if (status != IXGBE_SUCCESS) {
4307                 DEBUGOUT("Auto-Negotiation did not complete\n");
4308                 return status;
4309         }
4310
4311         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4312         status = hw->mac.ops.write_iosf_sb_reg(hw,
4313                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4314                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
4315
4316         return status;
4317 }
4318
4319 /**
4320  *  ixgbe_setup_fc_fiber_x550em_a - Set up flow control
4321  *  @hw: pointer to hardware structure
4322  *
4323  *  Called at init time to set up flow control.
4324  **/
4325 s32 ixgbe_setup_fc_fiber_x550em_a(struct ixgbe_hw *hw)
4326 {
4327         struct ixgbe_mac_info *mac = &hw->mac;
4328         s32 rc = IXGBE_SUCCESS;
4329         u32 an_cntl4, lctrl, pcs_an;
4330
4331         DEBUGFUNC("ixgbe_setup_fc_fiber_x550em_a");
4332
4333         /* Validate the requested mode */
4334         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4335                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4336                               "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4337                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4338         }
4339
4340         /* Enable clause 37 auto-negotiation in KRM_LINK_CTRL_1 */
4341         if (hw->fc.requested_mode == ixgbe_fc_default)
4342                 hw->fc.requested_mode = ixgbe_fc_full;
4343
4344         rc = mac->ops.read_iosf_sb_reg(hw,
4345                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4346                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4347         if (rc)
4348                 return rc;
4349
4350         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
4351         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
4352
4353         rc = mac->ops.write_iosf_sb_reg(hw,
4354                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4355                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4356         if (rc)
4357                 return rc;
4358
4359         /* Enable clause 37 over 73 in KRM_AN_CNTL_4 */
4360         rc = mac->ops.read_iosf_sb_reg(hw,
4361                                        IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4362                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl4);
4363         if (rc)
4364                 return rc;
4365
4366         an_cntl4 |= IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73;
4367
4368         rc = mac->ops.write_iosf_sb_reg(hw,
4369                                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
4370                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl4);
4371         if (rc)
4372                 return rc;
4373
4374         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4375                                           IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4376                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &pcs_an);
4377
4378         if (rc)
4379                 return rc;
4380
4381         /* The possible values of fc.requested_mode are:
4382          * 0: Flow control is completely disabled
4383          * 1: Rx flow control is enabled (we can receive pause frames,
4384          *    but not send pause frames).
4385          * 2: Tx flow control is enabled (we can send pause frames but
4386          *    we do not support receiving pause frames).
4387          * 3: Both Rx and Tx flow control (symmetric) are enabled.
4388          * other: Invalid.
4389          */
4390         switch (hw->fc.requested_mode) {
4391         case ixgbe_fc_none:
4392                 /* Flow control completely disabled by software override. */
4393                 pcs_an &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4394                             IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4395                 break;
4396         case ixgbe_fc_tx_pause:
4397                 /* Tx Flow control is enabled, and Rx Flow control is
4398                  * disabled by software override.
4399                  */
4400                 pcs_an |= IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4401                 pcs_an &= ~IXGBE_KRM_PCS_KX_AN_SYM_PAUSE;
4402                 break;
4403         case ixgbe_fc_rx_pause:
4404                 /* Rx Flow control is enabled and Tx Flow control is
4405                  * disabled by software override. Since there really
4406                  * isn't a way to advertise that we are capable of RX
4407                  * Pause ONLY, we will advertise that we support both
4408                  * symmetric and asymmetric Rx PAUSE, as such we fall
4409                  * through to the fc_full statement.  Later, we will
4410                  * disable the adapter's ability to send PAUSE frames.
4411                  */
4412         case ixgbe_fc_full:
4413                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4414                 pcs_an |= IXGBE_KRM_PCS_KX_AN_SYM_PAUSE |
4415                            IXGBE_KRM_PCS_KX_AN_ASM_PAUSE;
4416                 break;
4417         default:
4418                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4419                               "Flow control param set incorrectly\n");
4420                 return IXGBE_ERR_CONFIG;
4421         }
4422
4423         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4424                                            IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
4425                                            IXGBE_SB_IOSF_TARGET_KR_PHY, pcs_an);
4426
4427         /* Restart auto-negotiation. */
4428         rc = hw->mac.ops.read_iosf_sb_reg(hw,
4429                                           IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4430                                           IXGBE_SB_IOSF_TARGET_KR_PHY, &lctrl);
4431
4432         if (rc) {
4433                 DEBUGOUT("Auto-Negotiation did not complete\n");
4434                 return rc;
4435         }
4436
4437         lctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
4438         rc = hw->mac.ops.write_iosf_sb_reg(hw,
4439                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
4440                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lctrl);
4441
4442         return rc;
4443 }
4444
4445 /**
4446  * ixgbe_set_mux - Set mux for port 1 access with CS4227
4447  * @hw: pointer to hardware structure
4448  * @state: set mux if 1, clear if 0
4449  */
4450 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4451 {
4452         u32 esdp;
4453
4454         if (!hw->bus.lan_id)
4455                 return;
4456         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4457         if (state)
4458                 esdp |= IXGBE_ESDP_SDP1;
4459         else
4460                 esdp &= ~IXGBE_ESDP_SDP1;
4461         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4462         IXGBE_WRITE_FLUSH(hw);
4463 }
4464
4465 /**
4466  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4467  *  @hw: pointer to hardware structure
4468  *  @mask: Mask to specify which semaphore to acquire
4469  *
4470  *  Acquires the SWFW semaphore and sets the I2C MUX
4471  **/
4472 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4473 {
4474         s32 status;
4475
4476         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4477
4478         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4479         if (status)
4480                 return status;
4481
4482         if (mask & IXGBE_GSSR_I2C_MASK)
4483                 ixgbe_set_mux(hw, 1);
4484
4485         return IXGBE_SUCCESS;
4486 }
4487
4488 /**
4489  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4490  *  @hw: pointer to hardware structure
4491  *  @mask: Mask to specify which semaphore to release
4492  *
4493  *  Releases the SWFW semaphore and sets the I2C MUX
4494  **/
4495 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4496 {
4497         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4498
4499         if (mask & IXGBE_GSSR_I2C_MASK)
4500                 ixgbe_set_mux(hw, 0);
4501
4502         ixgbe_release_swfw_sync_X540(hw, mask);
4503 }
4504
4505 /**
4506  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4507  *  @hw: pointer to hardware structure
4508  *  @mask: Mask to specify which semaphore to acquire
4509  *
4510  *  Acquires the SWFW semaphore and get the shared phy token as needed
4511  */
4512 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4513 {
4514         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4515         int retries = FW_PHY_TOKEN_RETRIES;
4516         s32 status = IXGBE_SUCCESS;
4517
4518         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4519
4520         while (--retries) {
4521                 status = IXGBE_SUCCESS;
4522                 if (hmask)
4523                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4524                 if (status)
4525                         return status;
4526                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4527                         return IXGBE_SUCCESS;
4528
4529                 status = ixgbe_get_phy_token(hw);
4530                 if (status == IXGBE_SUCCESS)
4531                         return IXGBE_SUCCESS;
4532
4533                 if (hmask)
4534                         ixgbe_release_swfw_sync_X540(hw, hmask);
4535                 if (status != IXGBE_ERR_TOKEN_RETRY)
4536                         return status;
4537         }
4538
4539         return status;
4540 }
4541
4542 /**
4543  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4544  *  @hw: pointer to hardware structure
4545  *  @mask: Mask to specify which semaphore to release
4546  *
4547  *  Releases the SWFW semaphore and puts the shared phy token as needed
4548  */
4549 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4550 {
4551         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4552
4553         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4554
4555         if (mask & IXGBE_GSSR_TOKEN_SM)
4556                 ixgbe_put_phy_token(hw);
4557
4558         if (hmask)
4559                 ixgbe_release_swfw_sync_X540(hw, hmask);
4560 }
4561
4562 /**
4563  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4564  *  @hw: pointer to hardware structure
4565  *  @reg_addr: 32 bit address of PHY register to read
4566  *  @phy_data: Pointer to read data from PHY register
4567  *
4568  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4569  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4570  *  instances.
4571  **/
4572 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4573                              u32 device_type, u16 *phy_data)
4574 {
4575         s32 status;
4576         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4577
4578         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4579
4580         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4581                 return IXGBE_ERR_SWFW_SYNC;
4582
4583         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4584
4585         hw->mac.ops.release_swfw_sync(hw, mask);
4586
4587         return status;
4588 }
4589
4590 /**
4591  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4592  *  @hw: pointer to hardware structure
4593  *  @reg_addr: 32 bit PHY register to write
4594  *  @device_type: 5 bit device type
4595  *  @phy_data: Data to write to the PHY register
4596  *
4597  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4598  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4599  **/
4600 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4601                               u32 device_type, u16 phy_data)
4602 {
4603         s32 status;
4604         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4605
4606         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4607
4608         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4609                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4610                                                  phy_data);
4611                 hw->mac.ops.release_swfw_sync(hw, mask);
4612         } else {
4613                 status = IXGBE_ERR_SWFW_SYNC;
4614         }
4615
4616         return status;
4617 }
4618
4619 /**
4620  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4621  * @hw: pointer to hardware structure
4622  *
4623  * Handle external Base T PHY interrupt. If high temperature
4624  * failure alarm then return error, else if link status change
4625  * then setup internal/external PHY link
4626  *
4627  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4628  * failure alarm, else return PHY access status.
4629  */
4630 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4631 {
4632         bool lsc;
4633         u32 status;
4634
4635         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4636
4637         if (status != IXGBE_SUCCESS)
4638                 return status;
4639
4640         if (lsc)
4641                 return ixgbe_setup_internal_phy(hw);
4642
4643         return IXGBE_SUCCESS;
4644 }
4645
4646 /**
4647  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4648  * @hw: pointer to hardware structure
4649  * @speed: new link speed
4650  * @autoneg_wait_to_complete: true when waiting for completion is needed
4651  *
4652  * Setup internal/external PHY link speed based on link speed, then set
4653  * external PHY auto advertised link speed.
4654  *
4655  * Returns error status for any failure
4656  **/
4657 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4658                                   ixgbe_link_speed speed,
4659                                   bool autoneg_wait_to_complete)
4660 {
4661         s32 status;
4662         ixgbe_link_speed force_speed;
4663
4664         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4665
4666         /* Setup internal/external PHY link speed to iXFI (10G), unless
4667          * only 1G is auto advertised then setup KX link.
4668          */
4669         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4670                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4671         else
4672                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4673
4674         /* If internal link mode is XFI, then setup XFI internal link. */
4675         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4676                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4677
4678                 if (status != IXGBE_SUCCESS)
4679                         return status;
4680         }
4681
4682         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4683 }
4684
4685 /**
4686  * ixgbe_check_link_t_X550em - Determine link and speed status
4687  * @hw: pointer to hardware structure
4688  * @speed: pointer to link speed
4689  * @link_up: true when link is up
4690  * @link_up_wait_to_complete: bool used to wait for link up or not
4691  *
4692  * Check that both the MAC and X557 external PHY have link.
4693  **/
4694 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4695                               bool *link_up, bool link_up_wait_to_complete)
4696 {
4697         u32 status;
4698         u16 autoneg_status;
4699
4700         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4701                 return IXGBE_ERR_CONFIG;
4702
4703         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4704                                               link_up_wait_to_complete);
4705
4706         /* If check link fails or MAC link is not up, then return */
4707         if (status != IXGBE_SUCCESS || !(*link_up))
4708                 return status;
4709
4710         /* MAC link is up, so check external PHY link.
4711          * Read this twice back to back to indicate current status.
4712          */
4713         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4714                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4715                                       &autoneg_status);
4716
4717         if (status != IXGBE_SUCCESS)
4718                 return status;
4719
4720         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4721                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4722                                       &autoneg_status);
4723
4724         if (status != IXGBE_SUCCESS)
4725                 return status;
4726
4727         /* If external PHY link is not up, then indicate link not up */
4728         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4729                 *link_up = false;
4730
4731         return IXGBE_SUCCESS;
4732 }
4733
4734 /**
4735  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4736  *  @hw: pointer to hardware structure
4737  **/
4738 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4739 {
4740         s32 status;
4741
4742         status = ixgbe_reset_phy_generic(hw);
4743
4744         if (status != IXGBE_SUCCESS)
4745                 return status;
4746
4747         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4748         return ixgbe_enable_lasi_ext_t_x550em(hw);
4749 }
4750
4751 /**
4752  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4753  *  @hw: pointer to hardware structure
4754  *  @led_idx: led number to turn on
4755  **/
4756 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4757 {
4758         u16 phy_data;
4759
4760         DEBUGFUNC("ixgbe_led_on_t_X550em");
4761
4762         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4763                 return IXGBE_ERR_PARAM;
4764
4765         /* To turn on the LED, set mode to ON. */
4766         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4767                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4768         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4769         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4770                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4771
4772         return IXGBE_SUCCESS;
4773 }
4774
4775 /**
4776  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4777  *  @hw: pointer to hardware structure
4778  *  @led_idx: led number to turn off
4779  **/
4780 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4781 {
4782         u16 phy_data;
4783
4784         DEBUGFUNC("ixgbe_led_off_t_X550em");
4785
4786         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4787                 return IXGBE_ERR_PARAM;
4788
4789         /* To turn on the LED, set mode to ON. */
4790         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4791                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4792         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4793         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4794                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4795
4796         return IXGBE_SUCCESS;
4797 }
4798