drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 333  * @hw: pointer to hardware structure
 334  *
 335  * Returns error code
 336  */
 337 static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 338 {
 339         u16 phy_id_high;
 340         u16 phy_id_low;
 341         u32 val = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
 342
 343         hw->phy.addr = (val >> 3) & 0x1F;
 344         val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 345                                    hw->phy.addr, &phy_id_high);
 346         if (val || phy_id_high == 0xFFFF) {
 347                 hw->phy.type = ixgbe_phy_sgmii;
 348                 return 0;
 349         }
 350
 351         val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 352                                    hw->phy.addr, &phy_id_low);
 353         if (val)
 354                 return val;
 355
 356         hw->phy.id = (u32)phy_id_high << 16;
 357         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 358         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 359         hw->phy.type = ixgbe_phy_m88;
 360
 361         return 0;
 362 }
 363
 364 /**
 365  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 366  * @hw: pointer to hardware structure
 367  *
 368  * Returns error code
 369  */
 370 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 371 {
 372         switch (hw->device_id) {
 373         case IXGBE_DEV_ID_X550EM_A_SFP:
 374                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 375                 if (hw->bus.lan_id)
 376                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 377                 else
 378                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 379                 return ixgbe_identify_module_generic(hw);
 380         case IXGBE_DEV_ID_X550EM_X_SFP:
 381                 /* set up for CS4227 usage */
 382                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 383                 ixgbe_setup_mux_ctl(hw);
 384                 ixgbe_check_cs4227(hw);
 385                 /* Fallthrough */
 386
 387         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 388                 return ixgbe_identify_module_generic(hw);
 389                 break;
 390         case IXGBE_DEV_ID_X550EM_X_KX4:
 391                 hw->phy.type = ixgbe_phy_x550em_kx4;
 392                 break;
 393         case IXGBE_DEV_ID_X550EM_X_KR:
 394         case IXGBE_DEV_ID_X550EM_A_KR:
 395         case IXGBE_DEV_ID_X550EM_A_KR_L:
 396                 hw->phy.type = ixgbe_phy_x550em_kr;
 397                 break;
 398         case IXGBE_DEV_ID_X550EM_X_1G_T:
 399         case IXGBE_DEV_ID_X550EM_X_10G_T:
 400         case IXGBE_DEV_ID_X550EM_A_10G_T:
 401                 return ixgbe_identify_phy_generic(hw);
 402         case IXGBE_DEV_ID_X550EM_A_1G_T:
 403         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 404                 return ixgbe_identify_phy_1g(hw);
 405         default:
 406                 break;
 407         }
 408         return IXGBE_SUCCESS;
 409 }
 410
 411 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 412                                      u32 device_type, u16 *phy_data)
 413 {
 414         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 415         return IXGBE_NOT_IMPLEMENTED;
 416 }
 417
 418 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 419                                       u32 device_type, u16 phy_data)
 420 {
 421         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 422         return IXGBE_NOT_IMPLEMENTED;
 423 }
 424
 425 /**
 426  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 427  * @hw: pointer to the hardware structure
 428  * @addr: I2C bus address to read from
 429  * @reg: I2C device register to read from
 430  * @val: pointer to location to receive read value
 431  *
 432  * Returns an error code on error.
 433  **/
 434 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 435                                            u16 reg, u16 *val)
 436 {
 437         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 438 }
 439
 440 /**
 441  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 442  * @hw: pointer to the hardware structure
 443  * @addr: I2C bus address to read from
 444  * @reg: I2C device register to read from
 445  * @val: pointer to location to receive read value
 446  *
 447  * Returns an error code on error.
 448  **/
 449 static s32
 450 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 451                                          u16 reg, u16 *val)
 452 {
 453         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 454 }
 455
 456 /**
 457  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 458  * @hw: pointer to the hardware structure
 459  * @addr: I2C bus address to write to
 460  * @reg: I2C device register to write to
 461  * @val: value to write
 462  *
 463  * Returns an error code on error.
 464  **/
 465 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 466                                             u8 addr, u16 reg, u16 val)
 467 {
 468         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 469 }
 470
 471 /**
 472  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 473  * @hw: pointer to the hardware structure
 474  * @addr: I2C bus address to write to
 475  * @reg: I2C device register to write to
 476  * @val: value to write
 477  *
 478  * Returns an error code on error.
 479  **/
 480 static s32
 481 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 482                                           u8 addr, u16 reg, u16 val)
 483 {
 484         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 485 }
 486
 487 /**
 488 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 489 *  @hw: pointer to hardware structure
 490 *
 491 *  Initialize the function pointers and for MAC type X550EM.
 492 *  Does not touch the hardware.
 493 **/
 494 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 495 {
 496         struct ixgbe_mac_info *mac = &hw->mac;
 497         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 498         struct ixgbe_phy_info *phy = &hw->phy;
 499         struct ixgbe_link_info *link = &hw->link;
 500         s32 ret_val;
 501
 502         DEBUGFUNC("ixgbe_init_ops_X550EM");
 503
 504         /* Similar to X550 so start there. */
 505         ret_val = ixgbe_init_ops_X550(hw);
 506
 507         /* Since this function eventually calls
 508          * ixgbe_init_ops_540 by design, we are setting
 509          * the pointers to NULL explicitly here to overwrite
 510          * the values being set in the x540 function.
 511          */
 512         /* Thermal sensor not supported in x550EM */
 513         mac->ops.get_thermal_sensor_data = NULL;
 514         mac->ops.init_thermal_sensor_thresh = NULL;
 515         mac->thermal_sensor_enabled = false;
 516
 517         /* FCOE not supported in x550EM */
 518         mac->ops.get_san_mac_addr = NULL;
 519         mac->ops.set_san_mac_addr = NULL;
 520         mac->ops.get_wwn_prefix = NULL;
 521         mac->ops.get_fcoe_boot_status = NULL;
 522
 523         /* IPsec not supported in x550EM */
 524         mac->ops.disable_sec_rx_path = NULL;
 525         mac->ops.enable_sec_rx_path = NULL;
 526
 527         /* AUTOC register is not present in x550EM. */
 528         mac->ops.prot_autoc_read = NULL;
 529         mac->ops.prot_autoc_write = NULL;
 530
 531         /* X550EM bus type is internal*/
 532         hw->bus.type = ixgbe_bus_type_internal;
 533         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 534
 535         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 536                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 537                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 538                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 539                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 540                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 541                 link->ops.read_link_unlocked =
 542                                 ixgbe_read_i2c_combined_generic_unlocked;
 543                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 544                 link->ops.write_link_unlocked =
 545                                 ixgbe_write_i2c_combined_generic_unlocked;
 546                 link->addr = IXGBE_CS4227;
 547         }
 548         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 549                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 550                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 551                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 552                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 553         }
 554
 555         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 556         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 557         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 558         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 559         mac->ops.get_supported_physical_layer =
 560                                     ixgbe_get_supported_physical_layer_X550em;
 561
 562         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 563                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 564         else
 565                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 566
 567
 568         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 569                 mac->ops.setup_eee = NULL;
 570
 571         /* PHY */
 572         phy->ops.init = ixgbe_init_phy_ops_X550em;
 573         phy->ops.identify = ixgbe_identify_phy_x550em;
 574         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 575                 phy->ops.set_phy_power = NULL;
 576
 577
 578         /* EEPROM */
 579         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 580         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 581         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 582         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 583         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 584         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 585         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 586         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 587
 588         return ret_val;
 589 }
 590
 591 /**
 592  *  ixgbe_dmac_config_X550
 593  *  @hw: pointer to hardware structure
 594  *
 595  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 596  *  When disabling dmac, dmac enable dmac bit is cleared.
 597  **/
 598 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 599 {
 600         u32 reg, high_pri_tc;
 601
 602         DEBUGFUNC("ixgbe_dmac_config_X550");
 603
 604         /* Disable DMA coalescing before configuring */
 605         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 606         reg &= ~IXGBE_DMACR_DMAC_EN;
 607         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 608
 609         /* Disable DMA Coalescing if the watchdog timer is 0 */
 610         if (!hw->mac.dmac_config.watchdog_timer)
 611                 goto out;
 612
 613         ixgbe_dmac_config_tcs_X550(hw);
 614
 615         /* Configure DMA Coalescing Control Register */
 616         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 617
 618         /* Set the watchdog timer in units of 40.96 usec */
 619         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 620         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 621
 622         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 623         /* If fcoe is enabled, set high priority traffic class */
 624         if (hw->mac.dmac_config.fcoe_en) {
 625                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 626                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 627                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 628         }
 629         reg |= IXGBE_DMACR_EN_MNG_IND;
 630
 631         /* Enable DMA coalescing after configuration */
 632         reg |= IXGBE_DMACR_DMAC_EN;
 633         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 634
 635 out:
 636         return IXGBE_SUCCESS;
 637 }
 638
 639 /**
 640  *  ixgbe_dmac_config_tcs_X550
 641  *  @hw: pointer to hardware structure
 642  *
 643  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 644  *  be cleared before configuring.
 645  **/
 646 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 647 {
 648         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 649
 650         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 651
 652         /* Configure DMA coalescing enabled */
 653         switch (hw->mac.dmac_config.link_speed) {
 654         case IXGBE_LINK_SPEED_100_FULL:
 655                 pb_headroom = IXGBE_DMACRXT_100M;
 656                 break;
 657         case IXGBE_LINK_SPEED_1GB_FULL:
 658                 pb_headroom = IXGBE_DMACRXT_1G;
 659                 break;
 660         default:
 661                 pb_headroom = IXGBE_DMACRXT_10G;
 662                 break;
 663         }
 664
 665         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 666                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 667
 668         /* Set the per Rx packet buffer receive threshold */
 669         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 670                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 671                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 672
 673                 if (tc < hw->mac.dmac_config.num_tcs) {
 674                         /* Get Rx PB size */
 675                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 676                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 677                                 IXGBE_RXPBSIZE_SHIFT;
 678
 679                         /* Calculate receive buffer threshold in kilobytes */
 680                         if (rx_pb_size > pb_headroom)
 681                                 rx_pb_size = rx_pb_size - pb_headroom;
 682                         else
 683                                 rx_pb_size = 0;
 684
 685                         /* Minimum of MFS shall be set for DMCTH */
 686                         reg |= (rx_pb_size > maxframe_size_kb) ?
 687                                 rx_pb_size : maxframe_size_kb;
 688                 }
 689                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 690         }
 691         return IXGBE_SUCCESS;
 692 }
 693
 694 /**
 695  *  ixgbe_dmac_update_tcs_X550
 696  *  @hw: pointer to hardware structure
 697  *
 698  *  Disables dmac, updates per TC settings, and then enables dmac.
 699  **/
 700 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 701 {
 702         u32 reg;
 703
 704         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 705
 706         /* Disable DMA coalescing before configuring */
 707         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 708         reg &= ~IXGBE_DMACR_DMAC_EN;
 709         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 710
 711         ixgbe_dmac_config_tcs_X550(hw);
 712
 713         /* Enable DMA coalescing after configuration */
 714         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 715         reg |= IXGBE_DMACR_DMAC_EN;
 716         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 717
 718         return IXGBE_SUCCESS;
 719 }
 720
 721 /**
 722  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 723  *  @hw: pointer to hardware structure
 724  *
 725  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 726  *  ixgbe_hw struct in order to set up EEPROM access.
 727  **/
 728 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 729 {
 730         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 731         u32 eec;
 732         u16 eeprom_size;
 733
 734         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 735
 736         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 737                 eeprom->semaphore_delay = 10;
 738                 eeprom->type = ixgbe_flash;
 739
 740                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 741                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 742                                     IXGBE_EEC_SIZE_SHIFT);
 743                 eeprom->word_size = 1 << (eeprom_size +
 744                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 745
 746                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 747                           eeprom->type, eeprom->word_size);
 748         }
 749
 750         return IXGBE_SUCCESS;
 751 }
 752
 753 /**
 754  * ixgbe_enable_eee_x550 - Enable EEE support
 755  * @hw: pointer to hardware structure
 756  */
 757 static s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 758 {
 759         u16 autoneg_eee_reg;
 760         u32 link_reg;
 761         s32 status;
 762
 763         if (hw->mac.type == ixgbe_mac_X550) {
 764                 /* Advertise EEE capability */
 765                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 766                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 767                                      &autoneg_eee_reg);
 768
 769                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 770                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 771                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 772
 773                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 774                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 775                                       autoneg_eee_reg);
 776         } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 777
 778                 status = ixgbe_read_iosf_sb_reg_x550(hw,
 779                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 780                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 781                 if (status != IXGBE_SUCCESS)
 782                         return status;
 783
 784                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 785                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 786
 787                 /* Don't advertise FEC capability when EEE enabled. */
 788                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 789
 790                 status = ixgbe_write_iosf_sb_reg_x550(hw,
 791                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 792                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 793                 if (status != IXGBE_SUCCESS)
 794                         return status;
 795         }
 796
 797         return IXGBE_SUCCESS;
 798 }
 799
 800 /**
 801  * ixgbe_disable_eee_x550 - Disable EEE support
 802  * @hw: pointer to hardware structure
 803  */
 804 static s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 805 {
 806         u16 autoneg_eee_reg;
 807         u32 link_reg;
 808         s32 status;
 809
 810         if (hw->mac.type == ixgbe_mac_X550) {
 811                 /* Disable advertised EEE capability */
 812                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 813                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 814                                      &autoneg_eee_reg);
 815
 816                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 817                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 818                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 819
 820                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 821                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 822                                       autoneg_eee_reg);
 823         } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 824                 status = ixgbe_read_iosf_sb_reg_x550(hw,
 825                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 826                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 827                 if (status != IXGBE_SUCCESS)
 828                         return status;
 829
 830                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 831                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 832
 833                 /* Advertise FEC capability when EEE is disabled. */
 834                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 835
 836                 status = ixgbe_write_iosf_sb_reg_x550(hw,
 837                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 838                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 839                 if (status != IXGBE_SUCCESS)
 840                         return status;
 841         }
 842
 843         return IXGBE_SUCCESS;
 844 }
 845
 846 /**
 847  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 848  *  @hw: pointer to the HW structure
 849  *  @enable_eee: boolean flag to enable EEE
 850  *
 851  *  Enable/disable EEE based on enable_eee flag.
 852  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 853  *  are modified.
 854  *
 855  **/
 856 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 857 {
 858         s32 status;
 859         u32 eeer;
 860
 861         DEBUGFUNC("ixgbe_setup_eee_X550");
 862
 863         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 864         /* Enable or disable EEE per flag */
 865         if (enable_eee) {
 866                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 867
 868                 /* Not supported on first revision of X550EM_x. */
 869                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 870                     !(IXGBE_FUSES0_REV_MASK &
 871                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 872                         return IXGBE_SUCCESS;
 873                 status = ixgbe_enable_eee_x550(hw);
 874                 if (status)
 875                         return status;
 876         } else {
 877                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 878
 879                 status = ixgbe_disable_eee_x550(hw);
 880                 if (status)
 881                         return status;
 882         }
 883         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 884
 885         return IXGBE_SUCCESS;
 886 }
 887
 888 /**
 889  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 890  * @hw: pointer to hardware structure
 891  * @enable: enable or disable source address pruning
 892  * @pool: Rx pool to set source address pruning for
 893  **/
 894 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 895                                            unsigned int pool)
 896 {
 897         u64 pfflp;
 898
 899         /* max rx pool is 63 */
 900         if (pool > 63)
 901                 return;
 902
 903         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 904         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 905
 906         if (enable)
 907                 pfflp |= (1ULL << pool);
 908         else
 909                 pfflp &= ~(1ULL << pool);
 910
 911         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 912         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 913 }
 914
 915 /**
 916  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 917  *  @hw: pointer to hardware structure
 918  *  @enable: enable or disable switch for Ethertype anti-spoofing
 919  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 920  *
 921  **/
 922 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 923                 bool enable, int vf)
 924 {
 925         int vf_target_reg = vf >> 3;
 926         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 927         u32 pfvfspoof;
 928
 929         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 930
 931         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 932         if (enable)
 933                 pfvfspoof |= (1 << vf_target_shift);
 934         else
 935                 pfvfspoof &= ~(1 << vf_target_shift);
 936
 937         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 938 }
 939
 940 /**
 941  * ixgbe_iosf_wait - Wait for IOSF command completion
 942  * @hw: pointer to hardware structure
 943  * @ctrl: pointer to location to receive final IOSF control value
 944  *
 945  * Returns failing status on timeout
 946  *
 947  * Note: ctrl can be NULL if the IOSF control register value is not needed
 948  **/
 949 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 950 {
 951         u32 i, command = 0;
 952
 953         /* Check every 10 usec to see if the address cycle completed.
 954          * The SB IOSF BUSY bit will clear when the operation is
 955          * complete
 956          */
 957         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 958                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 959                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 960                         break;
 961                 usec_delay(10);
 962         }
 963         if (ctrl)
 964                 *ctrl = command;
 965         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 966                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 967                 return IXGBE_ERR_PHY;
 968         }
 969
 970         return IXGBE_SUCCESS;
 971 }
 972
 973 /**
 974  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 975  *  device
 976  *  @hw: pointer to hardware structure
 977  *  @reg_addr: 32 bit PHY register to write
 978  *  @device_type: 3 bit device type
 979  *  @data: Data to write to the register
 980  **/
 981 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 982                             u32 device_type, u32 data)
 983 {
 984         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 985         u32 command, error;
 986         s32 ret;
 987
 988         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 989         if (ret != IXGBE_SUCCESS)
 990                 return ret;
 991
 992         ret = ixgbe_iosf_wait(hw, NULL);
 993         if (ret != IXGBE_SUCCESS)
 994                 goto out;
 995
 996         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 997                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 998
 999         /* Write IOSF control register */
1000         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1001
1002         /* Write IOSF data register */
1003         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1004
1005         ret = ixgbe_iosf_wait(hw, &command);
1006
1007         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1008                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1009                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1010                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1011                               "Failed to write, error %x\n", error);
1012                 ret = IXGBE_ERR_PHY;
1013         }
1014
1015 out:
1016         ixgbe_release_swfw_semaphore(hw, gssr);
1017         return ret;
1018 }
1019
1020 /**
1021  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1022  *  device
1023  *  @hw: pointer to hardware structure
1024  *  @reg_addr: 32 bit PHY register to write
1025  *  @device_type: 3 bit device type
1026  *  @phy_data: Pointer to read data from the register
1027  **/
1028 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1029                            u32 device_type, u32 *data)
1030 {
1031         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1032         u32 command, error;
1033         s32 ret;
1034
1035         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1036         if (ret != IXGBE_SUCCESS)
1037                 return ret;
1038
1039         ret = ixgbe_iosf_wait(hw, NULL);
1040         if (ret != IXGBE_SUCCESS)
1041                 goto out;
1042
1043         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1044                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1045
1046         /* Write IOSF control register */
1047         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1048
1049         ret = ixgbe_iosf_wait(hw, &command);
1050
1051         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1052                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1053                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1054                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1055                                 "Failed to read, error %x\n", error);
1056                 ret = IXGBE_ERR_PHY;
1057         }
1058
1059         if (ret == IXGBE_SUCCESS)
1060                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1061
1062 out:
1063         ixgbe_release_swfw_semaphore(hw, gssr);
1064         return ret;
1065 }
1066
1067 /**
1068  * ixgbe_get_phy_token - Get the token for shared phy access
1069  * @hw: Pointer to hardware structure
1070  */
1071
1072 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1073 {
1074         struct ixgbe_hic_phy_token_req token_cmd;
1075         s32 status;
1076
1077         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1078         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1079         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1080         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1081         token_cmd.port_number = hw->bus.lan_id;
1082         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1083         token_cmd.pad = 0;
1084         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1085                                               sizeof(token_cmd),
1086                                               IXGBE_HI_COMMAND_TIMEOUT,
1087                                               true);
1088         if (status)
1089                 return status;
1090         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1091                 return IXGBE_SUCCESS;
1092         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1093                 return IXGBE_ERR_FW_RESP_INVALID;
1094
1095         return IXGBE_ERR_TOKEN_RETRY;
1096 }
1097
1098 /**
1099  * ixgbe_put_phy_token - Put the token for shared phy access
1100  * @hw: Pointer to hardware structure
1101  */
1102
1103 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1104 {
1105         struct ixgbe_hic_phy_token_req token_cmd;
1106         s32 status;
1107
1108         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1109         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1110         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1111         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1112         token_cmd.port_number = hw->bus.lan_id;
1113         token_cmd.command_type = FW_PHY_TOKEN_REL;
1114         token_cmd.pad = 0;
1115         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1116                                               sizeof(token_cmd),
1117                                               IXGBE_HI_COMMAND_TIMEOUT,
1118                                               true);
1119         if (status)
1120                 return status;
1121         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1122                 return IXGBE_SUCCESS;
1123         return IXGBE_ERR_FW_RESP_INVALID;
1124 }
1125
1126 /**
1127  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1128  *  of the IOSF device
1129  *  @hw: pointer to hardware structure
1130  *  @reg_addr: 32 bit PHY register to write
1131  *  @device_type: 3 bit device type
1132  *  @data: Data to write to the register
1133  **/
1134 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1135                                   u32 device_type, u32 data)
1136 {
1137         struct ixgbe_hic_internal_phy_req write_cmd;
1138         s32 status;
1139         UNREFERENCED_1PARAMETER(device_type);
1140
1141         memset(&write_cmd, 0, sizeof(write_cmd));
1142         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1143         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1144         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1145         write_cmd.port_number = hw->bus.lan_id;
1146         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1147         write_cmd.address = (u16)reg_addr;
1148         write_cmd.write_data = data;
1149
1150         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1151                                               sizeof(write_cmd),
1152                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1153
1154         return status;
1155 }
1156
1157 /**
1158  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1159  *  of the IOSF device.
1160  *  @hw: pointer to hardware structure
1161  *  @reg_addr: 32 bit PHY register to write
1162  *  @device_type: 3 bit device type
1163  *  @data: Pointer to read data from the register
1164  **/
1165 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1166                                  u32 device_type, u32 *data)
1167 {
1168         struct ixgbe_hic_internal_phy_req read_cmd;
1169         s32 status;
1170         UNREFERENCED_1PARAMETER(device_type);
1171
1172         memset(&read_cmd, 0, sizeof(read_cmd));
1173         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1174         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1175         read_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1176         read_cmd.port_number = hw->bus.lan_id;
1177         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1178         read_cmd.address = (u16)reg_addr;
1179
1180         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1181                                               sizeof(read_cmd),
1182                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1183
1184         /* Extract the register value from the response. */
1185         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1186
1187         return status;
1188 }
1189
1190 /**
1191  *  ixgbe_disable_mdd_X550
1192  *  @hw: pointer to hardware structure
1193  *
1194  *  Disable malicious driver detection
1195  **/
1196 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1197 {
1198         u32 reg;
1199
1200         DEBUGFUNC("ixgbe_disable_mdd_X550");
1201
1202         /* Disable MDD for TX DMA and interrupt */
1203         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1204         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1205         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1206
1207         /* Disable MDD for RX and interrupt */
1208         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1209         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1210         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1211 }
1212
1213 /**
1214  *  ixgbe_enable_mdd_X550
1215  *  @hw: pointer to hardware structure
1216  *
1217  *  Enable malicious driver detection
1218  **/
1219 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1220 {
1221         u32 reg;
1222
1223         DEBUGFUNC("ixgbe_enable_mdd_X550");
1224
1225         /* Enable MDD for TX DMA and interrupt */
1226         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1227         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1228         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1229
1230         /* Enable MDD for RX and interrupt */
1231         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1232         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1233         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1234 }
1235
1236 /**
1237  *  ixgbe_restore_mdd_vf_X550
1238  *  @hw: pointer to hardware structure
1239  *  @vf: vf index
1240  *
1241  *  Restore VF that was disabled during malicious driver detection event
1242  **/
1243 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1244 {
1245         u32 idx, reg, num_qs, start_q, bitmask;
1246
1247         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1248
1249         /* Map VF to queues */
1250         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1251         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1252         case IXGBE_MRQC_VMDQRT8TCEN:
1253                 num_qs = 8;  /* 16 VFs / pools */
1254                 bitmask = 0x000000FF;
1255                 break;
1256         case IXGBE_MRQC_VMDQRSS32EN:
1257         case IXGBE_MRQC_VMDQRT4TCEN:
1258                 num_qs = 4;  /* 32 VFs / pools */
1259                 bitmask = 0x0000000F;
1260                 break;
1261         default:            /* 64 VFs / pools */
1262                 num_qs = 2;
1263                 bitmask = 0x00000003;
1264                 break;
1265         }
1266         start_q = vf * num_qs;
1267
1268         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1269         idx = start_q / 32;
1270         reg = 0;
1271         reg |= (bitmask << (start_q % 32));
1272         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1273         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1274 }
1275
1276 /**
1277  *  ixgbe_mdd_event_X550
1278  *  @hw: pointer to hardware structure
1279  *  @vf_bitmap: vf bitmap of malicious vfs
1280  *
1281  *  Handle malicious driver detection event.
1282  **/
1283 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1284 {
1285         u32 wqbr;
1286         u32 i, j, reg, q, shift, vf, idx;
1287
1288         DEBUGFUNC("ixgbe_mdd_event_X550");
1289
1290         /* figure out pool size for mapping to vf's */
1291         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1292         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1293         case IXGBE_MRQC_VMDQRT8TCEN:
1294                 shift = 3;  /* 16 VFs / pools */
1295                 break;
1296         case IXGBE_MRQC_VMDQRSS32EN:
1297         case IXGBE_MRQC_VMDQRT4TCEN:
1298                 shift = 2;  /* 32 VFs / pools */
1299                 break;
1300         default:
1301                 shift = 1;  /* 64 VFs / pools */
1302                 break;
1303         }
1304
1305         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1306         for (i = 0; i < 4; i++) {
1307                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1308                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1309
1310                 if (!wqbr)
1311                         continue;
1312
1313                 /* Get malicious queue */
1314                 for (j = 0; j < 32 && wqbr; j++) {
1315
1316                         if (!(wqbr & (1 << j)))
1317                                 continue;
1318
1319                         /* Get queue from bitmask */
1320                         q = j + (i * 32);
1321
1322                         /* Map queue to vf */
1323                         vf = (q >> shift);
1324
1325                         /* Set vf bit in vf_bitmap */
1326                         idx = vf / 32;
1327                         vf_bitmap[idx] |= (1 << (vf % 32));
1328                         wqbr &= ~(1 << j);
1329                 }
1330         }
1331 }
1332
1333 /**
1334  *  ixgbe_get_media_type_X550em - Get media type
1335  *  @hw: pointer to hardware structure
1336  *
1337  *  Returns the media type (fiber, copper, backplane)
1338  */
1339 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1340 {
1341         enum ixgbe_media_type media_type;
1342
1343         DEBUGFUNC("ixgbe_get_media_type_X550em");
1344
1345         /* Detect if there is a copper PHY attached. */
1346         switch (hw->device_id) {
1347         case IXGBE_DEV_ID_X550EM_X_KR:
1348         case IXGBE_DEV_ID_X550EM_X_KX4:
1349         case IXGBE_DEV_ID_X550EM_A_KR:
1350         case IXGBE_DEV_ID_X550EM_A_KR_L:
1351                 media_type = ixgbe_media_type_backplane;
1352                 break;
1353         case IXGBE_DEV_ID_X550EM_X_SFP:
1354         case IXGBE_DEV_ID_X550EM_A_SFP:
1355         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1356         case IXGBE_DEV_ID_X550EM_A_QSFP:
1357         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1358                 media_type = ixgbe_media_type_fiber;
1359                 break;
1360         case IXGBE_DEV_ID_X550EM_X_1G_T:
1361         case IXGBE_DEV_ID_X550EM_X_10G_T:
1362         case IXGBE_DEV_ID_X550EM_A_10G_T:
1363                 media_type = ixgbe_media_type_copper;
1364                 break;
1365         case IXGBE_DEV_ID_X550EM_A_1G_T:
1366         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1367                 media_type = ixgbe_media_type_sgmii;
1368                 hw->phy.type = ixgbe_phy_sgmii;
1369                 break;
1370         default:
1371                 media_type = ixgbe_media_type_unknown;
1372                 break;
1373         }
1374         return media_type;
1375 }
1376
1377 /**
1378  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1379  *  @hw: pointer to hardware structure
1380  *  @linear: true if SFP module is linear
1381  */
1382 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1383 {
1384         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1385
1386         switch (hw->phy.sfp_type) {
1387         case ixgbe_sfp_type_not_present:
1388                 return IXGBE_ERR_SFP_NOT_PRESENT;
1389         case ixgbe_sfp_type_da_cu_core0:
1390         case ixgbe_sfp_type_da_cu_core1:
1391                 *linear = true;
1392                 break;
1393         case ixgbe_sfp_type_srlr_core0:
1394         case ixgbe_sfp_type_srlr_core1:
1395         case ixgbe_sfp_type_da_act_lmt_core0:
1396         case ixgbe_sfp_type_da_act_lmt_core1:
1397         case ixgbe_sfp_type_1g_sx_core0:
1398         case ixgbe_sfp_type_1g_sx_core1:
1399         case ixgbe_sfp_type_1g_lx_core0:
1400         case ixgbe_sfp_type_1g_lx_core1:
1401                 *linear = false;
1402                 break;
1403         case ixgbe_sfp_type_unknown:
1404         case ixgbe_sfp_type_1g_cu_core0:
1405         case ixgbe_sfp_type_1g_cu_core1:
1406         default:
1407                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1408         }
1409
1410         return IXGBE_SUCCESS;
1411 }
1412
1413 /**
1414  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1415  *  @hw: pointer to hardware structure
1416  *
1417  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1418  **/
1419 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1420 {
1421         s32 status;
1422         bool linear;
1423
1424         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1425
1426         status = ixgbe_identify_module_generic(hw);
1427
1428         if (status != IXGBE_SUCCESS)
1429                 return status;
1430
1431         /* Check if SFP module is supported */
1432         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1433
1434         return status;
1435 }
1436
1437 /**
1438  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1439  *  @hw: pointer to hardware structure
1440  */
1441 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1442 {
1443         s32 status;
1444         bool linear;
1445
1446         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1447
1448         /* Check if SFP module is supported */
1449         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1450
1451         if (status != IXGBE_SUCCESS)
1452                 return status;
1453
1454         ixgbe_init_mac_link_ops_X550em(hw);
1455         hw->phy.ops.reset = NULL;
1456
1457         return IXGBE_SUCCESS;
1458 }
1459
1460 /**
1461  * ixgbe_setup_sgmii - Set up link for sgmii
1462  * @hw: pointer to hardware structure
1463  */
1464 static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1465                              bool autoneg_wait_to_complete)
1466 {
1467         struct ixgbe_mac_info *mac = &hw->mac;
1468         u32 lval, sval;
1469         s32 rc;
1470         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1471
1472         rc = mac->ops.read_iosf_sb_reg(hw,
1473                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1474                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1475         if (rc)
1476                 return rc;
1477
1478         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1479         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1480         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1481         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1482         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1483         rc = mac->ops.write_iosf_sb_reg(hw,
1484                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1485                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1486         if (rc)
1487                 return rc;
1488
1489         rc = mac->ops.read_iosf_sb_reg(hw,
1490                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1491                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1492         if (rc)
1493                 return rc;
1494
1495         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1496         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1497         rc = mac->ops.write_iosf_sb_reg(hw,
1498                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1499                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1500         if (rc)
1501                 return rc;
1502
1503         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1504         rc = mac->ops.write_iosf_sb_reg(hw,
1505                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1506                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1507
1508         return rc;
1509 }
1510
1511 /**
1512  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1513  *  @hw: pointer to hardware structure
1514  */
1515 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1516 {
1517         struct ixgbe_mac_info *mac = &hw->mac;
1518
1519         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1520
1521         switch (hw->mac.ops.get_media_type(hw)) {
1522         case ixgbe_media_type_fiber:
1523                 /* CS4227 does not support autoneg, so disable the laser control
1524                  * functions for SFP+ fiber
1525                  */
1526                 mac->ops.disable_tx_laser = NULL;
1527                 mac->ops.enable_tx_laser = NULL;
1528                 mac->ops.flap_tx_laser = NULL;
1529                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1530                 mac->ops.set_rate_select_speed =
1531                                         ixgbe_set_soft_rate_select_speed;
1532                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
1533                         mac->ops.setup_mac_link =
1534                                 ixgbe_setup_mac_link_sfp_x550a;
1535                 else
1536                         mac->ops.setup_mac_link =
1537                                 ixgbe_setup_mac_link_sfp_x550em;
1538                 break;
1539         case ixgbe_media_type_copper:
1540                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1541                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1542                 break;
1543         case ixgbe_media_type_backplane:
1544                 break;
1545         case ixgbe_media_type_sgmii:
1546                 mac->ops.setup_link = ixgbe_setup_sgmii;
1547                 break;
1548         default:
1549                 break;
1550         }
1551 }
1552
1553 /**
1554  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1555  *  @hw: pointer to hardware structure
1556  *  @speed: pointer to link speed
1557  *  @autoneg: true when autoneg or autotry is enabled
1558  */
1559 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1560                                        ixgbe_link_speed *speed,
1561                                        bool *autoneg)
1562 {
1563         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1564
1565         /* SFP */
1566         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1567
1568                 /* CS4227 SFP must not enable auto-negotiation */
1569                 *autoneg = false;
1570
1571                 /* Check if 1G SFP module. */
1572                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1573                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1574                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1575                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1576                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1577                         return IXGBE_SUCCESS;
1578                 }
1579
1580                 /* Link capabilities are based on SFP */
1581                 if (hw->phy.multispeed_fiber)
1582                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1583                                  IXGBE_LINK_SPEED_1GB_FULL;
1584                 else
1585                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1586         } else {
1587                 switch (hw->phy.type) {
1588                 case ixgbe_phy_m88:
1589                         *speed = IXGBE_LINK_SPEED_100_FULL |
1590                                  IXGBE_LINK_SPEED_1GB_FULL;
1591                         break;
1592                 case ixgbe_phy_sgmii:
1593                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1594                         break;
1595                 default:
1596                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1597                                  IXGBE_LINK_SPEED_1GB_FULL;
1598                         break;
1599                 }
1600                 *autoneg = true;
1601         }
1602
1603         return IXGBE_SUCCESS;
1604 }
1605
1606 /**
1607  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1608  * @hw: pointer to hardware structure
1609  * @lsc: pointer to boolean flag which indicates whether external Base T
1610  *       PHY interrupt is lsc
1611  *
1612  * Determime if external Base T PHY interrupt cause is high temperature
1613  * failure alarm or link status change.
1614  *
1615  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1616  * failure alarm, else return PHY access status.
1617  */
1618 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1619 {
1620         u32 status;
1621         u16 reg;
1622
1623         *lsc = false;
1624
1625         /* Vendor alarm triggered */
1626         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1627                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1628                                       &reg);
1629
1630         if (status != IXGBE_SUCCESS ||
1631             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1632                 return status;
1633
1634         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1635         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1636                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1637                                       &reg);
1638
1639         if (status != IXGBE_SUCCESS ||
1640             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1641             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1642                 return status;
1643
1644         /* Global alarm triggered */
1645         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1646                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1647                                       &reg);
1648
1649         if (status != IXGBE_SUCCESS)
1650                 return status;
1651
1652         /* If high temperature failure, then return over temp error and exit */
1653         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1654                 /* power down the PHY in case the PHY FW didn't already */
1655                 ixgbe_set_copper_phy_power(hw, false);
1656                 return IXGBE_ERR_OVERTEMP;
1657         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1658                 /*  device fault alarm triggered */
1659                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1660                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1661                                           &reg);
1662
1663                 if (status != IXGBE_SUCCESS)
1664                         return status;
1665
1666                 /* if device fault was due to high temp alarm handle and exit */
1667                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1668                         /* power down the PHY in case the PHY FW didn't */
1669                         ixgbe_set_copper_phy_power(hw, false);
1670                         return IXGBE_ERR_OVERTEMP;
1671                 }
1672         }
1673
1674         /* Vendor alarm 2 triggered */
1675         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1676                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1677
1678         if (status != IXGBE_SUCCESS ||
1679             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1680                 return status;
1681
1682         /* link connect/disconnect event occurred */
1683         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1684                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1685
1686         if (status != IXGBE_SUCCESS)
1687                 return status;
1688
1689         /* Indicate LSC */
1690         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1691                 *lsc = true;
1692
1693         return IXGBE_SUCCESS;
1694 }
1695
1696 /**
1697  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1698  * @hw: pointer to hardware structure
1699  *
1700  * Enable link status change and temperature failure alarm for the external
1701  * Base T PHY
1702  *
1703  * Returns PHY access status
1704  */
1705 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1706 {
1707         u32 status;
1708         u16 reg;
1709         bool lsc;
1710
1711         /* Clear interrupt flags */
1712         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1713
1714         /* Enable link status change alarm */
1715         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1716                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1717
1718         if (status != IXGBE_SUCCESS)
1719                 return status;
1720
1721         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1722
1723         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1724                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1725
1726         if (status != IXGBE_SUCCESS)
1727                 return status;
1728
1729         /* Enable high temperature failure and global fault alarms */
1730         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1731                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1732                                       &reg);
1733
1734         if (status != IXGBE_SUCCESS)
1735                 return status;
1736
1737         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1738                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1739
1740         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1741                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1742                                        reg);
1743
1744         if (status != IXGBE_SUCCESS)
1745                 return status;
1746
1747         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1748         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1749                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1750                                       &reg);
1751
1752         if (status != IXGBE_SUCCESS)
1753                 return status;
1754
1755         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1756                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1757
1758         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1759                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1760                                        reg);
1761
1762         if (status != IXGBE_SUCCESS)
1763                 return status;
1764
1765         /* Enable chip-wide vendor alarm */
1766         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1767                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1768                                       &reg);
1769
1770         if (status != IXGBE_SUCCESS)
1771                 return status;
1772
1773         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1774
1775         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1776                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1777                                        reg);
1778
1779         return status;
1780 }
1781
1782 /**
1783  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1784  *  @hw: pointer to hardware structure
1785  *  @speed: link speed
1786  *
1787  *  Configures the integrated KR PHY.
1788  **/
1789 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1790                                        ixgbe_link_speed speed)
1791 {
1792         s32 status;
1793         u32 reg_val;
1794
1795         status = ixgbe_read_iosf_sb_reg_x550(hw,
1796                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1797                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1798         if (status)
1799                 return status;
1800
1801         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1802         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1803                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1804
1805         /* Advertise 10G support. */
1806         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1807                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1808
1809         /* Advertise 1G support. */
1810         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1811                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1812
1813         /* Restart auto-negotiation. */
1814         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1815         status = ixgbe_write_iosf_sb_reg_x550(hw,
1816                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1817                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1818
1819         return status;
1820 }
1821
1822 /**
1823  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1824  *  @hw: pointer to hardware structure
1825  *
1826  *  Initialize any function pointers that were not able to be
1827  *  set during init_shared_code because the PHY/SFP type was
1828  *  not known.  Perform the SFP init if necessary.
1829  */
1830 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1831 {
1832         struct ixgbe_phy_info *phy = &hw->phy;
1833         s32 ret_val;
1834
1835         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1836
1837         hw->mac.ops.set_lan_id(hw);
1838
1839         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1840                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1841                 ixgbe_setup_mux_ctl(hw);
1842
1843                 /* Save NW management interface connected on board. This is used
1844                  * to determine internal PHY mode.
1845                  */
1846                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1847                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1848         }
1849
1850         /* Identify the PHY or SFP module */
1851         ret_val = phy->ops.identify(hw);
1852         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1853                 return ret_val;
1854
1855         /* Setup function pointers based on detected hardware */
1856         ixgbe_init_mac_link_ops_X550em(hw);
1857         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1858                 phy->ops.reset = NULL;
1859
1860         /* Set functions pointers based on phy type */
1861         switch (hw->phy.type) {
1862         case ixgbe_phy_x550em_kx4:
1863                 phy->ops.setup_link = NULL;
1864                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1865                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1866                 break;
1867         case ixgbe_phy_x550em_kr:
1868                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1869                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1870                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1871                 break;
1872         case ixgbe_phy_x550em_ext_t:
1873                 /* Save NW management interface connected on board. This is used
1874                  * to determine internal PHY mode
1875                  */
1876                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1877
1878                 /* If internal link mode is XFI, then setup iXFI internal link,
1879                  * else setup KR now.
1880                  */
1881                 phy->ops.setup_internal_link =
1882                                               ixgbe_setup_internal_phy_t_x550em;
1883
1884                 /* setup SW LPLU only for first revision of X550EM_x */
1885                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1886                     !(IXGBE_FUSES0_REV_MASK &
1887                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1888                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1889
1890                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1891                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1892                 break;
1893         case ixgbe_phy_sgmii:
1894                 phy->ops.setup_link = NULL;
1895                 break;
1896         case ixgbe_phy_m88:
1897                 break;
1898         default:
1899                 break;
1900         }
1901         return ret_val;
1902 }
1903
1904 /**
1905  * ixgbe_set_mdio_speed - Set MDIO clock speed
1906  *  @hw: pointer to hardware structure
1907  */
1908 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1909 {
1910         u32 hlreg0;
1911
1912         switch (hw->device_id) {
1913         case IXGBE_DEV_ID_X550EM_X_10G_T:
1914         case IXGBE_DEV_ID_X550EM_A_1G_T:
1915         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1916         case IXGBE_DEV_ID_X550EM_A_10G_T:
1917         case IXGBE_DEV_ID_X550EM_A_SFP:
1918         case IXGBE_DEV_ID_X550EM_A_QSFP:
1919                 /* Config MDIO clock speed before the first MDIO PHY access */
1920                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1921                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1922                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1923                 break;
1924         default:
1925                 break;
1926         }
1927 }
1928
1929 /**
1930  *  ixgbe_reset_hw_X550em - Perform hardware reset
1931  *  @hw: pointer to hardware structure
1932  *
1933  *  Resets the hardware by resetting the transmit and receive units, masks
1934  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1935  *  reset.
1936  */
1937 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1938 {
1939         ixgbe_link_speed link_speed;
1940         s32 status;
1941         u32 ctrl = 0;
1942         u32 i;
1943         bool link_up = false;
1944
1945         DEBUGFUNC("ixgbe_reset_hw_X550em");
1946
1947         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1948         status = hw->mac.ops.stop_adapter(hw);
1949         if (status != IXGBE_SUCCESS)
1950                 return status;
1951
1952         /* flush pending Tx transactions */
1953         ixgbe_clear_tx_pending(hw);
1954
1955         ixgbe_set_mdio_speed(hw);
1956
1957         /* PHY ops must be identified and initialized prior to reset */
1958         status = hw->phy.ops.init(hw);
1959
1960         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1961                 return status;
1962
1963         /* start the external PHY */
1964         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1965                 status = ixgbe_init_ext_t_x550em(hw);
1966                 if (status)
1967                         return status;
1968         }
1969
1970         /* Setup SFP module if there is one present. */
1971         if (hw->phy.sfp_setup_needed) {
1972                 status = hw->mac.ops.setup_sfp(hw);
1973                 hw->phy.sfp_setup_needed = false;
1974         }
1975
1976         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1977                 return status;
1978
1979         /* Reset PHY */
1980         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1981                 hw->phy.ops.reset(hw);
1982
1983 mac_reset_top:
1984         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1985          * If link reset is used when link is up, it might reset the PHY when
1986          * mng is using it.  If link is down or the flag to force full link
1987          * reset is set, then perform link reset.
1988          */
1989         ctrl = IXGBE_CTRL_LNK_RST;
1990         if (!hw->force_full_reset) {
1991                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1992                 if (link_up)
1993                         ctrl = IXGBE_CTRL_RST;
1994         }
1995
1996         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1997         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1998         IXGBE_WRITE_FLUSH(hw);
1999
2000         /* Poll for reset bit to self-clear meaning reset is complete */
2001         for (i = 0; i < 10; i++) {
2002                 usec_delay(1);
2003                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2004                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2005                         break;
2006         }
2007
2008         if (ctrl & IXGBE_CTRL_RST_MASK) {
2009                 status = IXGBE_ERR_RESET_FAILED;
2010                 DEBUGOUT("Reset polling failed to complete.\n");
2011         }
2012
2013         msec_delay(50);
2014
2015         /* Double resets are required for recovery from certain error
2016          * conditions.  Between resets, it is necessary to stall to
2017          * allow time for any pending HW events to complete.
2018          */
2019         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2020                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2021                 goto mac_reset_top;
2022         }
2023
2024         /* Store the permanent mac address */
2025         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2026
2027         /* Store MAC address from RAR0, clear receive address registers, and
2028          * clear the multicast table.  Also reset num_rar_entries to 128,
2029          * since we modify this value when programming the SAN MAC address.
2030          */
2031         hw->mac.num_rar_entries = 128;
2032         hw->mac.ops.init_rx_addrs(hw);
2033
2034         ixgbe_set_mdio_speed(hw);
2035
2036         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2037                 ixgbe_setup_mux_ctl(hw);
2038
2039         return status;
2040 }
2041
2042 /**
2043  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2044  * @hw: pointer to hardware structure
2045  */
2046 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2047 {
2048         u32 status;
2049         u16 reg;
2050
2051         status = hw->phy.ops.read_reg(hw,
2052                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2053                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2054                                       &reg);
2055
2056         if (status != IXGBE_SUCCESS)
2057                 return status;
2058
2059         /* If PHY FW reset completed bit is set then this is the first
2060          * SW instance after a power on so the PHY FW must be un-stalled.
2061          */
2062         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2063                 status = hw->phy.ops.read_reg(hw,
2064                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2065                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2066                                         &reg);
2067
2068                 if (status != IXGBE_SUCCESS)
2069                         return status;
2070
2071                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2072
2073                 status = hw->phy.ops.write_reg(hw,
2074                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2075                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2076                                         reg);
2077
2078                 if (status != IXGBE_SUCCESS)
2079                         return status;
2080         }
2081
2082         return status;
2083 }
2084
2085 /**
2086  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2087  *  @hw: pointer to hardware structure
2088  *
2089  *  Configures the integrated KR PHY.
2090  **/
2091 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2092 {
2093         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2094 }
2095
2096 /**
2097  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2098  *  @hw: pointer to hardware structure
2099  *
2100  *  Configure the external PHY and the integrated KR PHY for SFP support.
2101  **/
2102 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2103                                     ixgbe_link_speed speed,
2104                                     bool autoneg_wait_to_complete)
2105 {
2106         s32 ret_val;
2107         u16 reg_slice, reg_val;
2108         bool setup_linear = false;
2109         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2110
2111         /* Check if SFP module is supported and linear */
2112         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2113
2114         /* If no SFP module present, then return success. Return success since
2115          * there is no reason to configure CS4227 and SFP not present error is
2116          * not excepted in the setup MAC link flow.
2117          */
2118         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2119                 return IXGBE_SUCCESS;
2120
2121         if (ret_val != IXGBE_SUCCESS)
2122                 return ret_val;
2123
2124         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2125                 /* Configure CS4227 LINE side to 10G SR. */
2126                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2127                             (hw->bus.lan_id << 12);
2128                 reg_val = IXGBE_CS4227_SPEED_10G;
2129                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2130                                                   reg_val);
2131
2132                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2133                             (hw->bus.lan_id << 12);
2134                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2135                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2136                                                   reg_val);
2137
2138                 /* Configure CS4227 for HOST connection rate then type. */
2139                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2140                             (hw->bus.lan_id << 12);
2141                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2142                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2143                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2144                                                   reg_val);
2145
2146                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2147                             (hw->bus.lan_id << 12);
2148                 if (setup_linear)
2149                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2150                 else
2151                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2152                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2153                                                   reg_val);
2154
2155                 /* Setup XFI internal link. */
2156                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2157         } else {
2158                 /* Configure internal PHY for KR/KX. */
2159                 ixgbe_setup_kr_speed_x550em(hw, speed);
2160
2161                 /* Configure CS4227 LINE side to proper mode. */
2162                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2163                             (hw->bus.lan_id << 12);
2164                 if (setup_linear)
2165                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2166                 else
2167                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2168                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2169                                                   reg_val);
2170         }
2171         return ret_val;
2172 }
2173
2174 /**
2175  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2176  *  @hw: pointer to hardware structure
2177  *
2178  *  Configure the the integrated PHY for SFP support.
2179  **/
2180 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2181                                    ixgbe_link_speed speed,
2182                                    bool autoneg_wait_to_complete)
2183 {
2184         s32 ret_val;
2185         u32 reg_val;
2186         bool setup_linear = false;
2187
2188         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2189
2190         /* Check if SFP module is supported and linear */
2191         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2192
2193         /* If no SFP module present, then return success. Return success since
2194          * SFP not present error is not excepted in the setup MAC link flow.
2195          */
2196         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2197                 return IXGBE_SUCCESS;
2198
2199         if (ret_val != IXGBE_SUCCESS)
2200                 return ret_val;
2201
2202         /* Configure internal PHY for native SFI */
2203         ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2204                        IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2205                        IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2206
2207         if (ret_val != IXGBE_SUCCESS)
2208                 return ret_val;
2209
2210         if (setup_linear) {
2211                 reg_val &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2212                 reg_val |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2213         } else {
2214                 reg_val |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2215                 reg_val &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2216         }
2217
2218         ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2219                         IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2220                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2221
2222         if (ret_val != IXGBE_SUCCESS)
2223                 return ret_val;
2224
2225         /* Setup XFI/SFI internal link. */
2226         ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2227
2228         return ret_val;
2229 }
2230
2231 /**
2232  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2233  *  @hw: pointer to hardware structure
2234  *
2235  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2236  **/
2237 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2238 {
2239         s32 status;
2240         u32 reg_val;
2241
2242         /* Disable training protocol FSM. */
2243         status = ixgbe_read_iosf_sb_reg_x550(hw,
2244                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2245                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2246         if (status != IXGBE_SUCCESS)
2247                 return status;
2248         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2249         status = ixgbe_write_iosf_sb_reg_x550(hw,
2250                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2251                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2252         if (status != IXGBE_SUCCESS)
2253                 return status;
2254
2255         /* Disable Flex from training TXFFE. */
2256         status = ixgbe_read_iosf_sb_reg_x550(hw,
2257                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2258                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2259         if (status != IXGBE_SUCCESS)
2260                 return status;
2261         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2262         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2263         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2264         status = ixgbe_write_iosf_sb_reg_x550(hw,
2265                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2266                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2267         if (status != IXGBE_SUCCESS)
2268                 return status;
2269         status = ixgbe_read_iosf_sb_reg_x550(hw,
2270                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2271                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2272         if (status != IXGBE_SUCCESS)
2273                 return status;
2274         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2275         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2276         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2277         status = ixgbe_write_iosf_sb_reg_x550(hw,
2278                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2279                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2280         if (status != IXGBE_SUCCESS)
2281                 return status;
2282
2283         /* Enable override for coefficients. */
2284         status = ixgbe_read_iosf_sb_reg_x550(hw,
2285                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2286                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2287         if (status != IXGBE_SUCCESS)
2288                 return status;
2289         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2290         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2291         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2292         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2293         status = ixgbe_write_iosf_sb_reg_x550(hw,
2294                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2295                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2296         return status;
2297 }
2298
2299 /**
2300  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2301  *  @hw: pointer to hardware structure
2302  *  @speed: the link speed to force
2303  *
2304  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2305  *  internal and external PHY at a specific speed, without autonegotiation.
2306  **/
2307 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2308 {
2309         s32 status;
2310         u32 reg_val;
2311
2312         /* Disable AN and force speed to 10G Serial. */
2313         status = ixgbe_read_iosf_sb_reg_x550(hw,
2314                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2315                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2316         if (status != IXGBE_SUCCESS)
2317                 return status;
2318
2319         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2320         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2321
2322         /* Select forced link speed for internal PHY. */
2323         switch (*speed) {
2324         case IXGBE_LINK_SPEED_10GB_FULL:
2325                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2326                 break;
2327         case IXGBE_LINK_SPEED_1GB_FULL:
2328                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2329                 break;
2330         default:
2331                 /* Other link speeds are not supported by internal KR PHY. */
2332                 return IXGBE_ERR_LINK_SETUP;
2333         }
2334
2335         status = ixgbe_write_iosf_sb_reg_x550(hw,
2336                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2337                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2338         if (status != IXGBE_SUCCESS)
2339                 return status;
2340
2341         /* Additional configuration needed for x550em_x */
2342         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2343                 status = ixgbe_setup_ixfi_x550em_x(hw);
2344                 if (status != IXGBE_SUCCESS)
2345                         return status;
2346         }
2347
2348         /* Toggle port SW reset by AN reset. */
2349         status = ixgbe_read_iosf_sb_reg_x550(hw,
2350                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2351                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2352         if (status != IXGBE_SUCCESS)
2353                 return status;
2354         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2355         status = ixgbe_write_iosf_sb_reg_x550(hw,
2356                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2357                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2358
2359         return status;
2360 }
2361
2362 /**
2363  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2364  * @hw: address of hardware structure
2365  * @link_up: address of boolean to indicate link status
2366  *
2367  * Returns error code if unable to get link status.
2368  */
2369 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2370 {
2371         u32 ret;
2372         u16 autoneg_status;
2373
2374         *link_up = false;
2375
2376         /* read this twice back to back to indicate current status */
2377         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2378                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2379                                    &autoneg_status);
2380         if (ret != IXGBE_SUCCESS)
2381                 return ret;
2382
2383         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2384                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2385                                    &autoneg_status);
2386         if (ret != IXGBE_SUCCESS)
2387                 return ret;
2388
2389         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2390
2391         return IXGBE_SUCCESS;
2392 }
2393
2394 /**
2395  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2396  * @hw: point to hardware structure
2397  *
2398  * Configures the link between the integrated KR PHY and the external X557 PHY
2399  * The driver will call this function when it gets a link status change
2400  * interrupt from the X557 PHY. This function configures the link speed
2401  * between the PHYs to match the link speed of the BASE-T link.
2402  *
2403  * A return of a non-zero value indicates an error, and the base driver should
2404  * not report link up.
2405  */
2406 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2407 {
2408         ixgbe_link_speed force_speed;
2409         bool link_up;
2410         u32 status;
2411         u16 speed;
2412
2413         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2414                 return IXGBE_ERR_CONFIG;
2415
2416         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2417                 /* If link is down, there is no setup necessary so return  */
2418                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2419                 if (status != IXGBE_SUCCESS)
2420                         return status;
2421
2422                 if (!link_up)
2423                         return IXGBE_SUCCESS;
2424
2425                 status = hw->phy.ops.read_reg(hw,
2426                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2427                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2428                                               &speed);
2429                 if (status != IXGBE_SUCCESS)
2430                         return status;
2431
2432                 /* If link is still down - no setup is required so return */
2433                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2434                 if (status != IXGBE_SUCCESS)
2435                         return status;
2436                 if (!link_up)
2437                         return IXGBE_SUCCESS;
2438
2439                 /* clear everything but the speed and duplex bits */
2440                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2441
2442                 switch (speed) {
2443                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2444                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2445                         break;
2446                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2447                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2448                         break;
2449                 default:
2450                         /* Internal PHY does not support anything else */
2451                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2452                 }
2453
2454                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2455         } else {
2456                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2457                         IXGBE_LINK_SPEED_1GB_FULL;
2458                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2459         }
2460 }
2461
2462 /**
2463  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2464  *  @hw: pointer to hardware structure
2465  *
2466  *  Configures the integrated KR PHY to use internal loopback mode.
2467  **/
2468 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2469 {
2470         s32 status;
2471         u32 reg_val;
2472
2473         /* Disable AN and force speed to 10G Serial. */
2474         status = ixgbe_read_iosf_sb_reg_x550(hw,
2475                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2476                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2477         if (status != IXGBE_SUCCESS)
2478                 return status;
2479         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2480         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2481         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2482         status = ixgbe_write_iosf_sb_reg_x550(hw,
2483                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2484                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2485         if (status != IXGBE_SUCCESS)
2486                 return status;
2487
2488         /* Set near-end loopback clocks. */
2489         status = ixgbe_read_iosf_sb_reg_x550(hw,
2490                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2491                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2492         if (status != IXGBE_SUCCESS)
2493                 return status;
2494         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2495         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2496         status = ixgbe_write_iosf_sb_reg_x550(hw,
2497                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2498                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2499         if (status != IXGBE_SUCCESS)
2500                 return status;
2501
2502         /* Set loopback enable. */
2503         status = ixgbe_read_iosf_sb_reg_x550(hw,
2504                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2505                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2506         if (status != IXGBE_SUCCESS)
2507                 return status;
2508         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2509         status = ixgbe_write_iosf_sb_reg_x550(hw,
2510                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2511                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2512         if (status != IXGBE_SUCCESS)
2513                 return status;
2514
2515         /* Training bypass. */
2516         status = ixgbe_read_iosf_sb_reg_x550(hw,
2517                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2518                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2519         if (status != IXGBE_SUCCESS)
2520                 return status;
2521         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2522         status = ixgbe_write_iosf_sb_reg_x550(hw,
2523                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2524                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2525
2526         return status;
2527 }
2528
2529 /**
2530  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2531  *  assuming that the semaphore is already obtained.
2532  *  @hw: pointer to hardware structure
2533  *  @offset: offset of  word in the EEPROM to read
2534  *  @data: word read from the EEPROM
2535  *
2536  *  Reads a 16 bit word from the EEPROM using the hostif.
2537  **/
2538 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2539                                    u16 *data)
2540 {
2541         s32 status;
2542         struct ixgbe_hic_read_shadow_ram buffer;
2543
2544         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2545         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2546         buffer.hdr.req.buf_lenh = 0;
2547         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2548         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2549
2550         /* convert offset from words to bytes */
2551         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2552         /* one word */
2553         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2554
2555         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2556                                               sizeof(buffer),
2557                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2558
2559         if (status)
2560                 return status;
2561
2562         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2563                                           FW_NVM_DATA_OFFSET);
2564
2565         return 0;
2566 }
2567
2568 /**
2569  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2570  *  @hw: pointer to hardware structure
2571  *  @offset: offset of  word in the EEPROM to read
2572  *  @data: word read from the EEPROM
2573  *
2574  *  Reads a 16 bit word from the EEPROM using the hostif.
2575  **/
2576 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2577                               u16 *data)
2578 {
2579         s32 status = IXGBE_SUCCESS;
2580
2581         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2582
2583         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2584             IXGBE_SUCCESS) {
2585                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2586                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2587         } else {
2588                 status = IXGBE_ERR_SWFW_SYNC;
2589         }
2590
2591         return status;
2592 }
2593
2594 /**
2595  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2596  *  @hw: pointer to hardware structure
2597  *  @offset: offset of  word in the EEPROM to read
2598  *  @words: number of words
2599  *  @data: word(s) read from the EEPROM
2600  *
2601  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2602  **/
2603 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2604                                      u16 offset, u16 words, u16 *data)
2605 {
2606         struct ixgbe_hic_read_shadow_ram buffer;
2607         u32 current_word = 0;
2608         u16 words_to_read;
2609         s32 status;
2610         u32 i;
2611
2612         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2613
2614         /* Take semaphore for the entire operation. */
2615         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2616         if (status) {
2617                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2618                 return status;
2619         }
2620         while (words) {
2621                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2622                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2623                 else
2624                         words_to_read = words;
2625
2626                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2627                 buffer.hdr.req.buf_lenh = 0;
2628                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2629                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2630
2631                 /* convert offset from words to bytes */
2632                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2633                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2634
2635                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2636                                                       sizeof(buffer),
2637                                                       IXGBE_HI_COMMAND_TIMEOUT,
2638                                                       false);
2639
2640                 if (status) {
2641                         DEBUGOUT("Host interface command failed\n");
2642                         goto out;
2643                 }
2644
2645                 for (i = 0; i < words_to_read; i++) {
2646                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2647                                   2 * i;
2648                         u32 value = IXGBE_READ_REG(hw, reg);
2649
2650                         data[current_word] = (u16)(value & 0xffff);
2651                         current_word++;
2652                         i++;
2653                         if (i < words_to_read) {
2654                                 value >>= 16;
2655                                 data[current_word] = (u16)(value & 0xffff);
2656                                 current_word++;
2657                         }
2658                 }
2659                 words -= words_to_read;
2660         }
2661
2662 out:
2663         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2664         return status;
2665 }
2666
2667 /**
2668  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2669  *  @hw: pointer to hardware structure
2670  *  @offset: offset of  word in the EEPROM to write
2671  *  @data: word write to the EEPROM
2672  *
2673  *  Write a 16 bit word to the EEPROM using the hostif.
2674  **/
2675 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2676                                     u16 data)
2677 {
2678         s32 status;
2679         struct ixgbe_hic_write_shadow_ram buffer;
2680
2681         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2682
2683         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2684         buffer.hdr.req.buf_lenh = 0;
2685         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2686         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2687
2688          /* one word */
2689         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2690         buffer.data = data;
2691         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2692
2693         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2694                                               sizeof(buffer),
2695                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2696
2697         return status;
2698 }
2699
2700 /**
2701  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2702  *  @hw: pointer to hardware structure
2703  *  @offset: offset of  word in the EEPROM to write
2704  *  @data: word write to the EEPROM
2705  *
2706  *  Write a 16 bit word to the EEPROM using the hostif.
2707  **/
2708 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2709                                u16 data)
2710 {
2711         s32 status = IXGBE_SUCCESS;
2712
2713         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2714
2715         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2716             IXGBE_SUCCESS) {
2717                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2718                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2719         } else {
2720                 DEBUGOUT("write ee hostif failed to get semaphore");
2721                 status = IXGBE_ERR_SWFW_SYNC;
2722         }
2723
2724         return status;
2725 }
2726
2727 /**
2728  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2729  *  @hw: pointer to hardware structure
2730  *  @offset: offset of  word in the EEPROM to write
2731  *  @words: number of words
2732  *  @data: word(s) write to the EEPROM
2733  *
2734  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2735  **/
2736 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2737                                       u16 offset, u16 words, u16 *data)
2738 {
2739         s32 status = IXGBE_SUCCESS;
2740         u32 i = 0;
2741
2742         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2743
2744         /* Take semaphore for the entire operation. */
2745         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2746         if (status != IXGBE_SUCCESS) {
2747                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2748                 goto out;
2749         }
2750
2751         for (i = 0; i < words; i++) {
2752                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2753                                                          data[i]);
2754
2755                 if (status != IXGBE_SUCCESS) {
2756                         DEBUGOUT("Eeprom buffered write failed\n");
2757                         break;
2758                 }
2759         }
2760
2761         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2762 out:
2763
2764         return status;
2765 }
2766
2767 /**
2768  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2769  * @hw: pointer to hardware structure
2770  * @ptr: pointer offset in eeprom
2771  * @size: size of section pointed by ptr, if 0 first word will be used as size
2772  * @csum: address of checksum to update
2773  *
2774  * Returns error status for any failure
2775  */
2776 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2777                                    u16 size, u16 *csum, u16 *buffer,
2778                                    u32 buffer_size)
2779 {
2780         u16 buf[256];
2781         s32 status;
2782         u16 length, bufsz, i, start;
2783         u16 *local_buffer;
2784
2785         bufsz = sizeof(buf) / sizeof(buf[0]);
2786
2787         /* Read a chunk at the pointer location */
2788         if (!buffer) {
2789                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2790                 if (status) {
2791                         DEBUGOUT("Failed to read EEPROM image\n");
2792                         return status;
2793                 }
2794                 local_buffer = buf;
2795         } else {
2796                 if (buffer_size < ptr)
2797                         return  IXGBE_ERR_PARAM;
2798                 local_buffer = &buffer[ptr];
2799         }
2800
2801         if (size) {
2802                 start = 0;
2803                 length = size;
2804         } else {
2805                 start = 1;
2806                 length = local_buffer[0];
2807
2808                 /* Skip pointer section if length is invalid. */
2809                 if (length == 0xFFFF || length == 0 ||
2810                     (ptr + length) >= hw->eeprom.word_size)
2811                         return IXGBE_SUCCESS;
2812         }
2813
2814         if (buffer && ((u32)start + (u32)length > buffer_size))
2815                 return IXGBE_ERR_PARAM;
2816
2817         for (i = start; length; i++, length--) {
2818                 if (i == bufsz && !buffer) {
2819                         ptr += bufsz;
2820                         i = 0;
2821                         if (length < bufsz)
2822                                 bufsz = length;
2823
2824                         /* Read a chunk at the pointer location */
2825                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2826                                                                   bufsz, buf);
2827                         if (status) {
2828                                 DEBUGOUT("Failed to read EEPROM image\n");
2829                                 return status;
2830                         }
2831                 }
2832                 *csum += local_buffer[i];
2833         }
2834         return IXGBE_SUCCESS;
2835 }
2836
2837 /**
2838  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2839  *  @hw: pointer to hardware structure
2840  *  @buffer: pointer to buffer containing calculated checksum
2841  *  @buffer_size: size of buffer
2842  *
2843  *  Returns a negative error code on error, or the 16-bit checksum
2844  **/
2845 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2846 {
2847         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2848         u16 *local_buffer;
2849         s32 status;
2850         u16 checksum = 0;
2851         u16 pointer, i, size;
2852
2853         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2854
2855         hw->eeprom.ops.init_params(hw);
2856
2857         if (!buffer) {
2858                 /* Read pointer area */
2859                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2860                                                      IXGBE_EEPROM_LAST_WORD + 1,
2861                                                      eeprom_ptrs);
2862                 if (status) {
2863                         DEBUGOUT("Failed to read EEPROM image\n");
2864                         return status;
2865                 }
2866                 local_buffer = eeprom_ptrs;
2867         } else {
2868                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2869                         return IXGBE_ERR_PARAM;
2870                 local_buffer = buffer;
2871         }
2872
2873         /*
2874          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2875          * checksum word itself
2876          */
2877         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2878                 if (i != IXGBE_EEPROM_CHECKSUM)
2879                         checksum += local_buffer[i];
2880
2881         /*
2882          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2883          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2884          */
2885         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2886                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2887                         continue;
2888
2889                 pointer = local_buffer[i];
2890
2891                 /* Skip pointer section if the pointer is invalid. */
2892                 if (pointer == 0xFFFF || pointer == 0 ||
2893                     pointer >= hw->eeprom.word_size)
2894                         continue;
2895
2896                 switch (i) {
2897                 case IXGBE_PCIE_GENERAL_PTR:
2898                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2899                         break;
2900                 case IXGBE_PCIE_CONFIG0_PTR:
2901                 case IXGBE_PCIE_CONFIG1_PTR:
2902                         size = IXGBE_PCIE_CONFIG_SIZE;
2903                         break;
2904                 default:
2905                         size = 0;
2906                         break;
2907                 }
2908
2909                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2910                                                 buffer, buffer_size);
2911                 if (status)
2912                         return status;
2913         }
2914
2915         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2916
2917         return (s32)checksum;
2918 }
2919
2920 /**
2921  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2922  *  @hw: pointer to hardware structure
2923  *
2924  *  Returns a negative error code on error, or the 16-bit checksum
2925  **/
2926 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2927 {
2928         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2929 }
2930
2931 /**
2932  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2933  *  @hw: pointer to hardware structure
2934  *  @checksum_val: calculated checksum
2935  *
2936  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2937  *  caller does not need checksum_val, the value can be NULL.
2938  **/
2939 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2940 {
2941         s32 status;
2942         u16 checksum;
2943         u16 read_checksum = 0;
2944
2945         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2946
2947         /* Read the first word from the EEPROM. If this times out or fails, do
2948          * not continue or we could be in for a very long wait while every
2949          * EEPROM read fails
2950          */
2951         status = hw->eeprom.ops.read(hw, 0, &checksum);
2952         if (status) {
2953                 DEBUGOUT("EEPROM read failed\n");
2954                 return status;
2955         }
2956
2957         status = hw->eeprom.ops.calc_checksum(hw);
2958         if (status < 0)
2959                 return status;
2960
2961         checksum = (u16)(status & 0xffff);
2962
2963         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2964                                            &read_checksum);
2965         if (status)
2966                 return status;
2967
2968         /* Verify read checksum from EEPROM is the same as
2969          * calculated checksum
2970          */
2971         if (read_checksum != checksum) {
2972                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2973                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2974                              "Invalid EEPROM checksum");
2975         }
2976
2977         /* If the user cares, return the calculated checksum */
2978         if (checksum_val)
2979                 *checksum_val = checksum;
2980
2981         return status;
2982 }
2983
2984 /**
2985  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2986  * @hw: pointer to hardware structure
2987  *
2988  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2989  * checksum and updates the EEPROM and instructs the hardware to update
2990  * the flash.
2991  **/
2992 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2993 {
2994         s32 status;
2995         u16 checksum = 0;
2996
2997         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2998
2999         /* Read the first word from the EEPROM. If this times out or fails, do
3000          * not continue or we could be in for a very long wait while every
3001          * EEPROM read fails
3002          */
3003         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3004         if (status) {
3005                 DEBUGOUT("EEPROM read failed\n");
3006                 return status;
3007         }
3008
3009         status = ixgbe_calc_eeprom_checksum_X550(hw);
3010         if (status < 0)
3011                 return status;
3012
3013         checksum = (u16)(status & 0xffff);
3014
3015         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3016                                             checksum);
3017         if (status)
3018                 return status;
3019
3020         status = ixgbe_update_flash_X550(hw);
3021
3022         return status;
3023 }
3024
3025 /**
3026  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3027  *  @hw: pointer to hardware structure
3028  *
3029  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3030  **/
3031 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3032 {
3033         s32 status = IXGBE_SUCCESS;
3034         union ixgbe_hic_hdr2 buffer;
3035
3036         DEBUGFUNC("ixgbe_update_flash_X550");
3037
3038         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3039         buffer.req.buf_lenh = 0;
3040         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3041         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3042
3043         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3044                                               sizeof(buffer),
3045                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3046
3047         return status;
3048 }
3049
3050 /**
3051  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3052  *  @hw: pointer to hardware structure
3053  *
3054  *  Determines physical layer capabilities of the current configuration.
3055  **/
3056 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3057 {
3058         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3059         u16 ext_ability = 0;
3060
3061         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3062
3063         hw->phy.ops.identify(hw);
3064
3065         switch (hw->phy.type) {
3066         case ixgbe_phy_x550em_kr:
3067                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3068                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3069                 break;
3070         case ixgbe_phy_x550em_kx4:
3071                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3072                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3073                 break;
3074         case ixgbe_phy_x550em_ext_t:
3075                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3076                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3077                                      &ext_ability);
3078                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3079                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3080                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3081                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3082                 break;
3083         default:
3084                 break;
3085         }
3086
3087         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3088                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3089
3090         return physical_layer;
3091 }
3092
3093 /**
3094  * ixgbe_get_bus_info_x550em - Set PCI bus info
3095  * @hw: pointer to hardware structure
3096  *
3097  * Sets bus link width and speed to unknown because X550em is
3098  * not a PCI device.
3099  **/
3100 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3101 {
3102
3103         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3104
3105         hw->bus.width = ixgbe_bus_width_unknown;
3106         hw->bus.speed = ixgbe_bus_speed_unknown;
3107
3108         hw->mac.ops.set_lan_id(hw);
3109
3110         return IXGBE_SUCCESS;
3111 }
3112
3113 /**
3114  * ixgbe_disable_rx_x550 - Disable RX unit
3115  *
3116  * Enables the Rx DMA unit for x550
3117  **/
3118 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3119 {
3120         u32 rxctrl, pfdtxgswc;
3121         s32 status;
3122         struct ixgbe_hic_disable_rxen fw_cmd;
3123
3124         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3125
3126         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3127         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3128                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3129                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3130                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3131                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3132                         hw->mac.set_lben = true;
3133                 } else {
3134                         hw->mac.set_lben = false;
3135                 }
3136
3137                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3138                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3139                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3140                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3141
3142                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3143                                         sizeof(struct ixgbe_hic_disable_rxen),
3144                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3145
3146                 /* If we fail - disable RX using register write */
3147                 if (status) {
3148                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3149                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3150                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3151                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3152                         }
3153                 }
3154         }
3155 }
3156
3157 /**
3158  * ixgbe_enter_lplu_x550em - Transition to low power states
3159  *  @hw: pointer to hardware structure
3160  *
3161  * Configures Low Power Link Up on transition to low power states
3162  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3163  * X557 PHY immediately prior to entering LPLU.
3164  **/
3165 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3166 {
3167         u16 an_10g_cntl_reg, autoneg_reg, speed;
3168         s32 status;
3169         ixgbe_link_speed lcd_speed;
3170         u32 save_autoneg;
3171         bool link_up;
3172
3173         /* SW LPLU not required on later HW revisions. */
3174         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3175             (IXGBE_FUSES0_REV_MASK &
3176              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3177                 return IXGBE_SUCCESS;
3178
3179         /* If blocked by MNG FW, then don't restart AN */
3180         if (ixgbe_check_reset_blocked(hw))
3181                 return IXGBE_SUCCESS;
3182
3183         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3184         if (status != IXGBE_SUCCESS)
3185                 return status;
3186
3187         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3188
3189         if (status != IXGBE_SUCCESS)
3190                 return status;
3191
3192         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3193          * disabled, then force link down by entering low power mode.
3194          */
3195         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3196             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3197                 return ixgbe_set_copper_phy_power(hw, FALSE);
3198
3199         /* Determine LCD */
3200         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3201
3202         if (status != IXGBE_SUCCESS)
3203                 return status;
3204
3205         /* If no valid LCD link speed, then force link down and exit. */
3206         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3207                 return ixgbe_set_copper_phy_power(hw, FALSE);
3208
3209         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3210                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3211                                       &speed);
3212
3213         if (status != IXGBE_SUCCESS)
3214                 return status;
3215
3216         /* If no link now, speed is invalid so take link down */
3217         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3218         if (status != IXGBE_SUCCESS)
3219                 return ixgbe_set_copper_phy_power(hw, false);
3220
3221         /* clear everything but the speed bits */
3222         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3223
3224         /* If current speed is already LCD, then exit. */
3225         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3226              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3227             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3228              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3229                 return status;
3230
3231         /* Clear AN completed indication */
3232         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3233                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3234                                       &autoneg_reg);
3235
3236         if (status != IXGBE_SUCCESS)
3237                 return status;
3238
3239         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3240                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3241                              &an_10g_cntl_reg);
3242
3243         if (status != IXGBE_SUCCESS)
3244                 return status;
3245
3246         status = hw->phy.ops.read_reg(hw,
3247                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3248                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3249                              &autoneg_reg);
3250
3251         if (status != IXGBE_SUCCESS)
3252                 return status;
3253
3254         save_autoneg = hw->phy.autoneg_advertised;
3255
3256         /* Setup link at least common link speed */
3257         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3258
3259         /* restore autoneg from before setting lplu speed */
3260         hw->phy.autoneg_advertised = save_autoneg;
3261
3262         return status;
3263 }
3264
3265 /**
3266  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3267  *  @hw: pointer to hardware structure
3268  *  @lcd_speed: pointer to lowest common link speed
3269  *
3270  * Determine lowest common link speed with link partner.
3271  **/
3272 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3273 {
3274         u16 an_lp_status;
3275         s32 status;
3276         u16 word = hw->eeprom.ctrl_word_3;
3277
3278         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3279
3280         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3281                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3282                                       &an_lp_status);
3283
3284         if (status != IXGBE_SUCCESS)
3285                 return status;
3286
3287         /* If link partner advertised 1G, return 1G */
3288         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3289                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3290                 return status;
3291         }
3292
3293         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3294         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3295             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3296                 return status;
3297
3298         /* Link partner not capable of lower speeds, return 10G */
3299         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3300         return status;
3301 }
3302
3303 /**
3304  *  ixgbe_setup_fc_X550em - Set up flow control
3305  *  @hw: pointer to hardware structure
3306  *
3307  *  Called at init time to set up flow control.
3308  **/
3309 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3310 {
3311         s32 ret_val = IXGBE_SUCCESS;
3312         u32 pause, asm_dir, reg_val;
3313
3314         DEBUGFUNC("ixgbe_setup_fc_X550em");
3315
3316         /* Validate the requested mode */
3317         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3318                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3319                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3320                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3321                 goto out;
3322         }
3323
3324         /* 10gig parts do not have a word in the EEPROM to determine the
3325          * default flow control setting, so we explicitly set it to full.
3326          */
3327         if (hw->fc.requested_mode == ixgbe_fc_default)
3328                 hw->fc.requested_mode = ixgbe_fc_full;
3329
3330         /* Determine PAUSE and ASM_DIR bits. */
3331         switch (hw->fc.requested_mode) {
3332         case ixgbe_fc_none:
3333                 pause = 0;
3334                 asm_dir = 0;
3335                 break;
3336         case ixgbe_fc_tx_pause:
3337                 pause = 0;
3338                 asm_dir = 1;
3339                 break;
3340         case ixgbe_fc_rx_pause:
3341                 /* Rx Flow control is enabled and Tx Flow control is
3342                  * disabled by software override. Since there really
3343                  * isn't a way to advertise that we are capable of RX
3344                  * Pause ONLY, we will advertise that we support both
3345                  * symmetric and asymmetric Rx PAUSE, as such we fall
3346                  * through to the fc_full statement.  Later, we will
3347                  * disable the adapter's ability to send PAUSE frames.
3348                  */
3349         case ixgbe_fc_full:
3350                 pause = 1;
3351                 asm_dir = 1;
3352                 break;
3353         default:
3354                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3355                         "Flow control param set incorrectly\n");
3356                 ret_val = IXGBE_ERR_CONFIG;
3357                 goto out;
3358         }
3359
3360         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3361                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3362                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3363                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3364                 if (ret_val != IXGBE_SUCCESS)
3365                         goto out;
3366                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3367                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3368                 if (pause)
3369                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3370                 if (asm_dir)
3371                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3372                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3373                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3374                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3375
3376                 /* This device does not fully support AN. */
3377                 hw->fc.disable_fc_autoneg = true;
3378         }
3379
3380 out:
3381         return ret_val;
3382 }
3383
3384 /**
3385  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3386  * @hw: pointer to hardware structure
3387  * @state: set mux if 1, clear if 0
3388  */
3389 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3390 {
3391         u32 esdp;
3392
3393         if (!hw->bus.lan_id)
3394                 return;
3395         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3396         if (state)
3397                 esdp |= IXGBE_ESDP_SDP1;
3398         else
3399                 esdp &= ~IXGBE_ESDP_SDP1;
3400         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3401         IXGBE_WRITE_FLUSH(hw);
3402 }
3403
3404 /**
3405  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3406  *  @hw: pointer to hardware structure
3407  *  @mask: Mask to specify which semaphore to acquire
3408  *
3409  *  Acquires the SWFW semaphore and sets the I2C MUX
3410  **/
3411 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3412 {
3413         s32 status;
3414
3415         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3416
3417         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3418         if (status)
3419                 return status;
3420
3421         if (mask & IXGBE_GSSR_I2C_MASK)
3422                 ixgbe_set_mux(hw, 1);
3423
3424         return IXGBE_SUCCESS;
3425 }
3426
3427 /**
3428  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3429  *  @hw: pointer to hardware structure
3430  *  @mask: Mask to specify which semaphore to release
3431  *
3432  *  Releases the SWFW semaphore and sets the I2C MUX
3433  **/
3434 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3435 {
3436         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3437
3438         if (mask & IXGBE_GSSR_I2C_MASK)
3439                 ixgbe_set_mux(hw, 0);
3440
3441         ixgbe_release_swfw_sync_X540(hw, mask);
3442 }
3443
3444 /**
3445  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3446  *  @hw: pointer to hardware structure
3447  *  @mask: Mask to specify which semaphore to acquire
3448  *
3449  *  Acquires the SWFW semaphore and get the shared phy token as needed
3450  */
3451 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3452 {
3453         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3454         int retries = FW_PHY_TOKEN_RETRIES;
3455         s32 status = IXGBE_SUCCESS;
3456
3457         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3458
3459         while (--retries) {
3460                 if (hmask)
3461                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3462                 if (status)
3463                         break;
3464                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3465                         break;
3466                 status = ixgbe_get_phy_token(hw);
3467                 if (status != IXGBE_ERR_TOKEN_RETRY)
3468                         break;
3469                 if (hmask)
3470                         ixgbe_release_swfw_sync_X540(hw, hmask);
3471                 msec_delay(FW_PHY_TOKEN_DELAY);
3472         }
3473
3474         return status;
3475 }
3476
3477 /**
3478  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3479  *  @hw: pointer to hardware structure
3480  *  @mask: Mask to specify which semaphore to release
3481  *
3482  *  Releases the SWFW semaphore and puts the shared phy token as needed
3483  */
3484 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3485 {
3486         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3487
3488         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3489
3490         if (mask & IXGBE_GSSR_TOKEN_SM)
3491                 ixgbe_put_phy_token(hw);
3492
3493         if (hmask)
3494                 ixgbe_release_swfw_sync_X540(hw, hmask);
3495 }
3496
3497 /**
3498  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3499  * @hw: pointer to hardware structure
3500  *
3501  * Handle external Base T PHY interrupt. If high temperature
3502  * failure alarm then return error, else if link status change
3503  * then setup internal/external PHY link
3504  *
3505  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3506  * failure alarm, else return PHY access status.
3507  */
3508 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3509 {
3510         bool lsc;
3511         u32 status;
3512
3513         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3514
3515         if (status != IXGBE_SUCCESS)
3516                 return status;
3517
3518         if (lsc)
3519                 return ixgbe_setup_internal_phy(hw);
3520
3521         return IXGBE_SUCCESS;
3522 }
3523
3524 /**
3525  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3526  * @hw: pointer to hardware structure
3527  * @speed: new link speed
3528  * @autoneg_wait_to_complete: true when waiting for completion is needed
3529  *
3530  * Setup internal/external PHY link speed based on link speed, then set
3531  * external PHY auto advertised link speed.
3532  *
3533  * Returns error status for any failure
3534  **/
3535 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3536                                   ixgbe_link_speed speed,
3537                                   bool autoneg_wait_to_complete)
3538 {
3539         s32 status;
3540         ixgbe_link_speed force_speed;
3541
3542         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3543
3544         /* Setup internal/external PHY link speed to iXFI (10G), unless
3545          * only 1G is auto advertised then setup KX link.
3546          */
3547         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3548                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3549         else
3550                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3551
3552         /* If internal link mode is XFI, then setup XFI internal link. */
3553         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3554                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3555
3556                 if (status != IXGBE_SUCCESS)
3557                         return status;
3558         }
3559
3560         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3561 }
3562
3563 /**
3564  * ixgbe_check_link_t_X550em - Determine link and speed status
3565  * @hw: pointer to hardware structure
3566  * @speed: pointer to link speed
3567  * @link_up: true when link is up
3568  * @link_up_wait_to_complete: bool used to wait for link up or not
3569  *
3570  * Check that both the MAC and X557 external PHY have link.
3571  **/
3572 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3573                               bool *link_up, bool link_up_wait_to_complete)
3574 {
3575         u32 status;
3576         u16 autoneg_status;
3577
3578         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3579                 return IXGBE_ERR_CONFIG;
3580
3581         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3582                                               link_up_wait_to_complete);
3583
3584         /* If check link fails or MAC link is not up, then return */
3585         if (status != IXGBE_SUCCESS || !(*link_up))
3586                 return status;
3587
3588         /* MAC link is up, so check external PHY link.
3589          * Read this twice back to back to indicate current status.
3590          */
3591         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3592                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3593                                       &autoneg_status);
3594
3595         if (status != IXGBE_SUCCESS)
3596                 return status;
3597
3598         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3599                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3600                                       &autoneg_status);
3601
3602         if (status != IXGBE_SUCCESS)
3603                 return status;
3604
3605         /* If external PHY link is not up, then indicate link not up */
3606         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3607                 *link_up = false;
3608
3609         return IXGBE_SUCCESS;
3610 }
3611
3612 /**
3613  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3614  *  @hw: pointer to hardware structure
3615  **/
3616 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3617 {
3618         s32 status;
3619
3620         status = ixgbe_reset_phy_generic(hw);
3621
3622         if (status != IXGBE_SUCCESS)
3623                 return status;
3624
3625         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3626         return ixgbe_enable_lasi_ext_t_x550em(hw);
3627 }
3628
3629 /**
3630  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3631  *  @hw: pointer to hardware structure
3632  *  @led_idx: led number to turn on
3633  **/
3634 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3635 {
3636         u16 phy_data;
3637
3638         DEBUGFUNC("ixgbe_led_on_t_X550em");
3639
3640         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3641                 return IXGBE_ERR_PARAM;
3642
3643         /* To turn on the LED, set mode to ON. */
3644         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3645                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3646         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3647         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3648                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3649
3650         return IXGBE_SUCCESS;
3651 }
3652
3653 /**
3654  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3655  *  @hw: pointer to hardware structure
3656  *  @led_idx: led number to turn off
3657  **/
3658 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3659 {
3660         u16 phy_data;
3661
3662         DEBUGFUNC("ixgbe_led_off_t_X550em");
3663
3664         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3665                 return IXGBE_ERR_PARAM;
3666
3667         /* To turn on the LED, set mode to ON. */
3668         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3669                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3670         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3671         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3672                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3673
3674         return IXGBE_SUCCESS;
3675 }
3676