drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42
  43 /**
  44  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  45  *  @hw: pointer to hardware structure
  46  *
  47  *  Initialize the function pointers and assign the MAC type for X550.
  48  *  Does not touch the hardware.
  49  **/
  50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_mac_info *mac = &hw->mac;
  53         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  54         s32 ret_val;
  55
  56         DEBUGFUNC("ixgbe_init_ops_X550");
  57
  58         ret_val = ixgbe_init_ops_X540(hw);
  59         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  60         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  61         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  62         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  63         mac->ops.set_source_address_pruning =
  64                         ixgbe_set_source_address_pruning_X550;
  65         mac->ops.set_ethertype_anti_spoofing =
  66                         ixgbe_set_ethertype_anti_spoofing_X550;
  67
  68         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  69         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  70         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  71         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  72         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  73         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  74         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  75         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  76         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  77
  78         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  79         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  80         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  81         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  82         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  83         switch (hw->device_id) {
  84         case IXGBE_DEV_ID_X550EM_X_10G_T:
  85         case IXGBE_DEV_ID_X550EM_A_10G_T:
  86                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  87                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  88                 break;
  89         default:
  90                 break;
  91         }
  92         return ret_val;
  93 }
  94
  95 /**
  96  * ixgbe_read_cs4227 - Read CS4227 register
  97  * @hw: pointer to hardware structure
  98  * @reg: register number to write
  99  * @value: pointer to receive value read
 100  *
 101  * Returns status code
 102  **/
 103 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 104 {
 105         return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 106 }
 107
 108 /**
 109  * ixgbe_write_cs4227 - Write CS4227 register
 110  * @hw: pointer to hardware structure
 111  * @reg: register number to write
 112  * @value: value to write to register
 113  *
 114  * Returns status code
 115  **/
 116 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 117 {
 118         return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
 119 }
 120
 121 /**
 122  * ixgbe_read_pe - Read register from port expander
 123  * @hw: pointer to hardware structure
 124  * @reg: register number to read
 125  * @value: pointer to receive read value
 126  *
 127  * Returns status code
 128  **/
 129 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 130 {
 131         s32 status;
 132
 133         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 134         if (status != IXGBE_SUCCESS)
 135                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 136                               "port expander access failed with %d\n", status);
 137         return status;
 138 }
 139
 140 /**
 141  * ixgbe_write_pe - Write register to port expander
 142  * @hw: pointer to hardware structure
 143  * @reg: register number to write
 144  * @value: value to write
 145  *
 146  * Returns status code
 147  **/
 148 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 149 {
 150         s32 status;
 151
 152         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 153         if (status != IXGBE_SUCCESS)
 154                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 155                               "port expander access failed with %d\n", status);
 156         return status;
 157 }
 158
 159 /**
 160  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 161  * @hw: pointer to hardware structure
 162  *
 163  * This function assumes that the caller has acquired the proper semaphore.
 164  * Returns error code
 165  **/
 166 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 167 {
 168         s32 status;
 169         u32 retry;
 170         u16 value;
 171         u8 reg;
 172
 173         /* Trigger hard reset. */
 174         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 175         if (status != IXGBE_SUCCESS)
 176                 return status;
 177         reg |= IXGBE_PE_BIT1;
 178         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 179         if (status != IXGBE_SUCCESS)
 180                 return status;
 181
 182         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 183         if (status != IXGBE_SUCCESS)
 184                 return status;
 185         reg &= ~IXGBE_PE_BIT1;
 186         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 187         if (status != IXGBE_SUCCESS)
 188                 return status;
 189
 190         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 191         if (status != IXGBE_SUCCESS)
 192                 return status;
 193         reg &= ~IXGBE_PE_BIT1;
 194         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 195         if (status != IXGBE_SUCCESS)
 196                 return status;
 197
 198         usec_delay(IXGBE_CS4227_RESET_HOLD);
 199
 200         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 201         if (status != IXGBE_SUCCESS)
 202                 return status;
 203         reg |= IXGBE_PE_BIT1;
 204         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 205         if (status != IXGBE_SUCCESS)
 206                 return status;
 207
 208         /* Wait for the reset to complete. */
 209         msec_delay(IXGBE_CS4227_RESET_DELAY);
 210         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 211                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 212                                            &value);
 213                 if (status == IXGBE_SUCCESS &&
 214                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 215                         break;
 216                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 217         }
 218         if (retry == IXGBE_CS4227_RETRIES) {
 219                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 220                         "CS4227 reset did not complete.");
 221                 return IXGBE_ERR_PHY;
 222         }
 223
 224         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 225         if (status != IXGBE_SUCCESS ||
 226             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 227                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 228                         "CS4227 EEPROM did not load successfully.");
 229                 return IXGBE_ERR_PHY;
 230         }
 231
 232         return IXGBE_SUCCESS;
 233 }
 234
 235 /**
 236  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 237  * @hw: pointer to hardware structure
 238  **/
 239 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 240 {
 241         s32 status = IXGBE_SUCCESS;
 242         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 243         u16 value = 0;
 244         u8 retry;
 245
 246         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 247                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 248                 if (status != IXGBE_SUCCESS) {
 249                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 250                                 "semaphore failed with %d", status);
 251                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 252                         continue;
 253                 }
 254
 255                 /* Get status of reset flow. */
 256                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 257
 258                 if (status == IXGBE_SUCCESS &&
 259                     value == IXGBE_CS4227_RESET_COMPLETE)
 260                         goto out;
 261
 262                 if (status != IXGBE_SUCCESS ||
 263                     value != IXGBE_CS4227_RESET_PENDING)
 264                         break;
 265
 266                 /* Reset is pending. Wait and check again. */
 267                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 268                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 269         }
 270
 271         /* If still pending, assume other instance failed. */
 272         if (retry == IXGBE_CS4227_RETRIES) {
 273                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 274                 if (status != IXGBE_SUCCESS) {
 275                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 276                                       "semaphore failed with %d", status);
 277                         return;
 278                 }
 279         }
 280
 281         /* Reset the CS4227. */
 282         status = ixgbe_reset_cs4227(hw);
 283         if (status != IXGBE_SUCCESS) {
 284                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 285                         "CS4227 reset failed: %d", status);
 286                 goto out;
 287         }
 288
 289         /* Reset takes so long, temporarily release semaphore in case the
 290          * other driver instance is waiting for the reset indication.
 291          */
 292         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 293                            IXGBE_CS4227_RESET_PENDING);
 294         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 295         msec_delay(10);
 296         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 297         if (status != IXGBE_SUCCESS) {
 298                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 299                         "semaphore failed with %d", status);
 300                 return;
 301         }
 302
 303         /* Record completion for next time. */
 304         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 305                 IXGBE_CS4227_RESET_COMPLETE);
 306
 307 out:
 308         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 309         msec_delay(hw->eeprom.semaphore_delay);
 310 }
 311
 312 /**
 313  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 314  * @hw: pointer to hardware structure
 315  **/
 316 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 317 {
 318         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 319
 320         if (hw->bus.lan_id) {
 321                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 322                 esdp |= IXGBE_ESDP_SDP1_DIR;
 323         }
 324         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 325         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 326         IXGBE_WRITE_FLUSH(hw);
 327 }
 328
 329 /**
 330  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 331  * @hw: pointer to hardware structure
 332  *
 333  * Returns error code
 334  */
 335 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 336 {
 337         switch (hw->device_id) {
 338         case IXGBE_DEV_ID_X550EM_A_SFP:
 339                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 340                 if (hw->bus.lan_id)
 341                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 342                 else
 343                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 344                 return ixgbe_identify_module_generic(hw);
 345         case IXGBE_DEV_ID_X550EM_X_SFP:
 346                 /* set up for CS4227 usage */
 347                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 348                 ixgbe_setup_mux_ctl(hw);
 349                 ixgbe_check_cs4227(hw);
 350                 /* Fallthrough */
 351
 352         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 353                 return ixgbe_identify_module_generic(hw);
 354                 break;
 355         case IXGBE_DEV_ID_X550EM_X_KX4:
 356                 hw->phy.type = ixgbe_phy_x550em_kx4;
 357                 break;
 358         case IXGBE_DEV_ID_X550EM_X_KR:
 359         case IXGBE_DEV_ID_X550EM_A_KR:
 360         case IXGBE_DEV_ID_X550EM_A_KR_L:
 361                 hw->phy.type = ixgbe_phy_x550em_kr;
 362                 break;
 363         case IXGBE_DEV_ID_X550EM_X_1G_T:
 364         case IXGBE_DEV_ID_X550EM_X_10G_T:
 365         case IXGBE_DEV_ID_X550EM_A_1G_T:
 366         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 367         case IXGBE_DEV_ID_X550EM_A_10G_T:
 368                 return ixgbe_identify_phy_generic(hw);
 369         default:
 370                 break;
 371         }
 372         return IXGBE_SUCCESS;
 373 }
 374
 375 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 376                                      u32 device_type, u16 *phy_data)
 377 {
 378         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 379         return IXGBE_NOT_IMPLEMENTED;
 380 }
 381
 382 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 383                                       u32 device_type, u16 phy_data)
 384 {
 385         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 386         return IXGBE_NOT_IMPLEMENTED;
 387 }
 388
 389 /**
 390 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 391 *  @hw: pointer to hardware structure
 392 *
 393 *  Initialize the function pointers and for MAC type X550EM.
 394 *  Does not touch the hardware.
 395 **/
 396 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 397 {
 398         struct ixgbe_mac_info *mac = &hw->mac;
 399         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 400         struct ixgbe_phy_info *phy = &hw->phy;
 401         s32 ret_val;
 402
 403         DEBUGFUNC("ixgbe_init_ops_X550EM");
 404
 405         /* Similar to X550 so start there. */
 406         ret_val = ixgbe_init_ops_X550(hw);
 407
 408         /* Since this function eventually calls
 409          * ixgbe_init_ops_540 by design, we are setting
 410          * the pointers to NULL explicitly here to overwrite
 411          * the values being set in the x540 function.
 412          */
 413         /* Thermal sensor not supported in x550EM */
 414         mac->ops.get_thermal_sensor_data = NULL;
 415         mac->ops.init_thermal_sensor_thresh = NULL;
 416         mac->thermal_sensor_enabled = false;
 417
 418         /* FCOE not supported in x550EM */
 419         mac->ops.get_san_mac_addr = NULL;
 420         mac->ops.set_san_mac_addr = NULL;
 421         mac->ops.get_wwn_prefix = NULL;
 422         mac->ops.get_fcoe_boot_status = NULL;
 423
 424         /* IPsec not supported in x550EM */
 425         mac->ops.disable_sec_rx_path = NULL;
 426         mac->ops.enable_sec_rx_path = NULL;
 427
 428         /* AUTOC register is not present in x550EM. */
 429         mac->ops.prot_autoc_read = NULL;
 430         mac->ops.prot_autoc_write = NULL;
 431
 432         /* X550EM bus type is internal*/
 433         hw->bus.type = ixgbe_bus_type_internal;
 434         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 435
 436         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 437                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 438                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 439                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 440                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 441         }
 442         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 443                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 444                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 445         }
 446
 447         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 448         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 449         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 450         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 451         mac->ops.get_supported_physical_layer =
 452                                     ixgbe_get_supported_physical_layer_X550em;
 453
 454         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 455                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 456         else
 457                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 458
 459
 460         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 461                 mac->ops.setup_eee = NULL;
 462
 463         /* PHY */
 464         phy->ops.init = ixgbe_init_phy_ops_X550em;
 465         phy->ops.identify = ixgbe_identify_phy_x550em;
 466         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 467                 phy->ops.set_phy_power = NULL;
 468
 469
 470         /* EEPROM */
 471         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 472         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 473         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 474         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 475         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 476         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 477         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 478         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 479
 480         return ret_val;
 481 }
 482
 483 /**
 484  *  ixgbe_dmac_config_X550
 485  *  @hw: pointer to hardware structure
 486  *
 487  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 488  *  When disabling dmac, dmac enable dmac bit is cleared.
 489  **/
 490 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 491 {
 492         u32 reg, high_pri_tc;
 493
 494         DEBUGFUNC("ixgbe_dmac_config_X550");
 495
 496         /* Disable DMA coalescing before configuring */
 497         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 498         reg &= ~IXGBE_DMACR_DMAC_EN;
 499         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 500
 501         /* Disable DMA Coalescing if the watchdog timer is 0 */
 502         if (!hw->mac.dmac_config.watchdog_timer)
 503                 goto out;
 504
 505         ixgbe_dmac_config_tcs_X550(hw);
 506
 507         /* Configure DMA Coalescing Control Register */
 508         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 509
 510         /* Set the watchdog timer in units of 40.96 usec */
 511         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 512         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 513
 514         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 515         /* If fcoe is enabled, set high priority traffic class */
 516         if (hw->mac.dmac_config.fcoe_en) {
 517                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 518                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 519                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 520         }
 521         reg |= IXGBE_DMACR_EN_MNG_IND;
 522
 523         /* Enable DMA coalescing after configuration */
 524         reg |= IXGBE_DMACR_DMAC_EN;
 525         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 526
 527 out:
 528         return IXGBE_SUCCESS;
 529 }
 530
 531 /**
 532  *  ixgbe_dmac_config_tcs_X550
 533  *  @hw: pointer to hardware structure
 534  *
 535  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 536  *  be cleared before configuring.
 537  **/
 538 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 539 {
 540         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 541
 542         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 543
 544         /* Configure DMA coalescing enabled */
 545         switch (hw->mac.dmac_config.link_speed) {
 546         case IXGBE_LINK_SPEED_100_FULL:
 547                 pb_headroom = IXGBE_DMACRXT_100M;
 548                 break;
 549         case IXGBE_LINK_SPEED_1GB_FULL:
 550                 pb_headroom = IXGBE_DMACRXT_1G;
 551                 break;
 552         default:
 553                 pb_headroom = IXGBE_DMACRXT_10G;
 554                 break;
 555         }
 556
 557         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 558                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 559
 560         /* Set the per Rx packet buffer receive threshold */
 561         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 562                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 563                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 564
 565                 if (tc < hw->mac.dmac_config.num_tcs) {
 566                         /* Get Rx PB size */
 567                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 568                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 569                                 IXGBE_RXPBSIZE_SHIFT;
 570
 571                         /* Calculate receive buffer threshold in kilobytes */
 572                         if (rx_pb_size > pb_headroom)
 573                                 rx_pb_size = rx_pb_size - pb_headroom;
 574                         else
 575                                 rx_pb_size = 0;
 576
 577                         /* Minimum of MFS shall be set for DMCTH */
 578                         reg |= (rx_pb_size > maxframe_size_kb) ?
 579                                 rx_pb_size : maxframe_size_kb;
 580                 }
 581                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 582         }
 583         return IXGBE_SUCCESS;
 584 }
 585
 586 /**
 587  *  ixgbe_dmac_update_tcs_X550
 588  *  @hw: pointer to hardware structure
 589  *
 590  *  Disables dmac, updates per TC settings, and then enables dmac.
 591  **/
 592 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 593 {
 594         u32 reg;
 595
 596         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 597
 598         /* Disable DMA coalescing before configuring */
 599         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 600         reg &= ~IXGBE_DMACR_DMAC_EN;
 601         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 602
 603         ixgbe_dmac_config_tcs_X550(hw);
 604
 605         /* Enable DMA coalescing after configuration */
 606         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 607         reg |= IXGBE_DMACR_DMAC_EN;
 608         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 609
 610         return IXGBE_SUCCESS;
 611 }
 612
 613 /**
 614  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 615  *  @hw: pointer to hardware structure
 616  *
 617  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 618  *  ixgbe_hw struct in order to set up EEPROM access.
 619  **/
 620 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 621 {
 622         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 623         u32 eec;
 624         u16 eeprom_size;
 625
 626         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 627
 628         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 629                 eeprom->semaphore_delay = 10;
 630                 eeprom->type = ixgbe_flash;
 631
 632                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 633                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 634                                     IXGBE_EEC_SIZE_SHIFT);
 635                 eeprom->word_size = 1 << (eeprom_size +
 636                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 637
 638                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 639                           eeprom->type, eeprom->word_size);
 640         }
 641
 642         return IXGBE_SUCCESS;
 643 }
 644
 645 /**
 646  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 647  *  @hw: pointer to the HW structure
 648  *  @enable_eee: boolean flag to enable EEE
 649  *
 650  *  Enable/disable EEE based on enable_eee flag.
 651  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 652  *  are modified.
 653  *
 654  **/
 655 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 656 {
 657         u32 eeer;
 658         u16 autoneg_eee_reg;
 659         u32 link_reg;
 660         s32 status;
 661
 662         DEBUGFUNC("ixgbe_setup_eee_X550");
 663
 664         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 665         /* Enable or disable EEE per flag */
 666         if (enable_eee) {
 667                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 668
 669                 if (hw->mac.type == ixgbe_mac_X550) {
 670                         /* Advertise EEE capability */
 671                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 672                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 673
 674                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 675                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 676                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 677
 678                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 679                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 680                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 681                         /* Not supported on first revision of X550EM_x. */
 682                         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 683                             !(IXGBE_FUSES0_REV_MASK &
 684                               IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 685                                 return IXGBE_SUCCESS;
 686
 687                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 688                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 689                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 690                         if (status != IXGBE_SUCCESS)
 691                                 return status;
 692
 693                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 694                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 695
 696                         /* Don't advertise FEC capability when EEE enabled. */
 697                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 698
 699                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 700                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 701                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 702                         if (status != IXGBE_SUCCESS)
 703                                 return status;
 704                 }
 705         } else {
 706                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 707
 708                 if (hw->mac.type == ixgbe_mac_X550) {
 709                         /* Disable advertised EEE capability */
 710                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 711                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 712
 713                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 714                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 715                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 716
 717                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 718                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 719                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 720                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 721                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 722                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 723                         if (status != IXGBE_SUCCESS)
 724                                 return status;
 725
 726                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 727                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 728
 729                         /* Advertise FEC capability when EEE is disabled. */
 730                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 731
 732                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 733                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 734                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 735                         if (status != IXGBE_SUCCESS)
 736                                 return status;
 737                 }
 738         }
 739         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 740
 741         return IXGBE_SUCCESS;
 742 }
 743
 744 /**
 745  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 746  * @hw: pointer to hardware structure
 747  * @enable: enable or disable source address pruning
 748  * @pool: Rx pool to set source address pruning for
 749  **/
 750 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 751                                            unsigned int pool)
 752 {
 753         u64 pfflp;
 754
 755         /* max rx pool is 63 */
 756         if (pool > 63)
 757                 return;
 758
 759         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 760         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 761
 762         if (enable)
 763                 pfflp |= (1ULL << pool);
 764         else
 765                 pfflp &= ~(1ULL << pool);
 766
 767         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 768         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 769 }
 770
 771 /**
 772  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 773  *  @hw: pointer to hardware structure
 774  *  @enable: enable or disable switch for Ethertype anti-spoofing
 775  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 776  *
 777  **/
 778 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 779                 bool enable, int vf)
 780 {
 781         int vf_target_reg = vf >> 3;
 782         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 783         u32 pfvfspoof;
 784
 785         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 786
 787         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 788         if (enable)
 789                 pfvfspoof |= (1 << vf_target_shift);
 790         else
 791                 pfvfspoof &= ~(1 << vf_target_shift);
 792
 793         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 794 }
 795
 796 /**
 797  * ixgbe_iosf_wait - Wait for IOSF command completion
 798  * @hw: pointer to hardware structure
 799  * @ctrl: pointer to location to receive final IOSF control value
 800  *
 801  * Returns failing status on timeout
 802  *
 803  * Note: ctrl can be NULL if the IOSF control register value is not needed
 804  **/
 805 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 806 {
 807         u32 i, command = 0;
 808
 809         /* Check every 10 usec to see if the address cycle completed.
 810          * The SB IOSF BUSY bit will clear when the operation is
 811          * complete
 812          */
 813         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 814                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 815                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 816                         break;
 817                 usec_delay(10);
 818         }
 819         if (ctrl)
 820                 *ctrl = command;
 821         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 822                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 823                 return IXGBE_ERR_PHY;
 824         }
 825
 826         return IXGBE_SUCCESS;
 827 }
 828
 829 /**
 830  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 831  *  device
 832  *  @hw: pointer to hardware structure
 833  *  @reg_addr: 32 bit PHY register to write
 834  *  @device_type: 3 bit device type
 835  *  @data: Data to write to the register
 836  **/
 837 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 838                             u32 device_type, u32 data)
 839 {
 840         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 841         u32 command, error;
 842         s32 ret;
 843
 844         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 845         if (ret != IXGBE_SUCCESS)
 846                 return ret;
 847
 848         ret = ixgbe_iosf_wait(hw, NULL);
 849         if (ret != IXGBE_SUCCESS)
 850                 goto out;
 851
 852         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 853                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 854
 855         /* Write IOSF control register */
 856         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 857
 858         /* Write IOSF data register */
 859         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 860
 861         ret = ixgbe_iosf_wait(hw, &command);
 862
 863         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 864                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 865                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 866                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 867                               "Failed to write, error %x\n", error);
 868                 ret = IXGBE_ERR_PHY;
 869         }
 870
 871 out:
 872         ixgbe_release_swfw_semaphore(hw, gssr);
 873         return ret;
 874 }
 875
 876 /**
 877  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 878  *  device
 879  *  @hw: pointer to hardware structure
 880  *  @reg_addr: 32 bit PHY register to write
 881  *  @device_type: 3 bit device type
 882  *  @phy_data: Pointer to read data from the register
 883  **/
 884 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 885                            u32 device_type, u32 *data)
 886 {
 887         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 888         u32 command, error;
 889         s32 ret;
 890
 891         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 892         if (ret != IXGBE_SUCCESS)
 893                 return ret;
 894
 895         ret = ixgbe_iosf_wait(hw, NULL);
 896         if (ret != IXGBE_SUCCESS)
 897                 goto out;
 898
 899         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 900                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 901
 902         /* Write IOSF control register */
 903         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 904
 905         ret = ixgbe_iosf_wait(hw, &command);
 906
 907         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 908                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 909                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 910                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 911                                 "Failed to read, error %x\n", error);
 912                 ret = IXGBE_ERR_PHY;
 913         }
 914
 915         if (ret == IXGBE_SUCCESS)
 916                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 917
 918 out:
 919         ixgbe_release_swfw_semaphore(hw, gssr);
 920         return ret;
 921 }
 922
 923 /**
 924  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
 925  *  of the IOSF device
 926  *  @hw: pointer to hardware structure
 927  *  @reg_addr: 32 bit PHY register to write
 928  *  @device_type: 3 bit device type
 929  *  @data: Data to write to the register
 930  **/
 931 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 932         u32 device_type, u32 data)
 933 {
 934         struct ixgbe_hic_internal_phy_req write_cmd;
 935         s32 status;
 936         UNREFERENCED_1PARAMETER(device_type);
 937
 938         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 939         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 940         write_cmd.port_number = hw->bus.lan_id;
 941         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 942         write_cmd.address = (u16)reg_addr;
 943         write_cmd.rsv1 = 0;
 944         write_cmd.write_data = data;
 945         write_cmd.pad = 0;
 946
 947         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
 948                 sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, false);
 949
 950         return status;
 951 }
 952
 953 /**
 954  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
 955  *  of the IOSF device.
 956  *  @hw: pointer to hardware structure
 957  *  @reg_addr: 32 bit PHY register to write
 958  *  @device_type: 3 bit device type
 959  *  @data: Pointer to read data from the register
 960  **/
 961 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 962         u32 device_type, u32 *data)
 963 {
 964         struct ixgbe_hic_internal_phy_req read_cmd;
 965         s32 status;
 966         UNREFERENCED_1PARAMETER(device_type);
 967
 968         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 969         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 970         read_cmd.port_number = hw->bus.lan_id;
 971         read_cmd.command_type = FW_INT_PHY_REQ_READ;
 972         read_cmd.address = (u16)reg_addr;
 973         read_cmd.rsv1 = 0;
 974         read_cmd.write_data = 0;
 975         read_cmd.pad = 0;
 976
 977         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
 978                 sizeof(read_cmd), IXGBE_HI_COMMAND_TIMEOUT, true);
 979
 980         /* Extract the register value from the response. */
 981         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
 982
 983         return status;
 984 }
 985
 986 /**
 987  *  ixgbe_disable_mdd_X550
 988  *  @hw: pointer to hardware structure
 989  *
 990  *  Disable malicious driver detection
 991  **/
 992 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 993 {
 994         u32 reg;
 995
 996         DEBUGFUNC("ixgbe_disable_mdd_X550");
 997
 998         /* Disable MDD for TX DMA and interrupt */
 999         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1000         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1001         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1002
1003         /* Disable MDD for RX and interrupt */
1004         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1005         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1006         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1007 }
1008
1009 /**
1010  *  ixgbe_enable_mdd_X550
1011  *  @hw: pointer to hardware structure
1012  *
1013  *  Enable malicious driver detection
1014  **/
1015 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1016 {
1017         u32 reg;
1018
1019         DEBUGFUNC("ixgbe_enable_mdd_X550");
1020
1021         /* Enable MDD for TX DMA and interrupt */
1022         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1023         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1024         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1025
1026         /* Enable MDD for RX and interrupt */
1027         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1028         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1029         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1030 }
1031
1032 /**
1033  *  ixgbe_restore_mdd_vf_X550
1034  *  @hw: pointer to hardware structure
1035  *  @vf: vf index
1036  *
1037  *  Restore VF that was disabled during malicious driver detection event
1038  **/
1039 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1040 {
1041         u32 idx, reg, num_qs, start_q, bitmask;
1042
1043         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1044
1045         /* Map VF to queues */
1046         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1047         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1048         case IXGBE_MRQC_VMDQRT8TCEN:
1049                 num_qs = 8;  /* 16 VFs / pools */
1050                 bitmask = 0x000000FF;
1051                 break;
1052         case IXGBE_MRQC_VMDQRSS32EN:
1053         case IXGBE_MRQC_VMDQRT4TCEN:
1054                 num_qs = 4;  /* 32 VFs / pools */
1055                 bitmask = 0x0000000F;
1056                 break;
1057         default:            /* 64 VFs / pools */
1058                 num_qs = 2;
1059                 bitmask = 0x00000003;
1060                 break;
1061         }
1062         start_q = vf * num_qs;
1063
1064         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1065         idx = start_q / 32;
1066         reg = 0;
1067         reg |= (bitmask << (start_q % 32));
1068         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1069         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1070 }
1071
1072 /**
1073  *  ixgbe_mdd_event_X550
1074  *  @hw: pointer to hardware structure
1075  *  @vf_bitmap: vf bitmap of malicious vfs
1076  *
1077  *  Handle malicious driver detection event.
1078  **/
1079 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1080 {
1081         u32 wqbr;
1082         u32 i, j, reg, q, shift, vf, idx;
1083
1084         DEBUGFUNC("ixgbe_mdd_event_X550");
1085
1086         /* figure out pool size for mapping to vf's */
1087         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1088         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1089         case IXGBE_MRQC_VMDQRT8TCEN:
1090                 shift = 3;  /* 16 VFs / pools */
1091                 break;
1092         case IXGBE_MRQC_VMDQRSS32EN:
1093         case IXGBE_MRQC_VMDQRT4TCEN:
1094                 shift = 2;  /* 32 VFs / pools */
1095                 break;
1096         default:
1097                 shift = 1;  /* 64 VFs / pools */
1098                 break;
1099         }
1100
1101         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1102         for (i = 0; i < 4; i++) {
1103                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1104                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1105
1106                 if (!wqbr)
1107                         continue;
1108
1109                 /* Get malicious queue */
1110                 for (j = 0; j < 32 && wqbr; j++) {
1111
1112                         if (!(wqbr & (1 << j)))
1113                                 continue;
1114
1115                         /* Get queue from bitmask */
1116                         q = j + (i * 32);
1117
1118                         /* Map queue to vf */
1119                         vf = (q >> shift);
1120
1121                         /* Set vf bit in vf_bitmap */
1122                         idx = vf / 32;
1123                         vf_bitmap[idx] |= (1 << (vf % 32));
1124                         wqbr &= ~(1 << j);
1125                 }
1126         }
1127 }
1128
1129 /**
1130  *  ixgbe_get_media_type_X550em - Get media type
1131  *  @hw: pointer to hardware structure
1132  *
1133  *  Returns the media type (fiber, copper, backplane)
1134  */
1135 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1136 {
1137         enum ixgbe_media_type media_type;
1138
1139         DEBUGFUNC("ixgbe_get_media_type_X550em");
1140
1141         /* Detect if there is a copper PHY attached. */
1142         switch (hw->device_id) {
1143         case IXGBE_DEV_ID_X550EM_X_KR:
1144         case IXGBE_DEV_ID_X550EM_X_KX4:
1145         case IXGBE_DEV_ID_X550EM_A_KR:
1146         case IXGBE_DEV_ID_X550EM_A_KR_L:
1147                 media_type = ixgbe_media_type_backplane;
1148                 break;
1149         case IXGBE_DEV_ID_X550EM_X_SFP:
1150         case IXGBE_DEV_ID_X550EM_A_SFP:
1151         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1152         case IXGBE_DEV_ID_X550EM_A_QSFP:
1153         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1154                 media_type = ixgbe_media_type_fiber;
1155                 break;
1156         case IXGBE_DEV_ID_X550EM_X_1G_T:
1157         case IXGBE_DEV_ID_X550EM_X_10G_T:
1158         case IXGBE_DEV_ID_X550EM_A_1G_T:
1159         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1160         case IXGBE_DEV_ID_X550EM_A_10G_T:
1161                 media_type = ixgbe_media_type_copper;
1162                 break;
1163         default:
1164                 media_type = ixgbe_media_type_unknown;
1165                 break;
1166         }
1167         return media_type;
1168 }
1169
1170 /**
1171  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1172  *  @hw: pointer to hardware structure
1173  *  @linear: true if SFP module is linear
1174  */
1175 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1176 {
1177         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1178
1179         switch (hw->phy.sfp_type) {
1180         case ixgbe_sfp_type_not_present:
1181                 return IXGBE_ERR_SFP_NOT_PRESENT;
1182         case ixgbe_sfp_type_da_cu_core0:
1183         case ixgbe_sfp_type_da_cu_core1:
1184                 *linear = true;
1185                 break;
1186         case ixgbe_sfp_type_srlr_core0:
1187         case ixgbe_sfp_type_srlr_core1:
1188         case ixgbe_sfp_type_da_act_lmt_core0:
1189         case ixgbe_sfp_type_da_act_lmt_core1:
1190         case ixgbe_sfp_type_1g_sx_core0:
1191         case ixgbe_sfp_type_1g_sx_core1:
1192         case ixgbe_sfp_type_1g_lx_core0:
1193         case ixgbe_sfp_type_1g_lx_core1:
1194                 *linear = false;
1195                 break;
1196         case ixgbe_sfp_type_unknown:
1197         case ixgbe_sfp_type_1g_cu_core0:
1198         case ixgbe_sfp_type_1g_cu_core1:
1199         default:
1200                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1201         }
1202
1203         return IXGBE_SUCCESS;
1204 }
1205
1206 /**
1207  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1208  *  @hw: pointer to hardware structure
1209  *
1210  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1211  **/
1212 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1213 {
1214         s32 status;
1215         bool linear;
1216
1217         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1218
1219         status = ixgbe_identify_module_generic(hw);
1220
1221         if (status != IXGBE_SUCCESS)
1222                 return status;
1223
1224         /* Check if SFP module is supported */
1225         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1226
1227         return status;
1228 }
1229
1230 /**
1231  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1232  *  @hw: pointer to hardware structure
1233  */
1234 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1235 {
1236         s32 status;
1237         bool linear;
1238
1239         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1240
1241         /* Check if SFP module is supported */
1242         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1243
1244         if (status != IXGBE_SUCCESS)
1245                 return status;
1246
1247         ixgbe_init_mac_link_ops_X550em(hw);
1248         hw->phy.ops.reset = NULL;
1249
1250         return IXGBE_SUCCESS;
1251 }
1252
1253 /**
1254  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1255  *  @hw: pointer to hardware structure
1256  */
1257 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1258 {
1259         struct ixgbe_mac_info *mac = &hw->mac;
1260
1261         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1262
1263          switch (hw->mac.ops.get_media_type(hw)) {
1264          case ixgbe_media_type_fiber:
1265                 /* CS4227 does not support autoneg, so disable the laser control
1266                  * functions for SFP+ fiber
1267                  */
1268                 mac->ops.disable_tx_laser = NULL;
1269                 mac->ops.enable_tx_laser = NULL;
1270                 mac->ops.flap_tx_laser = NULL;
1271                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1272                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1273                 mac->ops.set_rate_select_speed =
1274                                         ixgbe_set_soft_rate_select_speed;
1275                 break;
1276         case ixgbe_media_type_copper:
1277                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1278                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1279                 break;
1280         default:
1281                 break;
1282          }
1283 }
1284
1285 /**
1286  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1287  *  @hw: pointer to hardware structure
1288  *  @speed: pointer to link speed
1289  *  @autoneg: true when autoneg or autotry is enabled
1290  */
1291 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1292                                        ixgbe_link_speed *speed,
1293                                        bool *autoneg)
1294 {
1295         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1296
1297         /* SFP */
1298         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1299
1300                 /* CS4227 SFP must not enable auto-negotiation */
1301                 *autoneg = false;
1302
1303                 /* Check if 1G SFP module. */
1304                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1305                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1306                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1307                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1308                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1309                         return IXGBE_SUCCESS;
1310                 }
1311
1312                 /* Link capabilities are based on SFP */
1313                 if (hw->phy.multispeed_fiber)
1314                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1315                                  IXGBE_LINK_SPEED_1GB_FULL;
1316                 else
1317                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1318         } else {
1319                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1320                          IXGBE_LINK_SPEED_1GB_FULL;
1321                 *autoneg = true;
1322         }
1323
1324         return IXGBE_SUCCESS;
1325 }
1326
1327 /**
1328  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1329  * @hw: pointer to hardware structure
1330  * @lsc: pointer to boolean flag which indicates whether external Base T
1331  *       PHY interrupt is lsc
1332  *
1333  * Determime if external Base T PHY interrupt cause is high temperature
1334  * failure alarm or link status change.
1335  *
1336  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1337  * failure alarm, else return PHY access status.
1338  */
1339 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1340 {
1341         u32 status;
1342         u16 reg;
1343
1344         *lsc = false;
1345
1346         /* Vendor alarm triggered */
1347         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1348                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1349                                       &reg);
1350
1351         if (status != IXGBE_SUCCESS ||
1352             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1353                 return status;
1354
1355         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1356         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1357                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1358                                       &reg);
1359
1360         if (status != IXGBE_SUCCESS ||
1361             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1362             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1363                 return status;
1364
1365         /* Global alarm triggered */
1366         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1367                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1368                                       &reg);
1369
1370         if (status != IXGBE_SUCCESS)
1371                 return status;
1372
1373         /* If high temperature failure, then return over temp error and exit */
1374         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1375                 /* power down the PHY in case the PHY FW didn't already */
1376                 ixgbe_set_copper_phy_power(hw, false);
1377                 return IXGBE_ERR_OVERTEMP;
1378         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1379                 /*  device fault alarm triggered */
1380                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1381                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1382                                           &reg);
1383
1384                 if (status != IXGBE_SUCCESS)
1385                         return status;
1386
1387                 /* if device fault was due to high temp alarm handle and exit */
1388                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1389                         /* power down the PHY in case the PHY FW didn't */
1390                         ixgbe_set_copper_phy_power(hw, false);
1391                         return IXGBE_ERR_OVERTEMP;
1392                 }
1393         }
1394
1395         /* Vendor alarm 2 triggered */
1396         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1397                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1398
1399         if (status != IXGBE_SUCCESS ||
1400             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1401                 return status;
1402
1403         /* link connect/disconnect event occurred */
1404         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1405                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1406
1407         if (status != IXGBE_SUCCESS)
1408                 return status;
1409
1410         /* Indicate LSC */
1411         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1412                 *lsc = true;
1413
1414         return IXGBE_SUCCESS;
1415 }
1416
1417 /**
1418  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1419  * @hw: pointer to hardware structure
1420  *
1421  * Enable link status change and temperature failure alarm for the external
1422  * Base T PHY
1423  *
1424  * Returns PHY access status
1425  */
1426 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1427 {
1428         u32 status;
1429         u16 reg;
1430         bool lsc;
1431
1432         /* Clear interrupt flags */
1433         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1434
1435         /* Enable link status change alarm */
1436         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1437                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1438
1439         if (status != IXGBE_SUCCESS)
1440                 return status;
1441
1442         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1443
1444         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1445                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1446
1447         if (status != IXGBE_SUCCESS)
1448                 return status;
1449
1450         /* Enable high temperature failure and global fault alarms */
1451         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1452                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1453                                       &reg);
1454
1455         if (status != IXGBE_SUCCESS)
1456                 return status;
1457
1458         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1459                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1460
1461         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1462                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1463                                        reg);
1464
1465         if (status != IXGBE_SUCCESS)
1466                 return status;
1467
1468         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1469         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1470                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1471                                       &reg);
1472
1473         if (status != IXGBE_SUCCESS)
1474                 return status;
1475
1476         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1477                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1478
1479         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1480                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1481                                        reg);
1482
1483         if (status != IXGBE_SUCCESS)
1484                 return status;
1485
1486         /* Enable chip-wide vendor alarm */
1487         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1488                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1489                                       &reg);
1490
1491         if (status != IXGBE_SUCCESS)
1492                 return status;
1493
1494         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1495
1496         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1497                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1498                                        reg);
1499
1500         return status;
1501 }
1502
1503 /**
1504  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1505  *  @hw: pointer to hardware structure
1506  *  @speed: link speed
1507  *
1508  *  Configures the integrated KR PHY.
1509  **/
1510 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1511                                        ixgbe_link_speed speed)
1512 {
1513         s32 status;
1514         u32 reg_val;
1515
1516         status = ixgbe_read_iosf_sb_reg_x550(hw,
1517                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1518                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1519         if (status)
1520                 return status;
1521
1522         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1523         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1524                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1525
1526         /* Advertise 10G support. */
1527         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1528                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1529
1530         /* Advertise 1G support. */
1531         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1532                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1533
1534         /* Restart auto-negotiation. */
1535         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1536         status = ixgbe_write_iosf_sb_reg_x550(hw,
1537                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1538                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1539
1540         return status;
1541 }
1542
1543 /**
1544  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1545  *  @hw: pointer to hardware structure
1546  *
1547  *  Initialize any function pointers that were not able to be
1548  *  set during init_shared_code because the PHY/SFP type was
1549  *  not known.  Perform the SFP init if necessary.
1550  */
1551 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1552 {
1553         struct ixgbe_phy_info *phy = &hw->phy;
1554         s32 ret_val;
1555
1556         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1557
1558         hw->mac.ops.set_lan_id(hw);
1559
1560         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1561                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1562                 ixgbe_setup_mux_ctl(hw);
1563
1564                 /* Save NW management interface connected on board. This is used
1565                  * to determine internal PHY mode.
1566                  */
1567                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1568                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1569         }
1570
1571         /* Identify the PHY or SFP module */
1572         ret_val = phy->ops.identify(hw);
1573         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1574                 return ret_val;
1575
1576         /* Setup function pointers based on detected hardware */
1577         ixgbe_init_mac_link_ops_X550em(hw);
1578         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1579                 phy->ops.reset = NULL;
1580
1581         /* Set functions pointers based on phy type */
1582         switch (hw->phy.type) {
1583         case ixgbe_phy_x550em_kx4:
1584                 phy->ops.setup_link = NULL;
1585                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1586                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1587                 break;
1588         case ixgbe_phy_x550em_kr:
1589                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1590                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1591                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1592                 break;
1593         case ixgbe_phy_x550em_ext_t:
1594                 /* Save NW management interface connected on board. This is used
1595                  * to determine internal PHY mode
1596                  */
1597                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1598
1599                 /* If internal link mode is XFI, then setup iXFI internal link,
1600                  * else setup KR now.
1601                  */
1602                 phy->ops.setup_internal_link =
1603                                               ixgbe_setup_internal_phy_t_x550em;
1604
1605                 /* setup SW LPLU only for first revision of X550EM_x */
1606                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1607                     !(IXGBE_FUSES0_REV_MASK &
1608                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1609                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1610
1611                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1612                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1613                 break;
1614         default:
1615                 break;
1616         }
1617         return ret_val;
1618 }
1619
1620 /**
1621  *  ixgbe_reset_hw_X550em - Perform hardware reset
1622  *  @hw: pointer to hardware structure
1623  *
1624  *  Resets the hardware by resetting the transmit and receive units, masks
1625  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1626  *  reset.
1627  */
1628 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1629 {
1630         ixgbe_link_speed link_speed;
1631         s32 status;
1632         u32 ctrl = 0;
1633         u32 i;
1634         u32 hlreg0;
1635         bool link_up = false;
1636
1637         DEBUGFUNC("ixgbe_reset_hw_X550em");
1638
1639         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1640         status = hw->mac.ops.stop_adapter(hw);
1641         if (status != IXGBE_SUCCESS)
1642                 return status;
1643
1644         /* flush pending Tx transactions */
1645         ixgbe_clear_tx_pending(hw);
1646
1647         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1648                 /* Config MDIO clock speed before the first MDIO PHY access */
1649                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1650                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1651                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1652         }
1653
1654         /* PHY ops must be identified and initialized prior to reset */
1655         status = hw->phy.ops.init(hw);
1656
1657         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1658                 return status;
1659
1660         /* start the external PHY */
1661         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1662                 status = ixgbe_init_ext_t_x550em(hw);
1663                 if (status)
1664                         return status;
1665         }
1666
1667         /* Setup SFP module if there is one present. */
1668         if (hw->phy.sfp_setup_needed) {
1669                 status = hw->mac.ops.setup_sfp(hw);
1670                 hw->phy.sfp_setup_needed = false;
1671         }
1672
1673         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1674                 return status;
1675
1676         /* Reset PHY */
1677         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1678                 hw->phy.ops.reset(hw);
1679
1680 mac_reset_top:
1681         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1682          * If link reset is used when link is up, it might reset the PHY when
1683          * mng is using it.  If link is down or the flag to force full link
1684          * reset is set, then perform link reset.
1685          */
1686         ctrl = IXGBE_CTRL_LNK_RST;
1687         if (!hw->force_full_reset) {
1688                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1689                 if (link_up)
1690                         ctrl = IXGBE_CTRL_RST;
1691         }
1692
1693         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1694         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1695         IXGBE_WRITE_FLUSH(hw);
1696
1697         /* Poll for reset bit to self-clear meaning reset is complete */
1698         for (i = 0; i < 10; i++) {
1699                 usec_delay(1);
1700                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1701                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1702                         break;
1703         }
1704
1705         if (ctrl & IXGBE_CTRL_RST_MASK) {
1706                 status = IXGBE_ERR_RESET_FAILED;
1707                 DEBUGOUT("Reset polling failed to complete.\n");
1708         }
1709
1710         msec_delay(50);
1711
1712         /* Double resets are required for recovery from certain error
1713          * conditions.  Between resets, it is necessary to stall to
1714          * allow time for any pending HW events to complete.
1715          */
1716         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1717                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1718                 goto mac_reset_top;
1719         }
1720
1721         /* Store the permanent mac address */
1722         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1723
1724         /* Store MAC address from RAR0, clear receive address registers, and
1725          * clear the multicast table.  Also reset num_rar_entries to 128,
1726          * since we modify this value when programming the SAN MAC address.
1727          */
1728         hw->mac.num_rar_entries = 128;
1729         hw->mac.ops.init_rx_addrs(hw);
1730
1731         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1732                 ixgbe_setup_mux_ctl(hw);
1733
1734         return status;
1735 }
1736
1737 /**
1738  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1739  * @hw: pointer to hardware structure
1740  */
1741 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1742 {
1743         u32 status;
1744         u16 reg;
1745
1746         status = hw->phy.ops.read_reg(hw,
1747                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1748                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1749                                       &reg);
1750
1751         if (status != IXGBE_SUCCESS)
1752                 return status;
1753
1754         /* If PHY FW reset completed bit is set then this is the first
1755          * SW instance after a power on so the PHY FW must be un-stalled.
1756          */
1757         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1758                 status = hw->phy.ops.read_reg(hw,
1759                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1760                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1761                                         &reg);
1762
1763                 if (status != IXGBE_SUCCESS)
1764                         return status;
1765
1766                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1767
1768                 status = hw->phy.ops.write_reg(hw,
1769                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1770                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1771                                         reg);
1772
1773                 if (status != IXGBE_SUCCESS)
1774                         return status;
1775         }
1776
1777         return status;
1778 }
1779
1780 /**
1781  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1782  *  @hw: pointer to hardware structure
1783  *
1784  *  Configures the integrated KR PHY.
1785  **/
1786 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1787 {
1788         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1789 }
1790
1791 /**
1792  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1793  *  @hw: pointer to hardware structure
1794  *
1795  *  Configure the external PHY and the integrated KR PHY for SFP support.
1796  **/
1797 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1798                                     ixgbe_link_speed speed,
1799                                     bool autoneg_wait_to_complete)
1800 {
1801         s32 ret_val;
1802         u16 reg_slice, reg_val;
1803         bool setup_linear = false;
1804         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1805
1806         /* Check if SFP module is supported and linear */
1807         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1808
1809         /* If no SFP module present, then return success. Return success since
1810          * there is no reason to configure CS4227 and SFP not present error is
1811          * not excepted in the setup MAC link flow.
1812          */
1813         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1814                 return IXGBE_SUCCESS;
1815
1816         if (ret_val != IXGBE_SUCCESS)
1817                 return ret_val;
1818
1819         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1820                 /* Configure CS4227 LINE side to 10G SR. */
1821                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1822                             (hw->bus.lan_id << 12);
1823                 reg_val = IXGBE_CS4227_SPEED_10G;
1824                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1825                                                    reg_val);
1826
1827                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1828                             (hw->bus.lan_id << 12);
1829                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1830                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1831                                                    reg_val);
1832
1833                 /* Configure CS4227 for HOST connection rate then type. */
1834                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1835                             (hw->bus.lan_id << 12);
1836                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1837                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1838                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1839                                                    reg_val);
1840
1841                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1842                             (hw->bus.lan_id << 12);
1843                 if (setup_linear)
1844                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1845                 else
1846                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1847                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1848                                                    reg_val);
1849
1850                 /* Setup XFI internal link. */
1851                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1852         } else {
1853                 /* Configure internal PHY for KR/KX. */
1854                 ixgbe_setup_kr_speed_x550em(hw, speed);
1855
1856                 /* Configure CS4227 LINE side to proper mode. */
1857                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1858                             (hw->bus.lan_id << 12);
1859                 if (setup_linear)
1860                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1861                 else
1862                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1863                 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1864                                                    reg_val);
1865         }
1866         return ret_val;
1867 }
1868
1869 /**
1870  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1871  *  @hw: pointer to hardware structure
1872  *
1873  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1874  **/
1875 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1876 {
1877         s32 status;
1878         u32 reg_val;
1879
1880         /* Disable training protocol FSM. */
1881         status = ixgbe_read_iosf_sb_reg_x550(hw,
1882                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1883                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1884         if (status != IXGBE_SUCCESS)
1885                 return status;
1886         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1887         status = ixgbe_write_iosf_sb_reg_x550(hw,
1888                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1889                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1890         if (status != IXGBE_SUCCESS)
1891                 return status;
1892
1893         /* Disable Flex from training TXFFE. */
1894         status = ixgbe_read_iosf_sb_reg_x550(hw,
1895                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1896                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1897         if (status != IXGBE_SUCCESS)
1898                 return status;
1899         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1900         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1901         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1902         status = ixgbe_write_iosf_sb_reg_x550(hw,
1903                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1904                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1905         if (status != IXGBE_SUCCESS)
1906                 return status;
1907         status = ixgbe_read_iosf_sb_reg_x550(hw,
1908                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1909                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1910         if (status != IXGBE_SUCCESS)
1911                 return status;
1912         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1913         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1914         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1915         status = ixgbe_write_iosf_sb_reg_x550(hw,
1916                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1917                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1918         if (status != IXGBE_SUCCESS)
1919                 return status;
1920
1921         /* Enable override for coefficients. */
1922         status = ixgbe_read_iosf_sb_reg_x550(hw,
1923                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1924                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1925         if (status != IXGBE_SUCCESS)
1926                 return status;
1927         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1928         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1929         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1930         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1931         status = ixgbe_write_iosf_sb_reg_x550(hw,
1932                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1933                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1934         return status;
1935 }
1936
1937 /**
1938  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1939  *  @hw: pointer to hardware structure
1940  *  @speed: the link speed to force
1941  *
1942  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1943  *  internal and external PHY at a specific speed, without autonegotiation.
1944  **/
1945 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1946 {
1947         s32 status;
1948         u32 reg_val;
1949
1950         /* Disable AN and force speed to 10G Serial. */
1951         status = ixgbe_read_iosf_sb_reg_x550(hw,
1952                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1953                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1954         if (status != IXGBE_SUCCESS)
1955                 return status;
1956
1957         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1958         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1959
1960         /* Select forced link speed for internal PHY. */
1961         switch (*speed) {
1962         case IXGBE_LINK_SPEED_10GB_FULL:
1963                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1964                 break;
1965         case IXGBE_LINK_SPEED_1GB_FULL:
1966                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1967                 break;
1968         default:
1969                 /* Other link speeds are not supported by internal KR PHY. */
1970                 return IXGBE_ERR_LINK_SETUP;
1971         }
1972
1973         status = ixgbe_write_iosf_sb_reg_x550(hw,
1974                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1975                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1976         if (status != IXGBE_SUCCESS)
1977                 return status;
1978
1979         /* Additional configuration needed for x550em_x */
1980         if (hw->mac.type == ixgbe_mac_X550EM_x) {
1981                 status = ixgbe_setup_ixfi_x550em_x(hw);
1982                 if (status != IXGBE_SUCCESS)
1983                         return status;
1984         }
1985
1986         /* Toggle port SW reset by AN reset. */
1987         status = ixgbe_read_iosf_sb_reg_x550(hw,
1988                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1989                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1990         if (status != IXGBE_SUCCESS)
1991                 return status;
1992         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1993         status = ixgbe_write_iosf_sb_reg_x550(hw,
1994                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1995                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1996
1997         return status;
1998 }
1999
2000 /**
2001  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2002  * @hw: address of hardware structure
2003  * @link_up: address of boolean to indicate link status
2004  *
2005  * Returns error code if unable to get link status.
2006  */
2007 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2008 {
2009         u32 ret;
2010         u16 autoneg_status;
2011
2012         *link_up = false;
2013
2014         /* read this twice back to back to indicate current status */
2015         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2016                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2017                                    &autoneg_status);
2018         if (ret != IXGBE_SUCCESS)
2019                 return ret;
2020
2021         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2022                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2023                                    &autoneg_status);
2024         if (ret != IXGBE_SUCCESS)
2025                 return ret;
2026
2027         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2028
2029         return IXGBE_SUCCESS;
2030 }
2031
2032 /**
2033  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2034  * @hw: point to hardware structure
2035  *
2036  * Configures the link between the integrated KR PHY and the external X557 PHY
2037  * The driver will call this function when it gets a link status change
2038  * interrupt from the X557 PHY. This function configures the link speed
2039  * between the PHYs to match the link speed of the BASE-T link.
2040  *
2041  * A return of a non-zero value indicates an error, and the base driver should
2042  * not report link up.
2043  */
2044 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2045 {
2046         ixgbe_link_speed force_speed;
2047         bool link_up;
2048         u32 status;
2049         u16 speed;
2050
2051         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2052                 return IXGBE_ERR_CONFIG;
2053
2054         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2055                 /* If link is down, there is no setup necessary so return  */
2056                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2057                 if (status != IXGBE_SUCCESS)
2058                         return status;
2059
2060                 if (!link_up)
2061                         return IXGBE_SUCCESS;
2062
2063                 status = hw->phy.ops.read_reg(hw,
2064                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2065                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2066                                               &speed);
2067                 if (status != IXGBE_SUCCESS)
2068                         return status;
2069
2070                 /* If link is still down - no setup is required so return */
2071                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2072                 if (status != IXGBE_SUCCESS)
2073                         return status;
2074                 if (!link_up)
2075                         return IXGBE_SUCCESS;
2076
2077                 /* clear everything but the speed and duplex bits */
2078                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2079
2080                 switch (speed) {
2081                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2082                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2083                         break;
2084                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2085                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2086                         break;
2087                 default:
2088                         /* Internal PHY does not support anything else */
2089                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2090                 }
2091
2092                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2093         } else {
2094                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2095                         IXGBE_LINK_SPEED_1GB_FULL;
2096                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2097         }
2098 }
2099
2100 /**
2101  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2102  *  @hw: pointer to hardware structure
2103  *
2104  *  Configures the integrated KR PHY to use internal loopback mode.
2105  **/
2106 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2107 {
2108         s32 status;
2109         u32 reg_val;
2110
2111         /* Disable AN and force speed to 10G Serial. */
2112         status = ixgbe_read_iosf_sb_reg_x550(hw,
2113                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2114                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2115         if (status != IXGBE_SUCCESS)
2116                 return status;
2117         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2118         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2119         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2120         status = ixgbe_write_iosf_sb_reg_x550(hw,
2121                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2122                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2123         if (status != IXGBE_SUCCESS)
2124                 return status;
2125
2126         /* Set near-end loopback clocks. */
2127         status = ixgbe_read_iosf_sb_reg_x550(hw,
2128                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2129                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2130         if (status != IXGBE_SUCCESS)
2131                 return status;
2132         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2133         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2134         status = ixgbe_write_iosf_sb_reg_x550(hw,
2135                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2136                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2137         if (status != IXGBE_SUCCESS)
2138                 return status;
2139
2140         /* Set loopback enable. */
2141         status = ixgbe_read_iosf_sb_reg_x550(hw,
2142                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2143                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2144         if (status != IXGBE_SUCCESS)
2145                 return status;
2146         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2147         status = ixgbe_write_iosf_sb_reg_x550(hw,
2148                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2149                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2150         if (status != IXGBE_SUCCESS)
2151                 return status;
2152
2153         /* Training bypass. */
2154         status = ixgbe_read_iosf_sb_reg_x550(hw,
2155                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2156                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2157         if (status != IXGBE_SUCCESS)
2158                 return status;
2159         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2160         status = ixgbe_write_iosf_sb_reg_x550(hw,
2161                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2162                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2163
2164         return status;
2165 }
2166
2167 /**
2168  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2169  *  assuming that the semaphore is already obtained.
2170  *  @hw: pointer to hardware structure
2171  *  @offset: offset of  word in the EEPROM to read
2172  *  @data: word read from the EEPROM
2173  *
2174  *  Reads a 16 bit word from the EEPROM using the hostif.
2175  **/
2176 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2177                                    u16 *data)
2178 {
2179         s32 status;
2180         struct ixgbe_hic_read_shadow_ram buffer;
2181
2182         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2183         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2184         buffer.hdr.req.buf_lenh = 0;
2185         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2186         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2187
2188         /* convert offset from words to bytes */
2189         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2190         /* one word */
2191         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2192
2193         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2194                                               sizeof(buffer),
2195                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2196
2197         if (status)
2198                 return status;
2199
2200         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2201                                           FW_NVM_DATA_OFFSET);
2202
2203         return 0;
2204 }
2205
2206 /**
2207  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2208  *  @hw: pointer to hardware structure
2209  *  @offset: offset of  word in the EEPROM to read
2210  *  @data: word read from the EEPROM
2211  *
2212  *  Reads a 16 bit word from the EEPROM using the hostif.
2213  **/
2214 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2215                               u16 *data)
2216 {
2217         s32 status = IXGBE_SUCCESS;
2218
2219         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2220
2221         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2222             IXGBE_SUCCESS) {
2223                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2224                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2225         } else {
2226                 status = IXGBE_ERR_SWFW_SYNC;
2227         }
2228
2229         return status;
2230 }
2231
2232 /**
2233  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2234  *  @hw: pointer to hardware structure
2235  *  @offset: offset of  word in the EEPROM to read
2236  *  @words: number of words
2237  *  @data: word(s) read from the EEPROM
2238  *
2239  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2240  **/
2241 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2242                                      u16 offset, u16 words, u16 *data)
2243 {
2244         struct ixgbe_hic_read_shadow_ram buffer;
2245         u32 current_word = 0;
2246         u16 words_to_read;
2247         s32 status;
2248         u32 i;
2249
2250         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2251
2252         /* Take semaphore for the entire operation. */
2253         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2254         if (status) {
2255                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2256                 return status;
2257         }
2258         while (words) {
2259                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2260                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2261                 else
2262                         words_to_read = words;
2263
2264                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2265                 buffer.hdr.req.buf_lenh = 0;
2266                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2267                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2268
2269                 /* convert offset from words to bytes */
2270                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2271                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2272
2273                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2274                                                       sizeof(buffer),
2275                                                       IXGBE_HI_COMMAND_TIMEOUT,
2276                                                       false);
2277
2278                 if (status) {
2279                         DEBUGOUT("Host interface command failed\n");
2280                         goto out;
2281                 }
2282
2283                 for (i = 0; i < words_to_read; i++) {
2284                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2285                                   2 * i;
2286                         u32 value = IXGBE_READ_REG(hw, reg);
2287
2288                         data[current_word] = (u16)(value & 0xffff);
2289                         current_word++;
2290                         i++;
2291                         if (i < words_to_read) {
2292                                 value >>= 16;
2293                                 data[current_word] = (u16)(value & 0xffff);
2294                                 current_word++;
2295                         }
2296                 }
2297                 words -= words_to_read;
2298         }
2299
2300 out:
2301         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2302         return status;
2303 }
2304
2305 /**
2306  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2307  *  @hw: pointer to hardware structure
2308  *  @offset: offset of  word in the EEPROM to write
2309  *  @data: word write to the EEPROM
2310  *
2311  *  Write a 16 bit word to the EEPROM using the hostif.
2312  **/
2313 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2314                                     u16 data)
2315 {
2316         s32 status;
2317         struct ixgbe_hic_write_shadow_ram buffer;
2318
2319         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2320
2321         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2322         buffer.hdr.req.buf_lenh = 0;
2323         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2324         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2325
2326          /* one word */
2327         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2328         buffer.data = data;
2329         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2330
2331         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2332                                               sizeof(buffer),
2333                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2334
2335         return status;
2336 }
2337
2338 /**
2339  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2340  *  @hw: pointer to hardware structure
2341  *  @offset: offset of  word in the EEPROM to write
2342  *  @data: word write to the EEPROM
2343  *
2344  *  Write a 16 bit word to the EEPROM using the hostif.
2345  **/
2346 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2347                                u16 data)
2348 {
2349         s32 status = IXGBE_SUCCESS;
2350
2351         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2352
2353         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2354             IXGBE_SUCCESS) {
2355                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2356                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2357         } else {
2358                 DEBUGOUT("write ee hostif failed to get semaphore");
2359                 status = IXGBE_ERR_SWFW_SYNC;
2360         }
2361
2362         return status;
2363 }
2364
2365 /**
2366  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2367  *  @hw: pointer to hardware structure
2368  *  @offset: offset of  word in the EEPROM to write
2369  *  @words: number of words
2370  *  @data: word(s) write to the EEPROM
2371  *
2372  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2373  **/
2374 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2375                                       u16 offset, u16 words, u16 *data)
2376 {
2377         s32 status = IXGBE_SUCCESS;
2378         u32 i = 0;
2379
2380         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2381
2382         /* Take semaphore for the entire operation. */
2383         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2384         if (status != IXGBE_SUCCESS) {
2385                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2386                 goto out;
2387         }
2388
2389         for (i = 0; i < words; i++) {
2390                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2391                                                          data[i]);
2392
2393                 if (status != IXGBE_SUCCESS) {
2394                         DEBUGOUT("Eeprom buffered write failed\n");
2395                         break;
2396                 }
2397         }
2398
2399         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2400 out:
2401
2402         return status;
2403 }
2404
2405 /**
2406  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2407  * @hw: pointer to hardware structure
2408  * @ptr: pointer offset in eeprom
2409  * @size: size of section pointed by ptr, if 0 first word will be used as size
2410  * @csum: address of checksum to update
2411  *
2412  * Returns error status for any failure
2413  */
2414 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2415                                    u16 size, u16 *csum, u16 *buffer,
2416                                    u32 buffer_size)
2417 {
2418         u16 buf[256];
2419         s32 status;
2420         u16 length, bufsz, i, start;
2421         u16 *local_buffer;
2422
2423         bufsz = sizeof(buf) / sizeof(buf[0]);
2424
2425         /* Read a chunk at the pointer location */
2426         if (!buffer) {
2427                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2428                 if (status) {
2429                         DEBUGOUT("Failed to read EEPROM image\n");
2430                         return status;
2431                 }
2432                 local_buffer = buf;
2433         } else {
2434                 if (buffer_size < ptr)
2435                         return  IXGBE_ERR_PARAM;
2436                 local_buffer = &buffer[ptr];
2437         }
2438
2439         if (size) {
2440                 start = 0;
2441                 length = size;
2442         } else {
2443                 start = 1;
2444                 length = local_buffer[0];
2445
2446                 /* Skip pointer section if length is invalid. */
2447                 if (length == 0xFFFF || length == 0 ||
2448                     (ptr + length) >= hw->eeprom.word_size)
2449                         return IXGBE_SUCCESS;
2450         }
2451
2452         if (buffer && ((u32)start + (u32)length > buffer_size))
2453                 return IXGBE_ERR_PARAM;
2454
2455         for (i = start; length; i++, length--) {
2456                 if (i == bufsz && !buffer) {
2457                         ptr += bufsz;
2458                         i = 0;
2459                         if (length < bufsz)
2460                                 bufsz = length;
2461
2462                         /* Read a chunk at the pointer location */
2463                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2464                                                                   bufsz, buf);
2465                         if (status) {
2466                                 DEBUGOUT("Failed to read EEPROM image\n");
2467                                 return status;
2468                         }
2469                 }
2470                 *csum += local_buffer[i];
2471         }
2472         return IXGBE_SUCCESS;
2473 }
2474
2475 /**
2476  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2477  *  @hw: pointer to hardware structure
2478  *  @buffer: pointer to buffer containing calculated checksum
2479  *  @buffer_size: size of buffer
2480  *
2481  *  Returns a negative error code on error, or the 16-bit checksum
2482  **/
2483 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2484 {
2485         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2486         u16 *local_buffer;
2487         s32 status;
2488         u16 checksum = 0;
2489         u16 pointer, i, size;
2490
2491         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2492
2493         hw->eeprom.ops.init_params(hw);
2494
2495         if (!buffer) {
2496                 /* Read pointer area */
2497                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2498                                                      IXGBE_EEPROM_LAST_WORD + 1,
2499                                                      eeprom_ptrs);
2500                 if (status) {
2501                         DEBUGOUT("Failed to read EEPROM image\n");
2502                         return status;
2503                 }
2504                 local_buffer = eeprom_ptrs;
2505         } else {
2506                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2507                         return IXGBE_ERR_PARAM;
2508                 local_buffer = buffer;
2509         }
2510
2511         /*
2512          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2513          * checksum word itself
2514          */
2515         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2516                 if (i != IXGBE_EEPROM_CHECKSUM)
2517                         checksum += local_buffer[i];
2518
2519         /*
2520          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2521          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2522          */
2523         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2524                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2525                         continue;
2526
2527                 pointer = local_buffer[i];
2528
2529                 /* Skip pointer section if the pointer is invalid. */
2530                 if (pointer == 0xFFFF || pointer == 0 ||
2531                     pointer >= hw->eeprom.word_size)
2532                         continue;
2533
2534                 switch (i) {
2535                 case IXGBE_PCIE_GENERAL_PTR:
2536                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2537                         break;
2538                 case IXGBE_PCIE_CONFIG0_PTR:
2539                 case IXGBE_PCIE_CONFIG1_PTR:
2540                         size = IXGBE_PCIE_CONFIG_SIZE;
2541                         break;
2542                 default:
2543                         size = 0;
2544                         break;
2545                 }
2546
2547                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2548                                                 buffer, buffer_size);
2549                 if (status)
2550                         return status;
2551         }
2552
2553         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2554
2555         return (s32)checksum;
2556 }
2557
2558 /**
2559  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2560  *  @hw: pointer to hardware structure
2561  *
2562  *  Returns a negative error code on error, or the 16-bit checksum
2563  **/
2564 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2565 {
2566         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2567 }
2568
2569 /**
2570  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2571  *  @hw: pointer to hardware structure
2572  *  @checksum_val: calculated checksum
2573  *
2574  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2575  *  caller does not need checksum_val, the value can be NULL.
2576  **/
2577 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2578 {
2579         s32 status;
2580         u16 checksum;
2581         u16 read_checksum = 0;
2582
2583         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2584
2585         /* Read the first word from the EEPROM. If this times out or fails, do
2586          * not continue or we could be in for a very long wait while every
2587          * EEPROM read fails
2588          */
2589         status = hw->eeprom.ops.read(hw, 0, &checksum);
2590         if (status) {
2591                 DEBUGOUT("EEPROM read failed\n");
2592                 return status;
2593         }
2594
2595         status = hw->eeprom.ops.calc_checksum(hw);
2596         if (status < 0)
2597                 return status;
2598
2599         checksum = (u16)(status & 0xffff);
2600
2601         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2602                                            &read_checksum);
2603         if (status)
2604                 return status;
2605
2606         /* Verify read checksum from EEPROM is the same as
2607          * calculated checksum
2608          */
2609         if (read_checksum != checksum) {
2610                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2611                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2612                              "Invalid EEPROM checksum");
2613         }
2614
2615         /* If the user cares, return the calculated checksum */
2616         if (checksum_val)
2617                 *checksum_val = checksum;
2618
2619         return status;
2620 }
2621
2622 /**
2623  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2624  * @hw: pointer to hardware structure
2625  *
2626  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2627  * checksum and updates the EEPROM and instructs the hardware to update
2628  * the flash.
2629  **/
2630 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2631 {
2632         s32 status;
2633         u16 checksum = 0;
2634
2635         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2636
2637         /* Read the first word from the EEPROM. If this times out or fails, do
2638          * not continue or we could be in for a very long wait while every
2639          * EEPROM read fails
2640          */
2641         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2642         if (status) {
2643                 DEBUGOUT("EEPROM read failed\n");
2644                 return status;
2645         }
2646
2647         status = ixgbe_calc_eeprom_checksum_X550(hw);
2648         if (status < 0)
2649                 return status;
2650
2651         checksum = (u16)(status & 0xffff);
2652
2653         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2654                                             checksum);
2655         if (status)
2656                 return status;
2657
2658         status = ixgbe_update_flash_X550(hw);
2659
2660         return status;
2661 }
2662
2663 /**
2664  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2665  *  @hw: pointer to hardware structure
2666  *
2667  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2668  **/
2669 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2670 {
2671         s32 status = IXGBE_SUCCESS;
2672         union ixgbe_hic_hdr2 buffer;
2673
2674         DEBUGFUNC("ixgbe_update_flash_X550");
2675
2676         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2677         buffer.req.buf_lenh = 0;
2678         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2679         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2680
2681         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2682                                               sizeof(buffer),
2683                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2684
2685         return status;
2686 }
2687
2688 /**
2689  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2690  *  @hw: pointer to hardware structure
2691  *
2692  *  Determines physical layer capabilities of the current configuration.
2693  **/
2694 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2695 {
2696         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2697         u16 ext_ability = 0;
2698
2699         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2700
2701         hw->phy.ops.identify(hw);
2702
2703         switch (hw->phy.type) {
2704         case ixgbe_phy_x550em_kr:
2705                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2706                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2707                 break;
2708         case ixgbe_phy_x550em_kx4:
2709                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2710                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2711                 break;
2712         case ixgbe_phy_x550em_ext_t:
2713                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2714                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2715                                      &ext_ability);
2716                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2717                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2718                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2719                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2720                 break;
2721         default:
2722                 break;
2723         }
2724
2725         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2726                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2727
2728         return physical_layer;
2729 }
2730
2731 /**
2732  * ixgbe_get_bus_info_x550em - Set PCI bus info
2733  * @hw: pointer to hardware structure
2734  *
2735  * Sets bus link width and speed to unknown because X550em is
2736  * not a PCI device.
2737  **/
2738 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2739 {
2740
2741         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2742
2743         hw->bus.width = ixgbe_bus_width_unknown;
2744         hw->bus.speed = ixgbe_bus_speed_unknown;
2745
2746         hw->mac.ops.set_lan_id(hw);
2747
2748         return IXGBE_SUCCESS;
2749 }
2750
2751 /**
2752  * ixgbe_disable_rx_x550 - Disable RX unit
2753  *
2754  * Enables the Rx DMA unit for x550
2755  **/
2756 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2757 {
2758         u32 rxctrl, pfdtxgswc;
2759         s32 status;
2760         struct ixgbe_hic_disable_rxen fw_cmd;
2761
2762         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2763
2764         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2765         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2766                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2767                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2768                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2769                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2770                         hw->mac.set_lben = true;
2771                 } else {
2772                         hw->mac.set_lben = false;
2773                 }
2774
2775                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2776                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2777                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2778                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2779
2780                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2781                                         sizeof(struct ixgbe_hic_disable_rxen),
2782                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2783
2784                 /* If we fail - disable RX using register write */
2785                 if (status) {
2786                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2787                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2788                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2789                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2790                         }
2791                 }
2792         }
2793 }
2794
2795 /**
2796  * ixgbe_enter_lplu_x550em - Transition to low power states
2797  *  @hw: pointer to hardware structure
2798  *
2799  * Configures Low Power Link Up on transition to low power states
2800  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2801  * X557 PHY immediately prior to entering LPLU.
2802  **/
2803 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2804 {
2805         u16 an_10g_cntl_reg, autoneg_reg, speed;
2806         s32 status;
2807         ixgbe_link_speed lcd_speed;
2808         u32 save_autoneg;
2809         bool link_up;
2810
2811         /* SW LPLU not required on later HW revisions. */
2812         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2813             (IXGBE_FUSES0_REV_MASK &
2814              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2815                 return IXGBE_SUCCESS;
2816
2817         /* If blocked by MNG FW, then don't restart AN */
2818         if (ixgbe_check_reset_blocked(hw))
2819                 return IXGBE_SUCCESS;
2820
2821         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2822         if (status != IXGBE_SUCCESS)
2823                 return status;
2824
2825         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2826
2827         if (status != IXGBE_SUCCESS)
2828                 return status;
2829
2830         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2831          * disabled, then force link down by entering low power mode.
2832          */
2833         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2834             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2835                 return ixgbe_set_copper_phy_power(hw, FALSE);
2836
2837         /* Determine LCD */
2838         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2839
2840         if (status != IXGBE_SUCCESS)
2841                 return status;
2842
2843         /* If no valid LCD link speed, then force link down and exit. */
2844         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2845                 return ixgbe_set_copper_phy_power(hw, FALSE);
2846
2847         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2848                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2849                                       &speed);
2850
2851         if (status != IXGBE_SUCCESS)
2852                 return status;
2853
2854         /* If no link now, speed is invalid so take link down */
2855         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2856         if (status != IXGBE_SUCCESS)
2857                 return ixgbe_set_copper_phy_power(hw, false);
2858
2859         /* clear everything but the speed bits */
2860         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2861
2862         /* If current speed is already LCD, then exit. */
2863         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2864              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2865             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2866              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2867                 return status;
2868
2869         /* Clear AN completed indication */
2870         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2871                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2872                                       &autoneg_reg);
2873
2874         if (status != IXGBE_SUCCESS)
2875                 return status;
2876
2877         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2878                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2879                              &an_10g_cntl_reg);
2880
2881         if (status != IXGBE_SUCCESS)
2882                 return status;
2883
2884         status = hw->phy.ops.read_reg(hw,
2885                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2886                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2887                              &autoneg_reg);
2888
2889         if (status != IXGBE_SUCCESS)
2890                 return status;
2891
2892         save_autoneg = hw->phy.autoneg_advertised;
2893
2894         /* Setup link at least common link speed */
2895         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2896
2897         /* restore autoneg from before setting lplu speed */
2898         hw->phy.autoneg_advertised = save_autoneg;
2899
2900         return status;
2901 }
2902
2903 /**
2904  * ixgbe_get_lcd_x550em - Determine lowest common denominator
2905  *  @hw: pointer to hardware structure
2906  *  @lcd_speed: pointer to lowest common link speed
2907  *
2908  * Determine lowest common link speed with link partner.
2909  **/
2910 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2911 {
2912         u16 an_lp_status;
2913         s32 status;
2914         u16 word = hw->eeprom.ctrl_word_3;
2915
2916         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2917
2918         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2919                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2920                                       &an_lp_status);
2921
2922         if (status != IXGBE_SUCCESS)
2923                 return status;
2924
2925         /* If link partner advertised 1G, return 1G */
2926         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2927                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2928                 return status;
2929         }
2930
2931         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2932         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2933             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2934                 return status;
2935
2936         /* Link partner not capable of lower speeds, return 10G */
2937         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2938         return status;
2939 }
2940
2941 /**
2942  *  ixgbe_setup_fc_X550em - Set up flow control
2943  *  @hw: pointer to hardware structure
2944  *
2945  *  Called at init time to set up flow control.
2946  **/
2947 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2948 {
2949         s32 ret_val = IXGBE_SUCCESS;
2950         u32 pause, asm_dir, reg_val;
2951
2952         DEBUGFUNC("ixgbe_setup_fc_X550em");
2953
2954         /* Validate the requested mode */
2955         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2956                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2957                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2958                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2959                 goto out;
2960         }
2961
2962         /* 10gig parts do not have a word in the EEPROM to determine the
2963          * default flow control setting, so we explicitly set it to full.
2964          */
2965         if (hw->fc.requested_mode == ixgbe_fc_default)
2966                 hw->fc.requested_mode = ixgbe_fc_full;
2967
2968         /* Determine PAUSE and ASM_DIR bits. */
2969         switch (hw->fc.requested_mode) {
2970         case ixgbe_fc_none:
2971                 pause = 0;
2972                 asm_dir = 0;
2973                 break;
2974         case ixgbe_fc_tx_pause:
2975                 pause = 0;
2976                 asm_dir = 1;
2977                 break;
2978         case ixgbe_fc_rx_pause:
2979                 /* Rx Flow control is enabled and Tx Flow control is
2980                  * disabled by software override. Since there really
2981                  * isn't a way to advertise that we are capable of RX
2982                  * Pause ONLY, we will advertise that we support both
2983                  * symmetric and asymmetric Rx PAUSE, as such we fall
2984                  * through to the fc_full statement.  Later, we will
2985                  * disable the adapter's ability to send PAUSE frames.
2986                  */
2987         case ixgbe_fc_full:
2988                 pause = 1;
2989                 asm_dir = 1;
2990                 break;
2991         default:
2992                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2993                         "Flow control param set incorrectly\n");
2994                 ret_val = IXGBE_ERR_CONFIG;
2995                 goto out;
2996         }
2997
2998         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2999                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3000                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3001                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3002                 if (ret_val != IXGBE_SUCCESS)
3003                         goto out;
3004                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3005                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3006                 if (pause)
3007                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3008                 if (asm_dir)
3009                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3010                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3011                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3012                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3013
3014                 /* This device does not fully support AN. */
3015                 hw->fc.disable_fc_autoneg = true;
3016         }
3017
3018 out:
3019         return ret_val;
3020 }
3021
3022 /**
3023  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3024  * @hw: pointer to hardware structure
3025  * @state: set mux if 1, clear if 0
3026  */
3027 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3028 {
3029         u32 esdp;
3030
3031         if (!hw->bus.lan_id)
3032                 return;
3033         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3034         if (state)
3035                 esdp |= IXGBE_ESDP_SDP1;
3036         else
3037                 esdp &= ~IXGBE_ESDP_SDP1;
3038         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3039         IXGBE_WRITE_FLUSH(hw);
3040 }
3041
3042 /**
3043  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3044  *  @hw: pointer to hardware structure
3045  *  @mask: Mask to specify which semaphore to acquire
3046  *
3047  *  Acquires the SWFW semaphore and sets the I2C MUX
3048  **/
3049 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3050 {
3051         s32 status;
3052
3053         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3054
3055         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3056         if (status)
3057                 return status;
3058
3059         if (mask & IXGBE_GSSR_I2C_MASK)
3060                 ixgbe_set_mux(hw, 1);
3061
3062         return IXGBE_SUCCESS;
3063 }
3064
3065 /**
3066  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3067  *  @hw: pointer to hardware structure
3068  *  @mask: Mask to specify which semaphore to release
3069  *
3070  *  Releases the SWFW semaphore and sets the I2C MUX
3071  **/
3072 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3073 {
3074         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3075
3076         if (mask & IXGBE_GSSR_I2C_MASK)
3077                 ixgbe_set_mux(hw, 0);
3078
3079         ixgbe_release_swfw_sync_X540(hw, mask);
3080 }
3081
3082 /**
3083  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3084  * @hw: pointer to hardware structure
3085  *
3086  * Handle external Base T PHY interrupt. If high temperature
3087  * failure alarm then return error, else if link status change
3088  * then setup internal/external PHY link
3089  *
3090  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3091  * failure alarm, else return PHY access status.
3092  */
3093 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3094 {
3095         bool lsc;
3096         u32 status;
3097
3098         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3099
3100         if (status != IXGBE_SUCCESS)
3101                 return status;
3102
3103         if (lsc)
3104                 return ixgbe_setup_internal_phy(hw);
3105
3106         return IXGBE_SUCCESS;
3107 }
3108
3109 /**
3110  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3111  * @hw: pointer to hardware structure
3112  * @speed: new link speed
3113  * @autoneg_wait_to_complete: true when waiting for completion is needed
3114  *
3115  * Setup internal/external PHY link speed based on link speed, then set
3116  * external PHY auto advertised link speed.
3117  *
3118  * Returns error status for any failure
3119  **/
3120 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3121                                   ixgbe_link_speed speed,
3122                                   bool autoneg_wait_to_complete)
3123 {
3124         s32 status;
3125         ixgbe_link_speed force_speed;
3126
3127         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3128
3129         /* Setup internal/external PHY link speed to iXFI (10G), unless
3130          * only 1G is auto advertised then setup KX link.
3131          */
3132         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3133                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3134         else
3135                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3136
3137         /* If internal link mode is XFI, then setup XFI internal link. */
3138         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3139                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3140
3141                 if (status != IXGBE_SUCCESS)
3142                         return status;
3143         }
3144
3145         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3146 }
3147
3148 /**
3149  * ixgbe_check_link_t_X550em - Determine link and speed status
3150  * @hw: pointer to hardware structure
3151  * @speed: pointer to link speed
3152  * @link_up: true when link is up
3153  * @link_up_wait_to_complete: bool used to wait for link up or not
3154  *
3155  * Check that both the MAC and X557 external PHY have link.
3156  **/
3157 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3158                               bool *link_up, bool link_up_wait_to_complete)
3159 {
3160         u32 status;
3161         u16 autoneg_status;
3162
3163         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3164                 return IXGBE_ERR_CONFIG;
3165
3166         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3167                                               link_up_wait_to_complete);
3168
3169         /* If check link fails or MAC link is not up, then return */
3170         if (status != IXGBE_SUCCESS || !(*link_up))
3171                 return status;
3172
3173         /* MAC link is up, so check external PHY link.
3174          * Read this twice back to back to indicate current status.
3175          */
3176         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3177                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3178                                       &autoneg_status);
3179
3180         if (status != IXGBE_SUCCESS)
3181                 return status;
3182
3183         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3184                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3185                                       &autoneg_status);
3186
3187         if (status != IXGBE_SUCCESS)
3188                 return status;
3189
3190         /* If external PHY link is not up, then indicate link not up */
3191         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3192                 *link_up = false;
3193
3194         return IXGBE_SUCCESS;
3195 }
3196
3197 /**
3198  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3199  *  @hw: pointer to hardware structure
3200  **/
3201 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3202 {
3203         s32 status;
3204
3205         status = ixgbe_reset_phy_generic(hw);
3206
3207         if (status != IXGBE_SUCCESS)
3208                 return status;
3209
3210         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3211         return ixgbe_enable_lasi_ext_t_x550em(hw);
3212 }
3213
3214 /**
3215  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3216  *  @hw: pointer to hardware structure
3217  *  @led_idx: led number to turn on
3218  **/
3219 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3220 {
3221         u16 phy_data;
3222
3223         DEBUGFUNC("ixgbe_led_on_t_X550em");
3224
3225         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3226                 return IXGBE_ERR_PARAM;
3227
3228         /* To turn on the LED, set mode to ON. */
3229         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3230                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3231         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3232         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3233                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3234
3235         return IXGBE_SUCCESS;
3236 }
3237
3238 /**
3239  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3240  *  @hw: pointer to hardware structure
3241  *  @led_idx: led number to turn off
3242  **/
3243 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3244 {
3245         u16 phy_data;
3246
3247         DEBUGFUNC("ixgbe_led_off_t_X550em");
3248
3249         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3250                 return IXGBE_ERR_PARAM;
3251
3252         /* To turn on the LED, set mode to ON. */
3253         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3254                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3255         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3256         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3257                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3258
3259         return IXGBE_SUCCESS;
3260 }
3261