drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  98                 if (hw->bus.lan_id) {
  99
 100                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 101                         esdp |= IXGBE_ESDP_SDP1_DIR;
 102                 }
 103                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 104                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 105
 106                 return ixgbe_identify_module_generic(hw);
 107                 break;
 108         case IXGBE_DEV_ID_X550EM_X_KX4:
 109                 hw->phy.type = ixgbe_phy_x550em_kx4;
 110                 break;
 111         case IXGBE_DEV_ID_X550EM_X_KR:
 112                 hw->phy.type = ixgbe_phy_x550em_kr;
 113                 break;
 114         case IXGBE_DEV_ID_X550EM_X_1G_T:
 115         case IXGBE_DEV_ID_X550EM_X_10G_T:
 116                 return ixgbe_identify_phy_generic(hw);
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* X550EM bus type is internal*/
 177         hw->bus.type = ixgbe_bus_type_internal;
 178         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 179
 180         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 181         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 182         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 183         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 184         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 185         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 186         mac->ops.get_supported_physical_layer =
 187                                     ixgbe_get_supported_physical_layer_X550em;
 188
 189         /* PHY */
 190         phy->ops.init = ixgbe_init_phy_ops_X550em;
 191         phy->ops.identify = ixgbe_identify_phy_x550em;
 192         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 193                 phy->ops.set_phy_power = NULL;
 194
 195
 196         /* EEPROM */
 197         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 198         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 199         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 200         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 201         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 202         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 203         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 204         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_dmac_config_X550
 211  *  @hw: pointer to hardware structure
 212  *
 213  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 214  *  When disabling dmac, dmac enable dmac bit is cleared.
 215  **/
 216 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 217 {
 218         u32 reg, high_pri_tc;
 219
 220         DEBUGFUNC("ixgbe_dmac_config_X550");
 221
 222         /* Disable DMA coalescing before configuring */
 223         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 224         reg &= ~IXGBE_DMACR_DMAC_EN;
 225         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 226
 227         /* Disable DMA Coalescing if the watchdog timer is 0 */
 228         if (!hw->mac.dmac_config.watchdog_timer)
 229                 goto out;
 230
 231         ixgbe_dmac_config_tcs_X550(hw);
 232
 233         /* Configure DMA Coalescing Control Register */
 234         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 235
 236         /* Set the watchdog timer in units of 40.96 usec */
 237         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 238         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 239
 240         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 241         /* If fcoe is enabled, set high priority traffic class */
 242         if (hw->mac.dmac_config.fcoe_en) {
 243                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 244                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 245                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 246         }
 247         reg |= IXGBE_DMACR_EN_MNG_IND;
 248
 249         /* Enable DMA coalescing after configuration */
 250         reg |= IXGBE_DMACR_DMAC_EN;
 251         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 252
 253 out:
 254         return IXGBE_SUCCESS;
 255 }
 256
 257 /**
 258  *  ixgbe_dmac_config_tcs_X550
 259  *  @hw: pointer to hardware structure
 260  *
 261  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 262  *  be cleared before configuring.
 263  **/
 264 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 265 {
 266         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 267
 268         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 269
 270         /* Configure DMA coalescing enabled */
 271         switch (hw->mac.dmac_config.link_speed) {
 272         case IXGBE_LINK_SPEED_100_FULL:
 273                 pb_headroom = IXGBE_DMACRXT_100M;
 274                 break;
 275         case IXGBE_LINK_SPEED_1GB_FULL:
 276                 pb_headroom = IXGBE_DMACRXT_1G;
 277                 break;
 278         default:
 279                 pb_headroom = IXGBE_DMACRXT_10G;
 280                 break;
 281         }
 282
 283         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 284                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 285
 286         /* Set the per Rx packet buffer receive threshold */
 287         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 288                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 289                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 290
 291                 if (tc < hw->mac.dmac_config.num_tcs) {
 292                         /* Get Rx PB size */
 293                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 294                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 295                                 IXGBE_RXPBSIZE_SHIFT;
 296
 297                         /* Calculate receive buffer threshold in kilobytes */
 298                         if (rx_pb_size > pb_headroom)
 299                                 rx_pb_size = rx_pb_size - pb_headroom;
 300                         else
 301                                 rx_pb_size = 0;
 302
 303                         /* Minimum of MFS shall be set for DMCTH */
 304                         reg |= (rx_pb_size > maxframe_size_kb) ?
 305                                 rx_pb_size : maxframe_size_kb;
 306                 }
 307                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 308         }
 309         return IXGBE_SUCCESS;
 310 }
 311
 312 /**
 313  *  ixgbe_dmac_update_tcs_X550
 314  *  @hw: pointer to hardware structure
 315  *
 316  *  Disables dmac, updates per TC settings, and then enables dmac.
 317  **/
 318 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 319 {
 320         u32 reg;
 321
 322         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 323
 324         /* Disable DMA coalescing before configuring */
 325         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 326         reg &= ~IXGBE_DMACR_DMAC_EN;
 327         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 328
 329         ixgbe_dmac_config_tcs_X550(hw);
 330
 331         /* Enable DMA coalescing after configuration */
 332         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 333         reg |= IXGBE_DMACR_DMAC_EN;
 334         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 335
 336         return IXGBE_SUCCESS;
 337 }
 338
 339 /**
 340  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 341  *  @hw: pointer to hardware structure
 342  *
 343  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 344  *  ixgbe_hw struct in order to set up EEPROM access.
 345  **/
 346 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 347 {
 348         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 349         u32 eec;
 350         u16 eeprom_size;
 351
 352         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 353
 354         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 355                 eeprom->semaphore_delay = 10;
 356                 eeprom->type = ixgbe_flash;
 357
 358                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 359                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 360                                     IXGBE_EEC_SIZE_SHIFT);
 361                 eeprom->word_size = 1 << (eeprom_size +
 362                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 363
 364                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 365                           eeprom->type, eeprom->word_size);
 366         }
 367
 368         return IXGBE_SUCCESS;
 369 }
 370
 371 /**
 372  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 373  *  @hw: pointer to the HW structure
 374  *  @enable_eee: boolean flag to enable EEE
 375  *
 376  *  Enable/disable EEE based on enable_eee flag.
 377  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 378  *  are modified.
 379  *
 380  **/
 381 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 382 {
 383         u32 eeer;
 384         u16 autoneg_eee_reg;
 385         u32 link_reg;
 386         s32 status;
 387
 388         DEBUGFUNC("ixgbe_setup_eee_X550");
 389
 390         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 391         /* Enable or disable EEE per flag */
 392         if (enable_eee) {
 393                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 394
 395                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 396                         /* Advertise EEE capability */
 397                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 398                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 399
 400                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 401                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 402                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 403
 404                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 405                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 406                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 407                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 408                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 409                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 410                         if (status != IXGBE_SUCCESS)
 411                                 return status;
 412
 413                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 414                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 415
 416                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 417                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 418                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 419                         if (status != IXGBE_SUCCESS)
 420                                 return status;
 421                 }
 422         } else {
 423                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 424
 425                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 426                         /* Disable advertised EEE capability */
 427                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 428                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 429
 430                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 431                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 432                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 433
 434                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 435                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 436                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 437                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 438                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 439                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 440                         if (status != IXGBE_SUCCESS)
 441                                 return status;
 442
 443                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 444                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 445
 446                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 447                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 448                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 449                         if (status != IXGBE_SUCCESS)
 450                                 return status;
 451                 }
 452         }
 453         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 454
 455         return IXGBE_SUCCESS;
 456 }
 457
 458 /**
 459  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 460  * @hw: pointer to hardware structure
 461  * @enable: enable or disable source address pruning
 462  * @pool: Rx pool to set source address pruning for
 463  **/
 464 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 465                                            unsigned int pool)
 466 {
 467         u64 pfflp;
 468
 469         /* max rx pool is 63 */
 470         if (pool > 63)
 471                 return;
 472
 473         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 474         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 475
 476         if (enable)
 477                 pfflp |= (1ULL << pool);
 478         else
 479                 pfflp &= ~(1ULL << pool);
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 482         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 483 }
 484
 485 /**
 486  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 487  *  @hw: pointer to hardware structure
 488  *  @enable: enable or disable switch for Ethertype anti-spoofing
 489  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 490  *
 491  **/
 492 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 493                 bool enable, int vf)
 494 {
 495         int vf_target_reg = vf >> 3;
 496         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 497         u32 pfvfspoof;
 498
 499         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 500
 501         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 502         if (enable)
 503                 pfvfspoof |= (1 << vf_target_shift);
 504         else
 505                 pfvfspoof &= ~(1 << vf_target_shift);
 506
 507         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 508 }
 509
 510 /**
 511  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 512  *  device
 513  *  @hw: pointer to hardware structure
 514  *  @reg_addr: 32 bit PHY register to write
 515  *  @device_type: 3 bit device type
 516  *  @data: Data to write to the register
 517  **/
 518 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 519                             u32 device_type, u32 data)
 520 {
 521         u32 i, command, error;
 522
 523         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 524                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 525
 526         /* Write IOSF control register */
 527         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 528
 529         /* Write IOSF data register */
 530         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 531         /*
 532          * Check every 10 usec to see if the address cycle completed.
 533          * The SB IOSF BUSY bit will clear when the operation is
 534          * complete
 535          */
 536         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 537                 usec_delay(10);
 538
 539                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 540                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 541                         break;
 542         }
 543
 544         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 545                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 546                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 547                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 548                               "Failed to write, error %x\n", error);
 549                 return IXGBE_ERR_PHY;
 550         }
 551
 552         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 553                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 554                 return IXGBE_ERR_PHY;
 555         }
 556
 557         return IXGBE_SUCCESS;
 558 }
 559
 560 /**
 561  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 562  *  device
 563  *  @hw: pointer to hardware structure
 564  *  @reg_addr: 32 bit PHY register to write
 565  *  @device_type: 3 bit device type
 566  *  @phy_data: Pointer to read data from the register
 567  **/
 568 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 569                            u32 device_type, u32 *data)
 570 {
 571         u32 i, command, error;
 572
 573         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 574                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 575
 576         /* Write IOSF control register */
 577         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 578
 579         /*
 580          * Check every 10 usec to see if the address cycle completed.
 581          * The SB IOSF BUSY bit will clear when the operation is
 582          * complete
 583          */
 584         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 585                 usec_delay(10);
 586
 587                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 588                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 589                         break;
 590         }
 591
 592         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 593                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 594                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 595                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 596                                 "Failed to read, error %x\n", error);
 597                 return IXGBE_ERR_PHY;
 598         }
 599
 600         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 601                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 602                 return IXGBE_ERR_PHY;
 603         }
 604
 605         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 606
 607         return IXGBE_SUCCESS;
 608 }
 609
 610 /**
 611  *  ixgbe_disable_mdd_X550
 612  *  @hw: pointer to hardware structure
 613  *
 614  *  Disable malicious driver detection
 615  **/
 616 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 617 {
 618         u32 reg;
 619
 620         DEBUGFUNC("ixgbe_disable_mdd_X550");
 621
 622         /* Disable MDD for TX DMA and interrupt */
 623         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 624         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 625         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 626
 627         /* Disable MDD for RX and interrupt */
 628         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 629         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 630         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 631 }
 632
 633 /**
 634  *  ixgbe_enable_mdd_X550
 635  *  @hw: pointer to hardware structure
 636  *
 637  *  Enable malicious driver detection
 638  **/
 639 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 640 {
 641         u32 reg;
 642
 643         DEBUGFUNC("ixgbe_enable_mdd_X550");
 644
 645         /* Enable MDD for TX DMA and interrupt */
 646         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 647         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 648         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 649
 650         /* Enable MDD for RX and interrupt */
 651         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 652         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 653         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 654 }
 655
 656 /**
 657  *  ixgbe_restore_mdd_vf_X550
 658  *  @hw: pointer to hardware structure
 659  *  @vf: vf index
 660  *
 661  *  Restore VF that was disabled during malicious driver detection event
 662  **/
 663 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 664 {
 665         u32 idx, reg, num_qs, start_q, bitmask;
 666
 667         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 668
 669         /* Map VF to queues */
 670         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 671         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 672         case IXGBE_MRQC_VMDQRT8TCEN:
 673                 num_qs = 8;  /* 16 VFs / pools */
 674                 bitmask = 0x000000FF;
 675                 break;
 676         case IXGBE_MRQC_VMDQRSS32EN:
 677         case IXGBE_MRQC_VMDQRT4TCEN:
 678                 num_qs = 4;  /* 32 VFs / pools */
 679                 bitmask = 0x0000000F;
 680                 break;
 681         default:            /* 64 VFs / pools */
 682                 num_qs = 2;
 683                 bitmask = 0x00000003;
 684                 break;
 685         }
 686         start_q = vf * num_qs;
 687
 688         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 689         idx = start_q / 32;
 690         reg = 0;
 691         reg |= (bitmask << (start_q % 32));
 692         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 693         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 694 }
 695
 696 /**
 697  *  ixgbe_mdd_event_X550
 698  *  @hw: pointer to hardware structure
 699  *  @vf_bitmap: vf bitmap of malicious vfs
 700  *
 701  *  Handle malicious driver detection event.
 702  **/
 703 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 704 {
 705         u32 wqbr;
 706         u32 i, j, reg, q, shift, vf, idx;
 707
 708         DEBUGFUNC("ixgbe_mdd_event_X550");
 709
 710         /* figure out pool size for mapping to vf's */
 711         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 712         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 713         case IXGBE_MRQC_VMDQRT8TCEN:
 714                 shift = 3;  /* 16 VFs / pools */
 715                 break;
 716         case IXGBE_MRQC_VMDQRSS32EN:
 717         case IXGBE_MRQC_VMDQRT4TCEN:
 718                 shift = 2;  /* 32 VFs / pools */
 719                 break;
 720         default:
 721                 shift = 1;  /* 64 VFs / pools */
 722                 break;
 723         }
 724
 725         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 726         for (i = 0; i < 4; i++) {
 727                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 728                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 729
 730                 if (!wqbr)
 731                         continue;
 732
 733                 /* Get malicious queue */
 734                 for (j = 0; j < 32 && wqbr; j++) {
 735
 736                         if (!(wqbr & (1 << j)))
 737                                 continue;
 738
 739                         /* Get queue from bitmask */
 740                         q = j + (i * 32);
 741
 742                         /* Map queue to vf */
 743                         vf = (q >> shift);
 744
 745                         /* Set vf bit in vf_bitmap */
 746                         idx = vf / 32;
 747                         vf_bitmap[idx] |= (1 << (vf % 32));
 748                         wqbr &= ~(1 << j);
 749                 }
 750         }
 751 }
 752
 753 /**
 754  *  ixgbe_get_media_type_X550em - Get media type
 755  *  @hw: pointer to hardware structure
 756  *
 757  *  Returns the media type (fiber, copper, backplane)
 758  */
 759 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 760 {
 761         enum ixgbe_media_type media_type;
 762
 763         DEBUGFUNC("ixgbe_get_media_type_X550em");
 764
 765         /* Detect if there is a copper PHY attached. */
 766         switch (hw->device_id) {
 767         case IXGBE_DEV_ID_X550EM_X_KR:
 768         case IXGBE_DEV_ID_X550EM_X_KX4:
 769                 media_type = ixgbe_media_type_backplane;
 770                 break;
 771         case IXGBE_DEV_ID_X550EM_X_SFP:
 772                 media_type = ixgbe_media_type_fiber;
 773                 break;
 774         case IXGBE_DEV_ID_X550EM_X_1G_T:
 775         case IXGBE_DEV_ID_X550EM_X_10G_T:
 776                 media_type = ixgbe_media_type_copper;
 777                 break;
 778         default:
 779                 media_type = ixgbe_media_type_unknown;
 780                 break;
 781         }
 782         return media_type;
 783 }
 784
 785 /**
 786  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 787  *  @hw: pointer to hardware structure
 788  */
 789 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 790 {
 791         bool setup_linear;
 792         u16 reg_slice, edc_mode;
 793         s32 ret_val;
 794
 795         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 796
 797         switch (hw->phy.sfp_type) {
 798         case ixgbe_sfp_type_unknown:
 799                 return IXGBE_SUCCESS;
 800         case ixgbe_sfp_type_not_present:
 801                 return IXGBE_ERR_SFP_NOT_PRESENT;
 802         case ixgbe_sfp_type_da_cu_core0:
 803         case ixgbe_sfp_type_da_cu_core1:
 804                 setup_linear = true;
 805                 break;
 806         case ixgbe_sfp_type_srlr_core0:
 807         case ixgbe_sfp_type_srlr_core1:
 808         case ixgbe_sfp_type_da_act_lmt_core0:
 809         case ixgbe_sfp_type_da_act_lmt_core1:
 810         case ixgbe_sfp_type_1g_sx_core0:
 811         case ixgbe_sfp_type_1g_sx_core1:
 812         case ixgbe_sfp_type_1g_lx_core0:
 813         case ixgbe_sfp_type_1g_lx_core1:
 814                 setup_linear = false;
 815                 break;
 816         default:
 817                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 818         }
 819
 820         ixgbe_init_mac_link_ops_X550em(hw);
 821         hw->phy.ops.reset = NULL;
 822
 823         /* The CS4227 slice address is the base address + the port-pair reg
 824          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 825          */
 826         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
 827
 828         if (setup_linear)
 829                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 830         else
 831                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 832
 833         /* Configure CS4227 for connection type. */
 834         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 835                                            edc_mode);
 836
 837         if (ret_val != IXGBE_SUCCESS)
 838                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 839                                                    edc_mode);
 840
 841         return ret_val;
 842 }
 843
 844 /**
 845  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 846  *  @hw: pointer to hardware structure
 847  */
 848 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 849 {
 850         struct ixgbe_mac_info *mac = &hw->mac;
 851
 852         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 853
 854         /* CS4227 does not support autoneg, so disable the laser control
 855          * functions for SFP+ fiber
 856          */
 857          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 858                 mac->ops.disable_tx_laser = NULL;
 859                 mac->ops.enable_tx_laser = NULL;
 860                 mac->ops.flap_tx_laser = NULL;
 861          }
 862 }
 863
 864 /**
 865  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 866  *  @hw: pointer to hardware structure
 867  *  @speed: pointer to link speed
 868  *  @autoneg: true when autoneg or autotry is enabled
 869  */
 870 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 871                                        ixgbe_link_speed *speed,
 872                                        bool *autoneg)
 873 {
 874         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 875
 876         /* SFP */
 877         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 878
 879                 /* CS4227 SFP must not enable auto-negotiation */
 880                 *autoneg = false;
 881
 882                 /* Check if 1G SFP module. */
 883                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 884                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 885                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 886                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 887                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 888                         return IXGBE_SUCCESS;
 889                 }
 890
 891                 /* Link capabilities are based on SFP */
 892                 if (hw->phy.multispeed_fiber)
 893                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 894                                  IXGBE_LINK_SPEED_1GB_FULL;
 895                 else
 896                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 897         } else {
 898                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 899                          IXGBE_LINK_SPEED_1GB_FULL;
 900                 *autoneg = true;
 901         }
 902
 903         return IXGBE_SUCCESS;
 904 }
 905
 906 /**
 907  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 908  *  @hw: pointer to hardware structure
 909  *
 910  *  Initialize any function pointers that were not able to be
 911  *  set during init_shared_code because the PHY/SFP type was
 912  *  not known.  Perform the SFP init if necessary.
 913  */
 914 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 915 {
 916         struct ixgbe_phy_info *phy = &hw->phy;
 917         s32 ret_val;
 918         u32 esdp;
 919
 920         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 921
 922         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 923                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 924                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 925
 926                 if (hw->bus.lan_id) {
 927                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 928                         esdp |= IXGBE_ESDP_SDP1_DIR;
 929                 }
 930                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 931                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 932         }
 933
 934         /* Identify the PHY or SFP module */
 935         ret_val = phy->ops.identify(hw);
 936         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 937                 return ret_val;
 938
 939         /* Setup function pointers based on detected SFP module and speeds */
 940         ixgbe_init_mac_link_ops_X550em(hw);
 941         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 942                 phy->ops.reset = NULL;
 943
 944         /* Set functions pointers based on phy type */
 945         switch (hw->phy.type) {
 946         case ixgbe_phy_x550em_kx4:
 947                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
 948                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 949                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 950                 break;
 951         case ixgbe_phy_x550em_kr:
 952                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 953                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 954                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 955                 break;
 956         case ixgbe_phy_x550em_ext_t:
 957                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
 958                 break;
 959         default:
 960                 break;
 961         }
 962         return ret_val;
 963 }
 964
 965 /**
 966  *  ixgbe_reset_hw_X550em - Perform hardware reset
 967  *  @hw: pointer to hardware structure
 968  *
 969  *  Resets the hardware by resetting the transmit and receive units, masks
 970  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 971  *  reset.
 972  */
 973 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 974 {
 975         ixgbe_link_speed link_speed;
 976         s32 status;
 977         u32 ctrl = 0;
 978         u32 i;
 979         bool link_up = false;
 980
 981         DEBUGFUNC("ixgbe_reset_hw_X550em");
 982
 983         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 984         status = hw->mac.ops.stop_adapter(hw);
 985         if (status != IXGBE_SUCCESS)
 986                 return status;
 987
 988         /* flush pending Tx transactions */
 989         ixgbe_clear_tx_pending(hw);
 990
 991         /* PHY ops must be identified and initialized prior to reset */
 992
 993         /* Identify PHY and related function pointers */
 994         status = hw->phy.ops.init(hw);
 995
 996         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 997                 return status;
 998
 999         /* start the external PHY */
1000         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1001                 status = ixgbe_init_ext_t_x550em(hw);
1002                 if (status)
1003                         return status;
1004         }
1005
1006         /* Setup SFP module if there is one present. */
1007         if (hw->phy.sfp_setup_needed) {
1008                 status = hw->mac.ops.setup_sfp(hw);
1009                 hw->phy.sfp_setup_needed = false;
1010         }
1011
1012         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1013                 return status;
1014
1015         /* Reset PHY */
1016         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1017                 hw->phy.ops.reset(hw);
1018
1019 mac_reset_top:
1020         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1021          * If link reset is used when link is up, it might reset the PHY when
1022          * mng is using it.  If link is down or the flag to force full link
1023          * reset is set, then perform link reset.
1024          */
1025         ctrl = IXGBE_CTRL_LNK_RST;
1026         if (!hw->force_full_reset) {
1027                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1028                 if (link_up)
1029                         ctrl = IXGBE_CTRL_RST;
1030         }
1031
1032         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1033         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1034         IXGBE_WRITE_FLUSH(hw);
1035
1036         /* Poll for reset bit to self-clear meaning reset is complete */
1037         for (i = 0; i < 10; i++) {
1038                 usec_delay(1);
1039                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1040                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1041                         break;
1042         }
1043
1044         if (ctrl & IXGBE_CTRL_RST_MASK) {
1045                 status = IXGBE_ERR_RESET_FAILED;
1046                 DEBUGOUT("Reset polling failed to complete.\n");
1047         }
1048
1049         msec_delay(50);
1050
1051         /* Double resets are required for recovery from certain error
1052          * conditions.  Between resets, it is necessary to stall to
1053          * allow time for any pending HW events to complete.
1054          */
1055         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1056                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1057                 goto mac_reset_top;
1058         }
1059
1060         /* Store the permanent mac address */
1061         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1062
1063         /* Store MAC address from RAR0, clear receive address registers, and
1064          * clear the multicast table.  Also reset num_rar_entries to 128,
1065          * since we modify this value when programming the SAN MAC address.
1066          */
1067         hw->mac.num_rar_entries = 128;
1068         hw->mac.ops.init_rx_addrs(hw);
1069
1070
1071         return status;
1072 }
1073
1074 /**
1075  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1076  * @hw: pointer to hardware structure
1077  */
1078 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1079 {
1080         u32 status;
1081         u16 reg;
1082         u32 retries = 1;
1083
1084         /* TODO: The number of attempts and delay between attempts is undefined */
1085         do {
1086                 /* decrement retries counter and exit if we hit 0 */
1087                 if (retries < 1) {
1088                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1089                                       "External PHY not yet finished resetting.");
1090                         return IXGBE_ERR_PHY;
1091                 }
1092                 retries--;
1093
1094                 usec_delay(0);
1095
1096                 status = hw->phy.ops.read_reg(hw,
1097                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1098                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1099                                               &reg);
1100
1101                 if (status != IXGBE_SUCCESS)
1102                         return status;
1103
1104                 /* Verify PHY FW reset has completed */
1105         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1106
1107         /* Set port to low power mode */
1108         status = hw->phy.ops.read_reg(hw,
1109                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1110                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1111                                       &reg);
1112
1113         if (status != IXGBE_SUCCESS)
1114                 return status;
1115
1116         reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1117
1118         status = hw->phy.ops.write_reg(hw,
1119                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1120                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1121                                        reg);
1122
1123         if (status != IXGBE_SUCCESS)
1124                 return status;
1125
1126         /* Enable the transmitter */
1127         status = hw->phy.ops.read_reg(hw,
1128                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1129                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1130                                       &reg);
1131
1132         if (status != IXGBE_SUCCESS)
1133                 return status;
1134
1135         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1136
1137         status = hw->phy.ops.write_reg(hw,
1138                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1139                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1140                                        reg);
1141
1142         if (status != IXGBE_SUCCESS)
1143                 return status;
1144
1145         /* Un-stall the PHY FW */
1146         status = hw->phy.ops.read_reg(hw,
1147                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1148                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1149                                       &reg);
1150
1151         if (status != IXGBE_SUCCESS)
1152                 return status;
1153
1154         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1155
1156         status = hw->phy.ops.write_reg(hw,
1157                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1158                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1159                                        reg);
1160
1161         return status;
1162 }
1163
1164 /**
1165  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1166  *  @hw: pointer to hardware structure
1167  *
1168  *  Configures the integrated KR PHY.
1169  **/
1170 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1171 {
1172         s32 status;
1173         u32 reg_val;
1174
1175         status = ixgbe_read_iosf_sb_reg_x550(hw,
1176                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1177                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1178         if (status)
1179                 return status;
1180
1181         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1182         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1183         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1184         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1185                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1186
1187         /* Advertise 10G support. */
1188         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1189                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1190
1191         /* Advertise 1G support. */
1192         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1193                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1194
1195         /* Restart auto-negotiation. */
1196         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1197         status = ixgbe_write_iosf_sb_reg_x550(hw,
1198                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1199                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1200
1201         return status;
1202 }
1203
1204 /**
1205  *  ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1206  *  @hw: pointer to hardware structure
1207  *
1208  *  Configures the integrated KX4 PHY.
1209  **/
1210 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1211 {
1212         s32 status;
1213         u32 reg_val;
1214
1215         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1216                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, &reg_val);
1217         if (status)
1218                 return status;
1219
1220         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1221                         IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1222
1223         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1224
1225         /* Advertise 10G support. */
1226         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1227                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1228
1229         /* Advertise 1G support. */
1230         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1231                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1232
1233         /* Restart auto-negotiation. */
1234         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1235         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1236                 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val);
1237
1238         return status;
1239 }
1240
1241 /**
1242  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1243  *  @hw: pointer to hardware structure
1244  *  @speed: the link speed to force
1245  *
1246  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1247  *  internal and external PHY at a specific speed, without autonegotiation.
1248  **/
1249 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1250 {
1251         s32 status;
1252         u32 reg_val;
1253
1254         /* Disable AN and force speed to 10G Serial. */
1255         status = ixgbe_read_iosf_sb_reg_x550(hw,
1256                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1257                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1258         if (status != IXGBE_SUCCESS)
1259                 return status;
1260
1261         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1262         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1263
1264         /* Select forced link speed for internal PHY. */
1265         switch (*speed) {
1266         case IXGBE_LINK_SPEED_10GB_FULL:
1267                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1268                 break;
1269         case IXGBE_LINK_SPEED_1GB_FULL:
1270                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1271                 break;
1272         default:
1273                 /* Other link speeds are not supported by internal KR PHY. */
1274                 return IXGBE_ERR_LINK_SETUP;
1275         }
1276
1277         status = ixgbe_write_iosf_sb_reg_x550(hw,
1278                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1279                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1280         if (status != IXGBE_SUCCESS)
1281                 return status;
1282
1283         /* Disable training protocol FSM. */
1284         status = ixgbe_read_iosf_sb_reg_x550(hw,
1285                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1286                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1287         if (status != IXGBE_SUCCESS)
1288                 return status;
1289         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1290         status = ixgbe_write_iosf_sb_reg_x550(hw,
1291                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1292                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1293         if (status != IXGBE_SUCCESS)
1294                 return status;
1295
1296         /* Disable Flex from training TXFFE. */
1297         status = ixgbe_read_iosf_sb_reg_x550(hw,
1298                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1299                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1300         if (status != IXGBE_SUCCESS)
1301                 return status;
1302         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1303         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1304         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1305         status = ixgbe_write_iosf_sb_reg_x550(hw,
1306                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1307                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1308         if (status != IXGBE_SUCCESS)
1309                 return status;
1310         status = ixgbe_read_iosf_sb_reg_x550(hw,
1311                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1312                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1313         if (status != IXGBE_SUCCESS)
1314                 return status;
1315         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1316         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1317         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1318         status = ixgbe_write_iosf_sb_reg_x550(hw,
1319                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1320                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1321         if (status != IXGBE_SUCCESS)
1322                 return status;
1323
1324         /* Enable override for coefficients. */
1325         status = ixgbe_read_iosf_sb_reg_x550(hw,
1326                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1327                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1328         if (status != IXGBE_SUCCESS)
1329                 return status;
1330         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1331         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1332         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1333         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1334         status = ixgbe_write_iosf_sb_reg_x550(hw,
1335                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1336                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1337         if (status != IXGBE_SUCCESS)
1338                 return status;
1339
1340         /* Toggle port SW reset by AN reset. */
1341         status = ixgbe_read_iosf_sb_reg_x550(hw,
1342                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1343                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1344         if (status != IXGBE_SUCCESS)
1345                 return status;
1346         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1347         status = ixgbe_write_iosf_sb_reg_x550(hw,
1348                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1349                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1350
1351         return status;
1352 }
1353
1354 /**
1355  * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1356  * @hw: point to hardware structure
1357  *
1358  * Configures the integrated KR PHY to talk to the external PHY. The base
1359  * driver will call this function when it gets notification via interrupt from
1360  * the external PHY. This function forces the internal PHY into iXFI mode at
1361  * the correct speed.
1362  *
1363  * A return of a non-zero value indicates an error, and the base driver should
1364  * not report link up.
1365  */
1366 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1367 {
1368         u32 status;
1369         u16 lasi, autoneg_status, speed;
1370         ixgbe_link_speed force_speed;
1371
1372         /* Verify that the external link status has changed */
1373         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1374                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1375                                       &lasi);
1376         if (status != IXGBE_SUCCESS)
1377                 return status;
1378
1379         /* If there was no change in link status, we can just exit */
1380         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1381                 return IXGBE_SUCCESS;
1382
1383         /* we read this twice back to back to indicate current status */
1384         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1385                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1386                                       &autoneg_status);
1387         if (status != IXGBE_SUCCESS)
1388                 return status;
1389
1390         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1391                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1392                                       &autoneg_status);
1393         if (status != IXGBE_SUCCESS)
1394                 return status;
1395
1396         /* If link is not up return an error indicating treat link as down */
1397         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1398                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1399
1400         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1401                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1402                                       &speed);
1403
1404         /* clear everything but the speed and duplex bits */
1405         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1406
1407         switch (speed) {
1408         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1409                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1410                 break;
1411         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1412                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1413                 break;
1414         default:
1415                 /* Internal PHY does not support anything else */
1416                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1417         }
1418
1419         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1420 }
1421
1422 /**
1423  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1424  *  @hw: pointer to hardware structure
1425  *
1426  *  Configures the integrated KR PHY to use internal loopback mode.
1427  **/
1428 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1429 {
1430         s32 status;
1431         u32 reg_val;
1432
1433         /* Disable AN and force speed to 10G Serial. */
1434         status = ixgbe_read_iosf_sb_reg_x550(hw,
1435                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1436                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1437         if (status != IXGBE_SUCCESS)
1438                 return status;
1439         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1440         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1441         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1442         status = ixgbe_write_iosf_sb_reg_x550(hw,
1443                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1444                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1445         if (status != IXGBE_SUCCESS)
1446                 return status;
1447
1448         /* Set near-end loopback clocks. */
1449         status = ixgbe_read_iosf_sb_reg_x550(hw,
1450                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1451                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1452         if (status != IXGBE_SUCCESS)
1453                 return status;
1454         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1455         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1456         status = ixgbe_write_iosf_sb_reg_x550(hw,
1457                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1458                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1459         if (status != IXGBE_SUCCESS)
1460                 return status;
1461
1462         /* Set loopback enable. */
1463         status = ixgbe_read_iosf_sb_reg_x550(hw,
1464                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1465                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1466         if (status != IXGBE_SUCCESS)
1467                 return status;
1468         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1469         status = ixgbe_write_iosf_sb_reg_x550(hw,
1470                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1471                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1472         if (status != IXGBE_SUCCESS)
1473                 return status;
1474
1475         /* Training bypass. */
1476         status = ixgbe_read_iosf_sb_reg_x550(hw,
1477                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1478                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1479         if (status != IXGBE_SUCCESS)
1480                 return status;
1481         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1482         status = ixgbe_write_iosf_sb_reg_x550(hw,
1483                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1484                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1485
1486         return status;
1487 }
1488
1489 /**
1490  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1491  *  assuming that the semaphore is already obtained.
1492  *  @hw: pointer to hardware structure
1493  *  @offset: offset of  word in the EEPROM to read
1494  *  @data: word read from the EEPROM
1495  *
1496  *  Reads a 16 bit word from the EEPROM using the hostif.
1497  **/
1498 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1499                                    u16 *data)
1500 {
1501         s32 status;
1502         struct ixgbe_hic_read_shadow_ram buffer;
1503
1504         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1505         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1506         buffer.hdr.req.buf_lenh = 0;
1507         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1508         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1509
1510         /* convert offset from words to bytes */
1511         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1512         /* one word */
1513         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1514
1515         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1516                                               sizeof(buffer),
1517                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1518
1519         if (status)
1520                 return status;
1521
1522         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1523                                           FW_NVM_DATA_OFFSET);
1524
1525         return 0;
1526 }
1527
1528 /**
1529  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1530  *  @hw: pointer to hardware structure
1531  *  @offset: offset of  word in the EEPROM to read
1532  *  @data: word read from the EEPROM
1533  *
1534  *  Reads a 16 bit word from the EEPROM using the hostif.
1535  **/
1536 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1537                               u16 *data)
1538 {
1539         s32 status = IXGBE_SUCCESS;
1540
1541         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1542
1543         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1544             IXGBE_SUCCESS) {
1545                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1546                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1547         } else {
1548                 status = IXGBE_ERR_SWFW_SYNC;
1549         }
1550
1551         return status;
1552 }
1553
1554 /**
1555  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1556  *  @hw: pointer to hardware structure
1557  *  @offset: offset of  word in the EEPROM to read
1558  *  @words: number of words
1559  *  @data: word(s) read from the EEPROM
1560  *
1561  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1562  **/
1563 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1564                                      u16 offset, u16 words, u16 *data)
1565 {
1566         struct ixgbe_hic_read_shadow_ram buffer;
1567         u32 current_word = 0;
1568         u16 words_to_read;
1569         s32 status;
1570         u32 i;
1571
1572         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1573
1574         /* Take semaphore for the entire operation. */
1575         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1576         if (status) {
1577                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1578                 return status;
1579         }
1580         while (words) {
1581                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1582                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1583                 else
1584                         words_to_read = words;
1585
1586                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1587                 buffer.hdr.req.buf_lenh = 0;
1588                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1589                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1590
1591                 /* convert offset from words to bytes */
1592                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1593                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1594
1595                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1596                                                       sizeof(buffer),
1597                                                       IXGBE_HI_COMMAND_TIMEOUT,
1598                                                       false);
1599
1600                 if (status) {
1601                         DEBUGOUT("Host interface command failed\n");
1602                         goto out;
1603                 }
1604
1605                 for (i = 0; i < words_to_read; i++) {
1606                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1607                                   2 * i;
1608                         u32 value = IXGBE_READ_REG(hw, reg);
1609
1610                         data[current_word] = (u16)(value & 0xffff);
1611                         current_word++;
1612                         i++;
1613                         if (i < words_to_read) {
1614                                 value >>= 16;
1615                                 data[current_word] = (u16)(value & 0xffff);
1616                                 current_word++;
1617                         }
1618                 }
1619                 words -= words_to_read;
1620         }
1621
1622 out:
1623         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1624         return status;
1625 }
1626
1627 /**
1628  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1629  *  @hw: pointer to hardware structure
1630  *  @offset: offset of  word in the EEPROM to write
1631  *  @data: word write to the EEPROM
1632  *
1633  *  Write a 16 bit word to the EEPROM using the hostif.
1634  **/
1635 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1636                                     u16 data)
1637 {
1638         s32 status;
1639         struct ixgbe_hic_write_shadow_ram buffer;
1640
1641         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1642
1643         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1644         buffer.hdr.req.buf_lenh = 0;
1645         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1646         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1647
1648          /* one word */
1649         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1650         buffer.data = data;
1651         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1652
1653         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1654                                               sizeof(buffer),
1655                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1656
1657         return status;
1658 }
1659
1660 /**
1661  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1662  *  @hw: pointer to hardware structure
1663  *  @offset: offset of  word in the EEPROM to write
1664  *  @data: word write to the EEPROM
1665  *
1666  *  Write a 16 bit word to the EEPROM using the hostif.
1667  **/
1668 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1669                                u16 data)
1670 {
1671         s32 status = IXGBE_SUCCESS;
1672
1673         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1674
1675         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1676             IXGBE_SUCCESS) {
1677                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1678                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1679         } else {
1680                 DEBUGOUT("write ee hostif failed to get semaphore");
1681                 status = IXGBE_ERR_SWFW_SYNC;
1682         }
1683
1684         return status;
1685 }
1686
1687 /**
1688  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1689  *  @hw: pointer to hardware structure
1690  *  @offset: offset of  word in the EEPROM to write
1691  *  @words: number of words
1692  *  @data: word(s) write to the EEPROM
1693  *
1694  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1695  **/
1696 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1697                                       u16 offset, u16 words, u16 *data)
1698 {
1699         s32 status = IXGBE_SUCCESS;
1700         u32 i = 0;
1701
1702         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1703
1704         /* Take semaphore for the entire operation. */
1705         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1706         if (status != IXGBE_SUCCESS) {
1707                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1708                 goto out;
1709         }
1710
1711         for (i = 0; i < words; i++) {
1712                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1713                                                          data[i]);
1714
1715                 if (status != IXGBE_SUCCESS) {
1716                         DEBUGOUT("Eeprom buffered write failed\n");
1717                         break;
1718                 }
1719         }
1720
1721         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1722 out:
1723
1724         return status;
1725 }
1726
1727 /**
1728  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1729  * @hw: pointer to hardware structure
1730  * @ptr: pointer offset in eeprom
1731  * @size: size of section pointed by ptr, if 0 first word will be used as size
1732  * @csum: address of checksum to update
1733  *
1734  * Returns error status for any failure
1735  */
1736 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1737                                    u16 size, u16 *csum, u16 *buffer,
1738                                    u32 buffer_size)
1739 {
1740         u16 buf[256];
1741         s32 status;
1742         u16 length, bufsz, i, start;
1743         u16 *local_buffer;
1744
1745         bufsz = sizeof(buf) / sizeof(buf[0]);
1746
1747         /* Read a chunk at the pointer location */
1748         if (!buffer) {
1749                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1750                 if (status) {
1751                         DEBUGOUT("Failed to read EEPROM image\n");
1752                         return status;
1753                 }
1754                 local_buffer = buf;
1755         } else {
1756                 if (buffer_size < ptr)
1757                         return  IXGBE_ERR_PARAM;
1758                 local_buffer = &buffer[ptr];
1759         }
1760
1761         if (size) {
1762                 start = 0;
1763                 length = size;
1764         } else {
1765                 start = 1;
1766                 length = local_buffer[0];
1767
1768                 /* Skip pointer section if length is invalid. */
1769                 if (length == 0xFFFF || length == 0 ||
1770                     (ptr + length) >= hw->eeprom.word_size)
1771                         return IXGBE_SUCCESS;
1772         }
1773
1774         if (buffer && ((u32)start + (u32)length > buffer_size))
1775                 return IXGBE_ERR_PARAM;
1776
1777         for (i = start; length; i++, length--) {
1778                 if (i == bufsz && !buffer) {
1779                         ptr += bufsz;
1780                         i = 0;
1781                         if (length < bufsz)
1782                                 bufsz = length;
1783
1784                         /* Read a chunk at the pointer location */
1785                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1786                                                                   bufsz, buf);
1787                         if (status) {
1788                                 DEBUGOUT("Failed to read EEPROM image\n");
1789                                 return status;
1790                         }
1791                 }
1792                 *csum += local_buffer[i];
1793         }
1794         return IXGBE_SUCCESS;
1795 }
1796
1797 /**
1798  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1799  *  @hw: pointer to hardware structure
1800  *  @buffer: pointer to buffer containing calculated checksum
1801  *  @buffer_size: size of buffer
1802  *
1803  *  Returns a negative error code on error, or the 16-bit checksum
1804  **/
1805 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
1806 {
1807         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1808         u16 *local_buffer;
1809         s32 status;
1810         u16 checksum = 0;
1811         u16 pointer, i, size;
1812
1813         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1814
1815         hw->eeprom.ops.init_params(hw);
1816
1817         if (!buffer) {
1818                 /* Read pointer area */
1819                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1820                                                      IXGBE_EEPROM_LAST_WORD + 1,
1821                                                      eeprom_ptrs);
1822                 if (status) {
1823                         DEBUGOUT("Failed to read EEPROM image\n");
1824                         return status;
1825                 }
1826                 local_buffer = eeprom_ptrs;
1827         } else {
1828                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1829                         return IXGBE_ERR_PARAM;
1830                 local_buffer = buffer;
1831         }
1832
1833         /*
1834          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1835          * checksum word itself
1836          */
1837         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1838                 if (i != IXGBE_EEPROM_CHECKSUM)
1839                         checksum += local_buffer[i];
1840
1841         /*
1842          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1843          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1844          */
1845         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1846                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1847                         continue;
1848
1849                 pointer = local_buffer[i];
1850
1851                 /* Skip pointer section if the pointer is invalid. */
1852                 if (pointer == 0xFFFF || pointer == 0 ||
1853                     pointer >= hw->eeprom.word_size)
1854                         continue;
1855
1856                 switch (i) {
1857                 case IXGBE_PCIE_GENERAL_PTR:
1858                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1859                         break;
1860                 case IXGBE_PCIE_CONFIG0_PTR:
1861                 case IXGBE_PCIE_CONFIG1_PTR:
1862                         size = IXGBE_PCIE_CONFIG_SIZE;
1863                         break;
1864                 default:
1865                         size = 0;
1866                         break;
1867                 }
1868
1869                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1870                                                 buffer, buffer_size);
1871                 if (status)
1872                         return status;
1873         }
1874
1875         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1876
1877         return (s32)checksum;
1878 }
1879
1880 /**
1881  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1882  *  @hw: pointer to hardware structure
1883  *
1884  *  Returns a negative error code on error, or the 16-bit checksum
1885  **/
1886 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1887 {
1888         return ixgbe_calc_checksum_X550(hw, NULL, 0);
1889 }
1890
1891 /**
1892  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1893  *  @hw: pointer to hardware structure
1894  *  @checksum_val: calculated checksum
1895  *
1896  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1897  *  caller does not need checksum_val, the value can be NULL.
1898  **/
1899 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1900 {
1901         s32 status;
1902         u16 checksum;
1903         u16 read_checksum = 0;
1904
1905         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1906
1907         /* Read the first word from the EEPROM. If this times out or fails, do
1908          * not continue or we could be in for a very long wait while every
1909          * EEPROM read fails
1910          */
1911         status = hw->eeprom.ops.read(hw, 0, &checksum);
1912         if (status) {
1913                 DEBUGOUT("EEPROM read failed\n");
1914                 return status;
1915         }
1916
1917         status = hw->eeprom.ops.calc_checksum(hw);
1918         if (status < 0)
1919                 return status;
1920
1921         checksum = (u16)(status & 0xffff);
1922
1923         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1924                                            &read_checksum);
1925         if (status)
1926                 return status;
1927
1928         /* Verify read checksum from EEPROM is the same as
1929          * calculated checksum
1930          */
1931         if (read_checksum != checksum) {
1932                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1933                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1934                              "Invalid EEPROM checksum");
1935         }
1936
1937         /* If the user cares, return the calculated checksum */
1938         if (checksum_val)
1939                 *checksum_val = checksum;
1940
1941         return status;
1942 }
1943
1944 /**
1945  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1946  * @hw: pointer to hardware structure
1947  *
1948  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1949  * checksum and updates the EEPROM and instructs the hardware to update
1950  * the flash.
1951  **/
1952 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1953 {
1954         s32 status;
1955         u16 checksum = 0;
1956
1957         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1958
1959         /* Read the first word from the EEPROM. If this times out or fails, do
1960          * not continue or we could be in for a very long wait while every
1961          * EEPROM read fails
1962          */
1963         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1964         if (status) {
1965                 DEBUGOUT("EEPROM read failed\n");
1966                 return status;
1967         }
1968
1969         status = ixgbe_calc_eeprom_checksum_X550(hw);
1970         if (status < 0)
1971                 return status;
1972
1973         checksum = (u16)(status & 0xffff);
1974
1975         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1976                                             checksum);
1977         if (status)
1978                 return status;
1979
1980         status = ixgbe_update_flash_X550(hw);
1981
1982         return status;
1983 }
1984
1985 /**
1986  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1987  *  @hw: pointer to hardware structure
1988  *
1989  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1990  **/
1991 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1992 {
1993         s32 status = IXGBE_SUCCESS;
1994         union ixgbe_hic_hdr2 buffer;
1995
1996         DEBUGFUNC("ixgbe_update_flash_X550");
1997
1998         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1999         buffer.req.buf_lenh = 0;
2000         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2001         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2002
2003         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2004                                               sizeof(buffer),
2005                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2006
2007         return status;
2008 }
2009
2010 /**
2011  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2012  *  @hw: pointer to hardware structure
2013  *
2014  *  Determines physical layer capabilities of the current configuration.
2015  **/
2016 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2017 {
2018         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2019         u16 ext_ability = 0;
2020
2021         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2022
2023         hw->phy.ops.identify(hw);
2024
2025         switch (hw->phy.type) {
2026         case ixgbe_phy_x550em_kr:
2027                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2028                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2029                 break;
2030         case ixgbe_phy_x550em_kx4:
2031                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2032                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2033                 break;
2034         case ixgbe_phy_x550em_ext_t:
2035                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2036                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2037                                      &ext_ability);
2038                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2039                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2040                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2041                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2042                 break;
2043         default:
2044                 break;
2045         }
2046
2047         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2048                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2049
2050         return physical_layer;
2051 }
2052
2053 /**
2054  * ixgbe_get_bus_info_x550em - Set PCI bus info
2055  * @hw: pointer to hardware structure
2056  *
2057  * Sets bus link width and speed to unknown because X550em is
2058  * not a PCI device.
2059  **/
2060 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2061 {
2062
2063         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2064
2065         hw->bus.width = ixgbe_bus_width_unknown;
2066         hw->bus.speed = ixgbe_bus_speed_unknown;
2067
2068         return IXGBE_SUCCESS;
2069 }
2070
2071 /**
2072  * ixgbe_disable_rx_x550 - Disable RX unit
2073  *
2074  * Enables the Rx DMA unit for x550
2075  **/
2076 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2077 {
2078         u32 rxctrl, pfdtxgswc;
2079         s32 status;
2080         struct ixgbe_hic_disable_rxen fw_cmd;
2081
2082         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2083
2084         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2085         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2086                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2087                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2088                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2089                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2090                         hw->mac.set_lben = true;
2091                 } else {
2092                         hw->mac.set_lben = false;
2093                 }
2094
2095                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2096                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2097                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2098                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2099
2100                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2101                                         sizeof(struct ixgbe_hic_disable_rxen),
2102                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2103
2104                 /* If we fail - disable RX using register write */
2105                 if (status) {
2106                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2107                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2108                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2109                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2110                         }
2111                 }
2112         }
2113 }